Journal of Electronic Testing (2019) 35:401–412https://doi.org/10.1007/s10836-019-05796-x

Modeling Soft Error Propagation in Near-Threshold CombinationalCircuits Using Neural Networks

Ali Hajian1 · Saeed Safari1

Received: 16 December 2018 / Accepted: 10 April 2019 / Published online: 29 May 2019© Springer Science+Business Media, LLC, part of Springer Nature 2019

AbstractWith CMOS technology down-scaling, an assuring approach to reduce the power consumption of VLSI designs is Near-Threshold Computing (NTC). However, lowering the supply voltage continuously, exacerbates reliability challenges inmodern CMOS logics due to creation of soft errors introduced by single event transients (SETs). In this work, we presenteda fast-yet-accurate neural network based model to calculate soft error rate (SER) in circuits in the near-threshold voltagedomain. Multi-Layer perceptron (MLP) and recurrent neural network (RNN) used for modeling each gate of a given library.The training data set includes injected SET samples, expected outputs and parameters of each gate. Finally, the propagationof faults in the investigated circuits is calculated using our proposed method. On average, experimental results show that wecan estimate soft error rate 10-20 times faster in comparison to HSPICE simulation, with less than 0.1% accuracy loss.

Keywords Soft error · Neural network · Near threshold

1 Introduction

In the last decade, power has become the primary designconstraint in chip design [9]. During the last severaldecades, exponential increase in the number of transistorson a chip has led to improvements in computational applica-tions. However, energy and power dissipation are substantialimpediments to this growth. Commercially viable solutionsto overcome these boundaries include enhanced devices,design styles, and architecture.

Device scaling no longer delivered the energy gain thatdrove the semiconductor growth in the past several decades[4]. Energy consumption can be reduced quadratically bylowering supply voltage (Vdd ) as a result, voltage scalingis one of the most effective methods to reduce powerconsumption in modern CMOS circuits.

Responsible Editor: F. L. Vargas

� Saeed Safarisaeed@ut.ac.ir

Ali Hajianahajian@ut.ac.ir

1 School of Electrical and Computer Engineering,College of Engineering, University of Tehran,Tehran, 14395-515, Iran

Voltage scaling down to Vth, known as near-thresholdregime, yields a 10 times energy reduction at the expenseof 10 times performance degradation [8]. Near thresholdis a suitable solution for energy and delay trade-off thatcan be used in energy consuming applications like high-performance computing. Especially in new applicationslike Internet of Things (IoT) and portable devices, energyconcerns are more important than performance.

Although near threshold leads to lower energy consump-tion, we should analyze effects of working in this regimeon circuit features beside performance. Reliability is oneof the prime concerns in this area. Especially, single eventupsets (change of state caused by one single ionizing parti-cle (SEU)) from radiation will increase in this regime[20].Whether a circuit experiences a soft error depends on theenergy of the incoming particle, the geometry of the impact,the location of the strike, and the design of the logic circuit.Decreasing the supply voltage will decrease critical charge(Qcrit ), the minimum electron charge disturbance needed tochange the logic level and it increases SER exponentiallydue to increase of SETs effect.

Preliminary works on soft error anticipation indicate thatsoft errors in combinational circuits and latches are themajority percent of the overall soft errors. This percent isincreasing with technology scaling [24]. To decrease SERof a circuit, we should immune combinational part of thecircuit against soft errors along with memory part. So we

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should consider immunizing combinational parts againstsoft error to achieve better reliability.

To investigate the effects of voltage scaling on reliability,we need a way to calculate or estimate SER. SER is therate at which a device or system encounters or is predictedto encounter soft errors. It is typically expressed as eitherthe number of failures-in-time (FIT) or mean time betweenfailures (MTBF).

In the literature various approaches have been proposedto calculate SER. Some studies have been published onexposing the circuit to artificial radiation with high energyions. Number of faults that reaches to the outputs iscalculated by studying every output [13, 18]. This procedureis fast and accurate, but unfortunately it is not applicablein design phase. Another drawback of this method isits uncontrollable fault injection. Applying this method,injecting the fault to a specific node is impossible and faultsare injected randomly. Hence this method is not suitable todetermine less reliable points of a design. An alternativesolution is simulating the fault injection using circuit-levelsimulation tools like HSPICE [2]. In this method a randomfault is injected and propagated to outputs using HSPICEsimulation. The benefits of this method are control overinjection nodes and applicability in the design stage. Akey problem with this method is its evaluation time. Asfor lots of nodes in a large circuit such as a processor,at least thousands of faults should be injected to calculateSER correctly. Last but not least, many efforts have beentaken in with the intention of modeling the generation andpropagation of soft errors [27, 36]. Error propagation usingthis method seems to be fast and yet accurate. It also has thecontrollability and in design applicability benefits.

As shown in Fig. 1, in this paper, we present two methodsfor the propagation of injected soft errors in near thresholdcombinational circuits using neural networks. A neural net-work is an information processing system inspired by study-ing human brain in learning from observation and general-izing according to the concept[22]. In the first method, each

gate in the library is modeled with an MLP neural net-work. The inputs of this MLP model consist of two parts:input SET samples and the gate’s parameters including itssource voltage and output fanout. This model is trainedusing the above-mentioned inputs and expected outputsextracted using HSPICE simulation. Each sample set isformed using error propagation simulation with differentenergies by varying the source voltage and fanout of thegate. In Section 5 the parameters required for obtainingtraining datasets are explained in detail. After training amodel for each gate in a library, to calculate the output ofeach node in a synthesized circuit using this library, eachgate is replaced by a trained model and the error is propa-gated to the desired node faster than HSPICE and with highaccuracy. In order to increase the precision of calculating theoutput of the first method, in the second method, modelingof complex gates in the library was performed using RNNs.In this model only one sample of the output is calculatedin each step. The input of each neural network includes thesource voltage, fanout, the next input sample and the pre-vious outputs calculated by the model. Using RNN modelsin error propagation modeling reduces errors of calculatedoutput by up to 13%.

In summary, fault propagation for calculating accurateSER of combinational circuits in near threshold is timeconsuming. In this paper, using neural networks, weproposed a model to calculate the SET about 10-20X fasterwith almost 100% accuracy for SER calculation. Our maincontributions in this paper are summarized as follow:

– Modeling fault propagation for calculating SER in nearthreshold.

– Improving calculation time using different neuralnetworks structure for each gate type.

– Using an MLP neural network to initialize first states ofRNN to improve accuracy.

The remainder of this paper is organized as follows.Section 2 explains various architectures of neural networks

Fig. 1 Overview of using our models to calculate SER

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used in this paper and provides a detailed background.Section 3 reviews related works. Sections 4 and 5 describeour neural network structure and training and evaluationprocedure for each model structure. In Section 6, we eval-uate the performance of our modeling and its effectivenessby propagating injected faults and calculating SER in differ-ent adder architectures. Finally, 7 states our conclusion anddirection for future work.

2 Preliminaries

As stated in Section 1, modeling is a fast and accuratemeans for calculating SER. Modeling is representing acomplex nonlinear function with a less complex one witha reasonable decrease of accuracy. Neural networks arepromising candidates for modeling nonlinear functions [32].Universal approximation theorem states that using an MLPstructure with three hidden layers we can approximateany multi-dimensional continuous function with arbitraryprecision [5].

An MLP is a feed forward artificial neural network.It consists of at least three layers of nodes. Aside fromthe input nodes, each node uses a nonlinear activationfunction. For training, MLP uses back propagation as asupervised learning technique. Because of its multiple non-linear activation layers, it can model data that are notlinearly separable. Each neuron in the network receives oneor more weighted inputs and a bias and pass their sumthrough its activation function. All weights and biases in thenetwork are calculated during the learning phase. Supposethe weights and bias vectors of the neuron layer is W =[w11, · · · , wNL2NL1

] , B = [b1, · · · , bNL2], respectively.

So, the input of each activation function is as the Eq. 1

γj (n) =⎛⎝

Nk∑i=1

xi(n)wji + bj

⎞⎠ (1)

where γj (n) is the input of activation function of j th neuronand Nk is the number neurons in the (j − 1)th layer, so wehave

Zij = σ(γj (n)) j = 1, · · · , NL2 (2)

Where σ(.) is the activation function and i is the levelof the layer. Activation functions are often monotonicallyincreasing, continuous, differentiable and bounded that actsas a relay for their inputs.

Another architecture of neural network is RNN thatseems to be more accurate than MLPs for modelingelectrical waveforms [11]. An RNN is a neural networkthat contains at least one feed-back connection, so theactivations can flow round in a loop. This allows it to exhibitdynamic temporal behavior for a time sequence. Unlike

feedforward neural networks, RNNs has internal memory(state) so it is able to process sequence of inputs. The outputof a simple neuron layers in RNN structure is the same asMLP (2).

To evaluate the quality of the model, we use integralsof the square of the error over time (ISE). Assume thatf : x(t) → y(t) is a bounded nonlinear function andf : x(t) → y(t) is the modeling of the function f . Qualityof this model in any arbitrary period [T1, T2] is defined asEq. 3:∫ T2

T1

||y(t) − y(t)||2dt (3)

in which ||.|| shows l2 norm. Values close to zero for ISEare associated with better overall model.

The aim of this study is to model the soft error signal andits propagation to outputs. A typical fault caused by an alphaparticle is a waveform expressed by the Eq. 4

Q

τf − τr

(e− t

τf − e− t

τr

)(4)

where Q is the total collected charge, t is the time, and τf

and τr are two features of the current peak named rising timeand falling time, respectively [35]. Figure 2 shows a samplealpha particle induced soft error waveform. So far the mostagreed model to simulate the actual charge deposition of aparticle strike uses double exponential currents [19], so weuse it for our analysis.

To analyze SER, we should propagate SETs anddetermine if they reach one of the circuit outputs. A transienterror in a logic circuit might not reach circuit’s outputsbecause it may be masked by one of the following threeevents [31]:

– Logical mask: Logical mask occurs when the faultis blocked from reaching the output because its sub-sequent gate’s output is determined completely by itsother input value.

Fig. 2 Example of a double-exponential pulse (τr = 8ps, τf = 5ps )

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– Electrical mask: Electrical masking occurs when afault attenuates by subsequent gates due to electricalproperties of the gate to where it doesn’t affect the resultof the circuit. Figure. 3 shows an example of electricalmasking. As shown the pulse is not latched due toattenuation in propagation.

– Latching window mask: Latching window maskoccurs when the pulse resulting from a particle reachesa latch but not at the clock transition when the latchcaptures its input value.

3 RelatedWork

Considerable research efforts have been conducted inthe context of modeling fault propagation and estimat-ing SER in combinational circuits. Rao et al. [29] useWeibull function to represent current generated waveformat each node. With technology and voltage scaling, espe-cially in near-threshold region, the output of CMOS gatesbecome more nonlinear. One of the drawbacks of thiswork is that by increasing the nonlinearity, the accu-racy of the fitting to Weibull function may decrease.Several studies have been conducted on estimating SERusing simulation based methods. An RTL-based combina-tional SER estimation method was proposed in [10] in orderto achieve fast RTL level SER analysis. Compared withRTL level SER analysis, circuit-level SER estimation ismore accurate. FASTER [36] uses binary decision diagramswith circuit partitioning and probability theory for SER esti-mation. In this paper, a trapezoidal model is chosen forpropagation, and the fall and rise times are calculated usingsimple low pass characteristics. As stated above, in the near-threshold region, the nonlinearity of the output of CMOSgates increases. Due to the use of a simple model for faultpropagation, the error in the near-threshold region increases.SEAT-LA [27] presented a SER estimation frameworkwhich characterizes the SET parametric waveform and anycells in the library. Soft error propagation is implementedusing simple analytical equations. One of the major draw-backs of this method is its simple analytical equations. Withtechnology and voltage scaling, analytical equations are too

Fig. 3 Example of electrical masking

complex to use for propagation. A hierarchical approachcalled HSEET was developed in [28], which improved thespeed of the SER estimation process in structural com-binational logic using pre-characterized block for currentgenerations and propagates through the gates using propaga-tion blocks and probability theory. Multi-cycle effects wereconsidered in [16], which accounted for those SETs lastingmore than one clock cycle. Miskov-Zivanov andMarculescu[25] proposed the MARS-C tool. This tool simultaneouslymodel the three derating factors using combination of BDDsand algebraic decision diagrams. The authors claim thatfor accurate results, consideration of the three derating fac-tors at the same time is essential. They present results forseveral small circuits. More recent work [34] consideredprocess variation by extending previous platforms. Authorsin [15] proposed statistical models for the transient pulsesand using transformations in the probability distributionfunctions, modeled the propagation of soft error to outputsof the circuit.

These prior works have established circuit-level SERestimation frameworks that target high accuracy, however,their efforts on speed improvement are limited to circuitpartitioning and parallel processing. Typical waveformmodeling with various functions and analytical equa-tions[27] are simple but can not be used with the complexityof voltage and technology scaling. Using them will increasethe complexity. Using pre-characterized model with lookuptable [25, 28] needs high memory to contain all the tablesin propagating fault. Also, to the best of our knowledge,no paper is published to directly provide models for cal-culating SER of combinational circuits in near-thresholdregion.

4 ProposedModel Structure

The proposed model can be used to propagate the SET froman arbitrary node to one of circuit’s saving elements in anycombinational circuit . In our proposed model we use neuralnetworks to propagate SET through circuit elements to itsoutputs. As stated in Section 2, an MLP structure can beused to approximate any multi-dimensional function and itis one of the most legitimate ways to model a nonlinearfunction such as circuit elements.

4.1 MLP Structure

The structure of the MLP neural network used in this paperis shown in Fig. 4. MLP utilizes a supervised learningtechnique called back propagation for training. We trainan MLP network to model a SET propagation through aspecific gate. This MLP network consists of three layersnamely input, hidden, and output layers.

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Fig. 4 A typical MLP structure

4.1.1 Input layer

The first layer of the proposed neural network is input layerthat is composed of two parts: waveform inputs and gateparameters.

The network’s waveform inputs are the sampled versionof SET signal. Since the inputs of a neural networkare discrete-time, a sampling process is required beforeapplying the SET signal to the network.

So the waveform inputs are defined by the Eq. 5

x [n] = x (nTs) (5)

where n indicates time in the discrete time domain and Ts isthe sampling interval.

Gate parameters are the modeled gate’s characteristicsthat slightly affect SET propagation to the output. Sourcevoltage and gate load are the most effective parameters. Indigital circuits, the gate load mainly depends on the gatefan-out. So to consider the gate load effect, the normalizedvalue of fan-out is considered as one of the network inputparameters. To avoid the complexity in training the neuralnetwork, we have considered 10 different possible fan-out in our training phase. This covers all digital circuitswe examined in this work but if a circuit has fan-out farfrom this range, a new training dataset is needed to avoiddecreases in model accuracy. To model propagation forcircuits with higher fanouts, we should repeat the followingsteps: 1 Create a dataset including the fanout 2 Train themodel with the given dataset 3 Use the trained model formodeling the propagation of faults in the circuit. The sourcevoltage is another important parameter in SET propagation.In 45nm technology, near-threshold voltage is between 400to 500 mV [7]. Simulation shows that changing the supplyvoltage in this region has a small effect on the output ofthe gate. So, we considered 5 equally distanced voltages

for the voltage parameter. Due to characteristic of activationfunction, each parameter is normalized to a value between 0and 1 before applying to the network.

The output of the first layer is as follows:

ZL1i =

{x(n − k) 0 � k < Kx

Pk 0 � k < Kp(6)

where Kx is the number of waveform inputs, Kp is the

number of gate parameters andZL1i is the output of the i−th

neuron in the first layer.

4.1.2 Hidden layer

The hidden layer (y − layer) is the core of the entirenetwork. Because of its activation function, the network’sability of modeling is closely related to the design ofthis layer. The activation function of the hidden layerhas been chosen as the sigmoid transfer function. Ingeneral, the sigmoid function is real-valued, monotonic,and differentiable. It has a non-negative bell-shaped firstderivative. A sigmoid function is constrained by a pair ofhorizontal asymptotes as x → ±∞. Common functions arelogistic, hyperbolic, arctangent, etc. (Fig. 5).

4.1.3 Output layer

The last layer is the output layer. The output of this layer isa linear combination of y − layer outputs. The output of thenetwork can be expressed as Eq. 7.

yi (n) = g(x1(n), . . . , xKx (n), p1, p2) i = 1 . . . Ky (7)

where n indicates time in the discrete time domain, Kx andKy are the number of inputs and outputs respectively, p1 andp2 are the gate parameters, yi is the outputs of our networkand g is our neural network model. Using this model we canpropagate an injected SET to any nodes of the circuit andcalculate SER. One of the drawbacks to use this structure isin more complex gates, e.g.XOR, the output error increases(Table 1) Also, in a few cases, due to an increase in error, theconnection between the output samples are completely lost.

To prevent these errors in our propagation model weproposed an RNN model for more complex gates.

4.2 RNN Structure

RNNs are neural networks with feedback from outputs toinputs. The proposed RNN structure is shown in Fig. 6.Like MLP structure, the proposed RNN structure is a three-layer neural network: input, hidden, and output layer. Theinput layer of this structure is composed of three parts: Kx

samples of input,Ky samples of output and gate parameters.As stated in Section 2, RNNs have memory to maintain theoutputs of the previous steps and is used as input to the

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Fig. 5 Sigmoid activationfunction

network. Ky is the number of stored outputs. The output ofthis layer (x − layer) is as follows:

ZL1i =

⎧⎨⎩

y(n − k) 1 � k � Ky

x(n − k) 0 � k < Kx

Pn 1 � n � Kp

i = 1 . . . (Kx + Ky + 1) (8)

where ZL1i is the output of ith neuron in this layer. Hidden

layer and output layers of this structure are the same asMLP structure with difference in number of neurons in eachlayer. Because in this structure only one sample is calculatedat a time, the output layer has one neuron that calculatesa linear combination of y − layer’s outputs. To propagatea SET using this model, all samples should be calculatedone after the other. Using this model will increase thepropagation calculation time. But on the other hand, gate’spropagation error will decrease especially in complicatedgates. Moreover, because of RNN’s state, the connectionbetween the output samples are preserved.

The number of input and output buffers affect precisionand delay of RNN networks. Also, the sum of these delays(Kx + Ky) defines network degree. To completely modelthe dynamic behavior of a gate with RNN, network degreeshould be more than gate degree. However, according to[33] with a less neural degree the behavior is modeledcorrectly. To model propagation behavior of gates we usedthe same buffer size for inputs and outputs (Kx = Ky).

Table 1 Error of sample gates using MLP structure

Gate Error

AND 2.9%

OR 3.7%

XOR 6.4%

5 Training the ProposedModel

We have proposed neural network-based models that sim-ulate SET propagation through gates. To use these models,we have to train the model first. Training the neural net-work is adjusting the values of the connection weightsand biases between its layers . To train a neural networkthree datasets are needed: train, validation and test set. Thetraining dataset consists of pairs of an input signal and thecorresponding output signal. The output of the model iscompared with the training dataset for each input vector inthe training dataset. Model parameters are adjusted accord-ing to the comparison result and the learning algorithm. Toestimate how well our model has been trained and estimatemodel properties, we use validation and test datasets. Toselect the best performing approach at each step, weuse the validation dataset and to estimate the accuracyof the selected approach we use the test dataset. Theadvantage of validation/test datasets are their invisibility tothe model during the training phase.

All datasets are generated using HSPICE simulationresults. For this reason we simulated the propagation of SETwith different levels of energy in a chain of gates e.g AND(Fig. 7) using Hspice. The minimum and maximum boundsof particles energy have been reported in [12], upon which,all parameters have been sweeped for investigating allpossible combinations of injected pulses. The input signal,output, and all intermediate signals are used to generatetraining datasets.

Before we can use these datasets to train the neuralnetwork, a pre-processing step is required. The form of pre-processing applied to the data is a very important factor indetermining the success of a practical application of neuralnetworks [3]. Our pre-processing has two stages: specifyingthe signal section required for training (sampling range) anddetermining the number of samples. The details of thesestages are described in the following sections.

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Fig. 6 A typical RNN structure

5.1 Sampling Range

The selection of samples is very important to provide thelargest range of information to build the dataset. In SETpropagation when a gate is derived with the fault signal,its output will be ready after the gate delay (Td ). Input andoutput of an AND gate propagation is shown in Fig. 8. Inthe sampling, the gate delay is ignored and only the mainpart of the signal is processed. In other words, the signalis not sampled when it is not present on the gates output.The transient part of the signal is only sampled and delayof each gate is not considered. This range selection has thefollowing benefits:

– Selecting samples from the main signal portionincreases the sampling accuracy and hence requiresfewer samples.

– Reducing the number of samples reduces number ofnetwork’s inputs and outputs that results in a smallertraining dataset.

– An additional module is not required to add the gate’sdelay to the output signal to use for fault propagation ina circuit.

Using this method, the gate delay is not calculated usingthe network. According to the above, this reduces thecomplexity of the neural network. A cutoff level is used toobtain the main signal portion and remove the delay. Thepart of the signal is above this level will be sampled and

used as the input of the network. Moreover, to calculatethe error propagation in the inverting gates, we use theinverted version of output. Each sample of inverted versionis calculated using x = −x + Vdd where x is the invertedoutput and Vdd is the source voltage.

In the SET propagation, delays play an important role incalculating the window latching mask. Delays are calculatedusing HSPICE simulation for all gates and all fan-outs.To calculate the total delay, delays of all the gates in thepath from the injection point to the calculation point isconsidered.

5.2 Number of Samples

As shown in Table 2 increasing the number of samplingpoints enhances the accuracy of the model up to a certainextent where further increment in sampling points leadsto accuracy reduction. This occurs because of the factthat as the number of samples is incremented, the numberof neurons are also increased which in turn results inaugmented network error. In other words, the number ofsampling points has been selected based on a trade-offbetween the sampling error and network error. In our modelwe use 50 points for sampling which gives the highestaccuracy.

Using these steps, we prepared the dataset required fornetwork training. We used the Python libraries tflearn [6]and tensorflow [1] to train the neural network models

Fig. 7 A sample chain gate simulated using Hspice to generate training datasets

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Fig. 8 Sample input and output fault signal calculated using HSPICEsimulation

and used numpy [26] and scipy [17] for the numericaldata structures and algorithms. Tensorflow is an open-source software library developed by Google brain teamfor machine learning in various projects. It is a symbolicmath library, and also used as a system for buildingand training neural networks to detect and decipherpatterns and correlations, analogous to human learning andreasoning [23]. Ability to run on multiple CPUs and GPUs(with optional CUDA extensions) is one of TensorFlow’sadvantages [1]. TFlearn is a modular and transparent deeplearning library built on top of Tensorflow. It has beendesigned to provide a higher-level API to TensorFlowin order to facilitate and speed-up experiments whileremaining fully transparent and compatible with it.

A loss function is a measure of how good the modelingis in terms of being able to model the expected output.Training is a minimization of the loss function f . Thisfunction that depends on the adaptive parameters (biasesand synaptic weights) evaluate how a neural network fitsthe dataset and on the other hand, prevent overfitting bycontrolling the effective complexity of the neural network[14]. Overfitting occurs when the model is over-optimizedto accurately predict the training dataset at the expenseof generalizing to unknown data. We use MSE (MeanSquare Error) as loss function. The error is defined as

Table 2 Effect of number of samples on proposed model accuracy

Number of Samples Propagation error

20 7%

30 6.5%

50 5.3%

70 5.4%

100 6.5%

the difference between the output of our neural modeland the estimated output calculated by the HSPICE. Theloss function measures the average of the squares of theerrors. The MSE is a measure of quality and valuescloser to zero are better. To update network weights, weuse Adam optimization algorithm. In this algorithm, thelearning rates are adopted based on the average of thefirst and second moments of the gradients. Specifically, thealgorithm calculates an exponential moving average of thegradient and the square gradient. Figure 9 shows a sampleoutput of AND gate from neural model and HSPICE. Theerrors and the simulation time of both HSPICE and ourmodel are reported in Table 3.

In RNN model, the dataset for training is generated asexpressed in the MLP model. In RNNs, the output of eachstage depends on its inputs and the state of the network soto train a waveform, all datasets should be applied one afterthe other. Network states must be initialized before applyingnew data waveform.

Initial states of the model are first Ky samples of output.Because the initial states of each SET are close to zero(Fig. 9), these states can be considered zero in training a newSET. This initial value causes an error in first output sam-ples of the model. To decrease this error, we proposed anMLP neural network to obtain the initial values of the RNNnetwork. The structure of this MLP network is similar to theone already mentioned (Fig. 4) and has three layers: inputand output layers with 3 neurons and hidden layer withfive neurons with Sigmoid activation function. The inputs ofthis network are three primary samples of the SET and theoutputs are initial states of the RNN network. To train thisnetwork, we used a dataset consists of the first three samplesof SET and three samples of the propagated output com-puted using HSPICE. Using this network, the calculationerror of the RNN model is reduced by an average of 1%.

Fig. 9 Runtime and accuracy comparison, proposed method vsHSPICE

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Table 3 Comparison between our model and HSPICE at runtime andaccuracy

HSPICE simulation Proposed model Error

time (s) simulation time (s)

AND Gate 0.21 3.91e−4 3.8 %

OR Gate 0.17 3.96e−4 4.1 %

XOR Gate 0.28 3.4e−3 4.6 %

6 Results and Analysis

As mentioned, in this paper, two methods are proposed forSET propagation. In the first method, all gates are modeledusing MLP networks (MLP method). In order to improvethe propagation error of this method, in the second method(Hybrid method) RNN networks are used to model complexgates. In this section, we show the validation results forour propagating model and SER estimation method fromthree aspects: propagation accuracy, speed up, and SERestimation performance. The experiment was performed ona machine with an Intel i7-5500 running at 2.4 GHz with 12GB of RAM.

6.1 Propagation Accuracy

In order to assess our model accuracy, we examined SETpropagation in three different adder structures: ripple carryadder (RCA), carry-lookahead adder (CLA) and carry-select adder (CSA) with 1 to 16 bits inputs. These adderswere designed in 45nm technology and operate in near-threshold voltage. Approximately 100 SETs with differentenergy levels have been injected to each node of theseadders. Each SET is propagated using the HSPICE andour model to the circuit outputs. For an injected SET toreach one of the outputs without being logically masked,proper inputs are calculated using Atalanta-M automatic testpattern generation tool [21]. The MSE of our model outputis used as a mean to show its accuracy. Table 4 provides theresults of calculating the average MSE of all injections. It

Table 4 SET propagation error for each model

RCA CLA CSA

Hybrid MLP Hybrid MLP Hybrid MLP

1-bit 3.2% 4.1% 3.7% 4.2% 4.5% 5.1%

2-bit 4.3% 4.9% 4.5% 5.8% 5.8% 6.9%

4-bit 5.56% 8.9% 5.31% 6.7% 6.87% 10.1%

8-bit 5.7% 14.2% 5.4% 11.3% 6.91% 14.2%

16-bit 5.8% 17.8% 5.5% 13.6% 7.1% 19.8%

is apparent from this table that using our methods, outputsestimation in different designs have an average error of15.2% with MLP method and 6% with Hybrid method.What is interesting in these data is that the error of circuitswith the same critical path are almost identical. This canbe seen in the case of 4-bit RCA adder and 16-bit CLAadder (Table 4) where they have the same critical path andmodeling error.

6.2 Speed Up

An initial objective of the proposed models was to decreasesimulation time. Figure 10 compares the mean simulationtime for propagating SETs to an output of examined addersusing Hspice and our methods. From this figure, we cansee that using our hybrid method compared with HSPICE,fault propagation simulation is 12 times faster on average.From the graph we can see that compared with HSPICE,the simulation speed increases with increasing number ofcircuit gates. This is due to the fact that in the simulationof SET propagation using the proposed model, the errorpropagation in each gate is investigated individually butHSPICE simulation time seems to increase exponentially byincreasing the number of gates. From the Fig. 11 we cansee that using MLP model for all gates leads to significantspeed up in SET propagation. However, due to the high errorrate of this method (Table 4), the use of RNN method isinevitable.

6.3 SER Estimation Performancce

To calculate the SER, SETs are injected at all nodes andconsidering the effect of all the masks, their reach to theoutput are examined. To do this, we should include all themasks influences simultaneously, but in this level, to avoidthe complexity of logical masking, primary inputs value are

Fig. 10 Calculation time comparison between HSPICE and our model

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Fig. 11 Calculation time comparison between Hybrid model and MLPmodel

calculated (using Atalanta-M) in such a way that a faultcan reach the output without being logically masked. Let’sconsider an ideal latch to illustrate the effect of the windowmask on the proposed model’s performance. In this latch,if its input is less than its threshold voltage at the edge ofthe clock, its output will become 0, otherwise, its outputwill become 1. Therefore, in our model, SER estimationperformance depends on the output value calculated at theclock edge. In Fig. 12, a fault propagated to the input ofa latch located at the output of a 4-bit adder using Hspiceand our model is shown at the same time. In this figure, y0is the threshold level of the latch, and x0 and x1 representsthe hypothetical rising edges of the clock. As shown in thefigure, at the edge of the clock at x0, the sampled value ofthe HSPICE output is 1, but the sampled value output of theproposed model is 0. In this case, although according toHSPICE simulation, SET should be latched to the flip-flop,

Fig. 12 False positive and false negative in calculating latchingwindow mask

the proposed model does not generate any latched pulse.This results in what we call ”false negative” in SERestimation. On the other hand, at the edge of the clock at x1,our model results in a latched SET in opposition to HSPICEsimulation. This will result in a ”false positive” error.

To illustrate the model’s efficiency in estimating SER,filp-flops(FFs) are used at every output of the addersreviewed, with 1GHz clock speed. Approximately 200 SETwith different energies and random injection time wereinjected at each node. Using the hybrid model, SET at theinput of each FF is calculated accurately by considering theproduced input patterns by Atalanta-M and the calculatedpath delay using the method described. Finally, the FFoutput is computed using its threshold and compared withthe value obtained from the Hspice simulation. Table 5shows the difference in the number of soft errors calculatedusing simulation with the proposed model and HSPICE. Asshown in this table, among about 140000 SETs injectionsonly the output of 19 injected SETs calculated using theproposed model differs from Hspice’s output. This showsthat using the proposed model, the SER of a circuit workingin NTC can be calculated with near to 100 confidence.

According to [30], the increase in frequency, linearly,increases the soft error rate. In the proposed model, theinjection and fault propagation in the combinational circuitare frequency independent. When the fault reaches a flipflop at a rising edge of the clock, utilizing SET width, setupand hold time of the flip-flop, the output of the flip-flopis calculated. The effect of frequency increasing takes intoaccount at this point This is due to the fact that, as clockfrequency increases, the probability of latching the error willincrease.

As shown in these results, our modeling is a fastand highly accurate method for calculating SER incombinational circuits. Our method represents an innovativeand 10X - 20X faster alternative to HSPICE simulation.It is plausible that a number of limitations may haveinfluenced the results obtained. First, in the proposed model,reconvergent fan-out has not been investigated. To considerreconvergent fan-out in simulations, a look-up table is usedto get the gate output. Another possible source of error isthat at this point a complete framework for SER calculationis not available.

Table 5 The difference between the number of soft errors in theproposed model and HSPICE

Faults Num. False pos. False neg. Sum

RCA 31000 2 3 5

CLA 52600 3 4 7

CSA 61500 4 3 7

J Electron Test (2019) 35:401–412 411

7 Conclusion and FutureWork

In this paper, we introduce a neural network based modelfor calculating SER in near-threshold circuits. The results ofthis study indicate that using the proposed model, the softerror can be calculated up to 20 times faster with approx-imately the same precision as HSPICE. Our work clearlyhas some limitations. Nevertheless, we believe that our workcan be a starting point for a fast and accurate framework forcalculating the soft error in digital circuits. Results so farhave been very promising and this approach has the abilityto be used in a complete framework to calculate the SERand identifying vulnerable nodes in a digital circuits. Forfurther research, we intend to implement reconvergent fan-outs in the proposed model. On a wider level, future studieson the current topic are therefore required to obtain a frame-work for calculating SER using the proposed model for anyarbitrary digital circuit.

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Saeed Safari received his Ph.D. degree in Computer Architecture fromComputer Engineering Department, Sharif University of Technology,Tehran, Iran, in 2005. Since then, he has been a faculty memberof Electrical and Computer Engineering Department, Universityof Tehran, Tehran, Iran. From May 2009 to September 2010, hecollaborated with Tele Robotics and Applications (TERA) Lab.,IIT, Genoa, Italy, working on different aspects of low-powerparallel implementation of machine vision applications. His researchinterests are Artificial Intelligence, High Performance Computing, andComputer Architecture.

Ali Hajian received his M.Sc. degree in Electronics from ElectricalEngineering Department, Sharif University of Technology, Tehran,Iran, in 2006. He is currently working on his Ph.D. degree in ElectricalEnginering at University of Tehran, Tehran, Iran. His research interestsinclude VLSI systems and digital design, neural networks, and lowpower circuit design.