Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Topics

Design methodologies. Kitchen timer example.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Design methodologies

Every company has its own design methodology.

Methodology depends on:– size of chip;– design time constraints;– cost/performance;– available tools.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Generic design flow

architecturalsimulation

floorplan

register-transferdesign

logicdesign

circuitdesign

layout

functional/performanceverification

testability

detailedspecs

tapeout

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Specification and planning

Driven by contradictory impulses:– customer-centric concerns about cost,

performance, etc.;– forecasts of feasibility of cost and performance.

Features, performance, power, etc. may be negotiated at early stages; negotiation at later stages creates problems.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Estimation and planning

Estimation techniques vary with module:– memories may be generated once size is

known;– data paths may be estimated from previous

design;– controllers are hard to estimate without details.

Estimates must include speed, area, power.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Floorplanning and budgeting

The purpose of early floorplanning is to establish budgets for each major component: area, delay, power, etc.

The project leader must ensure that budgets are met at all times. If it becomes clear that meeting a budget for a component is impossible, the floorplan must be redone ASAP.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Logic design

For controllers, good state assignment is usually requires CAD tools.

Logic synthesis is an option:– very good for non-critical logic;– can work well for speed-critical logic.

Logic synthesis system may be sensitive to changes in the input specification.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Circuit/layout design

Tasks:– size transistors;– draw layout.

Alternative design styles:– full custom logic (very tedious);– standard cell.

Full custom most likely for datapaths, least likely for random logic off critical path.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Design validation

Must verify:– layout (design rule check = DRC);– circuit performance;– clock distribution;– functionality;– power consumption / power bussing.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Testing

Automatic test pattern generation = ATPG. Must verify that circuit can be tested,

generate a compact set of manufacturing test vectors.

Test vectors often comprised of vectors taken from simulation + ATPG-generated vectors.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Tapeout

Tapeout: generating final files for masks. Shipped to mask-making house.

Pre-tapeout verification is importance since it will take months to get results from fab.

Tapeout party follows. Size of party depends on importance of chip design project.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Kitchen timer chip

Simple example which illustrates overall design process.

Kitchen timer keeps two independent timers:– set minutes, seconds.– go, clear;

Not performance-sensitive; is power-sensitive.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Kitchen timer system

timerchip

timer 1 timer 2 go

minutes seconds clear

seconds

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Timer chip architecture sketch

buttons

enable

segmentsbuzzer

controller

timer 1 timer 1buzz display

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Functional simulator

Given in Appendix C. Operates in event-driven style:

– seconds clock;– button depressions.

Provides basic functional verification, allows exercising major architectural components.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Major design decisions

Use binary-coded decimal (BCD) to represent times:– allows direct display of timer register values;– requires a few more registers than binary, but

BCD/7-segment decoder is much smaller than binary/7-segment decoder.

Use scanned display—send only one digit at a time to display to reduce wiring between components.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Kitchen timer component hierarchy

timer chip

controller buzz timers display

timer 1 timer 2

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Component inventory

Timers: Holds time in register; can increment, decrement, clear. – Inputs: incr_seconds[2], incr_minutes[2],

seconds, go[2], digit_select[2], timer.– Outputs: done, digit[4].

Display: Cycles through displayed digits.– Inputs: digit[4].– Outputs: digit_select[2], enable[4], segments[7].

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Component inventory (cont’d)

Buzz: Enables buzz signal until stop.– Inputs: done, stop. Outputs: buzz.

Controller: Generates all required control signals.– Inputs: timer_1, timer_2, minutes_in,

seconds_in, clear_in, go_in.– Outputs: timer_select, incr_minutes, go, clear,

output_select.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Component size estimates

One timer: 14 latches and about 30 gates. Timers: 28 latches and 70 gates. Display: 4 latches and about 15 gates. Buzz: 2 latches and 2 gates. Controller: 8 latches and 20 gates.

Modern VLSI Design 3e: Chapter 9 Copyright 1998, 2002 Prentice Hall PTR

Kitchen timer initial floorplan

timers

display

controller

buzz

4

4

4

1

4

7

1