mpc 5606 brm

MPC5606BK MicrocontrollerReference Manual

Devices Supported:

MPC5606BKRMRev. 2

05/2014

MPC5606BKMPC5605BK

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MPC5606BK Microcontroller Reference Manual, Rev. 2

Freescale Semiconductor 3

Chapter 1Preface

1.1 Overview .........................................................................................................................................211.2 Audience ..........................................................................................................................................211.3 Guide to this reference manual ........................................................................................................211.4 Register description conventions ....................................................................................................251.5 References .......................................................................................................................................261.6 How to use the MPC5606BK documents .......................................................................................26

1.6.1 The MPC5606BK document set .....................................................................................261.6.2 Reference manual content ..............................................................................................27

1.7 Using the MPC5606BK ..................................................................................................................281.7.1 Hardware design .............................................................................................................281.7.2 Input/output pins .............................................................................................................291.7.3 Software design ..............................................................................................................291.7.4 Other features .................................................................................................................30

Chapter 2Introduction

2.1 The MPC5606BK microcontroller family ......................................................................................312.2 MPC5606BK device comparison ....................................................................................................312.3 Device block diagram ......................................................................................................................322.4 Feature details .................................................................................................................................35

2.4.1 e200z0h core processor ..................................................................................................352.4.2 Crossbar switch (XBAR) ................................................................................................352.4.3 Interrupt Controller (INTC) ............................................................................................352.4.4 System Integration Unit Lite (SIUL) ..............................................................................362.4.5 Flash memory .................................................................................................................362.4.6 SRAM .............................................................................................................................382.4.7 Memory Protection Unit (MPU) ....................................................................................382.4.8 Boot Assist Module (BAM) ...........................................................................................382.4.9 Enhanced Modular Input Output System (eMIOS) ........................................................392.4.10 Deserial Serial Peripheral Interface Module (DSPI) ......................................................402.4.11 Controller Area Network module (FlexCAN) ................................................................402.4.12 System clocks and clock generation ...............................................................................412.4.13 System timers .................................................................................................................422.4.14 System watchdog timer ..................................................................................................432.4.15 Inter-Integrated Circuit (I2C) module ............................................................................432.4.16 On-chip voltage regulator (VREG) ................................................................................432.4.17 Analog-to-Digital Converter (ADC) ..............................................................................442.4.18 Enhanced Direct Memory Access controller (eDMA) ...................................................452.4.19 Cross Trigger Unit (CTU) ..............................................................................................452.4.20 Serial communication interface module (LINFlex) .......................................................462.4.21 JTAG Controller (JTAGC) .............................................................................................47

2.5 Developer support ..........................................................................................................................47


4 Freescale Semiconductor

Chapter 3Memory Map

Chapter 4Signal description

4.1 Package pinouts ...............................................................................................................................534.2 Pin muxing ......................................................................................................................................55

Chapter 5Microcontroller Boot

5.1 Boot mechanism ..............................................................................................................................755.1.1 Flash memory boot .........................................................................................................765.1.2 Serial boot mode .............................................................................................................785.1.3 Censorship ......................................................................................................................78

5.2 Boot Assist Module (BAM) ............................................................................................................835.2.1 BAM software flow ........................................................................................................835.2.2 LINFlex (RS232) boot ....................................................................................................915.2.3 FlexCAN boot ................................................................................................................92

5.3 System Status and Configuration Module (SSCM) ........................................................................945.3.1 Introduction ....................................................................................................................945.3.2 Features ...........................................................................................................................945.3.3 Modes of operation .........................................................................................................955.3.4 Memory map and register description ............................................................................95

Chapter 6Clock Description

6.1 Clock architecture .........................................................................................................................1056.2 Clock gating ..................................................................................................................................1066.3 Fast external crystal oscillator (FXOSC) digital interface ............................................................107

6.3.1 Main features ................................................................................................................1076.3.2 Functional description ..................................................................................................1076.3.3 Register description ......................................................................................................108

6.4 Slow external crystal oscillator (SXOSC) digital interface ..........................................................1096.4.1 Introduction ..................................................................................................................1096.4.2 Main features ................................................................................................................1096.4.3 Functional description ..................................................................................................1096.4.4 Register description ......................................................................................................110

6.5 Slow internal RC oscillator (SIRC) digital interface ....................................................................1116.5.1 Introduction ..................................................................................................................1116.5.2 Functional description ..................................................................................................1126.5.3 Register description ......................................................................................................112

6.6 Fast internal RC oscillator (FIRC) digital interface ......................................................................1136.6.1 Introduction ..................................................................................................................1136.6.2 Functional description ..................................................................................................1136.6.3 Register description ......................................................................................................114



6.7 Frequency-modulated phase-locked loop (FMPLL) .....................................................................1156.7.1 Introduction ..................................................................................................................1156.7.2 Overview ......................................................................................................................1156.7.3 Features .........................................................................................................................1156.7.4 Memory map ................................................................................................................1166.7.5 Register description ......................................................................................................1166.7.6 Functional description ..................................................................................................1206.7.7 Recommendations ........................................................................................................122

6.8 Clock monitor unit (CMU) ............................................................................................................1236.8.1 Introduction ..................................................................................................................1236.8.2 Main features ................................................................................................................1236.8.3 Block diagram ..............................................................................................................1246.8.4 Functional description ..................................................................................................1246.8.5 Memory map and register description ..........................................................................126

Chapter 7Clock Generation Module (MC_CGM)

7.1 Overview .......................................................................................................................................1317.2 Features .........................................................................................................................................1327.3 Modes of operation ........................................................................................................................133

7.3.1 Normal and reset modes of operation ...........................................................................1337.4 External signal description ............................................................................................................1337.5 Memory map and register definition .............................................................................................133

7.5.1 Register descriptions ....................................................................................................1377.5.2 Output Clock Division Select Register (CGM_OCDS_SC) ........................................1387.5.3 System Clock Select Status Register (CGM_SC_SS) ..................................................139

7.6 Functional Description ..................................................................................................................1427.6.1 System Clock Generation .............................................................................................1427.6.2 Output Clock Multiplexing ...........................................................................................1437.6.3 Output Clock Division Selection ..................................................................................144

Chapter 8Mode Entry Module (MC_ME)

8.1 Overview .......................................................................................................................................1458.1.1 Features .........................................................................................................................1458.1.2 Modes of operation .......................................................................................................146

8.2 External signal description ............................................................................................................1478.3 Memory map and register definition .............................................................................................147

8.3.1 Register descriptions ....................................................................................................1508.4 Functional description ...................................................................................................................163

8.4.1 Mode transition request ................................................................................................1638.4.2 Modes details ................................................................................................................1648.4.3 Mode transition process ................................................................................................1678.4.4 Protection of mode configuration registers ..................................................................1758.4.5 Mode transition interrupts ............................................................................................175



8.4.6 Application example .....................................................................................................177

Chapter 9Reset Generation Module (MC_RGM)

9.1 Introduction ...................................................................................................................................1799.1.1 Overview ......................................................................................................................1799.1.2 Features .........................................................................................................................1809.1.3 Modes of operation .......................................................................................................181



9.4.1 Reset state machine ......................................................................................................1889.4.2 Destructive resets ..........................................................................................................1919.4.3 External reset ................................................................................................................1929.4.4 Functional resets ...........................................................................................................1929.4.5 Alternate event generation ............................................................................................1929.4.6 Boot mode capturing ....................................................................................................193

Chapter 10Power Control Unit (MC_PCU)

10.1 Introduction ...................................................................................................................................19510.1.1 Overview ......................................................................................................................19510.1.2 Features .........................................................................................................................19610.1.3 Modes of operation .......................................................................................................196



10.4.1 General .........................................................................................................................20210.4.2 Reset / Power-On Reset ................................................................................................20310.4.3 MC_PCU configuration ................................................................................................20310.4.4 Mode transitions ...........................................................................................................203

10.5 Initialization information ...............................................................................................................20510.6 Application information ................................................................................................................206

10.6.1 STANDBY Mode Considerations ................................................................................206

Chapter 11Voltage Regulators and Power Supplies

11.1 Voltage regulators ..........................................................................................................................20711.1.1 High power regulator (HPREG) ...................................................................................20711.1.2 Low power regulator (LPREG) ....................................................................................20711.1.3 Ultra low power regulator (ULPREG) .........................................................................20811.1.4 LVDs and POR .............................................................................................................20811.1.5 VREG digital interface .................................................................................................208



11.1.6 Register description ......................................................................................................20911.2 Power supply strategy ...................................................................................................................20911.3 Power domain organization ...........................................................................................................210

Chapter 12Wakeup Unit (WKPU)

12.1 Overview .......................................................................................................................................21312.2 Features .........................................................................................................................................21512.3 External signal description ............................................................................................................21612.4 Memory map and register description ...........................................................................................216

12.4.1 Memory map ................................................................................................................21612.4.2 NMI Status Flag Register (NSR) ..................................................................................21712.4.3 NMI Configuration Register (NCR) .............................................................................21812.4.4 Wakeup/Interrupt Status Flag Register (WISR) ...........................................................21912.4.5 Interrupt Request Enable Register (IRER) ...................................................................21912.4.6 Wakeup Request Enable Register (WRER) ..................................................................22012.4.7 Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) .............................22012.4.8 Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) .............................22112.4.9 Wakeup/Interrupt Filter Enable Register (WIFER) ......................................................22112.4.10 Wakeup/Interrupt Pullup Enable Register (WIPUER) .................................................222

12.5 Functional description ...................................................................................................................22212.5.1 General .........................................................................................................................22212.5.2 Non-maskable interrupts ..............................................................................................22312.5.3 External wakeups/interrupts .........................................................................................22412.5.4 On-chip wakeups ..........................................................................................................226

Chapter 13Real Time Clock / Autonomous Periodic Interrupt (RTC/API)

13.1 Overview .......................................................................................................................................22713.2 Features .........................................................................................................................................22713.3 Device-specific information ..........................................................................................................22913.4 Modes of operation ........................................................................................................................229

13.4.1 Functional mode ...........................................................................................................22913.4.2 Debug mode ..................................................................................................................230

13.5 Register descriptions .....................................................................................................................23013.5.1 RTC Supervisor Control Register (RTCSUPV) ...........................................................23013.5.2 RTC Control Register (RTCC) .....................................................................................23113.5.3 RTC Status Register (RTCS) ........................................................................................23313.5.4 RTC Counter Register (RTCCNT) ...............................................................................234

13.6 RTC functional description ...........................................................................................................23413.7 API functional description ............................................................................................................235

Chapter 14CAN Sampler

14.1 Introduction ...................................................................................................................................237



14.2 Main features .................................................................................................................................23714.3 Memory map and register description ...........................................................................................238

14.3.1 Control Register (CR) ...................................................................................................23814.3.2 CAN Sampler Sample Registers 011 ..........................................................................239

14.4 Functional description ...................................................................................................................23914.4.1 Enabling/disabling the CAN sampler ...........................................................................24014.4.2 Selecting the Rx port ....................................................................................................24014.4.3 Baud rate generation .....................................................................................................241

Chapter 15e200z0h Core

15.1 Overview .......................................................................................................................................24515.2 Microarchitecture summary ..........................................................................................................24515.3 Block diagram ...............................................................................................................................24715.4 Features .........................................................................................................................................247

15.4.1 Instruction unit features ................................................................................................24815.4.2 Integer unit features ......................................................................................................24815.4.3 Load/Store unit features ...............................................................................................24915.4.4 e200z0h system bus features ........................................................................................249

15.5 Core registers and programmers model .......................................................................................249

Chapter 16Enhanced Direct Memory Access (eDMA)

16.1 Device-specific features ................................................................................................................25316.2 Introduction ...................................................................................................................................253

16.2.1 Features .........................................................................................................................25416.3 Memory map and register definition .............................................................................................255

16.3.1 Memory map ................................................................................................................25516.3.2 Register descriptions ....................................................................................................257

16.4 Functional description ...................................................................................................................27816.4.1 eDMA basic data flow ..................................................................................................280

16.5 Initialization / application information ..........................................................................................28316.5.1 eDMA initialization ......................................................................................................28316.5.2 DMA programming errors ............................................................................................28516.5.3 DMA request assignments ............................................................................................28616.5.4 DMA arbitration mode considerations .........................................................................28616.5.5 DMA transfer ................................................................................................................28716.5.6 TCD status ....................................................................................................................29016.5.7 Channel linking ............................................................................................................29116.5.8 Dynamic programming .................................................................................................292

Chapter 17eDMA Channel Multiplexer (DMA_MUX)

17.1 Introduction ...................................................................................................................................29517.2 Features .........................................................................................................................................295



17.3 Modes of operation ........................................................................................................................29617.4 External signal description ............................................................................................................29617.5 Memory map and register definition .............................................................................................296

17.5.1 Channel configuration registers (CHCONFIGn) ..........................................................29717.6 DMA_MUX inputs .......................................................................................................................298

17.6.1 DMA_MUX peripheral sources ...................................................................................29817.6.2 DMA_MUX periodic trigger inputs .............................................................................300

17.7 Functional description ...................................................................................................................30017.7.1 eDMA channels with periodic triggering capability ....................................................30017.7.2 eDMA channels with no triggering capability .............................................................302

17.8 Initialization/Application information ...........................................................................................30317.8.1 Reset .............................................................................................................................30317.8.2 Enabling and configuring sources ................................................................................303

Chapter 18Interrupt Controller (INTC)

18.1 Introduction ...................................................................................................................................30718.2 Features .........................................................................................................................................30718.3 Block diagram ...............................................................................................................................30918.4 Modes of operation ........................................................................................................................309

18.4.1 Normal mode ................................................................................................................30918.5 Memory map and register description ...........................................................................................311

18.5.1 Module memory map ...................................................................................................31118.5.2 Register description ......................................................................................................311

18.6 Functional description ...................................................................................................................31918.6.1 Interrupt request sources ...............................................................................................32718.6.2 Priority management ....................................................................................................32818.6.3 Handshaking with processor .........................................................................................330

18.7 Initialization/application information ............................................................................................33218.7.1 Initialization flow .........................................................................................................33218.7.2 Interrupt exception handler ...........................................................................................33218.7.3 ISR, RTOS, and task hierarchy .....................................................................................33418.7.4 Order of execution ........................................................................................................33518.7.5 Priority ceiling protocol ................................................................................................33618.7.6 Selecting priorities according to request rates and deadlines .......................................33618.7.7 Software configurable interrupt requests ......................................................................33718.7.8 Lowering priority within an ISR ..................................................................................33818.7.9 Negating an interrupt request outside of its ISR ..........................................................33818.7.10 Examining LIFO contents ............................................................................................339

Chapter 19Crossbar Switch (XBAR)

19.1 Introduction ...................................................................................................................................34119.2 Block diagram ...............................................................................................................................34119.3 Overview .......................................................................................................................................342



19.4 Features .........................................................................................................................................34219.5 Modes of operation ........................................................................................................................342

19.5.1 Normal mode ................................................................................................................34219.5.2 Debug mode ..................................................................................................................342

19.6 Functional description ...................................................................................................................34219.6.1 Overview ......................................................................................................................34219.6.2 General operation .........................................................................................................34319.6.3 Master ports ..................................................................................................................34319.6.4 Slave ports ....................................................................................................................34419.6.5 Priority assignment .......................................................................................................34419.6.6 Arbitration ....................................................................................................................344

Chapter 20System Integration Unit Lite (SIUL)

20.1 Introduction ...................................................................................................................................34720.2 Overview .......................................................................................................................................34720.3 Features .........................................................................................................................................34920.4 External signal description ............................................................................................................349

20.4.1 Detailed signal descriptions ..........................................................................................35020.5 Memory map and register description ...........................................................................................351

20.5.1 SIUL memory map .......................................................................................................35120.5.2 Register protection ........................................................................................................35220.5.3 Register descriptions ....................................................................................................353

20.6 Functional description ...................................................................................................................37220.6.1 Pad control ....................................................................................................................37220.6.2 General purpose input and output pads (GPIO) ...........................................................37220.6.3 External interrupts ........................................................................................................373

20.7 Pin muxing ....................................................................................................................................374

Chapter 21Memory Protection Unit (MPU)

21.1 Introduction ...................................................................................................................................37521.2 Features .........................................................................................................................................37621.3 Modes of operation ........................................................................................................................37721.4 External signal description ............................................................................................................37721.5 Memory map and register description ...........................................................................................377

21.5.1 Memory map ................................................................................................................37821.5.2 Register description ......................................................................................................379

21.6 Functional description ...................................................................................................................39021.6.1 Access evaluation macro ..............................................................................................39021.6.2 Putting it all together and AHB error terminations ......................................................391

21.7 Initialization information ...............................................................................................................39221.8 Application information ................................................................................................................392



Chapter 22Inter-Integrated Circuit Bus Controller Module (I2C)

22.1 Introduction ...................................................................................................................................39722.1.1 Overview ......................................................................................................................39722.1.2 Features .........................................................................................................................39722.1.3 Block diagram ..............................................................................................................398

22.2 External signal description ............................................................................................................39822.2.1 SCL ...............................................................................................................................39822.2.2 SDA ..............................................................................................................................398

22.3 Memory map and register description ...........................................................................................39822.3.1 Module memory map ...................................................................................................39822.3.2 I2C Bus Address Register (IBAD) ...............................................................................39922.3.3 I2C Bus Frequency Divider Register (IBFD) ...............................................................40022.3.4 I2C Bus Control Register (IBCR) .................................................................................40622.3.5 I2C Bus Status Register (IBSR) ....................................................................................40722.3.6 I2C Bus Data I/O Register (IBDR) ...............................................................................40822.3.7 I2C Bus Interrupt Configuration Register (IBIC) .........................................................409

22.4 DMA Interface ..............................................................................................................................40922.5 Functional description ...................................................................................................................411

22.5.1 I-Bus protocol ...............................................................................................................41122.5.2 Interrupts .......................................................................................................................414

22.6 Initialization/application information ............................................................................................41522.6.1 I2C programming examples ..........................................................................................415

Chapter 23LIN Controller (LINFlex)

23.1 Introduction ...................................................................................................................................42123.2 Main features .................................................................................................................................421

23.2.1 LIN mode features ........................................................................................................42123.2.2 UART mode features ....................................................................................................42123.2.3 Features common to LIN and UART ...........................................................................421

23.3 General description .......................................................................................................................42223.4 Fractional baud rate generation .....................................................................................................42323.5 Operating modes ...........................................................................................................................425

23.5.1 Initialization mode ........................................................................................................42623.5.2 Normal mode ................................................................................................................42623.5.3 Low power mode (Sleep) .............................................................................................426

23.6 Test modes .....................................................................................................................................42623.6.1 Loop Back mode ...........................................................................................................42623.6.2 Self Test mode ..............................................................................................................427

23.7 Memory map and registers description .........................................................................................42723.7.1 Memory map ................................................................................................................427

23.8 Functional description ...................................................................................................................45323.8.1 UART mode ..................................................................................................................45323.8.2 LIN mode ......................................................................................................................455



23.8.3 8-bit timeout counter ....................................................................................................46323.8.4 Interrupts .......................................................................................................................465

Chapter 24LIN Controller (LINFlexD)

24.1 Introduction ...................................................................................................................................46724.2 Main features .................................................................................................................................467

24.2.1 LIN mode features ........................................................................................................46824.2.2 UART mode features ....................................................................................................468

24.3 The LIN protocol ...........................................................................................................................46924.3.1 Dominant and recessive logic levels ............................................................................46924.3.2 LIN frames ....................................................................................................................46924.3.3 LIN header ....................................................................................................................47024.3.4 Response .......................................................................................................................471

24.4 LINFlexD and software intervention ............................................................................................47224.5 Summary of operating modes .......................................................................................................47224.6 Controller-level operating modes ..................................................................................................473

24.6.1 Initialization mode ........................................................................................................47324.6.2 Normal mode ................................................................................................................47424.6.3 Sleep (low-power) mode ..............................................................................................474

24.7 LIN modes .....................................................................................................................................47424.7.1 Master mode .................................................................................................................47424.7.2 Slave mode ...................................................................................................................47624.7.3 Slave mode with identifier filtering ..............................................................................47824.7.4 Slave mode with automatic resynchronization .............................................................481

24.8 Test modes .....................................................................................................................................48224.8.1 Loop Back mode ...........................................................................................................48224.8.2 Self Test mode ..............................................................................................................483

24.9 UART mode ..................................................................................................................................48324.9.1 Data frame structure .....................................................................................................48324.9.2 Buffer ............................................................................................................................48524.9.3 UART transmitter .........................................................................................................48524.9.4 UART receiver ..............................................................................................................486

24.10 Memory map and register description ...........................................................................................48824.10.1 LIN control register 1 (LINCR1) .................................................................................48824.10.2 LIN interrupt enable register (LINIER) .......................................................................49124.10.3 LIN status register (LINSR) .........................................................................................49324.10.4 LIN error status register (LINESR) ..............................................................................49624.10.5 UART mode control register (UARTCR) .....................................................................49724.10.6 UART mode status register (UARTSR) .......................................................................50024.10.7 LIN timeout control status register (LINTCSR) ..........................................................50224.10.8 LIN output compare register (LINOCR) ......................................................................50324.10.9 LIN timeout control register (LINTOCR) ....................................................................50424.10.10 LIN fractional baud rate register (LINFBRR) ..............................................................50524.10.11 LIN integer baud rate register (LINIBRR) ...................................................................505



24.10.12 LIN checksum field register (LINCFR) .......................................................................50624.10.13 LIN control register 2 (LINCR2) .................................................................................50724.10.14 Buffer identifier register (BIDR) ..................................................................................50824.10.15 Buffer data register least significant (BDRL) ..............................................................50924.10.16 Buffer data register most significant (BDRM) .............................................................51024.10.17 Identifier filter enable register (IFER) ..........................................................................51124.10.18 Identifier filter match index (IFMI) ..............................................................................51224.10.19 Identifier filter mode register (IFMR) ..........................................................................51324.10.20 Identifier filter control registers (IFCR0IFCR15) ......................................................51324.10.21 Global control register (GCR) ......................................................................................51424.10.22 UART preset timeout register (UARTPTO) .................................................................51624.10.23 UART current timeout register (UARTCTO) ...............................................................51624.10.24 DMA Tx enable register (DMATXE) ...........................................................................51724.10.25 DMA Rx enable register (DMARXE) ..........................................................................518

24.11 DMA interface ...............................................................................................................................51824.11.1 Master node, TX mode .................................................................................................51924.11.2 Master node, RX mode .................................................................................................52224.11.3 Slave node, TX mode ...................................................................................................52424.11.4 Slave node, RX mode ...................................................................................................52724.11.5 UART node, TX mode .................................................................................................53024.11.6 UART node, RX mode .................................................................................................53224.11.7 Use cases and limitations ..............................................................................................535

24.12 Functional description ...................................................................................................................53624.12.1 8-bit timeout counter ....................................................................................................53624.12.2 Interrupts .......................................................................................................................53724.12.3 Fractional baud rate generation ....................................................................................539

24.13 Programming considerations .........................................................................................................54024.13.1 Master node ..................................................................................................................54024.13.2 Slave node ....................................................................................................................54124.13.3 Extended frames ...........................................................................................................54524.13.4 Timeout .........................................................................................................................54524.13.5 UART mode ..................................................................................................................546

Chapter 25FlexCAN

25.1 Information specific to this device ................................................................................................54725.1.1 Device-specific features ...............................................................................................547

25.2 Introduction ...................................................................................................................................54725.2.1 Overview ......................................................................................................................54825.2.2 FlexCAN module features ............................................................................................54925.2.3 Modes of operation .......................................................................................................549

25.3 External signal description ............................................................................................................55025.3.1 Overview ......................................................................................................................55025.3.2 Signal descriptions ........................................................................................................551

25.4 Memory map/register definition ....................................................................................................551



25.4.1 FlexCAN memory mapping .........................................................................................55125.4.2 Message Buffer Structure .............................................................................................55325.4.3 Rx FIFO structure .........................................................................................................55625.4.4 Register descriptions ....................................................................................................557

25.5 Functional description ...................................................................................................................57625.5.1 Overview ......................................................................................................................57625.5.2 Local priority transmission ...........................................................................................57725.5.3 Transmit process ...........................................................................................................57725.5.4 Arbitration process .......................................................................................................57825.5.5 Receive process ............................................................................................................57925.5.6 Matching process ..........................................................................................................58025.5.7 Data coherence .............................................................................................................58125.5.8 Rx FIFO ........................................................................................................................58425.5.9 CAN protocol related features ......................................................................................58425.5.10 Modes of operation details ...........................................................................................58825.5.11 Interrupts .......................................................................................................................58925.5.12 Bus interface .................................................................................................................590

25.6 Initialization/application information ............................................................................................59125.6.1 FlexCAN initialization sequence ..................................................................................59125.6.2 FlexCAN addressing and RAM size configurations ....................................................592

Chapter 26Deserial Serial Peripheral Interface (DSPI)

26.1 Introduction ...................................................................................................................................59326.2 Features .........................................................................................................................................59426.3 Modes of operation ........................................................................................................................595

26.3.1 Master mode .................................................................................................................59526.3.2 Slave mode ...................................................................................................................59526.3.3 Module Disable mode ...................................................................................................59526.3.4 Debug mode ..................................................................................................................596

26.4 External signal description ............................................................................................................59626.4.1 Signal overview ............................................................................................................59626.4.2 Signal names and descriptions ......................................................................................596

26.5 Memory map and register description ...........................................................................................59726.5.1 Memory map ................................................................................................................59726.5.2 DSPI Module Configuration Register (DSPIx_MCR) .................................................59826.5.3 DSPI Transfer Count Register (DSPIx_TCR) ..............................................................60126.5.4 DSPI Clock and Transfer Attributes Registers 05 (DSPIx_CTARn) .........................60226.5.5 DSPI Status Register (DSPIx_SR) ...............................................................................61026.5.6 DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER) ..............61226.5.7 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) .......................................................61426.5.8 DSPI POP RX FIFO Register (DSPIx_POPR) ............................................................61626.5.9 DSPI Transmit FIFO Registers 03 (DSPIx_TXFRn) .................................................617

26.6 Functional description ...................................................................................................................61826.6.1 Modes of operation .......................................................................................................619



26.6.2 Start and stop of DSPI transfers ...................................................................................62026.6.3 Serial peripheral interface (SPI) configuration .............................................................62126.6.4 DSPI baud rate and clock delay generation ..................................................................62426.6.5 Transfer formats ...........................................................................................................62726.6.6 Continuous serial communications clock .....................................................................63426.6.7 Interrupt/DMA requests ................................................................................................63526.6.8 Power saving features ...................................................................................................637

26.7 Initialization and application information .....................................................................................63826.7.1 How to change queues ..................................................................................................63826.7.2 Baud rate settings .........................................................................................................63826.7.3 Delay settings ...............................................................................................................64026.7.4 Calculation of FIFO pointer addresses .........................................................................640

Chapter 27Timers

27.1 Introduction ...................................................................................................................................64527.2 Technical overview ........................................................................................................................645

27.2.1 Overview of the STM ...................................................................................................64727.2.2 Overview of the eMIOS ...............................................................................................64727.2.3 Overview of the PIT .....................................................................................................649

27.3 System Timer Module (STM) .......................................................................................................64927.3.1 Introduction ..................................................................................................................64927.3.2 External signal description ...........................................................................................65027.3.3 Memory map and register definition ............................................................................65027.3.4 Functional description ..................................................................................................654

27.4 Enhanced Modular IO Subsystem (eMIOS) .................................................................................65527.4.1 Introduction ..................................................................................................................65527.4.2 External signal description ...........................................................................................65827.4.3 Memory map and register description ..........................................................................65827.4.4 Functional description ..................................................................................................67027.4.5 Initialization/Application information ..........................................................................700

27.5 Periodic Interrupt Timer (PIT) ......................................................................................................70427.5.1 Introduction ..................................................................................................................70427.5.2 Features .........................................................................................................................70427.5.3 Signal description .........................................................................................................70527.5.4 Memory map and register description ..........................................................................70527.5.5 Functional description ..................................................................................................70927.5.6 Initialization and application information ....................................................................710

Chapter 28Analog-to-Digital Converter (ADC)

28.1 Overview .......................................................................................................................................71528.1.1 Device-specific features ...............................................................................................71528.1.2 Device-specific implementation ...................................................................................716

28.2 Introduction ...................................................................................................................................717



28.3 Functional description ...................................................................................................................71728.3.1 Analog channel conversion ..........................................................................................71728.3.2 Analog clock generator and conversion timings ..........................................................72028.3.3 ADC sampling and conversion timing .........................................................................72028.3.4 ADC CTU (Cross Triggering Unit) ..............................................................................72528.3.5 Presampling ..................................................................................................................72628.3.6 Programmable analog watchdog ..................................................................................72728.3.7 DMA functionality .......................................................................................................72828.3.8 Interrupts .......................................................................................................................72828.3.9 External decode signals delay ......................................................................................72928.3.10 Power-down mode ........................................................................................................72928.3.11 Auto-clock-off mode ....................................................................................................729

28.4 Register descriptions .....................................................................................................................73028.4.1 Introduction ..................................................................................................................73028.4.2 Control logic registers ..................................................................................................73728.4.3 Interrupt registers ..........................................................................................................74028.4.4 DMA registers ..............................................................................................................74828.4.5 Threshold registers .......................................................................................................75228.4.6 Presampling registers ....................................................................................................75328.4.7 Conversion timing registers CTR[0..2] ........................................................................75628.4.8 Mask registers ...............................................................................................................75728.4.9 Delay registers ..............................................................................................................76128.4.10 Data registers ................................................................................................................76328.4.11 Watchdog register .........................................................................................................765

Chapter 29Cross Triggering Unit (CTU)

29.1 Introduction ...................................................................................................................................77929.2 Main features .................................................................................................................................77929.3 Block diagram ...............................................................................................................................77929.4 Memory map and register descriptions .........................................................................................779

29.4.1 Event Configuration Registers (CTU_EVTCFGRx) (x = 0...63) .................................78029.5 Functional description ...................................................................................................................781

29.5.1 Channel value ...............................................................................................................783

Chapter 30Flash Memory

30.1 Introduction ...................................................................................................................................78930.2 Main features .................................................................................................................................79030.3 Block diagram ...............................................................................................................................79030.4 Functional description ...................................................................................................................791

30.4.1 Module structure ...........................................................................................................79130.4.2 Flash memory module sectorization .............................................................................79230.4.3 TestFlash block .............................................................................................................79330.4.4 Shadow sector ...............................................................................................................795



30.4.5 User mode operation .....................................................................................................79530.4.6 Reset .............................................................................................................................79630.4.7 Power-down mode ........................................................................................................79730.4.8 Low power mode ..........................................................................................................797

30.5 Register description .......................................................................................................................79830.5.1 CFlash register description ...........................................................................................79930.5.2 DFlash register description ...........................................................................................834

30.6 Programming considerations .........................................................................................................85730.6.1 Modify operation ..........................................................................................................85730.6.2 Double word program ...................................................................................................85830.6.3 Sector erase ...................................................................................................................860

30.7 Platform flash memory controller .................................................................................................86830.7.1 Introduction ..................................................................................................................86830.7.2 Memory map and register description ..........................................................................871

30.8 Functional description ...................................................................................................................88030.8.1 Access protections ........................................................................................................88030.8.2 Read cycles Buffer miss ............................................................................................88030.8.3 Read cycles Buffer hit ...............................................................................................88130.8.4 Write cycles ..................................................................................................................88130.8.5 Error termination ..........................................................................................................88130.8.6 Access pipelining ..........................................................................................................88130.8.7 Flash error response operation ......................................................................................88230.8.8 Bank0 page read buffers and prefetch operation ..........................................................88230.8.9 Bank1 Temporary Holding Register .............................................................................88430.8.10 Read-while-write functionality .....................................................................................88530.8.11 Wait-state emulation .....................................................................................................886

Chapter 31Static RAM (SRAM)

31.1 Introduction ...................................................................................................................................88931.2 Low power configuration ..............................................................................................................88931.3 Register memory map ...................................................................................................................88931.4 SRAM ECC mechanism ................................................................................................................890

31.4.1 Access timing ...............................................................................................................89031.4.2 Reset effects on SRAM accesses ..................................................................................891

31.5 Functional description ...................................................................................................................89131.6 Initialization and application information .....................................................................................891

Chapter 32Register Protection

32.1 Introduction ...................................................................................................................................89532.2 Features .........................................................................................................................................89532.3 Modes of operation ........................................................................................................................89632.4 External signal description ............................................................................................................89632.5 Memory map and register description ...........................................................................................896




32.6 Functional description ...................................................................................................................90032.6.1 General .........................................................................................................................90032.6.2 Change lock settings .....................................................................................................90032.6.3 Access errors ................................................................................................................904

32.7 Reset ..............................................................................................................................................90432.8 Protected registers .........................................................................................................................904

Chapter 33Software Watchdog Timer (SWT)

33.1 Overview .......................................................................................................................................91333.2 Features .........................................................................................................................................91333.3 Modes of operation ........................................................................................................................91333.4 External signal description ............................................................................................................91433.5 Memory map and register description ...........................................................................................914


33.6 Functional description ...................................................................................................................919

Chapter 34Error Correction Status Module (ECSM)

34.1 Introduction ...................................................................................................................................92334.2 Overview .......................................................................................................................................92334.3 Features .........................................................................................................................................92334.4 Memory map and register description ...........................................................................................923

34.4.1 Memory map ................................................................................................................92334.4.2 Register description ......................................................................................................92434.4.3 Register protection ........................................................................................................942

Chapter 35IEEE 1149.1 Test Access Port Controller (JTAGC)

35.1 Introduction ...................................................................................................................................94535.2 Block diagram ...............................................................................................................................94535.3 Overview .......................................................................................................................................94535.4 Features .........................................................................................................................................94635.5 Modes of operation ........................................................................................................................946

35.5.1 Reset .............................................................................................................................94635.5.2 IEEE 1149.1-2001 defined test modes .........................................................................946

35.6 External signal description ............................................................................................................94735.7 Memory map and register description ...........................................................................................947

35.7.1 Instruction register ........................................................................................................94735.7.2 Bypass register ..............................................................................................................94835.7.3 Device identification register .......................................................................................94835.7.4 Boundary scan register .................................................................................................949



35.8 Functional description ...................................................................................................................94935.8.1 JTAGC reset configuration ...........................................................................................94935.8.2 IEEE 1149.1-2001 (JTAG) Test Access Port ................................................................94935.8.3 TAP controller state machine .......................................................................................94935.8.4 JTAGC instructions ......................................................................................................95135.8.5 Boundary scan ..............................................................................................................953

35.9 e200z0 OnCE controller ................................................................................................................95335.9.1 e200z0 OnCE controller block diagram .......................................................................95335.9.2 e200z0 OnCE controller functional description ...........................................................95435.9.3 e200z0 OnCE controller register description ...............................................................954

35.10 Initialization/application information ............................................................................................956

Appendix ARevision History

A.1 Changes between revisions 1 and 2 ............................................................................................957

Chapter 1 Preface



Chapter 1 Preface

1.1 OverviewThe primary objective of this document is to define the functionality of the MPC5606BK microcontroller for use by software and hardware developers. The MPC5606BK is built on Power Architecture technology and integrates technologies that are important for todays automotive vehicle body applications.

The information in this book is subject to change without notice, as described in the disclaimers on the title page. As with any technical documentation, it is the readers responsibility to be sure he or she is using the most recent version of the documentation.

To locate any published errata or updates for this document, visit the Freescale Web site at freescale.com.

1.2 AudienceThis manual is intended for system software and hardware developers and applications programmers who want to develop products with the MPC5606BK device. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the Power Architecture.

1.3 Guide to this reference manualTable 1-1. Guide to this reference manual

ChapterDescription Functional group

# Title

2 Introduction General overview, family description, feature list, and information on how to use the reference manual in conjunction with other available documen

mpc 5606 brm

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