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KALASALINGAM UNIVERSITY

(Kalasalingam Academy of Research and Education)

CURRICULUM AND SYLLABUS

REGULATIONS – 2011

M. Tech. VLSI DESIGN

(4 Semese!s"

KALASALINGAM UNIERSI!"

ELE#!R$NI#S AN% #$MMUNI#A!I$N ENGINEERING %E&AR!MEN!

KRIS'NANK$IL * +*



M. Tech. VLSI DESIGN REGULATIONS 2011

TOTAL CREDITS- /

E.C.E. DEPARTMENT KALASALINGAM UNIVERSITY of 37




LIST O ELECTIVES

ELECTIVE I

C$%e C$&!se N'me L T # C

E#E,+0/ '%L Analysis and %esign of %igital Systems 0 / / 0

E#E,+0+ Electronic %esign Automation !ools 0 / / 0

E#E,+0* Scri6ting Languages for LSI %esign Automation 0 / / 0

E#E,+00 &hysical %esign of LSI #ircuits 0 / / 0

ELECTIVE II


E#E,+0. #A% for LSI #ircuits 0 / / 0E#E,+0, <&GA =ased System %esign 0 / / 0

E#E,+0 Genetic Algorithms and its A66lications 0 / / 0

E#E,+07 $6timi>ation Methods for Engineering %esign 0 / / 0

ELECTIVE III


E#E,+04 Ad3anced Micro6rocessors and Microcontrollers 0 / / 0

E#E,+09 %S& Architecture 0 / / 0

E#E,+./ Ad3anced #om6uter Architecture 0 / / 0

E#E,+.+ ideo and Audio &rocessing 0 / / 0

ELECTIVE IV


E#E++* R< Microelectronics #hi6 design 0 / / 0

E#E++0 System?on?chi6 %esign 0 / / 0

%#N #$%E R< MEMES 0 / / 0

E#E++, Em5edded Systems 0 / / 0

ELECTIVE V


E#E++ Nano Electronics 0 / / 0

E#E++7 EMI and #om6ati5ility in System %esign 0 / / 0

E#E++4 LSI Signal &rocessing 0 / / 0

E#E++9 LSI #ircuit %esign Methodology 0 / / 0





KALASALINGAM UNIVERSITY

(Kalasalingam Academy of Research and Education)

Eec!$cs '% C$mm&c'$ E3ee!3 De'!me

M. Tech. (VLSI DESIGN"

SYLLABUS





ECE,121 VLSI DESIGN TEC5NI6UESL ! & #

. / / .

CMOS CIRCUITS UNDAMENTALS

M$S transistors@ #M$S Logic@ LSI design flo1@ #ircuit and System Re6resentations@ M$S transistor

theory?Introduction@ M$S %e3ice design e-uations Ideal I? #haracteristics@ #? #haracteristics@ Non?Ideal

I? effects #om6lementary #M$S in3erter %# characteristics@ Static load M$S in3erters@ %ifferential

in3erter@ !ransmission gate@ !ristate in3erter@ =i6olar de3ices

CMOS #ROCESSING TEC5NOLOGY

#M$S <a5rication o3er3ie1@ =asic #M$S technology@ SticB %iagrams@ %esign rules and Layout@ S$I rules@

design rulesC M$SIS scala5le #M$S design rules@ micron design rules #M$S 6rocess enhancements@

Latchu6@ technology?related #A% issues@ manufacturing issues

CIRCUIT C5ARACTERSATION AND #ERORMANCE ESTIMATION

Resistance estimation@ #a6acitance estimation@ Inductance estimation@ S1itching characteristicsC %elay

estimation@ #M$S gate transistor si>ing@ Logical effort and transistor si>ing@ !iming analysis delay models@

&o1er %issi6ation@ Energy?delay o6timi>ation@ Lo1 6o1er architectures

INTERCONNECT AND ROBUSTNESS

Interconnect modelling@ Interconnect im6act@ Interconnect engineering@ Si>ing routing conductors@ #harge

sharing@ %esign Margin@ Ro5ustness introduction@ aria5ility@ "ield@ Relia5ility@ Scaling@ Statistical analysis

of 3aria5ility@ ariation?tolerant design

CMOS CIRCUIT DESIGN AND DESIGN MET5OD

#M$S Logic Gate %esign? =asic &hysical %esign of Sim6le Gate@ #M$S Logic Structures@ #locBing

Strategies@ ID$ Structures@ Lo1 &o1er %esign@ Su6er =uffers@ =I#M$S and Steering Logic@ %ri3ing Large

#a6aciti3e load@ %esign Strategies@ #hi6 %esign $6tions@ %esign Methods@ %esign #a6ture and erification

!ools@ %ata sheets@ =asics of testing

REFERENCES

+ Neil ' E Feste@ Eshraghian Kamran@ &rinci6les of #M$S LSI %esignC A System &ers6ecti3eH@

*nd Edition@ &earson@ */+/ (Re6rint)* Neil ' E Feste@ %a3id 'arris@ =aner;ee@ #M$S LSI %esignC A #ircuits and System &ers6ecti3eH@

0rd Edition@ &earson@ */+/ (Re6rint)

0 Neil ' E Feste@ %a3id 'arris@ #M$S LSI %esignH@ .th Edition@ &earson@ */+/

. %ouglas A &ucBnell and Eshraghian Kamran@ =asic LSI %esign? system and circuitsH@ &rentice

'all@ *//0

, Fayne Folf@ Modern LSI %esignH@ &earson@ *//7

ohn & Uyemura@ Introduction to LSI #ircuits and SystemsH @ Filey@ *//0




ECE,12* ANALOG DESIGNL ! & #

0 / / 0

IELD EECT TRANSISTORS

?<E!s@ MES<E!s@ M$%<E!@ M$S diode@ M$S<E!sC <undamentals@ Essentials@ Non Ideal M$S@ =asic

de3ice characteristics@ Non uniform do6ing and 5uried?channel de3ice@ %e3ice scaling and Short?channel

Effects@ M$S<E! Structures@ #M$S and =I#M$S@ M$S<E! on Insulator@ M$S Memory Structures@ &o1er

M$S<E!@ Single Electron !ransistor

MODELLING O IELD EECT TRANSISTORS

&S&I#E ModellingC M$S<E!s? %#@ small signal@ high fre-uency and noise models of M$S<E!s M$S

#a6acitors@ %e3ice Scaling? short and narro1 channel M$S<E!s M$S<E! channel mo5ility model@ %I=L@

charge sharing and other non?linear effects@ M$S ModelsC Le3el?+ and le3el?* large signal M$S<E! models@

=SIM models@ E8traction of M$S<E! model 6arameters

B7T AND MOS TRANSISTOR AM#LIIERS8 CURRENT MIRRORS

Single transistor Am6lifiers stages@ Multi6le !ransistor Am6lifier stages@ %ifferential Am6lifiers@ #urrent

Mirrors of =i6olar@ M$S transistors@ oltage and current references@ $ut6ut Stages

O#ERATIONAL AM#LIIER

A66lications of o6erational Am6lifier@ theory and %esign %efinition of &erformance #haracteristics

?%e3iation from Ideality in Real $6erational Am6lifiers@ %esign of t1o stage M$S $6erational Am6lifier@

$6erational Am6lifier 1ith cascodes@ =i6olar o6erational am6lifiers <re-uency res6onse of Integrated

#ircuits Single Stage Am6lifiers@ Multistage Am6lifiers@ NE,*0. $&?AM&@ <eed5acB@ <re-uency res6onse

and sta5ility of feed5acB am6lifiers

NONLINEAR ANALOG CIRCUITS

Analysis of four -uadrant and 3aria5le !ran conductance multi6lier@ oltage controlled oscillator@

#om6arators@ Analog =uffers@ &hase LocBed !echni-ues &hase LocBed Loo6s (&LL)@ closed loo6 analysis of

&LL %igital?to?Analog (%DA) and Analog?to?%igital (AD%) #on3erters

REFERENCES

+ &aul = Gray@ RG Meyer@ Analysis and %esign of Analog Integrated #ircuitsH@ ,th Edition@ Filey@

*//9

* =eh>ad Ra>a3i@ %esign of Analog #M$S Integrated #ircuitsH@ !ata McGra1 'ill@ *//*

0 %a3id A ohns@ Kenneth F Martin@ Analog Integrated #ircuit %esignH@ Filey@ */++

. EriB =run3and@ %igital LSI #hi6 %esign 1ith #adence and Syno6sys #A% !oolsH@ &earson@ */+/

, Arora N %@ M$S<E! Models for LSI #ircuit SimulationH@ S6ringer?erlag@ *//0

Simon M S>e@ Semiconductor %e3ices &hysics and !echnologyH@ *nd Edition@ Filey@ *//0

7 M ' Rashid@ Introduction to &S6ice using $r#A% for circuits and electronicsH@ &rentice 'all@ *//.




ECE,124 DIGITAL DESIGNL ! & #

0 / / 0

DIGITAL SYSTEMS OVERVIE9

Num5er Systems@ =asic Logic Gates@ #om5inational Logic #ircuits@ Se-uential Logic #ircuits@ Logic

<amilies@ #lassification of memories@ RAM organi>ation@ &R$M@ E&R$M@ EE&R$M@ EA&R$M@ and

Ad3anced <lash Memory Architecture

ADVANCED TO#ICS IN BOOLEAN ALGEBRA

ShannonJ e86ansion theorem@ consensus theorem octal designation@ fun measure@ IN'I=I!D IN#LUSI$ND

A$ID %ri3erD =uffer gates@ gate e86ander@ Reed Muller e86ansion@ synthesis of multi6le out6ut com5inational

logic circuits 5y 6roduct ma6 method

T5RES5OLD LOGIC8 SYMMETRIC UNCTIONS

Linear se6era5ility@ unateness@ 6hysical im6lementation@ dual com6ara5ility@ reduced functions@ 3arious

theorems in threshold logic@ synthesis of single gate and multigate threshold net1orB@ Symmetric <unctionsC

Elementary symmetric functions@ 6artially symmetric and totally symmetric functions@ Mc #lusBey

decom6osition method@ unity ratio symmetric ratio functions@ synthesis of symmetric function 5y contact

net1orBs@ #locB sBe1@ ;itter

SE6UENTIAL CIRCUITS DESIGN

Mealy machine@ Moore machine@ tri3ialDre3ersi5leD isomor6hic se-uential machines@ state diagram@ state ta5le

minimi>ation@ incom6letely s6ecified se-uential machines@ state assignments@ design of synchronous and

asynchronous se-uential logic circuits 1orBing in the fundamental mode and 6ulse mode@ ASM #hart@ ASM

Reali>ation@ Races in AS#@ 'a>ards@ Unger Js theorem

#ROGRAMMABLE LOGIC DEVICES

&rogramming logic de3ice families %esigning synchronous se-uential circuit using &LAD&AL Reali>ation

of <SM using &L% Introduction to field 6rogramma5le gate arrays !y6es of <&GA@ Logic #ell array (L#A)@

#L=@ I$=@ 6rogramma5le interconnect 6oint (&I&)@ Introduction to Actel A#!* family and 2ilin8 2#0///@

2#./// families@ %esign e8am6les

REFERENCES

+ Filliam I <letcher@ An Engineering A66roach to %igital %esignH@ &rentice 'all@ *//

* ames E &almer@ %a3id E &erlman@ Introduction to %igital SystemsH@ !ata McGra1 'ill@ *//

0 NN =is1as@ Logic %esign !heoryH@ &rentice 'all@ *//0

. S%e3adas A Ghosh and K Keut>er@ Logic synthesisH@ !ata McGra1 'ill@ *//.




ECE,12, MODELLING AND SYNT5ESIS 9IT5 VERILOG 5DLL ! & #

0 / / 0

5ARD9ARE MODELLING 9IT5 VERILOG 5DL

'%Ls in E%A@ System #@ '%L and erilog@ System erilog o3er3ie1@ 'ard1are Enca6sulation@ 'ard1are

Modeling 1ith erilog '%L@ 'ierarchical descri6tions of hard1are@ Structured design methodology@ Arrays@

Using erilog for synthesis@ Language con3entions@ Re6resentation of num5ers@ E3ent dri3en simulation and

test5enches@ Logic system@ data ty6es and o6erators@ User?defined 6rimiti3esC #om5inational 5eha3iour@

Se-uential 5eha3iour@ Se-uential 6rimiti3es initiali>ation

DELAY MODELS8 BE5AVIOURAL DESCRI#TION

erilog models of 6ro6agation delay@ =uilt?in constructs@ Signal transition@ Inertial delay@ !ime scales and

6recision@ %elays@ %elay effects and &ulse re;ection@ Race condition in erilog@ !y6es of race condition@ !asB

and function@ E3ents@ &rocess control@ <orBD;oin@ %isa5le a 5locB@ Fatchdog@ de5ugging@ #ode co3erage@

!esting strategies@ <ile handling@ =eha3ioral descri6tions in erilog '%L@

SYNT5ESIS O COMBINATIONAL LOGIC8 SE6UENTIAL LOGIC

Synthesis of #om5inational Logic@ '%L?=ased Synthesis@ !echnology?Inde6endent %esign@ Synthesis

Methodology@ Styles for Synthesis of #om5inational Logic@ !echnology Ma66ing and Shared Resources@

!hree?State =uffers@ $ut6uts and %ont #ares@ Synthesis of Se-uential Logic@ Synthesis of Se-uential U%&s@

Latches@ Edge?!riggered <li6?<lo6s@ Registered #om5inational Logic@ Shift Registers and #ounters <inite

State Machines@ Resets@ Gated #locBs@ %esign &artitions and 'ierarchical Structures

SYNT5ESIS O LANGUAGE CONSTRUCTS8 S9ITC5 LEVEL MODELS

Synthesis of Language constructs@ M$S !ransistor !echnology@ S1itch?Le3el Models@ &ULL gates@ #M$S!ransmission gates@ =i?%irectional gates (S1itches)@ Signal Strengths@ Am5iguous Signals@ Strength

Reduction 5y &rimiti3es@ #om5ination and Resolution of Signal Strengths@ Signal Strengths and Fired Logic@

<I<$=uffers for %ata Ac-uisition@ <I<$ A66lication@ UAR!@ =it?Slice Microcontroller@ Ra6id &rototy6ing

1ith erilog and <&GAs

ELECTRONIC DESIGN AUTOMATION

Electronic %esign Automation@ %esign@ Simulation@ Analysis@ erification@ !esting@ Synthesis@ %esign flo1C

'igh le3el synthesis@ Logic synthesis@ Schematic ca6ture@ Layout SimulationC !ransistor (lo1) le3el@ Logic

(R!L@ Gate?netlist 5oolean) le3el@ =eha3ioural simulation@ 'ard1are emulation@ AnalysisC <unctional

3erification@ #%# checB@ <ormal 3erification@ E-ui3alence checBing@ !iming analysis@ &hysical 3erification

<ormatsC netlist@ G%SII@ Ger5er@ $ASIS@ E%I<@ %E<@ LE<@ S%<@ !ools for Analog and %igital LSI %esign

%esign@ Simulation and Synthesis@ LSI =acB?end@ Layout tools@ !esting tools@ Shell scri6ts for LSI@ List

and o3er3ie1 of E%A tools

REFERENCES

+ M@%@#iletti@ Modeling@ Synthesis and Ra6id &rototy6ing 1ith the erilog '%LH@ &rentice 'all@ *//

* Ste3en M Ru5in@ #om6uter Aids for LSI %esignH@ htt6CDD111rula5insBycomDca3d (free online

5ooB)@ +997

0 M@G@ Arnold@ erilog %igital #om6uter %esignH@ &rentice 'all@ *//

. S &alnitBar@ erilog '%L A Guide to %igital %esign and SynthesisH@ &earson @ *//0




ECE,1+* 5DL #ROGRAMMING AND EDA TOOLS LABORATORYL ! & #

/ / 0 *

5DL #ROGRAMMING

+ Study of simulation tools@ Study of synthesis tools@ Study of <&GA 5oard

* R!L descri6tion of com5inational and se-uential circuits using erilog '%LD'%L

a All gates 1ith all modelling@ half adder and full adder@ Multi6le8er@ Address decoder

5 #locB generator 1ith 3aria5le duty cycle and fre-uency@ clocB generator 1ith ;itter@ clocB

multi6lier@ clocB di3ider and a 6ulse counter

c * 5it counter as a <SM (1ith #locB@ Reset@ Ena5le@ Load@ and #ount u6 or do1n)

d . 5it multi6lier@ 4 5it adder@ Accumulator@ #alculator (Addition@ Su5traction and

Multi6lication of *Js com6lement num5ers)

e .D4 5it =arrel shifter@ 4 5it &arallel to serial con3erter (1ith a goJ 5it for start of transmission)

f &R=S generator@ Memory unit0 erification of the <unctionality using a Simulator@ for a5o3e R!L designs 1ith test 5enchesC Linear

or <ile ID$ =ased or !asB 5ased !est 5ench

. Synthesis of the a5o3e R!L designs and 6o1er and timing analysis of the synthesised designs

#S#ICE MODELLING

, Introduction to S6ice language

Study of Netlist (R@ #@ diodes@ M$S transistors@ =!s)@ Models (diodes@ M$S transistors@ =!s)@ and

Analysis ty6es (dc@ ac and transient)

7 erify truth ta5les of N$!@ AN%@ $R gates im6lemented 5y NAN% gates using &S&I#E

4 %iode #ircuits

a %iode characteristics and 5asic diode circuitsC ? E86erimental identification of 5asic diode

S6ice model 6arameters 5 %esign of rectifiers and 6o1er su66liesC ? Ri66le@ line and load regulation s6ecs

9 M$S !ransistor #ircuits

a M$S characteristicsC ? E86erimental identification of 5asic M$S<E! S6ice model 6arameters

5 NM$S In3erterC ? %e6letion and Enhancement Mode #ircuit Simulation

c #M$S In3erterC ? #ircuit Simulation@ ad;ustment of FDL ratio of & N channel M$S

transistor for symmetrical dri3e out6ut and loading consideration@ Scaling of #M$S In3erter

for different technologies@ study of secondary effects

+/ #urrent sourceDMirrors

a #ircuit simulation of current Mirror using =! and M$S (Sim6le@ Filson and Fidler

configurations) study and modifications to im6ro3e 6o1er and load regulation

++ %ifferential Am6lifier a Study of s6ecifications of %ifferential am6lifier and %esign considerations@ Study of in6ut

loading and 5iasing techni-ues@ %etermination of gain@ 5and1idth@ out6ut im6edance and

#MRR

+* <re-uency res6onse of an o6?Am6 integrator circuit@ R#?cou6led #E Am6lifier

MINI #RO7ECT

(IN#LU%ING !'E <$LL$FING)

+0 %esign and characteri>ation of an 4?5it A%# circuit using '%L

+. %esign of <<! using '%L

+, %esign and simulation of 6i6elined serial and 6arallel adder to addD su5tract 4 num5ers of si>e@ +* 5its

each in *s com6lement





+

ECE,12 VLSI TEC5NOLOGYL ! & #

0 / / 0

SEMICONDUCTOR #5YSICS8 #N 7UNCTION

Semiconductor de3ices@ Energy 5ands and #arrier concentration@ #arrier modelling@ Ouanti>ation conce6t@

E-uili5rium carrier concentration@ #arrier action@ State e-uations@ 6?n unction@ !hermal e-uili5rium

condition@ %e6letion Region@ %e6letion #a6acitance@ I? #haracteristics@ Ideal diode e-uation@ 'etero

;unctions@ Metal?semiconductor contacts@ Ideal MIS #a6acitors@ Silicon M$S #a6acitorsC

&S&I#E ModellingC A#@ %#@ !ransient@ noise@ tem6erature e8tra analysis@ unction %iodes? %#@ small signal@

large signal@ high fre-uency and noise models of diodes Measurement of diode model?6arameters

BI#OLAR TRANSISTORS

=i6olar !ransistor <undamentals@ !ransistor action@ Static@ =! %ynamic Res6onse Modelling@ <re-uency

res6onse and s1itching of =i6olar !ransistors@ Micro1a3e characteristics@ 'etero?;unction =i6olar transistor

&S&I#E ModellingC =!? %#@ small signal@ high fre-uency and noise models of 5i6olar ;unction transistors

E8traction of =! model 6arameters

9AER #RE#ARATION8 E#ITA:Y AND O:IDATION

Electronic Grade Silicon@ Fafer 6re6aration@ #>ochralsBi crystal gro1ing@ Silicon Sha6ing@ 6rocessing

consideration@ E6ita8y@ Gro1th Mechanism and Binetics@ $8idation !echni-ues and Systems@ Models of

%iffusion in Solids@ Atomic %iffusion@ Ion im6lantation

LIT5OGRA#5Y8 ETC5ING AND DE#OSITION

!y6es of Lithogra6hy@ &lasma Etching techni-ues and E-ui6ments@ %e6osition 6rocess@ &olysilicon@ 6lasma

assisted %e6osition

METALLISATION AND #ROCESS INTEGRATION

MetallisationC &hysical 3a6our de6osition@ &atterning@ &rocess integratedC NM$S I# !echnology@ #M$S I#

!echnology@ M$S Memory I# technology ? =i6olar I# !echnology@ I# <a5rication

REFERENCES

+ SMS>e@ LSI !echnologyH@ McGra1 'ill@ *//0* %ouglas A &ucBnell@ Kamran Eshraghian@ =asic LSI %esignH@ &earson@ *//0

0 RS Muller and !I Kamins@ %e3ice Electronics for Integrated #ircuitsH@ 0rd Edition@ Filey@ *//0

. Simon M S>e@ Semiconductor %e3ices &hysics and !echnologyH@ *nd Edition@ Filey@ *//0

, M ' Rashid@ Introduction to &S6ice using $r#A% for circuits and electronicsH@ &rentice 'all@ *//.

Giuse66e Masso5rio@ &aolo Antognetti@ Semiconductor %e3ice Modeling 1ith S6iceH@ !ata McGra1

'ill@ */+/





ECE,12/ ADVANCED DIGITAL DESIGNL ! & #

0 / / 0

COMBINATIONAL8 SE6UENTIAL CIRCUITS DESIGN

Fire models@ #ircuit families@ #ircuit 6itfalls@ #om6arison of circuit families@ SoI circuit design@ su5?

threshold circuit design@ %esign methodology Simulation of com6le8 logic gates@ Se-uencing static circuits@

#ircuit design of latches and fli6?flo6s@ Se-uencing dynamic circuits@ !iming issues in digital circuits@

Synchronous design@ self?timed design@ Synchroni>ers and ar5iters@ #locBs@ &LLs and %LLs@ #locB synthesis

and synchroni>ation using &LL@ Fa3e 6i6elining@

DATA #AT58 ARRAY8 S#ECIAL;#UR#OSE SUBSYSTEMS

%ata 6aths@ AdditionDSu5traction@ $neDPero detectors@ #om6arators@ #ounters@ =oolean logical o6erations@#oding@ Shifters@ Multi6lication@ &arallel?6refi8 com6utation@ &o1er and S6eed tradeoff@ Memory architecture

and 5uilding 5locBs@ Memory #ore@ SRAM@ %RAM@ R$M@ SAM@ #AM@ Memory 6eri6heral circuits@ Ro5ust

Memory %esign@ &o1er distri5ution@ ID$@ . M5it SRAM design@ +G=I! NAN% <LAS' RAM design@ MI&S

6rocessor design

CIRCUITS AND MODELS8 ARC5ITECTURE LEVEL SYNT5ESIS

Gra6hs@ #om5inatorial o6timi>ation@ Gra6h o6timi>ation 6ro5lems and algorithms@ =oolean alge5ra and

functions@ 'ard1are Modelling Languages@ A5stract models@ #om6ilation and 5eha3ioural o6timi>ation@

#ircuit s6ecifications for architectural synthesis@ Synthesis 6ro5lems@ Area and 6erformance estimation@

Strategies for architectural o6timi>ation@ %ata 6ath synthesis@ control?unit synthesis@ synthesis of 6i6elined

circuits

SC5EDULING ALGORIT5MS AND RESOURCE S5ARING

Model for the scheduling 6ro5lems@ Scheduling 1ithout and 1ith constraints@ Scheduling algorithms for

e8tended se-uencing models@ Scheduling 6i6elined circuits@ Sharing and 5inding for resource dominated

circuits@ #oncurrent 5inding and scheduling@ Resource sharing and 5inding for non?scheduled se-uencing

gra6hs@ the module selection 6ro5lem@ Resource sharing and 5inding for 6i6elined circuits

LOGIC;LEVEL SYNT5ESIS AND O#TIMI<ATION

!1o?le3el com5inational logic simulation@ Multi6le?le3el com5inational logic simulation@ Se-uential logic

o6timi>ation@ #ell?li5rary 5inding

REFERENCES

+ Neil ' E Feste@ %a3id 'arris@ =aner;ee@ #M$S LSI %esignC A #ircuits and System &ers6ecti3eH@

0rd Edition@ &earson@ */+/

* an M Ra5aey@ etal@ %igital Integrated #ircuitsH@ *nd Edition@ &rentice 'all@ *//.

0 G%e Micheli@ Synthesis and o6timi>ation of %igital circuitsH@ McGra1 'ill@ +99.


, ames $ 'am5len@ etal@ Ra6id 6rototy6ing of digital systemsH@ S6ringer? S$&# Edition@ *//4





ECE,12+ ANALOG AND MI:ED SIGNAL DESIGNL ! & #

0 / / 0

ANALOG AND MI:ED SIGNAL DESIGN – UNDAMENTALS

#hallenges in Analog design@ Mi8ed signal 6rocessing 5locBs@ Mi8ed signal issues@ Mi8ed signal design

e8am6le@ Re3ie1 of =asic M$S !ransistors@ Re3ie1 of =asic Analog #ircuits Large signal@ Small signal

models@ Am6lifiers@ Signals@ <ilters@ Su5micron #M$S circuit design

ANALOG AND DIGITAL ILTERS

Sam6ling@ Sam6le and 'old #ircuits@ %ata con3erters@ %ifferential non?linearity and Integral non?linearity for

%A#s and A%#s@ %ata con3erter architectures@ Analog filters@ Integrator 5uilding 5locBs@ Analog <iltering

to6ologies@ %igital filters@ S&I#E models for %A#s and A%#s@ Sinc?sha6ed %igital filters@ %igital filtering

to6ologies

DATA CONVERTER SNR8 DESIGN BASICS

Ouanti>ation noise@ SNR@ #locB ;itter@ Im6ro3ing SNR using a3eraging@ using feed5acB@ %ecimating filters for

A%#@ Inter6olating filters for %A#@ %ata con3erter design@ $ne 5it A%# and %A#@ &assi3e noise?sha6ing@

Im6ro3ing SNR and linearity using an Acti3e circuit

NOISE S5A#ING8 BAND#ASS DATA CONVERTERS

<irst order noise sha6ing@ second order noise sha6ing@ Noise sha6ing to6ologies@ #ontinuous time =and6ass

noise?sha6ing@ &assi3e com6onent modulators@ Acti3e com6onent modulators@ Modulators at R< <re-uencies@

S1itched?ca6acitor@ =and6ass noise?sha6ing

5IG5 S#EED DATA CONVERTERS

!o6ology@ #locB signals@ &ath settling time@ Im6lementation@ filtering@ understanding the signals@ &ractical

im6lementation@ Generating clocB signals@ #om6onents S1itched ca6acitors@ Am6lifiers@ #locBed

com6arators 'igh s6eed A%#@ S1itched ca6acitor circuits

REFERENCES

+ R aco5 =aBer@ #M$SC Mi8ed?Signal #ircuit %esignH@ *nd Edition@ Filey?IEEE 6ress@ *//4

* ineeta & Gi;;i@ Analog and Mi8ed Mode LSI %esignH@ &rentice 'all@ */++

0 EriB =run3and@ %igital LSI #hi6 %esign 1ith #adence and Syno6sys #A% !oolsH@ &earson@ */+/




ECE,12) ASIC DESIGNL ! & #

. / / .

ASICs INTRODUCTION=

Introduction to ASI#s@ ASI#s ty6es@ %esign flo1@ #om6arison@ #ell li5raries@ #M$S transistors@ #M$S

6rocess@ #M$S rules@ #om5inational logic cells@ Se-uential logic cells@ %ata 6ath logic cells@ ID$ #ells@ #ell

com6ilers@ ASI# Li5rary design

#ROGRAMMABLE ASICs8 LOGIC CELLS8 I>O CELLS

Antifuse@ Static RAM@ E&R$M and EE&R$M technology@ Issues@ S6ecifications@ &RE& 5enchmarBs@ Actel

A#!@ 2ilin8 L#A@ Altera <LE2@ Altera MA2@ %# and A# ID$s@ #locB in6ut@ &o1er in6ut@ 2ilin8 ID$ 5locBs@

$ther ID$ cells

#ROGRAMMABLE ASIC INTERCONNECT8 DESIGN SOT9ARE8 LO9 LEVEL DESIGN

ENTRY

Interconnect Actel A#!@ 2ilin8 L#A@ 2ilin8 E&L%@ Altera MA2@ <LE2 %esign systems@ Logic synthesis@

'alfgate ASI#@ Schematic entry@ Lo1 le3el design languages@ &LA tools@ E%I<@ #<I design re6resentation@

'%L languages o3er3ie1 and design e8am6les

LOGIC SYNT5ESIS8 SIMULATION8 TESTING

Logic synthesi>er@ erilog and Logic synthesis@ <SM synthesis@ Memory synthesis@ &erformance dri3en

synthesis@ #ase studies@ Simulation ty6es@ %esign e8am6le@ Logic systems and Logic simulation@ #ell models@

%elay models@ Static timing analysis@ <ormal erification@ S1itch?le3el simulation@ !ransistor?le3el

simulation8 !esting im6ortance@ %esign e8am6le@ #ase study@ S$# Introduction@ %esign issues in S$#@ 'igh

6erformance algorithms for ASI#sD S$#s

#ARTITIONING8 LOOR#LANNING8 #LACEMENT8 ROUTING

ASI# construction@ &hysical design@ System 6artitioning@ Si>e estimation@ &o1er dissi6ation@ <&GA

6artitioning@ 6artitioning methods@ <loor6lanning@ &lacement@ Information formats@ Routing@ #ircuit e8traction

and %R#@ ASI#DS$# #ase studies? %esign ofC %igital camera@ =luetooth radioDmodem@ S%RAM and US=

controllers

REFERENCES

+ M Se5astian Smith@ A66lication S6ecific Integrated #ircuitsH@ &earson@ *//9

* EriB =run3and@ %igital LSI #hi6 %esign 1ith #adence and Syno6sys #A% !oolsH@ &earson@ */+/



ECE,1+4 VLSI DESIGN LABORATORYL ! & #

/ / 0 *

+ &lace and route @=acB annotation for <&GAs (Synthesis@ &R and &ost &R simulation@ #once6ts of

<&GA floor 6lan@ critical 6ath@ design gate count@ ID$ configuration and 6in assignment@ Generation of

configurationDfuse files@ ID$ data demonstration using Logic Analy>er)

* %esign and simulation of 5acB annotated erilog '%L files for multi6lying t1o signed@ 4 5it num5ers

in *s com6lement %esign must 5e 6i6elined and com6letely R!L com6liant

0 %esign of static random access memories (SRAMs)

. Im6lementation of 4 =it ALU in <&GA@ . 5it sliced 6rocessor in <&GA

, Im6lementation of <<!@ %igital <ilters

'%L im6lementation of I*# 5us 6rotocol

7 %esign a Synchronous <I<$ of . 8 + 5it 1ords 1ith test 5ench using System erilog

4 %esign the Models of R@ L@ #@ %iode@ $6 Am6@ 5asic gates@ using erilog?A or erilog AMS

9 Study of Synthesis@ simulation and 6hysical design of a digital circuit@ standard #A% tools to design@

layout and simulate LSI circuits@ gra6hical schematic entry and 6ost?6rocessing tools@ a com6lete

LSI design e8am6leC from R!L to G%SII

+/ Layout of a sim6le #M$S in3erter@ 6arasitic e8traction and simulation

++ %esign and o6timi>e the delay@ 6o1er@ and area of an in3erter chain

+* %esign@ analy>e@ simulate and layout of static #M$S gates@ dynamic #M$S gates

+0 %esign and o6timi>e a full adder circuit

+. %esign latches and fli6?flo6s and analy>e timing and clocBing issues

MINI #RO7ECT

(IN#LU%ING !'E <$LL$FING)

+, Im6lementation of a USAR! on <&GA

+ Im6lementation of a .?5it 2 .?5it array multi6lier 1ith carry?sa3e circuit techni-ues using Se-uential

#ircuit #om6onents

+7 Im6lement an ar5itrary se-uence generator $5ser3e 1a3eform on a logic analy>er E8change data

1ith &# and mani6ulate data in Matla5

+4 Im6lementation of a MA# on <&GA

+9 %esign ca6ture and mi8ed?mode simulation and analysis of a successi3e a66ro8imation A%#

*/ %esign of a +/ 5it num5er controlled oscillator using standard cell a66roach@ simulation follo1ed 5y

study of synthesis re6orts Automatic layout generation follo1ed 5y 6ost layout e8traction and

simulation of the designed circuit

Tools needed: Dolphin SMASH, Cadence/MAGMA/Tanner/Synopsys/Silvaco/Alliance, Electric with plugins

!"S!M, #ean Shell, and $ython, %ilin& !SE/Altera 'uartus, Magic, S(!CE so)tware, %ilin&/Altera *(GA +its

Design is to e carried atleast in -.u CM0S technology




ECE111 TESTING O VLSI CIRCUITSL ! & #

0 / / 0

AULT MODELLING AND AULT SIMULATION

Introduction to testing ? <aults in %igital #ircuits ? Modelling of faultsC ? <unctional modelling at logical@

register and structural le3els Logic simulation !y6es of simulation E3ent %ri3en simulation ? %elay

models <ault Modelling ? Logical <ault Models <ault detection <ault E-ui3alence and <ault Location

<ault dominance <ault simulation !echni-ue ? <ault simulation for com5inational circuits <ault sam6ling

TEST GENERATION OR CIRCUITS

Introduction ? #om6osite circuit re6resentation and 3alue systems ? !est generation 5asics ?Im6lication ?

Structural test generationC 6reliminaries ? S6ecific structural test generation 6aradigms ? Non?structural test

generation techni-ues ?!est generation systems ?!est generation for reduced heat and noise during test ?#lassification of se-uential A!&G methods and faults ? <ault colla6sing ? <ault simulation ? !est generation

for synchronous circuits ? !est generation for asynchronous circuits ? !est com6action ? I%%O testing

DESIGN OR TESTABILITY

!esta5ility ? Ad 'oc %esign for !esta5ility !echni-ues #ontrolla5ility and o5ser3a5ility 5y means of scan

registers? Generic scan 6ath designs =oard le3el and system le3el %<! a66roaches Ad3anced Scan

conce6ts =oundary scan standards ? #om6ression !echni-ues

SEL;TEST AND MEMORY TESTING

=uilt?In Self?!est conce6ts =IS! %esign Rules ? !est 6attern generation for =IS!? E8hausti3e !esting@

&seudorandom !esting@ &seudo e8hausti3e !esting@ Logic Segmentation and #onstant 1eight 6atterns

Generic offline =IS! architecture S6ecific =IS! architecture #S=L@ =ES!@ R!S@ L$#S!@

S!UM&S@#=IS!@ #E=S@ R!%@ SS!@ #A!S@ #S!& and =IL=$ Ad3anced =IS! #once6ts ? Memory testing

? !raditional tests ? March tests ? &seudorandom memory tests

AULT DIAGNOSIS8 SEL;C5ECKING DESIGN AND #LA TESTING

Logical Le3el %iagnosis %iagnosis 5y UU! reduction <ault %iagnosis for #om5inational #ircuits Self?

checBing design System Le3el %iagnosis &LA testing ? &LA testing 6ro5lems !est generation algorithms

for &LAs !esta5le &LA design

REFERENCES

1. MA5ramo3ici@ etal@ %igital systems and !esta5le%esignH@ aico IEEE &u5lishers@ *//*

* Nira; ;ha@ S Gu6ta@ !esting of %igital systemsH@ #am5ridge &ress@ *//0

0 Laung?! Fang@ etal (Editors)@ LSI !est 6rinci6les and architecturesC %esign for !esta5ilityH@

Kaufmann &u5lishers@ *//

. &arag KLala@ An Introduction to Logic #ircuit !estingH@ Morgan &u5lishers@ *//,

, &arag K Lala@ %igital #ircuit !esting and !esta5ilityH@ Klu1er Academic@ *//*

ML=ushnell@ %Agra1al@ Essentials of Electronic !esting for %igital@ Memory and Mi8ed?Signal

LSI #ircuitsH@ Klu1er Academic@ *//*





ECE,1*0 V5DL ANALYSIS AND DESIGN O0 DIGITAL SYSTEMS

L ! & #

0 / / 0

COMBINATIONAL DESIGN

#om5inational logic design?=oolean alge5ra@ logic gates@ timing@ com5inational logic using '%L gate

models?Entities and architectures@ identifiers@ s6aces and comments@ netlists@ signal assignments@ generics@ test

5enches@ configurations@ #om5inational 5uilding 5locBs?three?state 5uffers@ decoders@ multi6le8ers@ 6riority

encoder@ adders@ 6arity checBer@ test 5enches for com5inational 5locBs

SYNC5RONOUS SE6UENTIAL DESIGN

Synchronous Se-uential systems@ Algorithmic State machine@ synthesis from ASM charts@ state machine in

'%L@'%L test5enches for state machines@ '%L models of se-uential logic 5locBs?latches@ fli6 flo6s@ K

and ! fli6 flo6s@ registers and shift registers@ counters@ memory@ se-uential multi6lier@ test5enches for

se-uential 5uilding 5locBs

V5DL SYNT5ESIS AND SIMULATION

E3ent dri3en simulation@ simulation of '%L models@ simulation modelling issues@ fire o6erations@ R!L

synthesis@ constraints@ synthesis for <&GAs@ 5eha3ioural synthesis@ 3erifying synthesis results

TESTING AND DESIGN OR TESTABILITY

Need for testing@ fault models@ fault oriented test 6attern generation@ fault simulation in '%L@ Ad?'oc

testa5ility im6ro3ements@ structured design for test @5uilt in self test @5oundary scan

ASYNC5RONOUS SE6UENTIAL DESIGN

Analysis of asynchronous circuits@ design of asynchronous se-uential circuits@ asynchronous state machines@

setu6 and hold times and metasta5ility@ interfacing 1ith the analog 1orld@ '%L?AMS@ &hase locBed loo6@

'%L AMS simulators

REFERENCES

+ P1olinsBi@ %igital System %esign 1ith '%LH@ &earson@ *//7

* olnei A &edron@ %igital electronics and design 1ith '%LH@ Kaufmann@ *//4

0 <ranB ahid@ %igital %esign 1ith R!L %esign@ erilog and '%LH@ Filey@ */+/


, ames $ 'am5len@ etal@ Ra6id 6rototy6ing of digital systemsH@ S6ringer? S$&# Edition@ *//4





ECE,1*1 ELECTRONIC DESIGN AUTOMATION TOOLS

L ! & #

0 / / 0

ELECTRONIC DESIGN AUTOMATION

E%A@ %esign@ Simulation@ Analysis@ erification@ !esting@ and Synthesis@ Manufacturing 6re6aration@ <ield

sol3ers@ <unctional 3erification@ #%# checB@ &hysical 3erification Manufacturing 6re6arationC MasB %ata

&re6aration@ Resolution Enhancement !echni-ues@ $6tical &ro8imity #orrection@ MasB generation@ !est

6attern generation@ =IS!@ Signoff@ <ormatsC netlist@ G%SII@ Ger5er@ $ASIS@ E%I<@ %E<@ LE< and S%<

OVERVIE9 O EDA TOOLS

!ools for Analog and %igital LSI %esign@ LSI =acBend@ Layout tools@ &#= design and Layout tools@

!esting tools@ Shell scri6ts@ Mi8ed Signal %esign? Modelling@ Integration to #AE tools@ <eatures of E%A

toolsC L!S&I#E@ &S&I#E@ 'S&I#E@ NI Multisim@ Modelsim@ Lenoardo S6ectrum@ 2ilin8 ISE@ Ouartus@ Acti3e'%L@ Ri3iera@ ALIN!@ #adence@ Syno6sys@ Magic@ IRSIM@ gE%A@ netlist and G%SII 3ie1ers@ Auto!ra8@ I&

&roducts@ A%S

SYNT5ESIS AND SIMULATION

Synthesis and simulation using '%Ls?Logic synthesis using erilog and '%L@ Memory and <SM synthesis@

&erformance dri3en synthesis@ Simulation? !y6es of simulation@ Static timing analysis <ormal 3erification@

S1itch le3el and transistor le3el simulation

CIRCUIT SIMULATION AND DESIGN

#ircuit simulation using S6ice ? circuit descri6tion@ A#@ %# and transient analysis@ Ad3anced s6ice commands

and analysis@ Models for diodes@ transistors and $&AM&@ %igital 5uilding 5locBs@ AD%@ %DA and sam6le and

hold circuits@ %esign and analysis of mi8ed signal circuits@

ANALYSIS AND MODELLING O MI:ED SIGNAL8 SYSTEM DESIGN AND TESTING

Mi8ed signal circuit modelling and analysis using '%L AMS@ System design using System#? System#

models of com6utation@ #lassical hard1are modelling in system # <unctional modelling &arameteri>ed

modules and channels@ !est 5enches@ !racing and de5ugging

REFERENCES

+ M Se5astian Smith@ A66lication S6ecific Integrated #ircuitsH@ &earson@ *//9* M ' Rashid@ S6ice for #ircuits and Electronics using &s6iceH@ &rentice 'all@ *//.

0 ! GrdtBer@ et al@ System %esign 1ith System#H@ Klu1er@ *//.

. & Ashenden@ et al@ !he System %esignerJs Guide to '%L?AMSH@ Else3ier@ *//,

, EriB =run3and@ %igital LSI #hi6 %esign 1ith #adence and Syno6sys #A% !oolsH@ &earson@ */+/

ames $ 'am5len@ etal@ Ra6id 6rototy6ing of digital systemsH@ S6ringer? S$&# Edition@ *//4





ECE,1*2 SCRI#TING LANGUAGES 0OR VLSI DESIGN AUTOMATION

L ! & #

0 / / 0

SCRI#TING LANGUAGES

%efinition of scri6t@ Scri6ting #onte8t@ Shell scri6ts $3er3ie1 of Scri6ting Languages &ERL@ #GI@ =

Scri6t@ a3a Scri6t@ &ython@ Ru5y@ and !#L

#ERL8 INTERACING

$6erators@ Statements &attern Matching etc %ata Structures@ Modules@ $5;ects@ !ied aria5les@ Inter 6rocess

#ommunication !hreads@ #om6ilation and Line Interfacing

#ROGRAMMING IN #ERL8 TCL BASICS

%e5ugger Internal E8ternals &orta5le <unctions@ E8tensi3e E8ercises for &rogramming in &ERL@ !cLlanguage 5asics

#ROGRAMMING IN TCL

=asic commands@ #ontrol constructs@ Ad3anced constructs@ <ile ID$@ !cL a66lication in E%A tools@ tB and

1ish@ E8am6leC =acB?Annotating a erilog module

OT5ER LANGUAGES

=road %etails of #GI@ = Scri6t@ a3a Scri6t@ &ython@ Ru5y 1ith &rogramming E8am6les

REFERENCES

+ Randal L@ Sch1art> !om &hoeni8@ Learning &ERLH@ $reilly &u5lications@ *///

* Larry Fall@ etal@ &rogramming &ERLH@ $reilly &u5lications@ *///

0 !om #hristiansen@ Nathan !orBington@ &ERL #ooB5ooBH@ $reilly &u5lications@ *///





ECE,1** #5YSICAL DESIGN O VLSI CIRCUITSL ! & #

0 / / 0

INTRODUCTION TO VLSI TEC5NOLOGY

Layout Rules?#ircuit a5straction #ell generation using 6rogramma5le logic array transistor chaining@ Fein?

=erger arrays and gate matrices?layout of standard cells gate arrays and sea of gates@ field 6rogramma5le gate

array(<&GA)?layout methodologies?&acBaging?#om6utational #om6le8ity?Algorithmic &aradigms

#LACEMENT USING TO#;DO9N A##ROAC5

&artitioningC A66ro8imation of 'y6er Gra6hs 1ith Gra6hs@ Kernighan?Lin 'euristic? Ratio?cut? 6artition 1ith

ca6acity and iDo constraints <loor 6lanningC Rectangular dual floor 6lanning? hierarchical a66roach?

simulated annealing? <loor 6lan si>ing &lacementC #ost function? force directed method? 6lacement 5y

simulated annealing? 6artitioning 6lacement? module 6lacement on a resisti3e net1orB regular 6lacement?linear 6lacement

ROUTING USING TO# DO9N A##ROAC5

<undamentalsC Ma>e running? line searching? Steiner trees Glo5al RoutingC Se-uential A66roaches?

hierarchical a66roaches? multi?commodity flo1 5ased techni-ues? Randomised Routing? $ne Ste6 a66roach?

Integer Linear &rogramming %etailed RoutingC #hannel Routing? S1itch 5o8 routing Routing in <&GAC

Array 5ased <&GA? Ro1 5ased <&GAs

#ERORMANCE ISSUES IN CIRCUIT LAYOUT

%elay ModelsC Gate %elay Models? Models for interconnected %elay? %elay in R# trees !iming %ri3en

&lacementC Pero StacB Algorithm? Feight 5ased 6lacement? Linear &rogramming A66roach !iming %ri3ing

RoutingC %elay Minimi>ation? #licB SBe1 &ro5lem? =uffered #locB !rees Minimi>ationC constrained 3ia

Minimi>ation? unconstrained 3ia Minimi>ation? $ther issues in minimi>ation

SINGLE LAYER ROUTING8 CELL GENERATION AND COM#ACTION

&lanar su5set 6ro5lem (&S&) ? Single layer glo5al routing? Single Layer Glo5al Routing? Single Layer

detailed Routing? Fire length and 5end minimi>ation techni-ue $3er the #ell ($!#) Routing? Multi6le chi6

modules (M#M) ? &rogramma5le Logic Arrays? !ransistor chaining? Fein?=urger Arrays? Gate matri8

layout? +% com6action? *% com6action

REFERENCES

+ Saraf>adeh@ #K Fong@ An Introduction to LSI &hysical %esignH@ McGra1 'ill@ +99,

* &reas M Loren>atti@ &hysical %esign and Automation of LSI systemsH@ =en;amin #ummins

&u5lishers@ +994

0 =an Fong@ etal @ Nano #M$S #ircuit and &hysical %esignH Filey *//.

. NA Sher1ani@ Algorithms for LSI &hysical %esign AutomationH@ Klu1er Academic@ *//*

, Sadi- M Sait@ 'a5i5 "oussef@ LSI &hysical %esign Automation@ !heory and &racticeH Forld

Scientific &u5lishing #om6any@ *//0

=ryan ! &reas@ &hysical %esign Automation of LSI systemH@ =en;amin #ummins &u5lishers@ +994






ECE,1*4 CAD OR VLSI CIRCUITSL ! & #

0 / / 0

VLSI DESIGN MET5ODOLOGIES

Introduction to LSI %esign methodologies@ Re3ie1 of %ata structures and algorithms@ Re3ie1 of LSI

%esign automation tools@ Algorithmic Gra6h theory and #om6utational com6le8ity@ !racta5le and Intracta5le

6ro5lems@ General 6ur6ose methods for com5inatorial o6timi>ation

DESIGN RULES

Layout #om6action@ %esign rules@ &ro5lem formulation@ Algorithms for constraint gra6h com6action@

&lacement and 6artitioningC #ircuit re6resentation@ &lacement algorithms@ &artitioning

LOOR #LANNING8 ROUTING

<loor 6lanning conce6ts@ sha6e functions and floor 6lan si>ing@ !y6es of local routing 6ro5lems@ Area routing@

#hannel routing@ Glo5al routing@ Algorithms for glo5al routing

SIMULATION

Simulation@ Gate?le3el modelling and simulation@ S1itch?le3el modelling and simulation@ #om5inational

Logic Synthesis@ =inary %ecision %iagrams@ !1o Le3el Logic synthesis

MODELLING AND SYNT5ESIS

'igh le3el synthesis@ 'ard1are models@ Internal Re6resentation@ Allocation@ Assignment and scheduling@

Sim6le scheduling algorithm@ Assignment 6ro5lem@ 'igh le3el transformations@ &hysical %esign Automation

of <&GAs@ M#Ms

REFERENCES

+ S' Gere>@ Algorithms for LSI %esign AutomationH@ Filey@ *//*

* NA Sher1ani@ Algorithms for LSI &hysical %esign AutomationH@ Klu1er Academic@ *//*






ECE,1*, 0#GA BASED SYSTEM DESIGN

L ! & #

0 / / 0

#GA UNDAMENTALS

Introduction to ASI#s and <&GAs@ <undamentals in %igital I# design@ <&GA and #&L% architectures@ <&GA

de3elo6ment 5oard hard1are and ID$ features@ <&GA 6rogramming technologies@ <&GA logic cell structures@

<&GA 6rogramma5le interconnect and ID$ 6orts@ %o1nloading design to <&GA 5oard@ NiosII &rocessor

soft1are de3elo6ment@ Nios II 'ard1are design

#GA IM#LEMENTATION

<&GA im6lementation of #om5inational circuits@ Se-uential design and hierarchy@ <&GA im6lementation of

se-uential circuits@ !iming issues in <&GA synchronous circuits@ <&GA core li5rary functions@ erilog '%L@

%esign flo1 using erilog '%L@ Using erilog '%L for synthesis of hard1are

ARC5ITECTING S#EED8 AREA8 #O9ER

Architecting s6eed@ Architecting area@ architecting 6o1er@ high le3el design@ #locB domains@ %esign

e8am6lesC AES@ I*S 3s S&%I<@ State machine designC !he electric train controller@

#GA CIRCUITS

Arithmetic circuits@ Im6lementing Math functions@ E8am6le designC <&U@ %S& a66lications@ Reset circuits@

#oding for synthesis@ direct digital fre-uency synthesiser im6lementation@ E8am6le designC Secure 'ash

algorithm@ synthesis o6timi>ation@ GA dis6lay using <&GA@ Interfacing &SD* Key5oard and mouse@ %igital

ID$ interfacing standards

#GA DESIGN

<&GA Micro6rocessor design@ %esign of S%RAM controller@ %esign of half tone 6i8el con3erter@ %esign of

A%SL modem@ %esign of Soft1are Radio@ RIS# designC Synthesis of MI&S core@ &rogramming <&GA in

electronics systems@ dynamically reconfigura5le systems@ $6erating system su66ort for So&# design

REFERENCES

+ Fayne Folf@ <&GA?=ased System %esignH@ &rentice 'all@ *//.

* Ste3e Kilts@ Ad3anced <&GA %esignH@ Filey@ *//.

0 ames $ 'am5len@ etal@ Ra6id 6rototy6ing of digital systemsH@ S6ringer? S$&# Edition@ *//4





ECE,1* GENETIC ALGORIT5MS AND ITS A##LICATIONS

L ! & #

0 / / 0

GA TERMINOLOGY

Introduction@ <inding the 5est solution@ Minimum seeBing algorithms@ Natural o6timi>ation methods@

=iological $6timi>ation@ GA !erminology@ Sim6le (=inary coded) GA@ Steady State Algorithm@ Genetic

$6erators@ Selection@ #rosso3er@ Mutation@ <itness scaling@ In3ersion@ GA E8am6le

GA OR VLSI DESIGN

GA for LSI %esign@ Layout and !est automation ? 6artitioning@ automatic 6lacement@ routing technology

ma66ing for <&GA@ Automatic test generation@ &o1er estimation

#ARTITIONING8 #LACEMENT8 ROUTING

&artitioning algorithm@ !a8onomy@ #ircuit 6artitioning 5y GA@ 'y5rid genetic algorithm for Ratio?cut

6artitioning@ GA for Standard cell 6lacement and MA#R$ #ell &lacement

ROUTING8 #GA TEC5NOLOGY MA##ING8 TESTING

Glo5al routing@ <&GA technology ma66ing@ automatic test generation

#O9ER ESTIMATION8 #ARALLEL IM#LEMENTATIONS8 TY#ES O GA

GA for 6eaB 6o1er estimation@ &arallel im6lementation of GA@ &ro5lem encoding@ fitness function@ !y6es of

GA@ GA &arameters@ Genetic Algorithms 3s #on3entional algorithms

REFERENCES

+ &inaBi Ma>umder@ EMRudnicB@ Genetic Algorithm for LSI %esign@ Layout and test

AutomationH@ &rentice 'all@ *//4

* Randy L 'au6t@ Sue Ellen 'au6t@ &ractical Genetic AlgorithmsH@ Filey@ *//.

0 Ricardo Sal Pe5ulum@ etal@ E3olution ElectronicsC Automatic %esign of electronic #ircuits and

Systems Genetic AlgorithmsH@ #R# 6ress@ *//

. ohn RKo>a@ etal@ Genetic &rogramming Automatic 6rogramming and Automatic #ircuit

SynthesisH@ MI! &ress@ +999





ECE,1*/ O#TIMI<ATION MET5ODS 0OR ENGINEERING DESIGN

L ! & #

0 / / 0

LINEAR #ROGRAMMING

Linear 6rogramming formulation Gra6hical and sim6le8 methods =ig?M method !1o 6hase method

%ual sim6le8 method &rimal %ual 6ro5lems

UNCONSTRAINED ONE DIMENSIONAL O#TIMI<ATION TEC5NI6UES

Unconstrained one dimensional o6timi>ation techni-ues ? Necessary and sufficient conditions Unrestricted

search method ? <i5onacci and Golden section method Ouadratic inter6olation@ cu5ic inter6olation and

direct root methods

UNCONSTRAINED DIMENSIONAL O#TIMI<ATION TEC5NI6UES

Unconstrained n dimensional o6timi>ation techni-ues direct search methods Random search methods

&attern search methods ? Rosen5rocBJs method ? %escent methods ?Stee6est descent@ con;ugate gradient@

Ouasi ? Ne1ton methods

CONSTRAINED O#TIMI<ATION TEC5NI6UES

#onstrained o6timi>ation !echni-ues ? Necessary and sufficient conditions E-uality and ine-uality

constraints ? Kuhn?!ucBer conditions ? Gradient 6ro;ection method?cutting 6lane method? 6enalty function

method

DYNAMIC #ROGRAMMING

%ynamic 6rogramming &rinci6le of o6timality recursi3e e-uation a66roach a66lication to shortest route@

cargo?loading@ allocation and 6roduction schedule 6ro5lems

REFERENCES

+ <o8@ R L@ $6timi>ation methods for Engineering %esign Q@ Fesley@ +979

* Rao S S@ $6timi>ation C!heory and A66licationH@ Filey@ *//9

0 !aha@ 'A@ $6erations ResearchC An IntroductionH@ &rentice 'al@ *//4





ECE,1*+ ADVANCED MICRO#ROCESSORS AND MICROCONTROLLERS

L ! & #

0 / / 0

MICRO#ROCESSOR ARC5ITECTURE

$rgani>ation and Architectural <eatures of Micro6rocessor and Micro #ontrollers@ Instruction Set@ %ata

formats@ Addressing modes@ Memory hierarchy register file@ #ache@ irtual memory and 6aging@

Segmentation? 6i6elining the instruction 6i6eline 6i6eline ha>ards RIS# 6rinci6les RIS# 3ersus #IS#@

$3er3ie1 of 4/4D4/44@ I=M &# Architecture@ MASM? assem5ler directi3e@ real mode@ 6rotected mode@

%&MI ser3ices

5IG5 #ERORMANCE CISC ARC5ITECTURE – #ENTIUM

#&U Architecture@ Salient features@ =us o6erations@ &i6elining@ Instruction !ranslation@ Instruction !ranslation

LooB aside =uffer and =ranch &rediction@ <loating &oint Unit@ $6erating Modes@ Ra6id E8ecution Module@Memory Su5system@ &aging@ MultitasBing@ 'y6er threading !echnology@ E8tended Instruction set in

Ad3anced &entium &rocessors@ &rogramming the &entium 6rocessor

5IG5 #ERORMANCE RISC ARC5ITECTURE – ARM

$rgani>ation of #&U@ =us architecture@ Memory management unit@ Registers@ #urrent &rogram Status

Register@ &i6eline@ ARM instruction set@ !hum5 instruction set@ Addressing modes@ &rogramming the ARM

6rocessor

E8ce6tion 'andling@ Interru6ts@ Interru6t 'andling schemes@ <irm1are@ Em5edded $6erating Systems@

#aches?#ache Architecture@ #ache &olicy@ %S& on the ARM7!%MI@ ARM9!%MI@ Strong ARM@ ARM9E@

ARM+/E@ Em5edded ARM A66lications

#ICMICROCONTROLLERS

&I# MicrocontrollerC Architectural $3er3ie1@ Memory $rgani>ation@ %ata Memory and <lash Memory@

Instruction set@ Interru6ts and Reset@ ID$ &orts@ !imer@ I *# Interfacing@ &FM@ UAR! and Analog to %igital

#on3erters

INTERACING8 BUS STANDARDS

Interfacing of memory de3ices@ %ata transfer techni-ues and ID$ 6orts Interfacing of Bey5oard and dis6lay

de3ices@ &rogramma5le Interru6t and %MA controllers@ Standards for =us architectures and 6ortsC ISA =us@

EISA =us@ M#A =us@ &#I =us@ ESA =us@ AG&@ US=@ IEEE+09.@ RS*0*?#@ RS.*0?A@ RS?..9@ RS?0@

I%E@EI%E@A!A@ A!A&I and S#SI@ S#SI Ada6ter@ &#M#IA #ards and Slots@ IEEE+*4.@ IEEE.44

REFERENCES

+ %aniel !a5aB @ Ad3anced Micro6rocessorsH@ !ata McGra1 'ill@ *///

* ames L AntonaBos@ !he &entium Micro6rocessorH@ &earson Education@ +997

0 Ste3e <ur5er@ ARM System $n #hi6 architectureH@ Addison Fesley@ *///

. =arnett@ #o8 and $J#ull@ Em5edded # &rogramming and the Microchi6 &I#H !homson@ *//7

, ohn =&eatman@ %esign 1ith &I# MicrocontrollerH@ &rentice 'all@ +997

al3ano@ Em5edded Microcom6uter SystemsQ@ !homson@ *//+

7 =adri Ram@ Ad3anced Micro6rocessor and InterfacingH@ !ata McGra1 'ill@ *//7





ECE,1*) DS# ARC5ITECTUREL ! & #

0 / / 0

DS# UNDAMENTALS

%igital signal?6rocessing system@ Sam6ling 6rocess@ discrete time se-uences@ Linear time?in3ariant systems@

%<!@ <<!@ %igital filters@ %ecimation and inter6olation@ Analysis #om6utational accuracy@ Num5er formats

for signals and coefficients in %S& systems@ %ynamic Range and &recision@ Sources of error in %S&@ %S&

#om6utational errors@ AD%@ %DA #on3ersion Errors@ #om6ensating filter

ARC5ITECTURES OR #ROGRAMMABLE DS# DEVICES

=asic Architecture@ %S& #om6utational =locBs@ Multi6lier and Multi6lier accumulator@ Modified =us

Structures and Memory access in &?%S&s@ Multi6le access@ Multi?6orted memory@ LIF architecture@

&i6elining @ S6ecial Addressing modes@ Address Generation Unit@ $n chi6 &eri6herals

#ROGRAMMABLE DIGITAL SIGNAL #ROCESSORS

!MS0*/#,2@ !MS0*/#02 &R$#ESS$RSC Architecture@ synta8@ Addressing modes@ Instructions@ &i6eline

structure@ $6eration@ =locB %iagram of %S& starter Bit@ A66lication &rograms for 6rocessing real time signals

IM#LEMENTATION O BASIC DS# ALGORIT5MS

%esign tool for %S& Systems MA!LA=@ %S& Assem5ler and the Assem5ly Source <ile@ LinBer and Memory

Allocation@ # #om6iler@ #ode #om6oser Studio@ !he IEEE7,. O notation@ =it?Re3ersed inde8 generation@

$3erflo1 and scaling@ <IR <ilters@ IIR <ilters@ inter6olation <ilters@ %ecimation filters@ &I% #ontroller@

Ada6ti3e <ilters@ *?% Signal &rocessing@ #om6utation of signal s6ectrum

ADVANCED #ROCESSORS8 ADS# #ROCESSORS

Architecture of !MS0*/#2@ Architecture of Motorola %S&,022@ #om6arison of the features of %S&

family 6rocessors@ <&GA =ased %S& system design@ Architecture of A%S&?*+22 and A%S&?*+/22 series of

%S& 6rocessors@ Addressing modes and assem5ly language instructions

REFERENCES

+ =enBataramani@ M=hasBar@ %igital Signal &rocessorsC Architecture@ &rogramming and

A66licationsH@ !ata McGra1 'ill@ */+/

* A3tar Singh@ S Srini3asan@ %igital signal 6rocessing im6lementationsC using %S& micro6rocessors(1ith e8am6les from !MS0*/#,.88)H@ *//.

0 Falt Kester (Editor)@ Mi8ed?signal and %S& %esign !echni-uesH@ Else3ier@ *//*

. &hil La6sley@ etal@ %S& &rocessor <undamentalsC Architectures and <eaturesH@ Filey@ *///

, onathan (") Stein@ %igital Signal &rocessingC A #om6uter Science &ers6ecti3eH@ Filey@ *///

S K Mitra@ %igital Signal &rocessingC A #om6uter =ased A66roachH@ !ata McGra1 'ill@ */+/





ECE,140 ADVANCED COM#UTER ARC5ITECTUREL ! & #

0 / / 0

OVERVIE9 O COM#UTER ARC5ITECTURE

%igital logic@ 'FDSFD<F allocation@ $rgani>ation and architecture@ #om6uter e3olution and &erformance@

#om6uter com6onents@ #om6uter function@ Interconnect structures@ =us interconnection@ &#I

COM#UTER SYSTEM

Memory management and hierarchy@ #achesC associati3ity@ allocation and re6lacement 6olicies@ su5?5locB

6lacement Multile3el caches@ #ache 6erformance issues@ Uni6rocessor cache coherency issuesC self?

modifying code@ 6eri6herals@ address translation@ Si8 5asic cache o6timi>ations@ Ele3en Ad3anced

o6timi>ations of #ache 6erformance@ irtual memory@ irtual memory 6rotection and e8am6les@ irtual

memory and 3irtual machines@ #ross cutting issues@ AM% $6teron memory hierarchy

CENTRAL #ROCESSING UNIT

#om6uter arithmetic@ ISAC functions@ addressing modes and formats@ com6arisons@ Role of com6iler@ MI&S@

&rocessor structure and function@ RIS#@ #IS# architectures@ RIS# 3s #IS# architectures com6arison@ RIS#@

#IS# &rocessor s and o3er3ie1

INSTRUCTION LEVEL #ARALLELISM

Instruction Le3el &arallelism ? o3er coming data ha>ards? reducing 5ranch costs high 6erformance

instruction deli3ery@ Su6erscalar 6rocessors@ LIF@E&I#@ Itanium? architectures@ Instruction 6i6elining@ $ut?

of?order e8ecution@ Register naming@ S6eculati3e e8ecution@ =ranch 6rediction@ IL&C 'ard1are 3s Soft1area66roach@ Limits on IL&@ Memory Le3el &arallelism@

MULTI#ROCESSORS8 T5READ LEVEL #ARALLELISM

Multi6rocessors and !hread Le3el &arallelism@ #ontrol unit and o6eration@ Interlea3ed memory architecture@

Symmetric shared memory architectures@ %istri5uted shared memory ? synchroni>ation@ Symmetric

multi6rocessors@ =us?5ased snoo6ing 6rotocol design s6ace@ #ache coherence@ Scala5le shared memory@

$6en M& and M&I@ MESI 6rotocol@ #lusters@ NUMA@ ector com6uting@ Simultaneous multithreading (hy6er

threading)@ and 3ector instruction sets (such as SSE and A2)@ Gra6hics 6rocessors and Multicore com6utersC

SIM!@ the #U%A and $6en#L 6rogramming models

REFERENCES LIMIT BOOKS

+ Filliam Stallings@ %igital #om6uter $rgani>ation and ArchitectureC %esigning for &erformanceH@

4th Edition@ &earson@ */+/

* ohn L 'ennessy@ %a3id A &atterson@ #om6uter ArchitectureC A Ouantitati3e A66roachH@

.th Edition@ Else3ier (Morgan Kufmann Series)@ */+/

0 Kai '1ang@ Naresh ot1ani@ Ad3anced #om6uter ArchitectureC &arallelism@ Scala5ility and

&rogramma5ilityH@ !ata McGra1 'ill@ */+/

. ohn 'ayes@ #om6uter Architecture and $rgani>ationH@ !ata McGra1 'ill@ */+/

, %a3id #uller@ & Singh@ Anoo6 Gu6ta@ &arallel #om6uter ArchitectureC A 'ard1areDSoft1are

A66roachH@ Else3ier (Morgan Kufmann Series)@ *//,

Nicholas #arter@ Ra; Kamal@ #om6uter Architecture and $rgani>ationH@ !ata McGra1 'ill(Schaums $utline Series)@ *//9





ECE,141 VIDEO AND AUDIO #ROCESSINGL ! & #

0 / / 0

DS# UNDAMENTALS

%igital signal?6rocessing system@ Signal re6resentation@ Sam6ling 6rocess@ A%# architectures@ %iscrete time

se-uences@ Ouanti>ation of %iscrete time se-uences@ %<!@ <<!@ <ast con3olution and filtering@ <ast matri8

com6utations@ %igital filters@ %ecimation and inter6olation@ Statistical signal 6rocessing@ !ime?fre-uency and

Multirate signal 6rocessing

S#EEC5 #ROCESSING

&hysiology of s6eech generationC characteristic of s6eech sounds s6eech 6roduction models@ linear 6rediction

analysis@ s6ectral en3elo6es a66lications of L& analysis@ S6eech codingC #oders attri5utes 1a3eform coding

3ocoders analysis?5y?synthesis coding code?e8cited linear 6redicti3e 3ocoder regular 6ulse?e8cited L&#

IMAGE #ROCESSING

%igital image re6resentation and 3isual 6erce6tion@ Image enhancement@ Image coding and com6ression

techni-ues@ #odec e8am6les@ Image analysis and segmentation@ !hreshold@ Image re6resentation and

descri6tionC =oundary descri6tor #haincode <ourier descri6tor SBeletoni>ing !e8ture descri6tor Moments@

Stereosco6ic image 6rocessing@ Still image com6ression@ Image 6rocessing soft1are and data5ases

AUDIO #ROCESSING

=asic digital audio 6rocessing techni-ues@ %ithering Noise sha6ing@ %A#@ E-uali>ation@ %igital Audio

com6ression@ Am6litude masBing !em6oral masBing Fa3eform coding &erce6tual coding #oding

techni-uesC Su5 5and coding and !ransform coding #odec e8am6les

VIDEO #ROCESSING

%igital 3ideo formats@ =asic digital 3ideo 6rocessing techni-uesC Motion estimation Interframe filtering

Motion?com6ensated filtering Error concealment@ ideo coding techni-ues@ =locB?5ased motion estimation

and com6ensation #oding techni-ues@ #odec e8am6les

REFERENCES

+ i;ay Madisetti (Ed)@ !he %igital Signal &rocessing 'and5ooBH@ *nd Edition@ #R# &ress@ *//9

* A K ain@ <undamentals of digital image 6rocessingH@ &rentice 'all@ *//90 =en Gold@ Nelson Morgan@ S6eech and Audio Signal &rocessingH@ Filey@ *//.

. La1rence RRa5iner@ RFSchaffer@ %igital &rocessing of S6eech signalsH@ &rentice 'all@ *//9

, ames L <lanagan etal@ S6eech Analysis Synthesis and &erce6tionH@ S6ringer?erlag@ *//4

AM !eBal6@ %igital ideo &rocessingH@ &rentice 'all@ *//,

7 A L =o3iB(Editor)@ 'and5ooB of Image and ideo &rocessingH@ Else3ier@ *//,





ECE112 R0 MICROELECTRONICS C5I# DESIGN

L ! & #

0 / / 0

INTRODUCTION TO R DESIGN AND 9IRELESS TEC5NOLOGY

%esign and A66lications@ #om6le8ity and #hoice of !echnology@ =asic conce6ts in R< designC Nonlinearly

and !ime ariance@ Intersym5ol interference@ random 6rocesses and noise@ Sensiti3ity and dynamic range@

con3ersion of gains and distortion

R MODULATION8 R TESTING

Analog and digital modulation of R< circuits@ #om6arison of 3arious techni-ues for 6o1er efficiency@

#oherent and non?coherent detection@ Mo5ile R< communication and 5asics of Multi6le Access techni-ues@

Recei3er and !ransmitter architectures@ %irect con3ersion and t1o?ste6 transmitters@ R< testing for

heterodyne@ 'omodyne@ Image re;ection@ %irect I< and su5 sam6led recei3ers

B7T AND MOSET BE5AVIOR AT R RE6UENCIES

=! and M$S<E! 5eha3ior at R< fre-uencies@ modelling of the transistors and S&I#E model@ Noise

6erformance and limitations of de3ices@ integrated 6arasitic elements at high fre-uencies and their monolithic

im6lementation

R LO9 NOISE AM#LIIER8 MI:ERS DESIGN

$3er3ie1 of R< <ilter design@ Acti3e R< com6onents modeling@ Matching and =iasing Net1orBs@ =asic

5locBs in R< systems and their LSI im6lementation@ Lo1 noise Am6lifier design in 3arious technologies@

%esign of Mi8ers at G'> fre-uency range@ arious mi8ers? 1orBing and im6lementation@

R OSCILLATORS8 RE6UENCY SYNT5ESI<ER8 #O9ER AM#LIIER DESIGN

$scillators? =asic to6ologies #$ and definition of 6hase noise@ Noise 6o1er and trade off@ Resonator #$

designs@ Ouadrature and single side5and generators@ Radio fre-uency Synthesi>ers? &LLS@ arious R<

synthesi>er architectures and fre-uency di3iders@ &o1er Am6lifier design@ Li5erali>ation techni-ues@ %esign

issues in integrated R< filters@ Nonlinearly and !ime ariance@ intersym5ol Interference@ random 6rocesses

and Noise@ %efinitions of sensiti3ity and dynamic range@ con3ersion Gains and %istortion

REFERENCES

+ =Ra>a3i@ R< MicroelectronicsH@ &rentice?'all@ +994* !' Lee@ %esign of #M$S Radio?<re-uency Integrated #ircuitsH@ #am5ridge &ress@ *//.






ECE11* SYSTEM;ON;C5I# DESIGN

L ! & #

0 / / 0

INTRODUCTION TO SOC8 SYSTEM LEVEL DESIGN

S$# !echnology #hallenges@ Microsystems technology and a66lications@ S$# com6onents@ =! Modelling

1ith =I#@ M$S !ransistor Model for Mi8ed Analog?digital #ircuit %esign and Simulation@ Retargeta5le

A66lication?dri3en Analog?digital =locB %esign@ System le3el design@ System le3el s6ace and modelling

languages@ S$# 5locB 5ased design and I& assem5ly

SOC ISSUES AND #O9ER MANAGEMENT

S$# Issues@ S$# %esign Methodology@ &o1er #onsiderations@ S$# #ase study@ %esign #onsideration

#hallenges@ Memories@ &arameteri>ed S$# @ S$# &eri6heral #ores@ S$# and interconnect centric

Architectures@ System le3el 6o1er management@ Em5edded soft1are modelling and design using 6erformancemetrics to select micro6rocessor for I# design@ %esign Reuse

MICRO;ARC5ITECTURE DESIGN AND #O9ER O#TIMI<ATION

Micro?architecture design@ #ycle accurate system le3el modeling@ &erformance e3aluation@ Micro

architectural 6o1er estimation o6timi>ation@ %esign 6lanning S$# 6rotocols@ $#@ SI@ !arget architecture

models@ Intra?chi6 communication@ !asB time measurement@ Interconnect latency modeling@ =acB annotation

of lo1er le3el timing to high?le3el models@ Synthesis of S$# com6onents

SOT9ARE DESIGN VERIICATION

Logical 3erification@ %esign and erification languages@ %igital simulation@ using transactional@ le3el models

in an S$# design@ Assertion 5ased 3erification@ 'ard1areDSoft1are #o?%esign@ System Le3el@ =locB Le3el

and 'ard1areDSoft1are #o?3erification

5ARD9ARE DESIGN VERIICATION

S$# com6onentsC emulation@ co?simulation@ &hysical erification@ 'ard1are acceleration emulation@

<ormal 6ro6erty 3erification@ !ES!@ %<!@ A!&G@ Analog and mi8ed signal test @ I& #ore %esign issues@ I&

#ore %esign Methodology@ Reusa5ility and intellectual 6ro6erty@ I& #ore A66lications

REFERENCES

+ Louis Scheffer@ Grant Martin@etal@ E%A for I# System 3erification and !estingH@ #R#@ *//* &raBash RashniBar@ etal@ System?$n?A?#hi6 erification methodology and techni-uesH@ Klu1er

Academic@ *//,

0 =ada1y@ Fael ulien@ etal@ (Eds)@ System?on?#hi6 for Real?!ime A66licationsH@ S6ringer@ *//0

. Reis@ Ricardo@ etal (Eds)@ %esign of Systems on a #hi6C %esign and !estH@ S6ringer@ *//7

, Ricardo Reis@ A G ess@ %esign of System on a #hi6 %e3ices and #om6onentsH@ S6ringer@ *//7

Al5erto Sangio3anni incentelli@ Sur3i3ing the S$# Re3olutionC A Guide to &latform 5ased

%esignH@ Klu1er Academic@ *//0





DCN CODE R0 MEMS

L ! & #

0 / / 0

S9ITC5ING

R< MEMS relays and s1itchesC S1itch 6arameters@ Actuation mechanisms@ =ista5le relays and micro

actuators@ %ynamics of s1itching o6eration

MEMS INDUCTORS AND CA#ACITORS

MEMS inductors and ca6acitorsC Micro machined inductor@ Effect of inductor layout@ Modeling and design

issues of 6lanar inductor@ Ga6 tuning and area tuning ca6acitors@ %ielectric tuna5le ca6acitors

MEMS COM#ONENTS

MEMS 6hase?shiftersC !y6es Limitations@ S1itched delay lines@ Micro machined transmission lines@ co6lanar lines@ Micro machined directional cou6ler and mi8er

ILTERS

Micro machined R< filtersC Modeling of mechanical filters@ Electrostatic com5 dri3e@ Micromechanical filters

using com5 dri3es@ Electrostatic cou6led 5eam structures

ANTENNAS

Micro machined antennasC Micro stri6 antennas design 6arameters@ Micromachining to im6ro3e

6erformance@ Reconfigura5le antennas

REFERENCES

+ Karadan@ etal@ R< MEMS and their A66licationsH@ Filey@ *//0

* '%elos Santos@ R< MEMS circuit %esign for Fireless #ommunicationsH@ Artech house@ *//*

0 GMRe5ei>@ R< MEMS !heory@ %esign and !echnologyH@ Filey@ *//0





ECE11, EMBEDDED SYSTEMS

L ! & #

0 / / 0

UNDAMENTALS TO EMBEDDED SYSTEMS

%efinition and #lassification $3er3ie1 of &rocessors and 'ard1are Units in an Em5edded System

Soft1are Em5edded into the System E8em6lary Em5edded Systems Em5edded Systems on a #hi6 (S$#)

and the Use of LSI %esigned #ircuits

EMBEDDED #ROCESSOR AND COM#UTING #LATORM

Em5edded hard1are 5uilding 5locBs@ Em5edded 5oard@ Em5edded 6rocessors@ ARM 6rocessor? 6rocessor and

memory organi>ation@ %ata o6erations@ <lo1 of #ontrol@ S'AR# 6rocessor? Memory organi>ation@ %ata

o6erations@ <lo1 of #ontrol@ 6arallelism 1ith instructions@ =oard 5uses@ #&U =us configuration@ ARM =us@

S'AR# =us@ =oard Memory@ =oard ID$@ %e3ice dri3ers

DEVICES AND BUSES OR DEVICES NET9ORK

ID$ %e3ices %e3ice ID$ !y6es and E8am6les Synchronous IS$synchronous and Asynchronous

#ommunications from Serial %e3ices E8am6les of Internal Serial#ommunication %e3ices UAR! and

'%L# &arallel &ort %e3ices So6histicated interfacing features in %e3icesD&orts !imer and #ounting

%e3ices I*#J US=J #ANJ and Ad3anced ID$ Serial@ 'igh S6eed =uses ISA &#I &#I 2 #&#I

and Ad3anced 5uses

EMBEDDED #ROGRAMMING

&rogramming in Assem5ly Language (AL&) 3s 'igh Le3el Language # &rogram Elements Macros and

<unctions Use of &ointers NULL &ointers Use of <unction #alls Multi6le <unction #alls in a #yclic

$rder in the Main <unction &ointers <unction Oueues and Interru6t Ser3ice Routines Oueues &ointers

#once6ts of EM=E%%E% &R$GRAMMING in # $5;ected $riented &rogramming Em5edded

&rogramming in # #J &rogram com6ilers #ross com6iler $6timi>ation of Memory #odes

REAL TIME O#ERATING SYSTEMS

Em5edded o6erating systems (R!$S)@ Middle1are and a66lication soft1are @ $S Ser3ices Interru6t

Routines 'andling !asB Scheduling Models 'andling of !asB Scheduling and Latency and %eadlines as

&erformance Metrics Inter &rocess #ommunication and Synchroni>ation Shared %ata &ro5lem Use of

Sema6hore(s) &riority In3ersion &ro5lem and %eadlocB Situations Inter &rocess #ommunications using

Signals Sema6hore <lag or Mute8 as Resource Bey Message Oueues Mail5o8es &i6es irtual(Logical) SocBets R&#s

REFERENCES

+ Ra;Bamal@ Em5edded Systems Architecture@ &rogramming and %esignH@ !ata McGra1 'ill@ *//0

* %a3id E Simon@ An Em5edded Soft1are &rimerH@ &earson@ *///

0 Fayne Folf@ #om6uters as #om6onentsC &rinci6les of Em5edded #om6uting System %esignH@

Morgan Kaufman &u5lishers@ *//4

. aneFS Liu@ Real?!ime systemsH@ &earson@ *///





ECE11 LO9 #O9ER VLSI DESIGN

L ! & #

0 / / 0

#O9ER DISSI#ATION

Need for Lo1 6o1er design@ Sources of 6o1er dissi6ation@ &hysics of 6o1er dissi6ation in M$S<E!s@ &o1er

dissi6ation in #M$S@ #M$S leaBage current@ %esign for Lo1 6o1er dissi6ation@ =asic 6rinci6les of lo1

6o1er design@ #ircuit techni-ues for leaBage 6o1er reduction@ Lo1 6o1er design limits

#O9ER ESTIMATION

Simulation 6o1er analysis@ &ro5a5ilistic 6o1er analysis@ &o1er estimationC #ircuit@ Logic

DESIGN O LO9 #O9ER CIRCUITS

%esign and test of lo1 3oltage #M$S circuits@ S6ecial techni-ues@ Lo1 6o1er SRAM architectures@Architecture and systems@ Ad3anced !echni-ues

SYNT5ESIS8 SOT9ARE DESIGN OR LO9 #O9ER

Synthesis for lo1 6o1er@ Lo1 energy com6uting using energy reco3ery techni-ues@ Soft1are design for lo1

6o1er

LO9 #O9ER SYSTEM DESIGN

Lo1 3oltage lo1 6o1er adders@ Lo1 3oltage lo1 6o1er multi6liers@ Lo1?oltage Lo1?&o1er Read?$nly

Memories@ Large Lo1?&o1er LSI System %esign and A66lications

REFERENCES

1. Gary K "ea6@ &ractical lo1 6o1er digital LSI designQ@ S6ringer@ *//*

* K Seng "eo@ KaushiB Roy@ Lo1 oltage@ Lo1 &o1er LSI Su5systemsH@ !ata McGra1 'ill@ *//9

3. KaushiB Roy@ Sharat &rasad@ Lo1?&o1er #M$S LSI #ircuit %esignH@ Filey@ *///





NANOELECTRONICS

L T P C

3 0 0 3

BASIC SOLID STATE PHYSICS, SHRINK-DOWN APPROACHES

Energy bands, Localized particles, Organic compounds, Semiconductor materials and building

blocks, CMOS scaling, anoscale MOS!ET, Limits o" scaling # Constant electric "ield scaling, $rain

currents at present limits o" scaling, Small Size Limits "or t%e MOS!ET, ano#!ET dri&e currents, n#

and p# MOS!ET de&ices 'it% ( nm C%annel lengt%, )lternati&e to *ulk Silicon+ *uried Oide *O-,

Strain Engineering, *enzene Molecule as a !ield E""ect Transistor

NANO PHYSICS

Properties o" indi&idual nanoparticles, anoscale Materials and .uantum Mec%anics, T%ree#

$imensional /*ulk materials, T'o#$imensional Systems, One#$imensional, 1ero#$imensional

/.uantum 2ires, $ots, Energy Le&els o" a /Semiconductor .uantum $ot and &arieties,

Lit%ograp%ically $e"ined .uantum $ots, Epitaially Sel"#)ssembled .uantum $ots, Colloidal

.uantum $ots, Optical Properties o" .uantum $ots, Metal anoparticles, .uantum bits, .uantum

computation, Metal nanoclusters, Semiconducting nanoparticles, Carbon molecules, Carbon

clusters, Carbon nanotubes

LOGIC DESIGN IN NANOSPACE

Logic design in spatial dimensions, Met%odology, Eample+ %ypercube structure o" %ierarc%al

!P)s, anoelectronic de&ices, $igital nanoscale circuits, Molecular electronics, Operational limits

o" nanoelectronic de&ices, *asics o" logic design in nanospace

EMERGING DEVICE TECHNOLOGIES

.uantum Transport $e&ices *ased on 4esonant Tunneling, Single#Electron de&ices "or logic

applications, Superconductor digital electronics, .uantum Computing using Superconductors ,

.uantum Cellular )utomata5s /.C)s, Carbon nanotubes "or data processing

NANO MACHINES AND NANO DEVICES

Memories implemented based on Emerging $e&ices, P%otonic et'orks, Li6uid Crystal $isplays,

Organic Lig%t Emitting $e&ices, ano#Electro Mec%anical Systems /EMSs

REFERENCES

78 4ainer 2aser /Editor, 9anoelectronics and :n"ormation Tec%nology+ )d&anced ElectronicMaterials and o&el $e&ices;, 2iley, <00(

<8 Ed'ard L8 2ol", 9.uantum anoelectronics+ )n :ntroduction to Electronic anotec%nology and .uantum Computing;, 2iley, <00=

38 Mic%ael )8 ielsen, :saac L8 C%uang, 9.uantum Computation and .uantum :n"ormation;,Cambridge >ni&ersity Press, <070

?8 Mic%ael C8 Petty, 9Molecular Electronics+ !rom Principles to Practice;, 2iley, <00@(8 Ao%n B8 $a&ies, 9T%e P%ysics o" Lo'#dimensional Semiconductors+ )n :ntroduction;,

Cambridge >ni&ersity Press, 7==@8 Sergey Ed'ard Lys%e&ski et8al8, 9Logic $esign o" ano:Cs;, C4C Press, <00

D8 Sergey Ed'ard Lys%e&ski et8al8, 9Molecular Electronics, Circuits, and Processing Plat"orms;,C4C Press, <00D





ECE11/ EMI AND COM#ATIBILITY IN SYSTEM DESIGNL ! & #

0 / / 0

EMI ENVIRONMENT

%efinition of EMI and EM# 1ith e8am6les@ #lassification of EMIDEM# ? #E@ RE@ #S@ RS@ Units of

&arameters@ Sources of EMI@ EMI cou6ling modes ? #M and %M@ ES% &henomena and effects@ conducted

and radiated EMI@ !ransient EMI 6henomena and su66ression@ !ime domain 3s <re-uency domain EMI@

Emission and immunity conce6ts

EMI COU#LING #RINCI#LES

#onducted@ Radiated and !ransient #ou6ling@ #ommon im6edance ground #ou6ling@ Radiated common mode

and ground Loo6 cou6ling@ Radiated differential mode cou6ling@ Near field ca5le to ca5le cou6ling@ &o1er

mains and &o1er su66ly cou6ling

EMI>EMC STANDARDS AND MEASUREMENTS

#i3ilian standards ? <##@#IS&R@IE#@EN@ #S@ #E and RE Standards@ Military standards ? MIL S!%

.+%D.*@ EMI !est Instruments DSystems@ EMI Shielded #ham5er@ $6en Area !est Site@ !EM #ell@

SensorsDIn;ectorsD#ou6lers@ !est 5eds for ES% and E<!@ Military !est Method and &rocedures (.*)@ =asic

6rinci6les of RE@ #E@ RS and #S measurements@ EMI measuring instruments? Antennas@ LISN@ <eed through

ca6acitor@ current 6ro5e@ EM# analy>er and detection techni-ue o6en area site@ shielded anechoic cham5er@

!EM cell@ <re-uency assignment ? s6ectrum con3ersation

EMI CONTROL TEC5NI6UES

Shielding@ <iltering@ Grounding@ =onding@ EMI gasBet@ Isolation transformer@ o6to?isolator@ !ransient

su66ressors@ #a5le routing and connection@ Signal #ontrol@ #om6onent selection and mounting

EMC DESIGN O #CBs

&#= !race routing@ #ross talB@ Im6edance control@ &o1er distri5ution decou6ling@ Poning@ Mother5oard

designs and &ro6agation delay 6erformance models

REFERENCES

+ #layton R&aul@ Introduction to Electromagnetic #om6ati5ilityH @ Filey@ *//

* F &rasad Kodali@ Engineering Electromagnetic #om6ati5ilityC &rinci6les@ Measurements@!echnologies@ and #om6uter ModelsH@ Filey ? IEEE &ress@ *//+

0 =ernhard Keiser@ &rinci6les of Electromagnetic #om6ati5ilityH@ Artech 'ouse@ +947

. 'enry F$tt@ Electromagnetic #om6ati5ility EngineeringH@ Filey@ *//9





ECE11+ VLSI SIGNAL #ROCESSINGL ! & #

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DS# SYSTEMS8 IR ILTERS

%S& systems@ &rograms@ A66lications@ Re6resentation@ %ata flo1 gra6hs@ Loo6 =ound and Iteration =ound@

Algorithms@ Iteration =ound of Multirate %ate?flo1 gra6hs@ &i6elining of <IR filters@ &arallel &rocessing of

<IR filters@ &i6elining and &arallel &rocessing for Lo1 &o1er

RETIMING8 SYSTOLIC ARC5ITECTURE DESIGN

Retiming 6ro6erties@ a66lications@ Sol3ing ine-uality systems@ Retiming techni-ues@ Unfolding?algorithm@

a66lication@ 6ro6erties@ #ritical 6ath@ <olding transformation@ !echni-ues@ <olded architectures@ <olding of

Multirate systems@ Systolic architecture design methodology@ <IR systolic arrays@ Scheduling 3ector@ Matri8?

Matri8 multi6lication@ Systolic design for s6ace re6resentations 1ith delaysAST CONVOLUTION8 IIR ILTERS

<ast con3olution algorithms@ Iterated@ #yclic #on3olutions@ %esign 5y Ins6ection@ &arallel <IR <ilters@ %#!

and In3erse %#!@ &arallel architectures for ranB ?order filters@ &i6eline interlea3ing in digital filters@ &i6elining

in +st?order and higher?order IIR %igital <ilters@ &arallel 6rocessing for IIR <ilters@ #om5ined 6i6elining and

6arallel 6rocessing for IIR <ilters@ Lo1 6o1er IIR filter design using 6i6elining and 6arallel 6rocessing@

&i6elined ada6ti3e digital filters

SCALING AND ROUND O NOISE8 BIT;LEVEL ARIT5METIC ARC5ITECTURE

Scaling and Round off noise@ State 3aria5le descri6tion@ Scaling and Round?off noise com6utation@ Round off

noise in 6i6elined IIR filters@ Round off noise com6utation using state 3aria5le@ Slo1?%o1n@ Retiming@ and&i6elining@ <ast 5inary adders and multi6liers@ &arallel multi6liers@ Interlea3ed floor 6lan and 5it 6lane

designed filters@ =it?serial multi6liers@ =it?serial filter design and im6lementation@ #anonic Signed %igit

arithmetic@ %istri5uted arithmetic@ Redundant arithmetic

NUMERICAL STRENGT5 REDUCTION8 LO9 #O9ER DESIGN

Su5 e86ression elimination@ Multi6le #onstant Multi6lication@ Su5 e86ression sharing@ Additi3e and

multi6licati3e num5er s6litting@ Synchronous 6i6elining and clocBing styles@ #locB sBe1@ and clocB

distri5ution@ Fa3e 6i6elining@ #onstraint s6ace diagram@ Im6lementation@ Asynchronous 6i6elining@ Signal

!ransition Gra6hs and its a66lication@ Im6lementation of com6utational units@ Lo1 6o1er design@ &o1er

analysis@ &o1er estimation@ &o1er reduction

REFERENCES

+ K K &arhi@ LSI %igital Signal &rocessing SystemsC %esign and Im6lementationH@ Filey@ *//9

2. M Ismail and ! <ie>@ Analog LSIC Signal and Information &rocessingH@ McGra1?'ill@ *//.





ECE11) VLSI CIRCUIT DESIGN MET5ODOLOGY

L ! & #

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INTRODUCTION

I# definition@ Re-uirements@ technologies@ goals@ a66roaches@ tasBs@ costs in I# design@ =asics of the #M$S

6rocess and de3ices@ #hallenges in LSI circuit design@ #ell?5ased ASI# design methodology@ Introduction to

usual design flo1s in I# design

BASIC ANALOG DESIGN LO9

%esign entry and 6arameteri>ation@ Simulation set?u6 and 6ost?6rocessing@ analog 5eha3ioural modelling and

simulation@ assisted full?custom layout@ &hysical 3erification@ &ost?layout simulation@ Statistical analysis@ !a6e

out

MI:ED SIGNAL DESIGN LO9

%esign entry and floor 6lanning@ &artitioning@ Mi8ed?simulation@ set?u6@ Net list generation@ Mi8ed?mode

5acB annotation@ #o?simulation

BASIC DIGITAL DESIGN LO9

%esign entry and functional simulation@ automated synthesis and o6timi>ation@ Semi custom layoutC

automated 6lace and route@ =acB annotation and 6ost layout simulation@ Integration into full custom design

flo1

ADVANCED DIGITAL DESIGN LO9

!iming dri3en synthesis@ !iming dri3e 6lace and route@ Lo1 6o1er synthesis flo1@ #locB tree generation@

Introduction to Linear !ime ariant (L!) analysis@ L! analysis@ L! A# and transfer function analysis@

L! s?6arameters and noise analysis@ &assi3es@ &acBaging

REFERENCES

+ Liming 2iu@ LSI #ircuit %esign Methodology %emystifiedC A #once6tual !a8onomyH@ Filey?

IEEE 6ress@ *//7

* EriB =run3and@ %igital LSI #hi6 %esign 1ith #adence and Syno6sys #A% !oolsH@ &earson@ */+/

0 ames $ 'am5len@ etal@ Ra6id 6rototy6ing of digital systemsH@ S6ringer? S$&# Edition@ *//4

. Kenneth S Kunder@ !he %esigners Guide to S&I#E and S6ectreH@ Klu1er Academic@*//,

mtech vlsi syllabus old

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