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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2011.

Multi-/Many-core Modeling at FreescaleDavid Murrell, Jim Holt, Michele Reese

TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2011.

Perspective: Virtual Platform ROI

Schedules: SW and HW available on “day 1” becoming an industry expectation• FSL P4080 – Linux kernel boots on 1st silicon, within 2 days of receiving DS

boards• MOT P4080 – Software development enabled 1 year before silicon• XBOX360 and PS3 – OS kernels boot on 1st silicon within 2 weeks of

receiving first eval boards (IBM’s Mambo software VP)• Growing demand from customers• Evidenced by recent trends in industry strategic acquisitions

Quality: VP is the proving ground for complex HW/SW interactions• Both HW and SW are improved while still in formative stages (it’s not just

that SW has a running start) – functionality, usability and performance• Gain insight into pathological effects, and intercept them before solutions

become costly Typically 20-30 studies conducted per critical path IP block Verified bit and cycle-level accuracy is essential

2


Virtual Platform Consumers

3

Virtual Platforms

Verification &Validation

Debuggers, Tools/Partners

ArchitecturalDesign/

Exploration

Marketing/FAEs

Performance Analysis

Software Enablement

NPI Next GenerationDefinition

• Ecosystem development

• Pre-Si test bringup

• Reference • μ-arch analysis

• Tradeoff analysis

• Pre-Si BSP/SDK bringup

• μCode development

• Virtual DS• PRL

assessment• Proof/bench

development

• Customer SW bringup

• Demos

Primary Use Case

Functional

Performance

Hybrid

• Performance assurance

• Bake-offs


Plat

4

Concept thruPlanning Execution ProductionNPI ALE ALF TO

Trace

CornerstonePlatform

uBoot

Bare MetalPlatform

Linux

Linux SystemPlatform

Cycle

Func

CornerStone Exploration αPerformance

βPerformance

αFunctional

βFunctional


Technology Improvement Strategy

Scale UP Continue to optimize single-thread performance• Continue to leverage “JIT” (DBT) Technologies• OK for partial core cluster configurations

Scale OUT Migrate to distributed simulation platforms: multi-cores and multi-machine clusters• Explore transition to “COREMU” (or similar)• Assess the potential of the MIT Graphite platform

Possibilities to facilitate native execution for dedicated “sim farms”• FSL’s VortiQa UTM

Inexpensive (low $100’s per compute node) 32-bit e500v2 (with SPE) configuration (P2020UTM) 64-bit e5500 configuration (P5020UTM)

• Combine with Graphite for multi-UTM simulation cluster Port PIN or DynamoRIO to support Power ISA


What we’ve done with graphite so far

We’ve been using it in the context of the Angstrom project• Ported graphite to Redhat Linux• Learned overall system architecture & how to add syscalls• Lesson learned:

• Syscalls - when you bring new application code into graphite it will sometimes include unsupported syscalls

• If you see runtime message from graphite: “Unhandled syscall number ### …” then you can typically identify the offending syscall by going here and looking up the reported number: http://asm.sourceforge.net/syscall.html

Currently working on a cycle & power accurate Angstrom tile model using Freescale e200 cores

• goal is to integrate with graphite for Angstrom –related research

http://asm.sourceforge.net/syscall.html�


Porting to Redhat Linux

In common/Makefile.common change KERNEL to ETCH

Remove -Werror flag from all Makefiles (there are several warnings about classes with virtual functions that do not have virtual destructors)

There are a couple of instance of "invalid use of sizeof operator" in pin/handle_syscalls.cc, these are easy to fix

In common/misc/moving_average.h call of overloaded 'pow' is ambiguous.* line 120 changed UInt32 curr_window_size to Int curr_window_sizexxx

TM

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2011.

BACKUP


Customer Expectations: Functional Virtual Platform

9

High speed functional execution (programmer’s view of the system): • Model the behavior to arrive at the

correct result• 10’s of MIPS per core at a minimum

Evaluation board replacement:• Functional fidelity: firmware, OS,

drivers, and applications run without modification

• Linux console

Enhanced debug environment:• Source-level: CodeWarrior, GDB, etc.• Low-level: core/device registers, TLB’s,

disassembly, memory• Rich breakpoint/watchpoint support• Event callbacks (triggers)• Full system checkpoint/restore• Python command shell• Linux/Windows-32/64 hosts


Customer Expectations: Performance Virtual Platform

10

System-level cycle accurate models• Model the behavior and the number of cycles

consumed by the operation• Cores, caches, memory controllers,

interconnects, accelerators, data path, devices

Executes un-modified binaries and traces• Fast-forward to points of interest via checkpoints

and/or “gear-shifting”

Verified cycle-timing fidelity• Accurate to within 10% of hardware logic• Models micro-architectural structures and policies• Comprehensive set of system performance

metric data

Rich data visualization• Source-code traceability (multicore and

hypervisor aware)• Custom plots• System activity heat maps• Live display and data replay

Flexible instrumentation and control points• Event breakpoints• Event callbacks (triggers)• Application control of the simulator via specially-

encoded instructions


Performance Analysis and Design Exploration Flow

11

S&A

S&A: SoC Systems, S&A + PcP: Core+MSS

Select Workloads

Func Model

Port, Test, and Debug

Perf Model

Pre-ALF Measurements

Emulator

Post-ALF Measurements

Eval Boards

Post-Si Measurements

Analyze Data

Perf Model

Investigate Anomalies

Summary Analysis Report

Perf ModelExperimental

Design Alternatives

Design Improvements

EGFEPRL uBoot Linux

Bare Metal andLinux Platforms

Analysis Plan

Cornerstone, Bare Metal and

Linux PlatformsuBoot Linux

Traces


Verification Flow

12

HW Verification Flow Model Verification Addendum

Verification Plan

Specs

Develop Test

Cases

Func Model

Debug Test Cases

uBoot

Bare Metal Platform

Emulator

Execute Test Cases

Eval Boards

Execute Test Cases

RTL Simulator

Execute Test Cases

Function

Verify Bit Accuracy

Timing

Calibration

uBoot

Compare

Bare Metal Platform

Test Suites

Model Fixes

Verif TMT IPS&A


Software Development Flow

13

SWPRL

DevelopuBoot Func Model

Debug and Test

Function

Debug and Test

uBoot

Hypervisor

FM Microcode

Drivers USDPAA Linux VortiQa

TimingRace

Conditions & Optimize

Function

Debug and Test

uBoot

TimingRace

Conditions & Optimize

Linux

Bare Metal Platform Linux Platform

IP SW

IP: Drivers & Microcode


Embedded Reference Flow

14

PetraStampede

Func Model

Test and Debug

uBoot

Bare Metal Platform

Petra Platform

Func Model

Reference

Petra

Eval Board

a11

a223

a34

a4

b1b2b3b4

5678

Vcc10

GND0

Si

TMT

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