multiphase and control solutions · 2020. 10. 22. · vr14 smart power stage 4x5 industry standard...
TRANSCRIPT
TI Confidential – NDA Restrictions
Multiphase and Control Solutions
Multiphase and Control Solutions (MCS)
MCS: VR Controllers, Powerstages, DDR power, Sequencers 3V-60V Vin, up to 500A Iout, 90A Power Stages Processor power, DDR power, SVID/AVS/PMBus/PVID, Sequencing, Monitoring and Control up to 32 rails
• Complete 2-in-1 Vddq + Vtt solution
• Stand-alone DDR Vtt LDOs
• Fully JEDEC compliant
• Up to DDR4 specs; DDR5 in dev
• Lowest number of Vtt MLCCs
• Small footprint (as small as 2x2)
TPSM831D31 8-14V, 120A+40A PMBus
Dual Output Module
• 3 to 32 rails, Analog/Digital
• Blackbox fault logging
• PMBus Sequencing, Monitoring, Margining, Telemetry
• Easy-to-use Fusion GUI
TPS536C7 12-phase buck design (450A) Intel VR14 TPS53689 CPU SVID EVM
ENSW
PGOOD
PH
BOOT
PVIN
PGND
ENLDO
ILIM VDDQSNS
COMP VTT
VTTGND
VTTSNS
VIN
VLDOINSS/TR
VSNS
VDDQ
VI
VTT
VTTREF
AGND
RT/CLK VTTREF
VI
PowerPAD
TPS54116-Q1
Sequencers DDR Power Solutions
Multiphase Buck Controllers and Power Stages
Industrial PC
Video Surveillance
Rack Servers
DataCenter Switch
ADAS Domain Controller
Cluster
Rack Servers
MicroServers
HW Accelerators
Network Attach Storage
DataCenter Switch
Campus/Branch Switch
Base Station (BBU)
Router
ADAS Domain Controller
Front Sensor Fusion
Oscilloscope
Wireless Comm Test
Defense Radio
Radar
Video Surveillance
DataCenter Switch
Rack Servers
Base Station (BBU)
Router
ADAS Domain Controller
Cluster
TI Confidential – NDA Restrictions
Multiphase Roadmap
TI Multiphase DCAP+ PMBus VR Solution Roadmap for FPGA and ASIC Platforms
12
Vin
M
ult
iph
as
e
Production
Development
Definition
Status
TPS53647/667
Single
4/6 phases, PMBus,
Pinstrap
TPS53681
Dual
6+2 phases, PMBus
2015 2017 2020
TPS536C7
PMBus
Dual
N+M ≤ 12ph Samples now
RTM 4Q20
TPS53676
AVSBus, PMBus
Dual N+M, 7-
phases Samples now
RTM 1Q21
4
2021-2022 Definition
12V TPSM831D31
Module 12mm
Dual 120A+40A Samples now
RTM1Q21
12V 4.8mm Catshark Module
Dual 80A+80A
TPS53688
PMBus/VR13H.C
SVID
Dual N+M, 8- phases Samples now
RTM 4Q20
16
So
urc
e D
ow
n
Sm
art
Po
we
r S
tag
e
Production
Development
Status
CSD95372/3/8B VR12.5 Smart Power Stage 5x6
Smart Power Stage Roadmap
<2020 2020 Definition
CSD95410 (90A)
VR14 Smart Power Stage
5x6 Industry Standard
Package
CSD9549x VR13 Smart Power Stage
4x5, 5x6 Proprietary Packages
CSD9548x VR13 Smart Power Stage
5x6 Industry Standard Package
CSD95485 (75A)
VR13HC Smart Power Stage
5x6 Industry Standard Package
2021-2022
CSD95484 (25A)
VR13HC Smart Power Stage
4x5 Industry Standard Package
CSD95420/21 (50A/40)
VR14 Smart Power Stage
4x5 Industry Standard Package
Samples Now
RTM 4Q20
Stacked Clip QFN
Gen2.1/2.2
5x6 Hotrod
Stacked Clip QFN
Gen2.3
5x6
CSD96415 (80A)
25V Smart Power Stage
5x6 Industry Standard Package Samples 1Q21
RTM 3Q21
CSD96416 (50A)
25V Smart Power Stage
5x6 Industry Standard Package Samples 1Q21
RTM 4Q21
CSD95411 (60A)
VR14 Smart Power Stage
5x6 Industry Standard Package Samples 2Q21
RTM 2Q22
CSD95430 (90A)
Active Current Sharing
Smart Power Stage
5x6 Industry Standard Package Samples 2Q21
RTM 1Q22
TI Confidential – NDA Restrictions
DCAP+ Control
Buck Converter Basics
• Alternately turn on Q1 and Q2 so Average VSW = VOUT
• Average VSW is set by duty cycle using negative feedback
• Feedback can use VOUT or VOUT & IL defines control mode
• Feedback then adjusts one of either (ton or toff) or tsw, holding the other constant defines control
scheme
• Control Mode +Control Scheme e.g. Fixed Frequency Voltage Mode Control
• Lossless in theory 7
VIN
tON tSW
VSET H(s)
→
Average Model
𝐷 × 𝑉𝐼𝑁 = 𝐼𝐿 × 𝑅𝑃 + 𝑉𝑂𝑈𝑇
Temporal Aspect of Control
• Identical duty cycle can be achieved by modulating on time, off time or frequency
• Leading or trailing edges can be modulated
• All these methods can be used to control voltage, current or both
– “Fixed Frequency, Leading Edge, Voltage Mode Control”
– “Constant On Time Current Mode Control” 8
VOUT2
VOUT1
9
Hysteretic Mode, Controlling Frequency
• Duty cycle set by average VOUT
• On time has to change as VOUT and VIN change to maintain fixed frequency
VIN
tON tSW
VSET H(s)
10
DCAP1: Adaptive On-Time Modulator • Adaptive Constant On-Time Control
“ON” time set by Controller
•Adapts to Line, Load and Output Voltage
•“Constant” Steady-State Frequency
VIN
fSW
Hysteretic COT
DCAP1 𝑡𝑂𝑁 =
𝑉𝑂𝑈𝑇
𝑉𝐼𝑁× 𝑅 × 𝐶
𝑓𝑆𝑊 =1
𝑅 × 𝐶
R1
R2
Cout
L1
M1
M2
Loop comparator
ref
Vout
VFB
ControlLogic
&Driver RLDRVL
DRVH
On-timegenerator
VIN
Vout VIN
LL
Iload
D-CAP mode keeps on-time
constant.
D-CAP mode keeps on-time
constant in load transition
although cycle time varies .
Tcyc
A B C
Inductor current iL
Red : average inductor current (Load current)
LL
Tcyc Tcyc
A
B C
Ex. Vin=12V, Vout=1.2V, SWfreq=350kHz ,
On-time keeps 280ns in constant load
and load transition.
Fig 12 .D-CAP mode load transient
Fig 13 .D-CAP mode block diagram
DCAP (1-Phase) Load Transient Behavior
Dynamic Phase Add/Shed Improves Efficiency
12
Phase Change Current Thresholds
Load Line : Saves Power, Improves transient
14
Fixed Frequency Peak Current Mode Control
ADVANTAGES
Fast response to input voltage changes
Single-pole compensation
Inherent current limiting
Easier Stacking
DISADVANTAGES
Sensitive to current spikes (noise)
Two feedback loops (voltage/current) required
Requires slope compensation
Requires large amount of output capacitance
VOUT
VIN
EAREF
VOUT
PWM
COMP
VES
R Q
LATCH
RSENSE
VS
CLOCK
CLOCK
VE
VS
LATCH
OUTPUT
Compen-
sation
(PID)
𝐼𝐿𝑃𝐾 ∝ 𝑉𝐸
𝑅𝑆𝐸𝑁𝑆𝐸
Current Mode: Loop Gain
15
𝑣 𝑓𝑏𝑘 = 𝑖 𝐿 × 𝑍𝑜𝑢𝑡
LG = 𝐻(𝑠) × 𝑍𝑜𝑢𝑡
𝐾𝑖 × 𝑅𝑆𝐸𝑁𝑆𝐸
𝑖 𝐿 =𝐻(𝑠)×𝑣 𝑖𝑛𝑗
𝐾𝑖×𝑅𝑆𝐸𝑁𝑆𝐸
• 1st Order: Loop Gain & Stability independent of inductance
• Accommodates Phase Add/Drop
16
Current Mode Control Stacking
EAREF
VOUT
VE
Compen-
sation
( PID)
VOUT
VIN
PWM
COMP
S
R Q
LATCH
R SENSE
VS
CLOCK
VOUT
VIN
PWM
COMP
S
R Q
LATCH
R SENSE
VS
CLOCK
𝐼𝐿𝑃𝐾 ∝ 𝑉𝐸
𝑅𝑆𝐸𝑁𝑆𝐸
• CM control naturally balances phase currents
D-CAP+ Smart Power Stage Utilization
17
• Integrated Drivers and Current Sense
saves PCB area and BOM cost over
discrete solution
– Increased power density
• Easier PCB Layout
• Integrated Current Sense Amp improves
accuracy
• Optimized Driver-FET configuration
– Lower driver parasitics
– Minimized dead-time
– Optimal efficiency
• Supplies Current Information including
Cycle Accurate Ripple
General (DCAP+) Multiphase Controller Topology
• Five Loops
– Valley Current
– Load Line
– Output Voltage Regulation
– Current Balancing
– Frequency Correction
• Dynamic Phase Add & Non Linear Transient Response 18
Green: Voltage Loop
Red: Current Loop
Yellow: Current Balancing Loop
Blue: Frequency Control Loop
TI Confidential – NDA Restrictions
Current Balancing in DCAP+
Estimating Current Imbalance
• Current Imbalance due to
– On time mismatch propagation delays, Cgs variations, Rg variations etc
– Resistance mismatch -> Process variation, PCB routing, thermal environments
• Duty cycle must be identical at the inductors for volts-sec balance!
Estimating Current Imbalance
∆𝐼𝑃𝐻 = 𝐼𝑃𝐻_𝑁𝑂𝑀 ×∆𝑅
𝑅𝐴𝑉+
𝑉𝐼𝑁 × ∆𝑡𝑂𝑁𝑡𝑆𝑊
𝑅𝐴𝑉
𝑉𝐼𝑁=12V, 𝑉𝑂𝑈𝑇 = 1V, 𝑓𝑆𝑊 = 600𝑘𝐻𝑧, 𝐼𝑃𝐻 = 50𝐴, 𝑅𝐸𝑄 = 1.02𝑚Ω,∆𝑅
𝑅𝐸𝑄 = 0.5, ∆𝑡𝑂𝑁=5ns
∆𝐼𝑃𝐻 = 𝐼𝑃𝐻 × 0.5 +12𝑉×
5𝑛𝑠
1.67µ𝑠
1.02𝑚Ω = 𝐼𝑃𝐻 × 0.5 +
12× 5𝑛𝑠
1.67µ𝑠
1.02𝑚Ω = (25A + 35A) for IPH=50A
• Severe Imbalance without correction
• Resistance mismatch term increases as phase current increases
𝑉𝐴𝑉 = 𝐼𝐴𝑉 × 𝑅𝐴𝑉
Phase Current Balancing Scheme • Generate 𝐼𝐴𝑉𝐺 =
∑𝐼𝑃𝐻
𝑁𝑃𝐻
• Compare IPH to IAVG
• Adjust ton to make IPH-IAVG~0
• View as Additional average voltage that
makes phase currents equal
• ∆𝑡𝑂𝑁 can be +ve or -ve
22
TI Confidential – NDA Restrictions
Thermal Balance Management
No Thermal Balance example 7ph 800kHz/120nH @ 175A Load with 10 min soak (no airflow)
Conventional Multiphase VR Design (Current balance, but no thermal balance)
24
Temperature difference between inner phases and outer phases could be >10oC
Thermal Balancing
• Adjustable scaling factor KT applied to
each phase current
• If current sharing gain G∞,
– 𝐾𝑇𝑖 × 𝐼𝑖 = 𝐼𝐴𝑉
–𝑰𝒊
𝑰𝒋=
𝑲𝑻𝒋
𝑲𝑻𝒊
• Increase 𝐾𝑇𝑖 to reduce 𝐼𝑖 and hence
balance temperature
• Thermal balance is open loop and not
based on temperature measurements.
• Set all gains = 1.0 to disable this feature
(it is 100% optional)
25
Thermal Balance (Patent Pending) 7ph 800kHz/120nH @ 175A Load with 10 min soak (no airflow)
26
Power stages/inductors temperature are well balanced. Temperature was lowered by ~5oC => Improve reliability and efficiency
Innovative Multiphase VR Design (Thermal balance with intended current unbalance)
Thermal Balance: System-Level Trade-Off
• Power stage temperature is equalized across the system
– Hottest power stage can operates cooler as a result.
– TI measurements show ~5 degC temperature reduction for hottest power stage
• Per-phase OCL does not get scaled by Thermal balance
– Phases with better thermal grounding (e.g. which are given more current than avg.) do not need
over-sized inductors or higher OCL than other phases.
– All phases protected from inductor saturation, all the time.
– No impact to transient response, unless phases trigger OCL. In designs with low margin, phases
given more current, can trigger OCL more quickly, leading to slightly more undershoot.
• DC Loadline is based on ISUM current no impact to DCLL
• AC Ripple Cancellation is still maintained Un-noticeable output ripple change
27
TI Confidential – NDA Restrictions
Flexible Phase Firing Order
Layout Order #1 #2 #3 #4 #5 #6 #7 #8
Firing Order #1 1 5 3 7 4 6 8 2
Firing Order #2 1 5 7 3 8 4 6 2
Firing Order #X 1~8 1~8 1~8 1~8 1~8 1~8 1~8 1~8
Flexibility of re-order firing sequence to optimize performance & cost
Improved input decoupling
Avoid adjacent phase noise coupling
Improved thermal and efficiency
Improved EMI
….
Flexible Firing Order & Design Optimization
Layout Order #1 #2 #3 #4 #5 #6 #7 #8
Firing Order #1 1 5 3 7 4 6 2
Firing Order #2 1 5 7 3 6 4 2
Firing Order #X 1~7 1~7 1~7 1~7 1~7 1~7 1~7
Flexible Phase Firing Order and Dynamic Phase Shedding
30
Flexible phase firing order can help to dissipate heat better without changing the
layout/placement of power stages/inductors
1ph @ 17A 2ph @ 35A 3ph @ 52A
Phase Configuration Command
31
Pin Name Channel PHASE Firing
Order
APWM1 A (PAGE 0) PHASE=0 0
APWM2 A (PAGE 0) PHASE=1 3
APWM3 A (PAGE 0) PHASE=2 1
APWM4 A (PAGE 0) PHASE=3 4
APWM5 / BPWM4 A (PAGE 0) PHASE=4 2
APWM6 / BPWM3 B (PAGE 1) PHASE=0 0
APWM7 / BPWM2 B (PAGE 1) PHASE=1 2
APWM8 / BPWM1 B (PAGE 1) PHASE=2 1
Example: 5 phases in PAGE 0, 3 phases in PAGE 1
Any firing order (“5+3 configuration”)
15 14 13 12 11 10 9 8
RW RW R R R R R R
PH_EN TURBO 0 0 PHASE
7 6 5 4 3 2 1 0
R R R RW RW RW RW RW
0 0 0 PAGE ORDER
Byte # Pin Byte0 Byte1
0-1 PWM1 0x80 0x00
2-3 PWM2 0x81 0x03
4-5 PWM3 0x82 0x01
6-7 PWM4 0x83 0x04
8-9 PWM5 0x84 0x02
10-11 PWM6 0x82 0x10
12-13 PWM7 0x81 0x12
13-14 PWM8 0x80 0x11
15-16 PWM9 X X
17-18 PWM10 X X
19-20 PWM11 X X
21-22 PWM12 X X
Enable
PHASE
PAGE
ORDER
BYTE0
BYTE1
TI Confidential – NDA Restrictions
PMBus Commands Support
32
PMBus Standard Commands
33
• OPERATION
• ON_OFF_CONFIG
• PAGE, PHASE
• PAGE_PLUS_WRITE/READ
• WRITE_PROTECT
• MASK_SMBALERT
• CAPABILITY
• STORE/RESTORE_USER
System Level
• STATUS_BYTE
• STATUS_WORD
• STATUS_CML
• STATUS_VOUT
• STATUS_IOUT
• STATUS_INPUT
• STATUS_TEMP
• STATUS_CML
• STATUS_PAGE+PHASE
Status Reporting
• MFR_ID
• MFR_MODEL
• MFR_REV
• MFR_SERIAL
• MFR_DATE
• IC_DEVICE_ID/REV
Inventory Management
• VOUT_OV_WRN/FLT/RSP
• VOUT_UV_WRN/FLT/RSP
• IOUT_OC_WRN/FLT/RSP
• IOUT_UC_FLT/RESP
• OT_WARN/FLT/RSP
• VIN_OV_WRN/FLT/RSP
• VIN_UV_WARN
• VIN_ON + OFF
• IIN_OC_WRN/FLT/RSP
• PIN_OP_WARN
• TONMAX WRN/FLT/RSP
Warn, Fault, Response
• READ_VIN
• READ_IIN
• READ_VOUT
• READ_IOUT
• READ_TEMP (Power Stage)
• READ_PIN
• READ_POUT
Telemetry
• VOUT_MODE
• VOUT_COMMAND
• TRIM + MARGIN
• VOUT_MIN
• VOUT_MAX
• VOUT_TRANSITION_RATE
VOUT Adjust
• TON_RISE, DELAY
• TOFF_FALL, DELAY
• TON/TOFF_MAX
Sequencing
• VOUT_DROOP
• FREQUENCY_SWITCH
• IOUT CAL GAIN/OFFSET
Calibration, Config
3.3V and 1.8V bias support, up to 1 MHz CLK speed
Mfr Specific Standard Commands
34
• COMPENSATION (USER_DATA_01)
• NONLINEAR (USER_DATA_02)
• PHASE_CONFIG (USER_DATA_03)
• DVID (USER_DATA_04)
• PHASE_SHED (USER_DATA_07)
• SVID CONFIG (USER_DATA_08)
• ISHARE (USER_DATA_10)
• MFR_PROTECTION (USER_DATA_11)
• MFR_CALIBRATION (USER_DATA_13)
Configuration Data
3.3V and 1.8V bias support, up to 1 MHz CLK speed
• STATUS_EXTENDED
• STATUS_PHASES
• COMMAND_LOG
• SIMULATE_FAULT
• DISABLE_FAULT
STATUS and Debug
• PIN_DETECT_OVERRIDE
• MISC_OPTIONS
• NVM_LOCK
Other
Loop Tuning Commands (1)
35
COMPENSATION_CONFIG
(USER_DATA_01)
NONLINEAR_CONFIG
(USER_DATA_02)
* * * * * * * * *
*
* *
*
Check these parameters for every design
Loop Tuning Commands (2)
36
DVID_CONFIG
(USER_DATA_04)
* *
* *
Check these parameters for every design
Dynamic Phase Shedding
37
ISUM (Peak) Rising
PH_ADD8
PH_ADD7
PH_ADD6
PH_ADD5
PH_ADD4
PH_ADD2
DPA_HYST8
DPA_HYST7
DPA_HYST6
DPA_HYST5
DPA_HYST4
DPA_HYST3
DPA_HYST2
PH_ADD3
ISUM (Avg) Falling
PH_ADD8
PH_ADD7
PH_ADD6
PH_ADD5
PH_ADD4
PH_ADD2
PH_ADD3
7*DPS_HYST
6*DPS_HYST
5*DPS_HYST
4*DPS_HYST
3*DPS_HYST
2*DPS_HYST
1*DPS_HYST1 to 2 Add threshold
2 to 3 add threshold
3 to 4 add threshold
4 to 5 add threshold
5 to 6 add threshold
6 to 7 add threshold
7 to 8 add threshold
1 ph
2 ph
3 ph
4 ph
5 ph
6 ph
7 ph
8 ph
8 to 7 drop threshold
1 ph
2 ph
3 ph
4 ph
5 ph
6 ph
7 ph
8 ph
7 to 6 drop threshold
6 to 5 drop threshold
5 to 4 drop threshold
4 to 3 drop threshold
3 to 2 drop threshold
2 to 1 drop threshold
Protection Configuration
38
* *
* *
Check these parameters for every design
TI Confidential – NDA Restrictions
High-Current PMBus Buck Modules
VIN: 8-14V – No additional VBIAS required
PMBus interface
Vout 1: 0.25V to 1.52V @120A
Vout 2: 0.25 to 1.52V @40A
DCAP+ control mode for significant reduction in output MLCCs
PMBus programming and monitoring of parameters
PMBus programmable internal loop compensation, Vout (for AVS),
soft start time, turn on/off delay, and boot up voltage
Differential Vout sensing for outstanding load regulation
On-chip non-volatile memory to store custom configurations
EN55011/22 tested for low EMC
Shock, Vibration, and PCB Co-planarity tested
1.5% Output Current and 1.2% Vout Telemetry Accuracy
+/- 0.5% Vref Accuracy w/ Remote Sense. 0.25V min at +/- 5mV
Save ~2W Power Dissipation at 1V @ 100A Iout
400KHz operating freq. Set from 350KHz to 700KHz w/ PMBus
48 x 15mm PCB open frame Design = 720mm2 of total area/240W
12mm high
Easy Layout
Ethernet Switches, Telecom Infrastructure, Wireless Infrastructure
Network Attach Storage
Test & Measurement
TPSM831D31: 8V-14V Input, 120+40A, DCAP+, PMBus Dual Output Module 12mm height
Features Benefits Single supply
Easy to use Dual Rail systems (ie ASIC core + ASIC I/O)
Powers ASICs, FPGAs, and overclocked DDR core
PMBus interface for configuration & Telemetry
Optimized for efficiency or power density
Accurate Monitoring saves power by allowing AVS to exact levels
GET proprietary technology for manufacturing robustness
Clapton Module Family Internal Phase Config Iout (1) Iout (2)
TPSM831D31 (3+1) 3+1 120A 40A
Application Diagram
Market Sectors
Features Benefits
PMBus
ASIC core
ASIC I/O
3-Phase (Internal)
1- Phase (Internal)
8V-14V VIN
0.25V-1.52V Vout/120A
0.25V-1.52V Vout/40A
Samples/EVMS now
Production 1Q21
TPSM831D31 powering Virtex Ultrascale+ VU5P-VU11P
41
• Dual output PMBus
module for VCCINT
and VCCBRAM rails
to simply Multiphase
dc/dc design
• Solution Size ≈
2.64in2 (1705 mm2)
• Efficiency 90-96%
for all rails* *See datasheets for details on
Vin, Vout, IL graphs
TPSM831D31 powering Virtex Ultrascale+ VU5P-VU11P
VIN: 8-14V – No additional VBIAS required
Vout 1: 0.25V to 1.52V/80A, up to 5Vout
Vout 2: 0.25 to 1.52V/80A, up to 5Vout
Gen 3 DCAP+ control for output capacitor reduction
PMBus programming and monitoring of parameters
PMBus programmable internal loop compensation, Vout adjustment
(for AVS), soft start time, turn on/off delay, and boot up voltage
Differential Vout sensing for outstanding load regulation
Frequency Synchronization
On-chip non-volatile memory for custom configurations
CISPR-11/32 tested for low EMC
Shock, Vibration, and PCB Co-planarity tested
2.5% Output Current and 1.2% Vout Telemetry Accuracy
+/- 0.5% Vref Accuracy w/ Remote Sense. 0.25V min at +/- 5mV
Save ~2W Power Dissipation at 1V @ 100A Iout with
loadline setting
400KHz operating freq. Set from 350KHz to 700KHz w/ PMBus
Open frame Design, 48x26, 4.8mm high
Easy Layout
Aerospace & Defnse
Ethernet Switches, Telecom Infrastructure, Wireless Infrastructure
Network Attach Storage
Test & Measurement
TPSM832D22: 8V-14V Input, 80A+80A, Dual Output, PMBus Module with 4.8mm height
Features Benefits Single supply
Easy to use Dual Rail systems (ie ASIC core + ASIC I/O)
Powers ASICs, FPGAs, and overclocked DDR core
PMBus interface for configuration & Telemetry
Optimized for efficiency or power density
Accurate Monitoring saves power by allowing AVS to exact levels
GET proprietary technology for manufacturing robustness
4.8mm Catshark Module Internal Phase Config Iout (1) Iout (2)
TPSM832D22 (first) 2+2 80A 80A
TPSM832D40 (second) 4+0 160A N/A
Application Diagram
Market Sectors
Features Benefits
PMBus
ASIC core
ASIC I/O
2-Phase (Internal)
2- Phase (Internal)
8V-14V VIN
0.25V-1.52V Vout/80A
0.25V-1.52V Vout/80A
1Q21
samples
TI Confidential – NDA Restrictions
Design Support Tools
45
Processor Power and Multiphase solutions
CPU/FPGA attach landing page
Multiphase PWM Buck Controller
selection landing page
46
Multiphase DC/DC Training Landing Page
47
Sequencer Training Landing Page
Selecting CPU and FPGA/ASIC Multiphase Controllers
49
Power Stage Landing Page
50
DDR Power Solution Attach Landing Page
• Search our DDR solutions catalog by
DDR type, Vin, Iout or Rails needed.
• Find quick and easy reference
designs for your DDR type.
• Find training videos, app notes and
other useful tools for developing and
selling DDR solutions.
Application Notes
FPGA TI Designs
Intel Stratix 10 GX (SG2800-I1V ) FPGA with Smart VID PMBus power design/ PMP20176
Tools & Resources
• PMP20176 Tools Folder
• Design Files: Schematics, BOM,
Gerbers, Test Report, Power Up
Instructions
• Device Datasheets: ‒ TPS53647
‒ CSD95472Q5MC
Target Applications
• Software Defined Radio
• Radar
• Network_Attached_Storage
• Test and Measurement
Features
• 4-phase power supply 0.9V/140A Arria 10 GX (SG2800-I1V
part number)
• PMBus programming of Vout, and Voltage Margining for Arria
Smart VID, 10mV per step
• PMBus monitoring of Input/Output Voltage, Current, Power,
and Temperature
• 88% efficiency at 12VIN, 0.9V/140A
Benefits
• Cut-and-paste, compliant solution for Altera Stratix 10 GX
• Easy design via PMBus for reduced development time, for
customers implementing Smart VID with PMBus using Altera
Quartus Prime software version 15.1
• Easy diagnostics, high reliability
• Supported by TI PMBus Fusion GUI
• Low power loss, high reliability
Xilinx Virtex Ultrascale+ VU5-13P, VU31-37P FPGA PMBus power design/ TIDA – 050020
Tools & Resources
• TIDA – 050020 Tools Folder
• Design Files: Schematics, BOM,
Gerbers, Test Report, Power Up
Instructions
• Device Datasheets: ‒ TPS53681
‒ CSD95490Q5MC
Target Applications
• Data center, campus, and branch switches, and routers
• Servers
• Hardware accelerator cards
• Network attached storage
Features
• 6-phase power supply 0.85V/200A – VCCINT core rail
• PMBus programming of Vout, and Voltage Margining
Adaptive Voltage Scaling (AVS)
• PMBus monitoring of Input/Output Voltage, Current, Power,
and Temperature
• ± 2% DC and AC tolerance
• 90.6% efficiency at 12VIN, 0.9V/200A
Benefits
• Cut-and-paste solution for Virtex Ultrascale+ FPGA core
• Easy design via PMBus for reduced development time, for
customers implementing Core rail AVS
• Easy diagnostics, high reliability
• Supported by TI PMBus Fusion GUI
• Low power loss, high reliability, low component count