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Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwiseunder any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A

Tel: 781/329-4700 www.analog.com

Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved

800 MHz, 50 mWCurrent Feedback Amplifier

FEATURES

Excellent Video Specifications (RL = 150 , G = +2)Gain Flatness 0.1 dB to 100 MHz0.01% Differential Gain Error0.025 Differential Phase Error

Low Power5.5 mA Max Power Supply Current (55 mW)

High Speed and Fast Settling880 MHz, 3 dB Bandwidth (G = +1)440 MHz, 3 dB Bandwidth (G = +2)1200 V/s Slew Rate10 ns Settling Time to 0.1%

Low Distortion65 dBc THD, fC = 5 MHz33 dBm Third Order Intercept, F1 = 10 MHz

66 dB SFDR, f = 5 MHzHigh Output Drive

70 mA Output CurrentDrives Up to 4 Back-Terminated Loads (75 Each)

While Maintaining Good Differential Gain/PhasePerformance (0.05%/0.25)

APPLICATIONSA-to-D DriversVideo Line DriversProfessional CamerasVideo SwitchersSpecial EffectsRF Receivers

1

2

3

4

8

7

6

5AD8001

NC NC

IN

NC

+IN

NC = NO CONNECT

OUT

V

V+

1VOUT

AD8001

VS

+IN

2

3 4

5 +VS

IN

GENERAL DESCRIPTIONThe AD8001 is a low power, high speed amplifier designedto operate on 5 V supplies. The AD8001 features unique

GAINdB

9

6

1210M 100M 1G

3

0

3

6

9

FREQUENCY Hz

VS = 5VRFB = 820

VS = 5V

RFB = 1k

G = +2

RL = 100

Figure 1. Frequency Response of AD8001

transimpedance linearization circuitry. This allows it to drivevideo loads with excellent differential gain and phase perfor-

mance on only 50 mW of power. The AD8001 is a currentfeedback amplifier and features gain flatness of 0.1 dB to 100 MHzwhile offering differential gain and phase error of 0.01% and

0.025. This makes the AD8001 ideal for professional videoelectronics such as cameras and video switchers. Additionally,the AD8001s low distortion and fast settling make it ideal forbuffer high speed A-to-D converters.

The AD8001 offers low power of 5.5 mA max (VS = 5 V) andcan run on a single +12 V power supply, while being capable ofdelivering over 70 mA of load current. These features make thisamplifier ideal for portable and battery-powered applications

where size and power are critical.

The outstanding bandwidth of 800 MHz along with 1200 V/sof slew rate make the AD8001 useful in many general-purposehigh speed applications where dual power supplies of up to 6 Vand single supplies from 6 V to 12 V are needed. The AD8001 isavailable in the industrial temperature range of 40C to +85C.

Figure 2. Transient Response of AD8001; 2 V Step, G = +2

8-Lead PDIP (N-8),

CERDIP (Q-8) and SOIC (R-8)

5-Lead SOT-23-5

(RT-5)

FUNCTIONAL BLOCK DIAGRAMS
http://www.analog.com/http://www.analog.com/

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AD8001SPECIFICATIONS (@ TA = + 25C, VS = 5 V, RL = 100 , unless otherwise noted.)AD8001A

Model Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE3 dB Small Signal Bandwidth, N Package G = +2, < 0.1 dB Peaking, RF = 750 350 440 MHz

G = +1, < 1 dB Peaking, RF = 1 k 650 880 MHzR Package G = +2, < 0.1 dB Peaking, R F = 681 350 440 MHz

G = +1, < 0.1 dB Peaking, RF = 845 575 715 MHz

RT Package G = +2, < 0.1 dB Peaking, RF = 768 300 380 MHzG = +1, < 0.1 dB Peaking, RF = 1 k 575 795 MHzBandwidth for 0.1 dB Flatness

N Package G = +2, R F = 750 85 110 MHzR Package G = +2, R F = 681 100 125 MHzRT Package G = +2, R F = 768 120 145 MHz

Slew Rate G = +2, VO = 2 V Step 800 1000 V/sG = 1, VO = 2 V Step 960 1200 V/s

Settling Time to 0.1% G = 1, VO = 2 V Step 10 nsRise and Fall Time G = +2, VO = 2 V Step, RF = 649 1.4 ns

NOISE/HARMONIC PERFORMANCETotal Harmonic Distortion f C = 5 MHz, VO = 2 V p-p 65 dBc

G = +2, RL= 100 Input Voltage Noise f = 10 kHz 2.0 nV/HzInput Current Noise f = 10 kHz, +In 2.0 pA/Hz

In 18 pA/HzDifferential Gain Error NTSC, G = +2, R L= 150 0.01 0.025 %Differential Phase Error NTSC, G = +2, R L= 150 0.025 0.04 DegreeThird Order Intercept f = 10 MHz 33 dBm1 dB Gain Compression f = 10 MHz 14 dBmSFDR f = 5 MHz 66 dB

DC PERFORMANCEInput Offset Voltage 2.0 5.5 mV

TMINTMAX 2.0 9.0 mVOffset Drift 10 V/CInput Bias Current 5.0 25 A

TMINTMAX 35 A+Input Bias Current 3.0 6.0 A

TMINTMAX 10 AOpen-Loop Transresistance VO = 2.5 V 250 900 k

TMINTMAX 175 k

INPUT CHARACTERISTICSInput Resistance +Input 10 M

Input 50 Input Capacitance +Input 1.5 pFInput Common-Mode Voltage Range 3.2 VCommon-Mode Rejection Ratio

Offset Voltage VCM = 2.5 V 50 54 dBInput Current VCM = 2.5 V, TMINTMAX 0.3 1.0 A/V+Input Current VCM = 2.5 V, TMINTMAX 0.2 0.7 A/V

OUTPUT CHARACTERISTICSOutput Voltage Swing R L= 150 2.7 3.1 VOutput Current R L= 37.5 50 70 mAShort Circuit Current 85 110 mA

POWER SUPPLYOperating Range 3.0 6.0 VQuiescent Current TMINTMAX 5.0 5.5 mAPower Supply Rejection Ratio +VS = +4 V to +6 V, VS = 5 V 60 75 dB

VS = 4 V to 6 V, +VS = +5 V 50 56 dBInput Current TMINTMAX 0.5 2.5 A/V+Input Current TMINTMAX 0.1 0.5 A/V

Specifications subject to change without notice.

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ABSOLUTE MAXIMUM RATINGS1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 VInternal Power Dissipation @ 25C2

PDIP Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3 WSOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8 W8-Lead CERDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.1 WSOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . . 0.5 W

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VSDifferential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 1.2 VOutput Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating CurvesStorage Temperature Range N, R . . . . . . . . . 65C to +125COperating Temperature Range (A Grade) . . . 40C to +85CLead Temperature Range (Soldering 10 sec) . . . . . . . . . 300CNOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.2Specification is for device in free air:

8-Lead PDIP Package: JA = 90C/W8-Lead SOIC Package: JA = 155C/W8-Lead CERDIP Package: JA = 110C/W5-Lead SOT-23-5 Package: JA = 260C/W

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by theAD8001 is limited by the associated rise in junction tempera-ture. The maximum safe junction temperature for plasticencapsulated devices is determined by the glass transition tem-perature of the plastic, approximately 150C. Exceeding thislimit temporarily may cause a shift in parametric performance

due to a change in the stresses exerted on the die by the package.Exceeding a junction temperature of 175C for an extendedperiod can result in device failure.

While the AD8001 is internally short circuit protected, thismay not be sufficient to guarantee that the maximum junctiontemperature (150C) is not exceeded under all conditions. Toensure proper operation, it is necessary to observe the maximumpower derating curves.

2.0

050 80

1.5

0.5

40

1.0

0 10102030 20 30 40 50 60 70 90

AMBIENT TEMPERATURE C

MAXIMUMPOWERDISSIPA

TIONW

8-LEADPDIP PACKAGE

TJ = +150C

5-LEADSOT-23-5 PACKAGE

8-LEADSOIC PACKAGE

8-LEADCERDIP PACKAGE

Figure 3. Plot of Maximum Power Dissipation vs.

Temperature

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD8001 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Temperature Package Package

Model Range Description Option Branding

AD8001AN 40C to +85C 8-Lead PDIP N-8AD8001AQ 55C to +125C 8-Lead CERDIP Q-8AD8001AR 40C to +85C 8-Lead SOIC R-8AD8001AR-REEL 40C to +85C 13" Tape and REEL R-8AD8001AR-REEL7 40C to +85C 7" Tape and REEL R-8AD8001ART-REEL 40C to +85C 13" Tape and REEL RT-5 HEAAD8001ART-REEL7 40C to +85C 7" Tape and REEL RT-5 HEAAD8001ACHIPS 40C to +85C Die Form5962-9459301MPA* 55C to +125C 8-Lead CERDIP Q-8*Standard Military Drawing Device.

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HP8133APULSE

GENERATOR

806

+VS

RL = 100

50

VIN

0.1F

0.001F

AD80010.1F

0.001F

TR/TF = 50ps

806

VOUT TO

TEKTRONIXCSA 404 COMM.SIGNALANALYZER

VS

TPC 1. Test Circuit , Gain = +2

TPC 2. 1 V Step Response, G = +2

0.5V 5ns


5ns400mV


LeCROY 9210PULSE

GENERATOR

909

+VS

RL = 100

VS

50

VIN

0.1F

0.001F

AD8001

0.1F

0.001F

TR/TF = 350ps

VOUT TO

TEKTRONIXCSA 404 COMM.SIGNALANALYZER

TPC 5. Test Circuit, Gain = +1

TPC 6. 100 mV Step Response, G = +1

Typical Performance Characteristics

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GAIN

dB

9

6

1210M 100M 1G

3

0

3

6

9

FREQUENCY Hz

VS = 5VRFB = 820

VS = 5V

RFB = 1k

G = +2

RL = 100

TPC 7. Frequency Response, G = +2

OUTPUTdB

0.1

0

0.91M 10M 100M

0.1

0.2

0.3

0.4

0.5

FREQUENCY Hz

0.6

0.7

0.8

RF =

649RF = 698

RF = 750

G = +2RL = 100

VIN = 50mV

TPC 8. 0.1 dB Flatness, R Package (for N Package Add

50 to RF)

50

80

110100k 100M10M1M10k

90

100

70

60

FREQUENCY Hz

HARMO

NICDISTORTIONdBc

VOUT = 2V p-p

RL = 1k

G = +2

5V SUPPLIES

THIRD HARMONIC

SECOND HARMONIC

TPC 9. Distortion vs. Frequency, RL = 1 k

VALUE OF FEEDBACK RESISTOR (RF)

3dBBANDW

IDTHMHz

1000

01000

600

200

600

400

500

800

900800700

RPACKAGE

NPACKAGE

VS = 5V

RL = 100

G = +2

TPC 10. 3 dB Bandwidth vs. RF

50

70

100100k 100M10M1M10k

80

90

60

FREQUENCY Hz

HARMONICDISTORTIONdBc VOUT = 2V p-p

RL = 100

G = +2

5V SUPPLIES

SECOND HARMONIC

THIRD HARMONIC

TPC 11. Distortion vs. Frequency, RL = 100

0.08

0.01

0.01

0

0.00

0.00

0.02

0.02

0.04

0.06

100IRE

DIFFGAIN%

DIFFPHASEDegrees

0.02

G = +2RF = 806

1 BACK TERMINATEDLOAD (150)

2 BACK TERMINATEDLOADS (75)

1 AND 2 BACK TERMINATEDLOADS (150 AND 75)

TPC 12. Differential Gain and Differential Phase

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GAIN

dB

0

5

35100M 1G 3G

10

15

20

25

30

FREQUENCY Hz

5

VIN = 26dBm

RF = 909

TPC 13. Frequency Response, G = +1

1

4

910M 1G100M2M

3

2

1

0

8

7

6

5OUTPUTdB

FREQUENCY Hz

G = +1RL = 100

VIN = 50mV

RF = 649

RF = 953

TPC 14. Flatness, R Package, G = +1 (for N Package Add100 to RF)

40

60

110100k 100M10M1M10k

50

80

70

100

90

DISTORTIONdBc

FREQUENCY Hz

G = +1

RL = 1k

VOUT = 2V p-p

SECONDHARMONIC

THIRDHARMONIC

TPC 15. Distortion vs. Frequency, RL = 1 k

1000

900

500600 700 1100800 900

800

700

600

1000

VALUE OF FEEDBACK RESISTOR (RF)

3dBBANDWIDTHMHz

N PACKAGE

R PACKAGE

VIN = 50mV

RL = 100

G = +1

TPC 16. 3 dB Bandwidth vs. RF, G = +1

FREQUENCY Hz10k 100k 1M 10M 100M

40

70

100

80

90

60

50

DISTORTIONdBc

RL = 100

G = +1

VOUT = 2V p-p

SECOND HARMONIC

THIRD HARMONIC

TPC 17. Distortion vs. Frequency, RL = 100

3

9

24

1M 100M10M

12

15

6

3

FREQUENCY Hz

27

0

18

21

OUTPUTdBV

RL = 100

G = +1

TPC 18. Large Signal Frequency Response, G = +1

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25

10

5

1M 10M 100M

0

5

15

20

FREQUENCY Hz

GAIN

dB

25

20

15

10

1G

45

30

35

40

RF = 470

G = +100

G = +10

RL = 100

RF = 1000

TPC 19. Frequency Response, G = +10, G = +100

3.35

100

2.95

4060

3.05

3.15

3.25

80604020020

OUTPUTSWINGVolts

JUNCTION TEMPERATURE C

2.75

2.85

2.55

2.65

RL = 50

VS = 5V

RL = 150

VS = 5V

| VOUT |

| VOUT |

+VOUT

+VOUT

TPC 20. Output Swing vs. Temperature

60


INPUTBIASCURRENTA

4

2

2

1

0

5

3

40 20 0 20 40 60 80 100 120 140

1

3

4

+IN

IN

TPC 21. Input Bias Current vs. Temperature

2.2

0.4100

0.8

0.6

4060

1.0

1.2

1.4

1.6

1.8

2.0

80604020020

INPUTOFFSETVOLTAGEmV


DEVICE NO. 1

DEVICE NO. 2

DEVICE NO. 3

TPC 22. Input Offset vs. Temperature

60


SUPPLYCURRENTmA

4.4

4.8

5.8

40 20 0 20 40 60 80 100 120 140

5.2

5.4

4.6

5.6

5.0

VS = 5V

TPC 23. Supply Current vs. Temperature

125

85100

95

90

4060

105

100

110

115

120

80604020020


SHO

RTCIRCUITCURRENTmA

SOURCE ISC

| SINK ISC |

TPC 24. Short Circuit Current vs. Temperature

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TRANSRESISTANCEk

0

1

6

40 20 0 20 40 60 80 100 120 140

3

4

5

2

VS = 5V

RL = 150

VOUT = 2.5V

TZ

+TZ

TPC 25. Transresistance vs. Temperature

100

10

110 100 10k 1k

FREQUENCY Hz

100

10

1

NOISEVOLTAGEnV/Hz

NOISECURRENTpA/Hz

100k

INVERTING CURRENT VS = 5V

NONINVERTING CURRENT VS = 5V

VOLTAGE NOISE VS = 5V

TPC 26. Noise vs. Frequency

60


CMRRdB

48

40 20 0 20 40 60 80 100 120 140

51

50

49

53

55

54

52

56

+CMRR

CMRR

2.5V SPAN

TPC 27. CMRR vs. Temperature

100k 100M10M1M10k0.01

1k

10

0.1

100

FREQUENCY Hz

ROU

T

1

G = +2

RF = 909

TPC 28. Output Resistance vs. Frequency

1

4

91M 10M 1G100M

5

6

7

8

3

2

1

0

FREQUENCY Hz

OUTPUTdB

G = 1

RL = 100

VIN = 50mV

RF = 576

RF = 649

RF = 750

TPC 29. 3 dB Bandwidth vs. Frequency, G = 1

60


PSRRdB

52.5

40 20 0 20 40 60 80 100

62.5

60.0

57.5

67.5

75.0

72.5

65.0

77.5

70.0

55.0

+PSRR

PSRR

3V SPAN

CURVES ARE FOR WORST-

CASE CONDITION WHERE

ONE SUPPLY IS VARIED

WHILE THE OTHER IS

HELD CONSTANT.

TPC 30. PSRR vs. Temperature

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300k 100M10M1M

FREQUENCY Hz

20

10

40

30

CMRR

dB

910

VOUT

VIN150

150

910

51

62

1G

50

TPC 31. CMRR vs. Frequency

1

4

91M 10M 1G100M

5

6

7

8

3

2

1

0

FREQUENCY Hz

OUTPUTdB

RF = 750

RF = 649

RF = 549

G = 2

RL = 100

VIN = 50mVrms

TPC 32. 3 dB Bandwidth vs. Frequency, G = 2

TPC 33. 100 mV Step Response, G = 1

10

20

1M 10M 100M

10

0

20

FREQUENCY Hz

PSRR

dB

60

50

40

30

1G

30

CURVES ARE FOR WORST-

CASE CONDITION WHERE

ONE SUPPLY IS VARIED

WHILE THE OTHER IS

HELD CONSTANT.

RF = 909

G = +2

PSRR

+PSRR

PSRR

+PSRR

TPC 34. PSRR vs. Frequency

TPC 35. 2 V Step Response, G = 1

345 210123 54

100

20

0

10

80

90

70

60

50

40

30

100

20

0

10

80

90

70

60

50

40

30

COUNT

PERCENT

INPUT OFFSET VOLTAGE mV

3 WAFER LOTSCOUNT = 895MEAN = 1.37STD DEV = 1.13MIN = 2.45MAX = +4.69

FREQ DIST

CUMULATIVE

TPC 36. Input Offset Voltage Distribution

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THEORY OF OPERATION

A very simple analysis can put the operation of the AD8001, acurrent feedback amplifier, in familiar terms. Being a currentfeedback amplifier, the AD8001s open-loop behavior is expressed

as transimpedance, VO/IIN, or TZ. The open-loop transimped-ance behaves just as the open-loop voltage gain of a voltagefeedback amplifier, that is, it has a large dc value and decreases

at roughly 6 dB/octave in frequency.

Since the RIN is proportional to 1/gM, the equivalent voltagegain is just TZgM, where thegM in question is the trans-conductance of the input stage. This results in a low open-loopinput impedance at the inverting input, a now familiar result.Using this amplifier as a follower with gain, Figure 4, basicanalysis yields the following result.

V

VG

T S

T S G R R

GR

RR g

O

IN

Z

Z IN

IN M

= + +

= + =

( )

( )

/

1

11

21 50

VOUT

R1

R2

RIN

VIN

Figure 4. Follower with Gain

Recognizing that GRIN

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Printed Circuit Board Layout Considerations

As to be expected for a wideband amplifier, PC board parasiticscan affect the overall closed-loop performance. Of concern are

stray capacitances at the output and the inverting input nodes. Ifa ground plane is to be used on the same side of the board asthe signal traces, a space (5 mm min) should be left around thesignal lines to minimize coupling. Additionally, signal lines

connecting the feedback and gain resistors should be shortenough so that their associated inductance does not cause highfrequency gain errors. Line lengths on the order of less than5 mm are recommended. If long runs of coaxial cable are beingdriven, dispersion and loss must be considered.

Power Supply Bypassing

Adequate power supply bypassing can be critical when optimiz-ing the performance of a high frequency circuit. Inductance inthe power supply leads can form resonant circuits that producepeaking in the amplifiers response. In addition, if large currenttransients must be delivered to the load, then bypass capacitors(typically greater than 1 F) will be required to provide the bestsettling time and lowest distortion. A parallel combination of4.7

F and 0.1

F is recommended. Some brands of electrolytic

capacitors will require a small series damping resistor 4.7 foroptimum results.

DC Errors and Noise

There are three major noise and offset terms to consider in acurrent feedback amplifier. For offset errors, refer to the equationbelow. For noise error the terms are root-sum-squared to give anet output error. In the circuit in Figure 7 they are input offset(VIO), which appears at the output multiplied by the noise gainof the circuit (1 + RF/RI), noninverting input current (IBN RN)also multiplied by the noise gain, and the inverting input current,which when divided between RF and RI and subsequentlymultiplied by the noise gain always appears at the output asIBN RF. The input voltage noise of the AD8001 is a low 2 nV/

Hz. At low gains though the inverting input current noise timesRF is the dominant noise source. Careful layout and device

matching contribute to better offset and drift specifications forthe AD8001 compared to many other current feedback ampli-fiers. The typical performance curves in conjunction with the

following equations can be used to predict the performance ofthe AD8001 in any application.

V VR

RI R

R

RI ROUT IO

F

I

BN NF

I

BI F= +

+

1 1

RF

RI

RNIBN

VOUT

IBI

Figure 7. Output Offset Voltage

Driving Capacitive Loads

The AD8001 was designed primarily to drive nonreactive loads.If driving loads with a capacitive component is desired, best

frequency response is obtained by the addition of a small seriesresistance, as shown in Figure 8. The accompanying graphshows the optimum value for RSERIES versus capacitive load. It isworth noting that the frequency response of the circuit when

driving large capacitive loads will be dominated by the passiveroll-off of RSERIES and CL.

909

RSERIES

RL500

IN

CL

Figure 8. Driving Capacitive Loads

40

00 25

30

10

5

20

15 2010CL pF

G = +1

RSERIES

Figure 9. Recommended RSERIESvs. Capacitive Load

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Communications

Distortion is a key specification in communications applications.Intermodulation distortion (IMD) is a measure of the ability ofan amplifier to pass complex signals without the generation ofspurious harmonics. The third order products are usually themost problematic since several of them fall near the fundamentalsand do not lend themselves to filtering. Theory predicts that the

third order harmonic distortion components increase in power atthree times the rate of the fundamental tones. The specificationof third order intercept as the virtual point where fundamental and

harmonic power are equal is one standard measure of distortionperformance. Op amps used in closed-loop applications do notalways obey this simple theory. At a gain of +2, the AD8001

has performance summarized in Figure 10. Here the worst thirdorder products are plotted versus input power. The third orderintercept of the AD8001 is +33 dBm at 10 MHz.

8037

75

21045 62

70

65

60

55

50

45

1

THIRDORDERIMDdB

c

INPUT POWER dBm

68 4 53

2F2 F1

2F1 F2

G = +2

F1 = 10MHz

F2 = 12MHz

Figure 10. Third Order IMD; F1 = 10 MHz, F2= 12 MHz

Operation as a Video Line Driver

The AD8001 has been designed to offer outstanding perfor-mance as a video line driver. The important specifications ofdifferential gain (0.01%) and differential phase (0.025) meetthe most exacting HDTV demands for driving one video load.The AD8001 also drives up to two back terminated loads asshown in Figure 11, with equally impressive performance (0.01%,

0.07). Another important consideration is isolation betweenloads in a multiple load application. The AD8001 has morethan 40 dB of isolation at 5 MHz when driving two 75 backterminated loads.

909909

75CABLE

75

75

VOUT NO. 1

VOUT NO. 2

+VS

VS

VIN

0.1F

0.001F

AD8001

0.1F

75CABLE

75

75

75CABLE

+

0.001F

75

Figure 11. Video Line Driver

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0.1F

+VS

VS

20

50

1k

18

17

16

15

14

13

12

11

VREF A

10pF

CLOCK

5, 9, 22,

24, 37, 41

4,19, 21 25, 27, 42

0.1F

38

8

VREF B

6

+VINT2

3+VREF A

AIN A

649

324ANALOGIN A

0.5V

1.3k

AD707

43+VREF B

20k0.1F

2V

1.3k

20k

649

ANALOGIN B

0.5V

324

20

0.1F

40

COMP1

AIN B

ENCODE A ENCODE B

10 36

ENCODE 74ACT04

0.1F

+5V

28

29

30

31

32

33

34

35

RZ1

RZ2

D0A (LSB)

D7A (MSB)

D0B (LSB)

D7B (MSB)

7, 20,

26, 395V

1N4001

AD9058(J-LEAD)

RZ1, RZ2 = 2,000 SIP (8-PKG)

74ACT273

74ACT

273

8

8

AD8001

AD8001

Figure 12. AD8001 Driving a Dual A-to-D Converter

Driving A-to-D Converters

The AD8001 is well suited for driving high speed analog-to-digital converters such as the AD9058. The AD9058 is a dual

8-bit 50 MSPS ADC. In the circuit below, the AD8001 isshown driving the inputs of the AD9058, which are configuredfor 0 V to 2 V ranges. Bipolar input signals are buffered, amplified(2), and offset (by +1.0 V) into the proper input range of the

ADC. Using the AD9058s internal +2 V reference connectedto both ADCs as shown in Figure 12 reduces the number ofexternal components required to create a complete data

acquisition system. The 20 resistors in series with ADC inputsare used to help the AD8001s drive the 10 pF ADC inputcapacitance. The AD8001 only adds 100 mW to the powerconsumption while not limiting the performance of the circuit.

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REV. D

AD8001

14

Layout Considerations

The specified high speed performance of the AD8001 requirescareful attention to board layout and component selection. ProperRF design techniques and low parasitic component selectionare mandatory.

The PCB should have a ground plane covering all unused portionsof the component side of the board to provide a low impedanceground path. The ground plane should be removed from the areanear the input pins to reduce stray capacitance.

Chip capacitors should be used for supply bypassing (see Figure 13).

One end should be connected to the ground plane and the otherwithin 1/8 inch of each power pin. An additional large

(4.7 F10 F) tantalum electrolytic capacitor should be con-nected in parallel, but not necessarily so close, to supply currentfor fast, large-signal changes at the output.

The feedback resistor should be located close to the invertinginput pin in order to keep the stray capacitance at this node to a

minimum. Capacitance variations of less than 1 pF at the invert-ing input will significantly affect high speed performance.

Stripline design techniques should be used for long signal traces(greater than about 1 inch). These should be designed with acharacteristic impedance of 50 or 75 and be properly termi-nated at each end.

Inverting Configuration Supply Bypassing

C10.1F

C20.1F

+VS

VS

C310F

C410F

Noninverting Configuration

RF

ROIN

+VS

VS

RS

RT

RG

OUT

RF

RO

IN

+VS

VS

RT

RG

OUT

Figure 13. Inverting and Noninverting Configurations for Evaluation Boards

Table I. Recommended Component Values

AD8001AN (PDIP) AD8001AR (SOIC) AD8001ART (SOT-23-5)

Gain Gain Gain

Component 1 +1 +2 +10 +100 1 +1 +2 +10 +100 1 +1 +2 +10 +100

RF () 649 1050 750 470 1000 604 953 681 470 1000 845 1000 768 470 1000RG () 649 750 51 10 604 681 51 10 845 768 51 10R

O(Nominal) (

) 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9

RS () 0 0 0RT (Nominal) () 54.9 49.9 49.9 49.9 49.9 54.9 49.9 49.9 49.9 49.9 54.9 49.9 49.9 49.9 49.9Small Signal 340 880 460 260 20 370 710 440 260 20 240 795 380 260 20

BW (MHz)

0.1 dB Flatness 105 70 105 130 100 120 110 300 145

(MHz)

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REV. D

AD8001

15

8-Lead Plastic Dual In-Line Package [PDIP]

(N-8)

Dimensions shown in inches and (millimeters)

SEATINGPLANE

0.180(4.57)MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79) 0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

8

1 4

5 0.295 (7.49)

0.285 (7.24)

0.275 (6.98)

0.100 (2.54)BSC

0.375 (9.53)

0.365 (9.27)

0.355 (9.02)

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-095AA

0.015(0.38)MIN

8-Lead Standard Small Outline Package [SOIC]

(R-8)

Dimensions shown in millimeters and (inches)

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099) 45

80

1.75 (0.0688)

1.35 (0.0532)

SEATINGPLANE

0.25 (0.0098)

0.10 (0.0040)

8 5

41

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)BSC

6.20 (0.2440)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)COPLANARITY0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012AA

OUTLINE DIMENSIONS

8-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-8)

Dimensions shown in inches and (millimeters)

1 4

8 5

0.310 (7.87)

0.220 (5.59)PIN 1

0.005 (0.13)

MIN

0.055 (1.40)

MAX

0.100 (2.54) BSC

150

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)SEATINGPLANE

0.200 (5.08)MAX

0.405 (10.29) MAX

0.150 (3.81)MIN

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.015 (0.38)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

5-Lead Small Outline Transistor Package [SOT-23]

(RT-5)

Dimensions shown in millimeters

PIN 1

1.60 BSC 2.80 BSC

1.90BSC

0.95 BSC

1 3

45

2

0.22

0.08

10

5

00.50

0.30

0.15 MAXSEATINGPLANE

1.45 MAX

1.301.150.90

2.90 BSC

0.60

0.45

0.30COMPLIANT TO JEDEC STANDARDS MO-178AA

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AD8001

Revision HistoryLocation Page

7/03Data Sheet changed from REV. C to REV. D

Renumbered figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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