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7/30/2019 Nithin Intel

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NITHIN P


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INTEL 3D

Transistors using a three-dimensionalstructure

3-D transistor design also called Tri-Gate

high-volume manufacturing at the 22-nanometer node in Ivy Bridge


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http://images.anandtech.com/reviews/cpu/intel/22nm/multiplefins.jpg


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2D vs 3D

In 3-D, traditional "flat" two-dimensionalplanar gate is replaced with an incredibly thinthree-dimensional silicon fin that rises up

vertically from the silicon substrate Control of current is accomplished by

implementing a gate on each of the threesides of the fin two on each side and oneacross the top

In 2-D planar, just one gate on top


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Cont

Additional control:

-maximum current flows when the transistor

is in the "on" state (for performance)

-minimum current close to zero when it is in

the "off" state (to minimize power)

- enables the transistor to switch veryquickly between the two states (for

performance).


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LOWER OPERATING VOLTAGE

Intel's 3-D Tri-Gate transistors enable chips to

operate at lower voltage with lower leakage,

providing improved performance and energy

efficiency

flexible to choose transistors targeted for low

power or high performance, depending on the

application


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Intel demonstrated the world's first 22nm

microprocessor, code named "Ivy Bridge,"working in a laptop, server and desktop

computer

Ivy Bridge-based Core family processors willbe the first high-volume chips to use 3-D Tri-

Gate transistors

Ivy Bridge is slated for high-volume production


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MOORES LAW


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MODERN CHALLENGES IN

DIGITAL SYSTEM

With advance in technology size of the transistor and

area of design reduced and complexity increased

This give rise to following challenges

SIZING OF TRANSISTORS

ENERGY WASTE REDUCTION-COMPLEXITY

ENERGY-DELAY TRADEOFF

SWITCHING POWER REDUCTION

LEAKAGE CURRENT

THERMAL CONSTRAINT


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SIZING OF TRANSISTORS

Digital circuits are constructed with two major components

1. currents and parasitic capacitances of transistors

2. Voltages

CMOS technologies use transistors as the switches andswitching is done through charging and discharging the

parasitic capacitances

tuning transistors dimensions has substantial effect on the

energy and delay of the system since it directly impacts boththe parasitic caps and on-currents

Sizing transistors is the most basic form of circuit-level

optimization.


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SOLUTION BY 3D TRANSISTORS

Fins are vertical in nature, hence transistors

can be packed closer

For future generations, designers also have

the ability to continue growing the height of

the fins to get even more performance and

energy-efficiency gains


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ENERGY WASTE

REDUCTION-COMPLEXITY

Energy waste in digital systems results from the

simplicity of design.

can reduce energy waste by turning a simple and

energy-inefficient design into a complex but energy-efficient design

Energy waste is caused by spurious switching of

parasitic capacitances or transistor leakag


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modern energy-conscious digital systems have

success-fully minimized switching energywaste with the help of

clock gating for clock trees

bitline/wordline gating for SRAM arrays


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The 22nm 3-D Tri-Gate transistors provide up

to 37 percent performance increase at low

voltage vs Intel's 32nm planar 2-D transistors

The new transistors consume less than half

the power when at the same performance as

2-D planar transistors on 32nm chips


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http://images.anandtech.com/reviews/cpu/intel/22nm/power.jpg


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ENERGY-DELAY TRADEOFF

Tradeoffs to either increasing performance or

decreasing energy

High performance innovation increases energy

consumption for a performance gain and a low-energy innovation saves energy while sacrificing

performance

supply voltage can be up-scaled or down-scaled to

find the optimal level where the delay requirement is

tightly met and the energy consumption is minimized


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Cont

The future digital systems require an urgent change in

design philosophy: from purely high performance or

purely low-energy design to an energy-efficient design

using energy- delay tradeoffs

the challenge is to find the balance between these two


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At lower voltages Intel is claiming a 37%

increase in performance vs. its 32nm process


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http://images.anandtech.com/reviews/cpu/intel/22nm/delay.jpg


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SWITCHING POWER

REDUCTIONLow-power techniques have been developed

at various levels such as algorithms,

architectures, circuits, and devicesalso on various platforms such as general-

purpose processors, media processors, DSP

ASICS, and FPGAs


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LEAKAGE CURRENT

exponential increase in leakage current results from

two main factors

process scaling

die temperature increase

Linear scale-down of threshold voltage has led to an

exponential increase in leakage current

If this trend of constant threshold voltage scalingwould continue, leakage current would increase by

five times each generation

Leakage current is also exponentially proportional to

die temperature


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Cont

Continuous increase of total chip power has

increased the average die temperature and

contributed to leakage increase

Leakage power is now comparable to dynamicswitching power in high-performance digital systems


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THERMAL CONSTRAINT

Ever-increasing power consumption and ever-

decreasing form-factor of digital systems have

increased heat density and die temperature rapidly

Raised junction temperature causes decreased delayand increased leakage

The linear increase of temperature makes leakage

power increase exponentially

The leakage power increase might lead to the further

temperature increase in return


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Cont

This positive feedback can cause catastrophic

thermal runaway, if there is no dynamic thermal

management scheme to sense high temperature and

reduce temperature by decreasing power densitydynamically

Transistor aging also increase exponentially with

temperature


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REFERENCES

standards-revolutionary-22nm-transistor-

technology-presentation

standards-22nm-3d-tri-gate-transistors-presentation

http://www.intel.in/content/www/in/en/research/intel-research.html

http://www.intel.in/content/www/in/en/silicon-

innovations/silicon-innovations-technology.html

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