nithin seminar

TRANSIENT PERFORMANCE OF SiC MOSFETs AS A FUNCTION OF TEMPERATURE

Guided by: Tintu V.R

Presented by :Nithin Joseph

S7 EEERoll no:21

9-Aug-12 EEE.Dept. MCET Anad 1

OUTLINE OF PRESENTATIONAIM INTRODUCTIONTRANSIENT CONDITIONS IN MOSFETsTEST DEVICEEXPERIMENTAL SETUPMEASURMENTSEXPERIMENTAL RESULTSAPPLICATIONCONCLUSIONREFERENCE


AIM To study two transient conditions that are common in power

converters Effects of voltage rise time Effects of current pulses


INTRODUCTIONTask of PC: To process & control the

flow of electric energy by supplying voltages & currents

Important components: sources & switches

Sources: 1. voltage source- eg: capacitor

2. current source- eg: inductor


CONTD…

Principle of operation: based on the switch mode action of its switches

Commutation of switches generate fast current & voltage transients

By proper operation of switches ,they transfer energy between 2 sources

Widely used switches: semiconductor switches


ADVANTAGES InexpensiveSmall form factorsReduction in costEasy to controlPower density increasesOn state voltage drop is smallNegligible leakage current


WHY SiC RATHER THAN SI?Properties Sic Si

Band gap( eV) 3.2 1.11Allowable operating temperature

Higher Lower

Thermal conductivity(W/cm 0C at 270C)

4.9 1.5

Saturated e drift velocity(cm/s)

2*107 1*107

Electron mobility(cm2/V-sec at 270C)

500 1400


CONTD…Hole mobility(cm2/V-sec at 270C)

50 600

Break down electric field(V/cm)

20*105 3*105

Dielectric constant

9.8 11.8

Thermal runaway(0C)

> 800 150


TRANSIENT CONDITIONS IN MOSFETs

I. dV/dt riseII. Fault tolerance switch(effects of

current pulses with short pulse width & high peak currents)


I. dV/dt RISEdv/dt capability: maximum rate of

rise of drain source voltage allowed If this transient is too high, gate

voltage will rise above threshold voltage

it will lead to MOSFET trigger itself into conduction mode, while it should be in blocking mode

Results in the failure of power converter


threshold voltage

Simulation result for formation of inversion channel (electron density) and attainment of threshold voltage (IV) in a nanowire MOSFET. Note that the threshold voltage for this device lies around 0.45V.


II. FAULT TOLERANCE SWITCH

Accompanied by pulsing the switch with a current pulse that has high peak current & short pulse width

Occur due to noise coupling to gate signal

Gate driven false triggering


TEST DEVICECree Inc.Sic MOSFET (DUT)Rated for Blocking-1200 V Conducting-20 ARds(on)- 75 mΩ at 250CActive area- 0.1 cm2

Requires gate voltage of 20V to sufficiently turn on


CONTD…Tests are conducted at temperatures

of- 250C,500C & 1500CHigh wattage resistors as heating

elementsTemperature measurement -

thermocouples


dV/dt TEST SETUP• Goal: To provide rapid change in voltage across DUT to determine when the device will turn on

D

s

G


TEST SET UP CONSITS OF:

Manually actuated switch-to accomplish high dV/dt

Carbon composite potentiometer- to vary dV/dt

High value bus capacitor- to minimize ringing that would occur in a system

Parasitic capacitance- limits the rate at which voltage can change when a current is applied


PROCEDURETo control voltage rise time on DUT,

both source voltage & potentiometer are adjusted

dV/dt limits are tested with various Rgs values

Maximum dV/dt before the device is triggered on is given by the equation

[dVD/dt ]max= VTH/(RG *CGD) (1)


CONTD…For this MOSFET datasheet values areVTH =1.8 V at 250C

=1.9 V at 1500C CGD =20pFRG of 0.01,2.5,5,7.5 & 10 ΩSubstituting above values in (1),

maximum dV/dt can be calculated

9-Aug-12 EEE.Dept. MCET Anad 1 8

CONTD… Calculated Maximum dV/dt for Varying Gate

Resistances.RG

(Ω)

[dV/dt]max at 25 °C(V/ns)

[dV/dt]max at 150 °C(V/ns)

0.01 9000 95002.50

36 38

5.00 18 197.50

12 12.6

10.0 9 9.59-Aug-12 EEE.Dept. MCET Anad 19

PEAK CURRENT TEST SETUP•Goal: To simulate the temporary short of the dc bus through DUT in order to analyze the fault tolerance of the DUT

D

GS


RLC ring down circuit- to deliver a current pulse peaking at 10 times the rated current

Parasitic inductance- limits the rate at which current can change when a voltage is applied

Pinwheel design board setup- to accomplish minimal inductance

Load resistance- make system critically damped

TEST SET UP CONSITS OF:


Picture of the peak current test board using the pinwheel design tominimize the parasitic inductance of the circuit.

CONTD…


Experiment is done by pushing DUT into saturation & measuring the power dissipated by DUT

Minimum parasitic inductance maximize di/dt

Resistance chosen is given byR=2(L/C)1/2 (2)

PROCEDURE


Inductance of test board- 250 nHTotal capacitance= .88µFSubstituting the values in (2) R=1.066Ω

CONTD…


Equipment- Tektronix MSO 4054 Oscilloscope(500 MHz, 2.5 Gsamples/s)

3- P5200 high voltage differential probes(500:1)

VDS & VGS are taken For peak current test- high voltage

differential probe across the load resistor

Current is calculated from above voltage

MEASUREMENTS


dV/dt TEST RESULTS

The dashed waveforms are multiple shots of thedrain to source voltage. The solid line is a linear fit to the section of thecurve which has to the highest slew rate.


Summary of varying dV/dt’s for varying gate resistances. These shots were taken at a temperature of 25 °C.

Summary of varying dV/dt’s for varying gate resistances. These shots were taken at a temperature of 150 °C.

CONTD…

RESULT: DUT did’nt turn on still all of dV/dt exceed calculated value


PEAK CURRENT TEST RESULTS

Sample waveforms of voltage (black) and current (grey) of deviceunder test. Where the two waveforms overlap is the power dissipated in the device.


Current waveforms for various gate voltages at 25 °C (grey) and 150 °C (black).

Dissipated power by the device under test for various gate voltages at 25 °C (grey) and 150 °C (black).

CONTD…


Vgate (V)

Energy at 25 0C (mJ)

Energy dissipated by DUT at 25 0C

(%)

Energy at 150 0C (mJ)

Energy dissipated by DUT at 150 0C

(%)

15 216 76.6 212 75.220 172 61.0 173 61.425 141 50.0 144 51.130 120 42.6 127 44.0

CONTD…

Energy Dissipated in DUT at Different Temperatures

RESULT: The DUT is able to safely dissipate the energy since threshold for induced thermal runaway is high


I-V curves before the peak current test and after the peak current test.

Reverse breakdown curves before the peak current test and after the peak current test.

CONTD…

RESULT: The effects of peak current tests are not observed


Solar invertersMotor drivesPower factor correction

APPLICATIONS


SiC devices are robust & tolerant to extreme transient conditions

dV/dt capabilities are above operating conditions of typical PC

Peak current capabilities with current density up to 3000A/cm2

Can be operated above the temperatures of 150 0C

CONCLUSION


J.A. Carr, D. Hotz, J.A. Balda, H.A. Mantooth, A. Ong and A. Agarwal, "Assessing the Impact of SiC MOSFETs on Converter Interfaces for Distributed Energy Resources”, IEEE. Trans. Power Electronics,Vol.24, pp.260-270, 2009.

C. James, C. Hettler, and J. Dickens, "Design and Evaluation of a Compact Silicon Carbide Photoconductive Semiconductor Switch", IEEE. Trans. Electronic Devices, Vol. 58, No. 2, pp. 508-511, 2011.

Q. Zhang, R. Callanan, M.K. Das, S.H. Ryu, A. Agarwal, and J.W. Palmour, "SiC Power Devices for Microgrids", IEEE. Trans. Power Electronics, Vol. 25 pp. 2889-2896, 2010.

C.E. Weitzel, J.W. Palmour, C.H. Carter, K. Moore, S.A. Nordquist, C. Thero,and M. Bhatnagar, "Silicon Carbide High-Power Devices", IEEE. Trans.Electron Devices, Vol. 43, pp. 1732-1741, 1996..

REFERENCE


THANK YOU


nithin seminar

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