Norhayati Soin 05 KEEE 4425 WEEK 3/1 7/26/2005

LECTURE : KEEE 4425

WEEK 3/1

Norhayati Soin 05 KEEE 4425 WEEK 3/1 7/26/2005

WORKING EXAMPLES

EXAMPLE 1

Calculate the values of K’n and K’p for NMOS and PMOS transistors with gate oxide thickness of 160 Angs.. Assume that μn = 500 cm2/ V.s, μp = 200 cm2/ V.s, and the relative permittivity of the gate oxide is 3.9. (εo= 8.854 x 10-14F/cm)

Use K’n = 25 μA/V2 , K’p= 10 μA/V2, VTN = 1 V, VTP = -1 V unless otherwise stated

Norhayati Soin 05 KEEE 4425 WEEK 3/1 7/26/2005

WORKING EXAMPLES

EXAMPLE 2

A particular interconnection between two logic gates in an IC chip runs one-half the distance across a 5-mm wide die. If the line is 2 μm wide and the oxide (εr = 3.9, εo = 8.854 x 10-14F/cm) beneath the line is 1 μm thick, what is the total capacitance of this line, assuming that the capacitance is three times that predicted by the parallel plat capacitance formula. Assuming that the silicon beneath the oxide represents a conducting ground plane.

Norhayati Soin 05 KEEE 4425 WEEK 3/1 7/26/2005

WORKING EXAMPLES

EXAMPLE 3

What are the rise time, fall time and average propagation delay for a minimum size CMOS inverter in which both W/L ratios are 2/1. Assume a load capacitance of 0.5 pF and VDD = 5 V.

Norhayati Soin 05 KEEE 4425 WEEK 3/1 7/26/2005

WORKING EXAMPLES

EXAMPLE 4

What are the sizes of the transistors in the CMOS inverter if it must drive a 1 – pF capacitance with an average propagation delay of 3 ns? Design the inverter for equal rise and fall times. Use VDD = 5 V, VTN and VTP

= -1 V.

Norhayati Soin 05 KEEE 4425 WEEK 3/1 7/26/2005

WORKING EXAMPLESEXAMPLE 5

Design a symmetrical CMOS reference inverter to provide a delay of 1 ns when driving a 10 nF load.

(a) Assume VDD = 5 V(b) Assume VDD = 3.3 and VTN = 1 V, VTP = -1 V

Norhayati Soin 05 KEEE 4425 WEEK 3/1 7/26/2005

Solution to Example 5