nov 29, 2006dwingeloo, evn cbd meeting evn d igital b ase b and c onverter status report status...

Nov 29, 2006 Dwingeloo, EVN CBD Meeting

EVNEVN

DDigitaligital B Basease B Bandand C Converteronverter

Status ReportStatus Report

G. Tuccari


DDigital igital BBase ase BBand and CConverteronverter


Digital Base Band ConverterDigital Base Band Converter


DBBC v.1.1 General Features

• 4 RF/IF Input from 16 in a range up to 2.200 GHz

• Four polarizations or bands available for a single group of 64 output data channel selection (2 VSI output connectors with at present 1 or 2 Gb/s each)

• 230,29 Hz or 512,1024 MHz sampling clock frequency each of the 4 sampler boards

• Channel bandwidth ranging between 250KHz and 16 MHz (MK4 modes), U&L or I&Q

• Channel bandwidth between 32 and 512 MHz (wide modes), I&Q

• Tuning step 1 Hz with 230,29 Hz sampling clock

• Multiple architecture using fully re-configurable FPGA Core Modules (Down-Converter, Equally Spaced Multichannel [even schematically called ‘polyphase filters’], DRx, etc.)

• Modular realization for cascaded stack processing


DBBCDBBC ConditioningModuleConditioningModule

• Pre-AD Conversion Signal ConditioningPre-AD Conversion Signal Conditioning

• Pre-AD Conversion Nyquist Band DefinitionPre-AD Conversion Nyquist Band Definition

• 4 RF Input Selection4 RF Input Selection

• Output Level ControlOutput Level Control

• Total Power MesurementTotal Power Mesurement

• 2.2 GHz Bandwidth2.2 GHz Bandwidth


DBBCDBBCADBoardADBoard

• Max Sampling clock single board: Max Sampling clock single board: 1.5 G1.5 GHzHz

• Output Data: 2 x 8-bit @ Output Data: 2 x 8-bit @ ¼ SClk¼ SClk DDRDDR

• Analog to Digital ConverterAnalog to Digital Converter

• Analog input: 0 - 2.2 GHzAnalog input: 0 - 2.2 GHz

• Max eq. Sampling clock Max eq. Sampling clock interleaving four boards: 6.0 GHzinterleaving four boards: 6.0 GHz


DBBCDBBCCoreBoardCoreBoard - Front Side - Front Side

• Basic processing unitBasic processing unit

• Input Rate: Input Rate: (4 IFs x 2 bus x 8 bit x SClk/2) b/s(4 IFs x 2 bus x 8 bit x SClk/2) b/s

• Output Rate: Output Rate: (64 ch x 32-64-128) Mb/s(64 ch x 32-64-128) Mb/s

• Digital Down Converter:Digital Down Converter: 1 CoreModule = 1 BBC1 CoreModule = 1 BBC

• Programmable architectureProgrammable architecture

• Equally Spaced Multichannel:Equally Spaced Multichannel: 1 CoreModule = 64 real channels1 CoreModule = 64 real channels 1 CoreModule = 32 complex channels1 CoreModule = 32 complex channels


DBBCDBBCFiLaFiLa BoardBoard

• First and Last board in the stackFirst and Last board in the stack

• First: First: Communication InterfaceCommunication Interface JTAG programming channelJTAG programming channel 1PPS synchronizer1PPS synchronizer

• Last: Last: 2 VSI Interfaces2 VSI Interfaces DA ConverterDA Converter


DBBCDBBC4 ADBoard + 8 CoreModule Stack4 ADBoard + 8 CoreModule Stack


Minimal Architecture

With external RF control:

• 1 ADBoard • 1 CoreBoard (down-converter, multichannel

configuration, DRx)• 1+1 FiLa board (VSI interface, DA converter,

JTAG,etc.)


Maximum Architecture

• 4 Conditioning Modules• 1 FiLa board• 4 ADBoard • 16 CoreModule • 1 FiLa board• 1 CaT board• PC Set • PowerDistributor


DBBC System v.1.1 on Nov 28, 2006

• Down-converter system ready• CaT (Clock and Timing) board added• Configuration Firmware ready for most of the bandwidth• Equi-spaced Multi-channel Firmware in test• Testing in radiotelescopes is running • Since Dec06 part of geo observations recorded in

parallel to the std system for testing purposes


DBBC v.2.0 System on Nov 29, 2006Update program:

-FPGA Virtex4 device for double processing clock (first prototype tested in August06, more boards under production)

-FPGA Virtex5 engineer device waited for testing

-Faster AD sampler with ADB2 for input bandwidth increasing (2.2GS/s, max bwd 3.5GHz), in collaboration with MPI (Michael Wunderlich)

-FiLa10G under development in collaboration with with MPI (Michael Wunderlich)

- RFI Mitigation Board: the first CoreBoard in the chain acts as RFI processor. Some test performed: a channel can be recovered if the RFI is not wide band and if the FFT bin span is small with respect to the channel span (about < 1/10). Astron interested in a joint development.


ADB2


FiLa10G

• Piggy-back board• Triangle connection between HSI (DBBC fast sampled data bus) – 2xVSI – 10Gb link• It can be placed either at the beginning of the chain or at the end• The ADB2 is able to support FiLa10G for pure sampled data transmission• The FiLa output board is able to support FiLa10G for processed data transmission• It is a 2xVSI < - > 10G converter• DBBC output can be in parallel via 2xVSI and 10G• Completion expected in mid-2007


FiLa10G Connectivity

1ch HSI

Max10bit

Max 2.048GHz

2xVSI

64ch@128MHz

10G

FiLa10G

2 Optical Multimode Fibers (XPak Transceiver)


DBBC Technology application to Digital Receiver

• L Band digital receiver under development in Effelsberg and Noto (in collaboration with Reinhard Keller et al.)

• DBBC parts are used with appropriate firmware for recording/transfering the sky frequency

• Recording on PCEVN (included in the receiver)• Network data transfer with FiLa10G• Software development for data processing, including

entire band correlation• A graduate thesis on this subject in IRA Noto is active• A further thesis on this subject or 10G network

development in spring 2007 in MPI Bonn• A faster acquisition board development it’s necessary,with a data rate ≥ 2Gbps


DBBC System on Nov 29, 2006

• Observation of Aspiring stations in Evpatoria (Ukraine) and Irbene (Latvia), respectively in August and November

a) A reduced version of DBBC run experiments in both stationsb) PCEVN used to record such experiments in both 'pcevn format'

and 'mk5 format‘c) data saved on PCEVN disks and transferred in 'pcevn format' from

the station to JIVE for software correlation d) data saved in 'mk5 format' and then later copied on the MK5A

terminal for hardware correlatione) In Evpatoria fringes detected with Wb and Mc, problems with

magnitude bit for encoding reasonsf) Irbene test still under evaluation, no fringes at present with Tr and

Nt, even in theNt-Tr baseline with not-standard receivers (12 GHz). Magnitude bit encoding fixed.


DBBC Units production - IRA is at present taking care of the DBBC realization- Production of parts is realized by companies under IRA

management- Multiwire and microwave PCB (CoreModule, FiLa, Conditioning,

CaT) are realized in France by a specialized company- ADBoard realization: MPI- Boards are populated by an Italian company - Mechanical parts is done by an Italian company- Assembly, testing and validation in IRA- Three units ordered and under construction for Wettzel, Tigo,

O’Higgins- MPI-Bonn required one unit- Russian Space Agency required three units- Even single boards available without any firmware for different

applications (polarimeter, spectrometer, correlation, etc.)- Units today ordered are available after 3-6 months- A spin-of company is going to be set


DBBC Cost

Depends on the configuration

• Minimal architecture (1 ADB1 +1 CoreBoard + 2 FiLa+PowerDistributor): 6 K€

• Complete system with 4 IF + 4 CoreBoard (1VSI 0.5-1 Gbps): 30 K€

• Complete system with 4 IF + 8 CoreBoard (1VSI 1-2 Gbps): 45 K€

• Complete system with 4 IF + 16 CoreBoard (2 VSI 1-4 Gbps each): 65 K€

Complete includes: PowerDistributor, PCSet, ConditioningModules, 19” Case & Power Supply

nov 29, 2006dwingeloo, evn cbd meeting evn d igital b ase b and c onverter status report status...

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