nsf center for grid-connected advanced power electronic ... · 11/8/2017 · multilevel cascaded...

GRid-Connected Advanced Power Electronic Systems

Confidential – GRAPES

NSF Center for GRid-connected Advanced Power Electronic Systems (GRAPES)

PI: Dr. Alan Mantooth

Students: Janviere Umuhoza, Kenneth Mordi, Haider Mhiesan

November 9, 2017

GR-17-03

SiC-Based Direct Power Electronics Interface for

Battery Energy Storage System into Medium

Voltage Distribution System



Presentation Outline2

❑ Project Goals and Approach

❑ Project Milestones

❑ Financials

❑ Progress Updates

❑ Future Plans



3

Source: EPRI

Project Goals



4

Project Goals and Approach

Medium Voltage Distribution Line

DC/AC Three-

Phase

Inverter

Step-up

60 Hz

Transformer

DC/AC Modular CHB

Three-Phase Inverter

Transformerless

CHB:

Cascaded

H-Bridges

Integrating a battery energy storage

into a medium voltage distribution

system without a bulk step-up 60 Hz

transformer

Using ≥ 10 kV SiC modules for power

electronics interface

Minimizing the number of modules

and complexity.

Comparative analysis between two

enabling technologies, Si versus SiC

switching devices






❑ Financials


❑ Future Plans



Project Milestones6

Milestones for Year 1 (2017) Milestones for Year 2 (2018)Status

Task Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

1DC/AC topology selection and

designComplete

2Topology simulation and

controlsComplete

4 Experimental Verification, SiC versus Si On-going

5 Fault detection, protection circuitry design On-going

6Testing the prototype at NCREPT

testing facilityFuture

7

Testing the

system under

grid faults

Future

8Documentation/

technology transferFuture






❑ Financials


❑ Future Plans



Financials8

• On track to stay within our first year, 2017 budget of $79,946.45

• Second year, 2018 request: $79,653.47

‒ Co-sharing the budget:

i. Only two students are funded on this project, with three

students working on the project

ii. Using medium voltage materials and supplies that are

already in NCREPT






❑ First Year (2017) Expenses


❑ Future Plans



Topology Selection10

Breakdown of entire power electronics unit

losses for different configurations Cost comparison for various configurations



11

Topology Selection

Transformerless Energy Storage Interface by using nine-level Modular

Multilevel Cascaded H-Bridge (CHB) Inverters

Medium Voltage Distribution line

Submodule Battery Unit

AC Grid

A B C

N

CHB-BESS Interface

Topology

𝑉𝐴𝐵,𝑚𝑎𝑥 = 0.612 (𝑚 − 1) 𝑉𝑑𝑐With 𝑚 = 2N +1

N = 4



Building a Prototype for a 13.8 kV Line12

Availability of switching devices

SiC DeviceDC Bus

Voltage

# of cells

per phaseAC 3Փ output Number of Batteries

Number of

Switching

Devices

1.2 kV 720 V 4 3. 173 kV (30 per cell)x4x3 = 360 72

1.7 kV 1.020 kV 4 4.5 kV (43 per cell)x4x3= 516 72

3.3 kV 1.98 kV 4 8.725 kV (83 per cell)x4x3= 996 72

6.5 kV 3.5 kV 4 13.8 kV (146 per cell)x4x3 = 1752 72

10 kV 7 kV 2 13.8 kV (583 per cell)x4x3 = 1752 36

Battery Type Comments Current Grid-scale

Projects( > 1 MW) [1]

Cost for 13. 8kV Cost for 3 kV

Lead Acid Short cycle life, slow

charging, low power and

energy density

16 1752*$10

= $17,520

360*$10

= $3,600

Lithium Ion High energy density and

power, fast response

time, high cost and heat

management

69 1752*$48.09

= $ 84,253.68

360*$48.09

= $17,312.4

Battery bank for dc bus voltage requirement

[1] DOE global energy storage database website, “https://www.energystorageexchange.org/”



Decoupled Current Control13

Active power

control

Decoupled

current control

Discharging and

charging modes

+ -

d-q trans.uiviwi

d-q trans.wgv _

vgv _

ugv _

qidi

dgv _

qgv _

*p

*qqgv _

1

dgv _

1

*qi

*di PI

PI

di

+-

qiωLAC

ωLAC

-++ -

-+

3

1

3

1

Inv.d-q trans.

*dv

*qv

*uv*vv*wv



DC Bus Voltage Balancing Control14

A dc/dc converter is used to regulate the dc bus voltage and the battery current

dc bus voltage regulated by the dc/dc converter

Amps

Amps

Amps

Volts

Volts

Volts

Time (Sec)

Time (Sec)

C

V_ref

V_dc bus

2.0 kV

- 2.0 kV

0 kV

2.0 kV

- 2.0 kV

0 kV

Time [S]



Experimental Verification15

Low-voltage prototype, 5-level cascaded H-bridge inverter,

using SiC discrete devices, open-loop

CH2 5.00V

Van

Vbn

Vcn

Low-voltage prototype, with Vdc = 3.5 V

Testing results, with VAB = 8.66 V rms



16

Low-voltage prototype, 5-level cascaded H-bridge inverter, using SiC discrete devices,

closed-loop

Time (Sec) Time (Sec)

Amps

Amps

Volts Volts

Simulation and Experimental Verification

Discharging Mode Charging Mode



208 Vac Simulation Results17

208 Vac rms voltage prototype, 9-level cascaded H-bridge

inverter, using 1.2 kV SiC modules, closed-loop

𝑉𝐴𝐵,𝑚𝑎𝑥 = 0.612 (𝑚 − 1) 𝑽𝒅𝒄 ∗ 𝒎𝒊

With 𝑚 = 2N +1, Vdc = 48 V, mi =0.9

Volts

Volts

Volts

Time (Sec)

CHB inverter output

voltage

Grid voltage



18

480 Vac rms voltage prototype, 9-level cascaded H-bridge

inverter, using 1.2 kV SiC modules, closed-loop

𝑉𝐴𝐵,𝑚𝑎𝑥 = 0.612 (𝑚 − 1) 𝑽𝒅𝒄 ∗ 𝒎𝒊

With 𝑚 = 2N +1, Vdc = 110 V, mi = 0.9

Volts

Volts

Volts

Time (Sec)

480 Vac Simulation Results

CHB inverter output

voltage

Grid voltage



High Voltage Prototype 19

Up to 3 kV prototype using 1.2 kV SiC MOSFETs

Sensed signals (voltages and currents)

PWMs

FPGA

Board

ADC

Board

Signal

Conditioning

Board

Gate Drivers

1.2 kV SiC,

Prototype

PCB Layout

&

FPGA Programming



Controls Implementation Using FPGAs20

Programming FPGA for controls implementation

Simulation of PWM and sine

reference in Vivado software

Using Xilinx Artix-7 FPGA



Controls Verification on Nine-level CHB Inverter21

Reconfiguration

(Compensation)

Open-switch and short-circuit faults

With 12 V battery bank






Comparative Analysis of SiC vs Si Devices22

SiC MOSFET – 1200V @ 300A – CREE

Part No: CAS300M12BM2

Si IGBT – 1200V @ 300A – MITSUBUSHI

Part No: CM300DX-24T1

High frequency operation Lower frequency operation

High power density Lower power density

Reduced filter size with high switching

frequency

bulky filter size at low switching frequency

Junction temperature > 175 ˚C 175 ˚C max junction temperature

Low power loss per phase stack High power loss per phase stack

Reduced thermal requirements More thermal requirements (bulky heat

sinks)

Low Rds(on) Higher Rds(on)

Higher cost Lower cost

Higher efficiency and reliability Lower efficiency and reliability

Power loss per phase stack: PSW (VB) = 2nCell . (KSW (VB) .1

1000. 𝑖ph .

𝑢

0.5. fs )

Filter size:

…(1)

…(2) Reliability: …(3)



23

Comparative Analysis of SiC vs Si Devices

• Objectives

‒ Breakdown voltage

‒ Thermal performance

‒ Efficiency

‒ Diode reverse recovery

‒ Switching and conduction

losses

‒ Maximum operating

frequency for CHB

‒ EMI noise, dv/dt, di/dt

‒ Cost

Silicon

Saber

Simulator

Circuit physical

model

Si - based

Circuit physical

model

SiC - based

Controls Development

Using Matlab Simulink

Silicon

Carbide

Saber

Matlabsimulink

cosimulation

interface

COMPARISON FOR CHB

MEDIUM VOLTAGE

APPLICATION

Simulation of CHB

MMC using

Saber



Progress Updates (Summary)24

‒ Completed topology simulation for both open-loop and closed loop

controls

‒ Experimental verification on low-voltage prototype, five-level three-

phase CHB inverter

‒ Preliminary testing for nine-level three-phase CHB inverter

‒ Fault detection and protection scheme

• Remainder of Year 1

‒ Complete the experimental verification with 208 Vac

‒ Integrate with dc/dc stage for dc bus balancing and over-current

protection for each submodule batteries

‒ On-going Saber simulation for the comparative analysis between Si

and SiC as enabling technologies






❑ First Year (2017) Expenses


❑ Future Plans



Future Plans26

• Year 2

‒ Fault detection and protection circuitry design

‒ Experimental verification with 480 Vac

‒ Testing integrated system in NCREPT testing facility up to 3 kV

‒ Test the prototype under grid asymmetries and faults

‒ Research report and technology transfer to the IAB members

• Year 2 Request: $79,653.47

‒ 3 students working on this project, and only 2 students funded,

materials and supplies, fabrication/testing, and NCREPT facility

fees



Questions/Comments/Suggestions27

THANK YOU

FOR YOUR TIME

AND SUPPORT



Fault Detection Algorithm28

Switch failures:

Short-circuit

Open-circuit

Short-circuit faults can be detected with the gate driver ICs

Should be detected <10 μs

Open-circuit faults can cause:

Reliability issues

Unbalanced voltage

Destroy the current

System Shutdown

Fault-tolerance



Open Circuit Fault 29

Fault Detection

( Detect the

faulty cell)

Identification

(Locate the

faulty switch)

Isolation

(Isolate the

faulty cell)

Reconfiguration

(Compensation)



Open Circuit Fault30

Cell Fault Detection

If there is an open circuit switch fault, the

output voltage and current are less than the

expected values

The faulty switch acts as a diode, due to the

antiparallel diode

By knowing the relationship between the cell

output voltage and the current direction, the

faulty cell can be detectedCurrent

Direction𝒗𝑯𝟏 𝒗𝑯𝟐

Faulty

Cell

Possible Faulty

Switches

Case

1𝑖 >0 <0 𝑣𝐻2 𝐻1 𝑆11, 𝑆41

Case

2𝑖 <0 >0 𝑣𝐻2 𝐻1 𝑆21, 𝑆31

Case

3𝑖 >0 𝑣𝐻1 >0 𝐻2 𝑆12 , 𝑆42

Case

4𝑖 <0 𝑣𝐻1 <0 𝐻2 𝑆22, 𝑆32




Identification of Failed Switch Location

Once the faulty cell is detected, the LS-PWM is tested to identify the

exact switch that has failed and the subsequent isolation process.

Current

Direction𝒗𝑯𝟏 𝒗𝑯𝟐

Faulty

Cell

Possible

Faulty

Switches

Fault Conditions

Case 1 𝑖 >0 <0 𝑣𝐻2 𝐻1 𝑆11, 𝑆41𝑆41 is ON, 𝑆11 is fault

Otherwise, 𝑆41 is fault

Case 2 𝑖 <0 >0 𝑣𝐻2 𝐻1 𝑆21, 𝑆31𝑆21 is ON, 𝑆32 is fault


Case 3 𝑖 >0 𝑣𝐻1 >0 𝐻2 𝑆12 , 𝑆42𝑆42 is ON, 𝑆12 is fault


Case 4 𝑖 <0 𝑣𝐻1 <0 𝐻2 𝑆22, 𝑆32𝑆22 is ON, 𝑆32 is fault





Simulation result of an open circuit fault switch on 𝑆11 at t=0.054 s, (a) the output voltage;

(b) output voltage of H1; (c) PWM signal of 𝑆41; and (d) 𝑆11 ( red) and the fault detection

signal (black).




(a) (b)(a)

(a)

(a)(a) (b)

PWM signal of 𝑺𝟒𝟏 (ch1), 𝒗𝑯𝟏 (ch2), 𝒗𝑯𝟐 (ch3), and output current (ch4). (a) Normal operation.

(b) An open fault on 𝑺𝟏𝟏.

PWM signal of 𝑺𝟒𝟐 (ch1), 𝒗𝑯𝟏 (ch2), 𝒗𝑯𝟐 (ch3), and output current (ch4). (a) Normal operation. (b)

An open fault on 𝑺𝟏𝟐.




Isolation methods

Hardware- TRIACs, Thyristors, or Conductors

Software- Bypass the faulty switch

After the faulty cell isolate, one level is missed- From 7 to 5 level CHB

Hardware

Software

nsf center for grid-connected advanced power electronic ... · 11/8/2017 · multilevel cascaded...

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