150272-1732/00/$10.00 2000 IEEE

Interconnecting communicatingentities is one of the fundamental problems incomputer science and engineering. Intercon-nection problems occur at various levels—between gates in a chip, between chips on amodule or board, between boards across a back-plane, and among autonomous computer sys-tems that may span large geographical areas.The complexity of interconnections often hasa profound influence on the cost, performance,and reliability of the resulting system.

This special issue of IEEE Micro features sixarticles on the topic of interconnection andnetworking, drawn from the papers present-

ed at the Seventh IEEE Hot InterconnectsSymposium held at Stanford University inAugust 1999. The annual Hot Interconnectsis held as a companion to the IEEE Hot ChipsSymposium. Hot Interconnects covers a largespectrum of interconnect topics, from circuit-level technology to network architectures andprotocols. The organizers particularly directthe sessions at new, exciting product and tech-nology innovations in these areas. This year’ssymposium featured presentations on networkswitching and routing, optical interconnectsand networking, network-attached storagesystems, system-level I/O interconnect tech-

Anujan VarmaUniversity of California,

Santa Cruz

Mark LaubachInconvenient Networks

SOLVINGINTERCONNECTIONPROBLEMS

nologies, and home networks. The six articlesincluded here represent a cross section of the22 papers presented at the symposium.

The articles address interconnection andnetworking problems at various levels and indifferent contexts. The first article, “Archi-tectural Considerations for CPU and Net-work Interface Integration,” discusses thedesign of efficient network interfaces. Thisproblem is becoming increasingly importantbecause of the range of devices that are beingconnected to the Internet. Achieving thedesired performance at a low cost requires theintegration of processing and interface func-tions on the same chip. The authors proposean architecture that integrates network inter-face functions with a processor and evaluatesits performance in two example applications.

A critical function that needs to be per-formed within every packet switch or routeris address lookup. This function is responsi-ble for determining the outgoing link to for-ward an incoming packet, based on addressinformation contained within the packet.When forwarding occurs at the IP (InternetProtocol) layer, the operation is more com-plex than a flat lookup of an address to yieldthe forwarding information. The routing tablein an IP router or switch is usually organizedas a set of address prefixes, and the functionof the lookup algorithm is to determine thelongest prefix in the table that matches thedestination address of the incoming packet.The recent literature has proposed many algo-rithms for the efficient determination of suchlongest prefix matches. The “Cache MemoryDesign for Internet Processors” article pro-poses the caching of address ranges in thelookup table as a solution to the problem andevaluates the trade-offs involved.

Packet classification is another importantproblem in the design of routers and switches,where one or more header fields of an incom-ing packet are matched against a set of rules todetermine its class. Packet classification maybe necessary for several reasons (service differ-entiation, service guarantee provisions, policyenforcement, congestion control, and load bal-ancing). This function is becoming increas-ingly important because of the need forsupporting multiple types of traffic in packetnetworks. Because of the need to classify pack-ets along multiple dimensions, the problem is

computationally demanding. However, therecent literature has proposed a number ofalgorithms to provide this function in switch-es and routers. These algorithms make trade-offs among the classification time, size of thedata structure maintained by the algorithm,and time needed for preprocessing the ruledatabase into the internal data structures.

In “Classifying Packets with HierarchicalIntelligent Cuttings,” the authors observe thatdeterministic algorithms to solve the generalpacket classification problem can be tooexpensive for large rule bases and proposeheuristic algorithms as an attractive alterna-tive. Their approach is to divide the space ineach dimension recursively into intervals andorganize the rules that fall into each interval asthe nodes in a tree. The partitioning is donesuch that the number of rules represented byeach node in the tree is within a set limit. Thiscan result in an efficient search tree for a givenset of rules, making the classification fast.However, the drawback is the long prepro-cessing time to generate the data structure.The approach is attractive when the rules donot change frequently, so that the data struc-ture will not need to be updated often.

Traffic scheduling is yet another functionsupported by current-generation switches androuters. The function of a traffic-schedulingalgorithm is to determine the relative priori-ties among the packets that are competing fortransmission on an outgoing link. These algo-rithms are necessary for providing bandwidthand delay guarantees to packet streams, andfor the fair distribution of resources in the net-work. The authors of “A Scheduler ASIC fora Programmable Packet Switch” describe theimplementation of a scheduling algorithm ina chip designed at the University of Toronto.

The last two articles deal with I/O intercon-nection. The first, “Authenticating Network-Attached Storage,” concerns the attachment ofa storage device directly to a computer networksuch as a LAN (local-area network). This elim-inates the need for specialized standards andprotocols for I/O interconnection. However,computer networks are much more accessibleand much less secure than I/O networks, andrequire authentication mechanisms to main-tain the integrity of the I/O system in an opennetwork environment. The authors proposesolutions to this problem.

16

GUEST EDITORS’ INTRODUCTION

IEEE MICRO

The final article evaluates the IEEE-1394serial bus, which is widely used for the inter-connection of consumer electronics equip-ment such as camcorders to personalcomputers. In “An Empirical Analysis of theIEEE-1394 Serial Bus Protocol,” the authorsprovide insights into the operation of theIEEE-1394 bus protocols from measurementsperformed on several system configurations,using an analyzer they designed.

Hot Interconnects 8 will meet once againat Stanford University in 2000. For

information, visit the symposium Web site atwww.hoti.org. MICRO

AcknowledgmentsThe Hot Interconnects Program Committee

and a few other reviewers reviewed all the paperssubmitted to the symposium, including the arti-cles presented here. We thank them for theirefforts. We also thank Daniel Pitt, Hot Inter-connects 7 general chair, for the opportunity toserve as program chairs for the symposium.

Anujan Varma is a professor of computerengineering at the University of California,Santa Cruz. Previously, he worked at the IBMThomas J. Watson Research Center in York-town Heights, New York, and has consultedextensively for the networking and semicon-ductor industries. His current research inter-ests are in high-speed switching and routinghardware, traffic management, optical net-works, congestion control and scheduling,and video and audio transport over packetnetworks. Varma received his PhD in com-puter engineering from the University ofSouthern California. He has published over100 papers in refereed journals and confer-ence proceedings, and holds nine patents. Hehas received several awards including theNational Science Foundation Young Investi-gator award, the IEEE Darlington award, anda teaching innovation award from the Uni-versity of California.

Mark Laubach is an independent consultantand a cofounder and past vice president andchief technology officer at Com21 in Milpi-tas, California. There, he directed the end-to-end systems architecture, protocol design,performance, and technology of CATV

broadband access telecommunications prod-ucts. Earlier, he worked with the Hewlett-Packard Company. Laubach holds a bachelor’sdegree in electrical engineering and a master’sin computer science from the University ofDelaware. He is past chair of the IP-over-ATM working group and the author of theRFC1577/2225 Classical IP and ARP OverATM (IPOA) standard. He has participatedin cable TV standards activities (IEEE, IETF,ATM Forum, SCTE, and CableLabs’ DOC-SIS). He is a senior member of IEEE and amember of the ACM and SCTE (Society ofCable Telecommunications Engineers).

Direct comments about this special issueto Anujan Varma, Computer EngineeringDepartment, University of California, SantaCruz, CA 95064; varma@cse.ucsc.edu.

17JANUARY–FEBRUARY 2000

Call for ContributionsHot Interconnects 8

August 16-18, 2000 Stanford UniversityStanford, California, USA

Sponsored by the IEEE Computer Society Technical Committee on Microprocessors and

Microcomputers

General Chair: Mark Laubach, Inconvenient Networks

Program Chair:James Yee, COM21

Hot Interconnects is an international symposium focusing on the hard-ware and software architecture and implementation of high-performanceinterconnects of all scales. The theme of the year 2000 meeting addressesthe cross-cutting issues spanning computer systems and networking tech-nologies for providing universal services over packet networks.

Example topics include optical networking, network-attached storage,transport of emerging services over packet networks, high-performance net-work interfaces, wireless interconnects, novel switching and routing tech-nologies capable of providing differentiated services, plug-and-play networkinterfaces, and active network architectures. The conference is directed par-ticularly at new and exciting product and technology innovations in theseareas. Contributions should focus on real products, prototypes, or experi-mental systems and their performance evaluation.

Access the complete Call for Contributions and more information on thesymposium at

www.hoti.org