ntu confidential test asynchronous fir filter design presenter: po-chun hsieh advisor:tzi-dar chiueh...
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NTU Confidential
Test Asynchronous FIR Filter Test Asynchronous FIR Filter DesignDesign
Presenter: Po-Chun HsiehAdvisor:Tzi-Dar Chiueh
Date: 2003/12/1
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OutlineOutline
• Low Power Issue of Asynchronous Circuits• Test FIR Design - Logic circuits
- Multiplier - FIR Architecture• Future work• Conclusion• Reference
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Low Power Issue of Low Power Issue of Asynchronous CircuitsAsynchronous Circuits
• No global clock• Functions work only when
needed• Dynamic Logic and Domino
Logic
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Asynchronous FIR filter and other Asynchronous FIR filter and other Asynchronous ModulesAsynchronous Modules
• Every component of FIR works in each evaluation
• For other modules, functions work only when needed
A input 16bits B input 16bitsOperator 2 bits
Exponent Operationcomepare
Smaller Biger
Shift Right
Multiplier & Divider
Adder & Subtractor
MUX21 Array X12
MUX21 X5
MUX21 Array
Exponent of A or B
Adder_Subtractorexponent
Exponent of Sum
Control Unit
Z-1Z-1Z-1 Z-1
X X X X X
++++
h(o)h(1)h(N-2)h(N-1)h(N)
x(n)
y(n)
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Low power FilterLow power Filter
• Logic circuits• Multiplier• FIR Architecture
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Computation UnitsComputation Units
• 4-phase handshaking is easier to design
• Req in is low clean the content “done” is low
• Req in is high evaluate “done” is high
Previous ComputationB
ComputationA
Handshakecircuit
Rin Rout
Aout Ain
ComputationUnit
Reg
Rin
Aout
Rout
Ain
Rin Rout
AinAout
Aout +
Ain +
Aout -
Ain -
Rin -
Rin +
Rout +
Rout -
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Dynamic Logic and Domino Dynamic Logic and Domino LogicLogic
• Match the requirements for Computation Unit
• No spontaneous transitions, low power
• Drawbacks– Must be Monotonous Inputs– Completion Detection Methods
StaticCMOS
Dynamic(Domino)
A
Req
Req
A -A
B-B
Req
Req
Out
A
-A
-B
B
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Problem of Bounded delay Problem of Bounded delay methodmethod
• How to design delay element ?
Req
A
B C
BA
Req
Req
Cout
Req
Req
Req
Req
done
Req
done
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Problem of activity-monitoring Problem of activity-monitoring completion-detection (AMCD) method completion-detection (AMCD) method
(1/2)(1/2)
• Test the transitions at important points
• Used in Single-rail CMOS Logic
[1]
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Problem of activity-monitoring Problem of activity-monitoring completion-detection (AMCD) completion-detection (AMCD)
method (2/2)method (2/2)
• When used in dynamic (domino) logic, maybe it will never pull down the signal
[2]
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Differential Cascode Voltage Switch Differential Cascode Voltage Switch Logic (DCVSL)Logic (DCVSL)
• Dual-rail Domino Logic gate• Drawbacks: Area、 Power consumption• Completion detection method only add in the outpu
t cascode stages
A.t A.tA.f A.f
B.t B.tB.f B.f
C.t C.tC.f C.f
Req Req
Req
Sum.tSum.f
A.t
B.t C.t
B.tA.t
Cout.t
Req
Req
A.f
B.f C.f
B.fA.f
Cout.f
Req
Req
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Low power Logic gateLow power Logic gate
• Single-rail bounded-delay dynamic (domino) logic gates are very low power, but have two problems
• Before finding solutions, choose to use DCVSL
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Asynchronous MultiplierAsynchronous Multiplier
• Multiplier is the most important part in a FIR filter
• Sign and Magnitude [5]
Carry Resolution Adder
MD(0)MD(1)MD(2)MD(3)
MR(0)
MR(1)
MR(2)
MR(3)
P(0)P(1)P(2)P(3)P(4)P(5)P(6)P(7)
Carry SaveAdder Array
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Data Dependent Carry Save Data Dependent Carry Save Adder Array (1/2)Adder Array (1/2)
• MD: Multiplicand; MR: Multiplier; PP: Partial Product
(n)-thbit
(n+1)-thbit
(n)-thbit
(n+1)-thbit
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MR(0)=1
MR(1)=0
MR(2)=1
MR(3)=0
MD
Data Dependent Carry Save Data Dependent Carry Save Adder Array (2/2)Adder Array (2/2)
• 4X4 Carry Save Adder array
• By probability, only turn on 50% adders
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Partially work by DCVSL LogicPartially work by DCVSL Logic
• If MR(n)=“1” ( MR(n).t=“1”; MR(n).f=“0”; )
then the adder cell works• If MR(n)=“0” ( MR(n).t=“0”; MR(n).f=“1”; )
then the adder cell will not work
Pre/eva
Pre/eva
Pre/eva
Sum.tSum.f
Full AdderCO.tCO.f
Req
MR(n).tPre/eva
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FIR ArchitectureFIR Architecture
• H: Handshake Circuit; h(0)~h(N): coefficients
Z-1Z-1Z-1 Z-1
X X X X X
++++
HHHH
h(o)h(1)h(N-2)h(N-1)h(N)
x(n)
y(n)
Handshake Circuit
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Future WorkFuture Work
• Test the designed FIR module• Search for low power FIR architecture and
Multiplier• Try to find solutions to the problems of
single-rail dynamic (domino) logic
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ConclusionConclusion
• Unlike other kinds of Asynchronous circuits, every component of FIR works every time.
• Choose FIR architecture, Multiplier, and Implement Circuits to make FIR low power.
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ReferenceReference[1] Grass, E. and S. Jones, "Activity-monitoring completion-detect
ion (AMCD): a new approach to achieve self-timing", Electronics Letters, vol. 32, no. 2, pp. 86-88, January 1996
[2] Bartlett, V.A. and E. Grass, "Completion-detection technique for dynamic logic," Electronics Letters, vol. 33, no. 22, pp. 1850-1852, Oc
tober 1997. [3] Bartlett, V. A. and E. Grass, “A Self-Timed Multiplier using Con
dutional Evaluation", Proc. PATMOS'98, 8th International Workshop on Power, Timing, Modelling, Optimization and Simulation, Lyngby, Denmark, pp.429-438, October 1998
[4] D.Kearney and N.W.Bergmnn, “Bundled Data A syncheonous Multipliers with Data Dependent Computation Times”,Proc. ASYNC’97, 2nd Int.Symp. On Advanced Research in Asynchronous Circuits and Systems,pp. 186-197,1997
[5] Bartlett, V. A. and E. Grass, “A Low-Power Asynchronous VLSI FIR Filter", Proc. ARVLSI'01, 19th Conference on Advanced Research in
VLSI, Salt Lake City, Utah, USA, March 2001.