october 11-16 2009, chernogolovka 1 physikalisch-technische bundesanstalt, braunschweig m. khabipov,...
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October 11-16 2009, Chernogolovka 1
Physikalisch-Technische Bundesanstalt, Braunschweig
M. Khabipov, D. Balashov, F. Maibaum, A. ZorinPhysikalisch-Technische Bundesanstalt, Bundesallee 100, 38116 Braunschweig, Germany
V. A. Oboznov, V. V. Bolginov, A.N. Rossolenko and V. V. Ryazanov Institute of Solid State Physics, Chernogolovka, 142432 Moscow region, Russia
The work was supported by DFG (German Science Foundation) through grant ZO124/2-1 and the joint grant of DFG and the Russian Foundation of Basic Researches and grants of the Russian Academy of Sciences.
Application of phase shifters in superconducting digital circuits
October 11-16 2009, Chernogolovka 2
Outline
• Introduction• Basic principles of Rapid Single Flux Quantum (SFQ) circuits• SFQ circuits fabrication technology at PTB
• Operation of an SFQ circuits with integrated phase shifters based on – superconducting loop with trapped flux quantum– Superconductor-Ferromagnetic-Superconductor -junction
• Conclusion • Outlook
October 11-16 2009, Chernogolovka 3
V
ICJJ JJ - Josephson junction
C – self-capacitance
2c
c 20 p
2ICR2C= Stewart-McCumber parameter
V
I
Ic
IReturn
0
Underdamped JJ Overdamped JJ
C
I
V
Ic
IReturn
C
0
RSJ model of Josephson tunnel junction
Rdamping resistor
October 11-16 2009, Chernogolovka 4
V
I
Ic
a short trigger pulse
I(t)
time
“sweep” of the
dc I-V curve
V(t)Generation ofa SFQ pulse
(strictly 2-leap of phase!)
0V(t)dtResult:
Idc bias
This pulse (carrier of information) can be used as a trigger pulse
for other junctions - the basis of Rapid Single Flux Quantum circuits!
(Likharev et al. 1985)
Reaction on a short pulse
Advantages of RSFQ: quantized information, fast (typically, few ps) switching time, low level of dissipation
R
a few Ohm
October 11-16 2009, Chernogolovka 5
SFQ pulse generation move to the
adjacent minimum
U() = - EJcos - (0/2) I +const
washboard potential
effect of the trigger pulse!
R
Low amplitude signals (noise) not reproduced by the circuita noise discriminator
large damping due toexternal shunt resistor
October 11-16 2009, Chernogolovka 6
Definition of coding in RSFQ logic
„0“
„0“
„1“
„1“ „0“
„0“
The binary code: presence (absence) of SFQ pulse between adjacent clock SFQ pulses
(for comparison) different voltage levels (CMOS, TTL, “latching” logic)
Time, a. u.
V/Vc
V/Vc
V/Vc
clock pulses
information pulse
information pulse
October 11-16 2009, Chernogolovka 7
RSFQ dc/SFQ and SFQ/dc converter circuit
dc/SFQconverter
T-Flipflop with SFQ/dc converter
Josephson transmission line
J 20L1
J 1 9
J 1 7 J 18
L2
R
I _L
J 2 1 J 2 3
J 2 4
J 2 2
J 2L i n
J 3J 1 J 4 J 5
I _in
V_out
I _b
Circuit provide generation and back conversion of SFQ pulses into voltage signals
V. Kaplunenko et al. IEEE Trans. Magnetics 25, 861-864, 1989
K. Likharev and V. Semenov IEEE Trans. Appl. Supercond. 1, 3-28, 1991
October 11-16 2009, Chernogolovka 8
RSFQ T-flip-flop circuitCircuit provides a frequency division of SFQ pulses
K. Likharev and V. Semenov IEEE Trans. Appl. Supercond., 1, 1991
jc = 100 A/cm2 operation frequency f = Vc /Ф0 =Ic Rn /Ф0 up to 40 GHz power consumption P = V Ibias = 15 nW
As result frequency division !
Ibias
October 11-16 2009, Chernogolovka 9
T-flip-flop circuit, results of simulation
Phase drop, input junction
Phase drop, TFF junctions
Voltage, input junction
Voltage, TFF junction
Voltage, TFF junction
October 11-16 2009, Chernogolovka 10
Frequency division realised in CMOS logic(for comparison)
Pdyn = CeffV2DD x f
For example, at 30fF/gate at 100MHz and VDD = 5 V, 75 μW is dissipated per gate
UMBC, University in Mariland, Advanced VLSI designhttp://www.csee.umbc.edu
.The circuit consists of 10 gates and includes about 50 transistors
Paul Horowitz, Winfield Hill. The Art of Electronics,Cambridge University Press, Second Edition, 1989
October 11-16 2009, Chernogolovka 11
SFQ circuits Nb/Al thin-films fabrication technology established at PTB
Shielding of an electromagnetic noise, realization of the low value inductances
realization of the shunt and bias current resistors
jc between 100 A/cm2 and 1 kA/cm2
-deposition and etching of The Nb ground plane
- anodization of the ground plane
-deposition of the Nb/AlxOy/Nb trilayer-deposition of a thin SiO2 layer
- deposition and etching of the
- deposition of the SiO2 isolation layer- etching of the contact holes
Cr/Pt/Cr resistor trilayer
- deposition of the SiO2 isolation layer
October 11-16 2009, Chernogolovka 12
-etching of the thin SiO2 isolation layer and the Nb counter electrode, definition of JJs
-anodization with the thin SiO2 layer as a mask-etching of the base electrode
-deposition and etching of the SiO2 isolation layer
J J
S i O2- a n o d iz a t io n m a s k
A l2O
3
N b 2O 5
S i O2
SFQ circuits Nb/Al thin-films fabrication technology established at PTB
Smallest junction area A=10 µm2
October 11-16 2009, Chernogolovka 13
Cross-section of shunted Josephson junction in Nb/Al technology
Cr/Pt/Cr damping resistor Rsq=2Ω/sq.
Tunnel barrier AlxOy
Thermally oxidized silicon substrate
JJ
Si
SiO2
Nb
Al
Al2O3
Nb2O5
Cr/Pt/Cr
Vol
tage
V
A = 24 µm2
Ic 20 µA
Rn 59 Ω
IR
T = 4.2 K
(1m
V/d
iv)
IV curve of the underdamped JJ
Rsh IC
Current I (20µA/div)
IV curve of the overdamped JJ
Vol
tage
V
(1
00µ
V/d
iv)
JJ
Current I (20µA/div)
A = 24 µm2
Ic 24 µA
Rsh 4 Ω
IC
C>>1 C ~ 1
T = 4.2 K
October 11-16 2009, Chernogolovka 14
Qubit control and read out: low back action on Josephson qubit cells (low value Ic, large value of shunt resistor, low power
consumption)
Low Ic value due to Ic x L ~Ф0 result in proportionally increased value of inductances L, circuits have a large area and became sensitive to an electromagnetic noise
Physikalisch-Technische Bundesanstalt, Braunschweig
Why we need phase shifting elements in RSFQ?
October 11-16 2009, Chernogolovka 15
TFF with RC shunted Josephson junctions. Parameters: jc=100 A/cm2, Ic= 16µA, L=130 pH
Conventional TFF with large storing inductance
L
Symmetry of the TFF states is due to phase drop of about created by dc control current:
Compact phase shifters are required
0-JJ
L
Superconducting loop with trapped flux quanta
The shift can also be realized on the basis of HTS junctions exhibiting the d-wave symmetry of the order parameter (see T. Ortlepp et al. Science 312, 1495, 2006)
Icontr
=
SFS
October 11-16 2009, Chernogolovka 16
Superconducting loop with trapped flux quantum as a phase shifting element
I shifter
I shifter
External flux applied at T > TC Nb
(T = 10 K)
External flux turned of when T < TC Nb (liquid helium temperature T = 4.2K). Quantized flux
trapped trapped = n 0
0 2.07 mVps (single flux quantum)
trapped = n 0 Flux quantization law
The work carried out in collaboration with the group in TU Ilmenau
It was proposed as a phase-bias circuit for the Josephson qubit in J.B. Majer et al. APL 80, 3638, 2002.
T = 10 K T = 4.2 K
October 11-16 2009, Chernogolovka 17
Superconducting loop with trapped flux quantum as a phase shifting element
The work carried out in collaboration with the group in TU Ilmenau
During the cooldown, the flux is trapped in the ground plane hole.
Pinning a flux quanta into ground plane hole
October 11-16 2009, Chernogolovka 18
Conventional TFF and TFF with integrated π – shifter
J4J3
Lshifter
J1 J2
TFF input
TFF out2TFF out1
J4J3
Lint
J1 J2
TFF input
TFF out2TFF out1
Schematic diagram of the ordinary TFF circuit
Schematic diagram of the TFF with integrated -shifter
The large quantizing inductance Lint can be replaced by passive π – shifter, ensuring bistable functioning of the TFF
D. Balashov et al., IEEE Trans. Appl. Supercond. 17, 142, 2007
October 11-16 2009, Chernogolovka 19
Simpler circuit:dc-interferometer with integrated π–shifter
Microphotograph of the sample
Circuit parameters:
IC 270 µA, RN 0.8 , Lshifter 7 pH (at T=4.2K), and Lshifter 15 pH (at T=10K),
Flux bias current for single 0 operation mode Icontr 200 µA
Control line
JJJJ
VoutIbias
IsweepIsweep
dc-interferometer with integrated π – shifter
J2J1
Ibias Vout
IsweepIsweep
-shifter
+
October 11-16 2009, Chernogolovka 20
Experimental testing of the dc-interferometer with integrated π–shifter
No flux trapped in the shifter loopIcontr 0 µA
Voltage-flux characteristics of the dc-interferometer with integrated shifter loop realized in jC=1 kA/cm2 Nb/Al technology
1 0 trapped in the shifter loopIcontr 200 µA
V (
20
µV
/div
)
Flux Current Isweep ( 200 µA/div)
0/2
0
J2J1
Ibias Vout
IsweepIsweep
Voltage-flux characteristics
October 11-16 2009, Chernogolovka 21
TFF circuit with integrated π–shifter
Microphotograph of the sample
TFF input
-shifter
+
J4J3
TFF separate bias
Control line
TFF out-1 TFF out-2 Lshifter
J1 J2
TFF input
TFF out-2TFF out-1
Schematic diagram of the TFF with integrated -shifter
October 11-16 2009, Chernogolovka 22
Block-diagram of tested circuit including TFF with integrated π – shifter
TFF with -shifter should operate as a frequency divider 2:1
-shifter
+
Control line
V_out2V_out1
(Divider 2:1)(Divider 2:1)
I_in
October 11-16 2009, Chernogolovka 23
Experimental testing of the circuit with integrated π–shifter
Circuit realized in Nb/Al technology with jC=1k A/cm2
When no flux trapped in the
π – shifter loop fout1 = fout2= fin/2
Bias current margin of the circuit is 20%
Vol
tage
(2
00 µ
V/d
iv)
Cur
rent
(50
0 µ
A/d
iv)
Time t ( 5 ms/div)
When 0 trapped in the
π – shifter loop fout1 = fout2= fin/4
Bias current margin of the circuit is 17%
I_in
I_in
V_out2
V_out1
V_out2
V_out1
October 11-16 2009, Chernogolovka 24
-junction as a phase inverting element
Bulaevsky, Kuzii and Sobyanin, JETP Lett. (1977)
0-junctionenergy minimum at 0
-junctionenergy minimum at
I=Icsin[+]= -Icsin
I
I
E
E
0 -
22
Josephson current-phase relation
π-junction current- phase relation
E= EJ[1-cos]
I=Icsin
-JJSymbolic notation
- E= EJ[1-cos(+ )]=EJ[1+cos]
October 11-16 2009, Chernogolovka 25
Superconductor-Ferromagnet-Superconductor (SFS) junction: 0-state and π–state
-junction
“”- state
I = Icsin(+) = - Icsin()
Nb-Cu0.47Ni0.53-Nb
“0”-state I=Icsin
“0”-state I=Icsin
V. A. Oboznov et al. PRL 96, 197003, 2006
dF = 12-22 nm
October 11-16 2009, Chernogolovka 26
Cross-section of shunted Josephson junction in Nb/Al technology and ferromagnetic based junction
SIS-junctionjc=100 A/cm2
A = 10 µm2
SFS-junctionjc=850 A/cm2
A = 8x8 µm2
Topologically, the SFS junction is placed between Nb-wiring nodes of pre-fabricated circuit.
October 11-16 2009, Chernogolovka 27
dc-interferometer with integrated SFS π-junction
Voltage-flux characteristics of the dc interferometers:a) conventional, b) with SFS p-junction
October 11-16 2009, Chernogolovka 28
Integration of the - SFS junction into TFF circuit
JTL JTL
JTLIn
I_b
Out2Out1
JTL JTL
JTLIn
I_b
Out2Out1
∆ = π
L
π-SFS
JJ
JJ
JJ
JJ
JJ JJ
JJ JJ
Conventional TFF circuit TFF with integrated π-SFS junction
Proposed in: A. Ustinov and V. Kaplunenko J. Appl. Phys. 94, 5405, 2003
October 11-16 2009, Chernogolovka 29
Integration of the - SFS junction into TFF circuit
Phase drop, input junction
Phase drop, TFF junctions
Voltage, TFF junction
Voltage, TFF junction
Voltage, -junction
operation ranges: jc = 32%, Ib = 40%, L = 50% - junction substituted
by fixed phase shift of and junction having Ic of large value
October 11-16 2009, Chernogolovka 30
Microphotograph of integrated circuit
JTL
JTL
TFF
SFQ/dc
SFQ/dc
50 µmI_inI_bias
V_out2V_out1
SFS -junction
dc/SFQ
SFQ pulses generated by dc/SFQ converter, processed by TFF with integrated -SFS junction and converted to the voltage levels by SFQ/dc converter circuits
October 11-16 2009, Chernogolovka 31
TFF circuit with integrated SFS π–junction
a) Block diagram of the test circuit b) microphotograph of the TFF circuit
October 11-16 2009, Chernogolovka 32
Proof of correct operation of TFF circuit with integrated SFS π–junction
50 m
T F F o u t 2
T F F - c o r e c e l l
In
pu
t
T F F o u t 1
S F S j u n c t i o n - 20 A/div Iin
Vout1
Vout2
Time t, 10 ms/div
50 V/div
50 V/div
T in T T 4T out1 out2 in = =
When SFS junction is in a π–state then circuit operates properly
Tout1 = Tout2= 4Tin
Bias current margin of the circuit is 19% and limited by bias current margins of dc/SFQ converters!
Circuit realized in Nb/Al technology with jC=100 A/cm2
October 11-16 2009, Chernogolovka 33
Conclusion
• We have successfully integrated the phase shifting elements in RSFQ circuits without deep modification of currently available technological process.
• The following phase shifting elements were experimentally studied:
– superconducting ring with trapped
flux quantum
– SFS -junctions
0
-JJ
October 11-16 2009, Chernogolovka 34
Outlook
Measurements of operation ranges of bias current of SFQ circuits with integrated SFS -junctions
- design of the TFF circuit with separate bias currentBit error rate (BER) measurements
- realisation of the TFF circuit incorporated into ring oscillator