omap4430_es2.x_public_trm_vp

OMAPPublic Version

OMAP4430 Multimedia Device Silicon Revision 2.xVersion P

Texas Instruments OMAP Family of Products

Technical Reference Manual

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LI MLiterature Number: SWPU231P July 2010 Revised January 2011

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.................................................................................................................................... Introduction .................................................................................................................... 1.1 Overview .................................................................................................................. 1.2 Environment .............................................................................................................. 1.3 Description ................................................................................................................ 1.3.1 Cortex-A9 MPU Subsystem Description ..................................................................... 1.3.2 IVA-HD Subsystem Description ............................................................................... 1.3.3 Cortex-M3 MPU Subsystem Description ..................................................................... 1.3.4 Display Subsystem Description ............................................................................... 1.3.5 ABE Subsystem Description ................................................................................... 1.3.6 ISS Description .................................................................................................. 1.3.7 2D/3D Graphics Accelerator Description .................................................................... 1.3.8 Face Detect Module Description .............................................................................. 1.3.9 On-Chip Debug Support Description ......................................................................... 1.3.10 Power, Reset, and Clock Management Description ....................................................... 1.3.11 On-Chip Memory Description ................................................................................ 1.3.12 Memory Management Description ........................................................................... 1.3.13 External Memory Interface Description ..................................................................... 1.3.14 System and Connection Peripherals ........................................................................ 1.3.14.1 System Peripherals ....................................................................................... 1.3.14.2 Connection Peripherals .................................................................................. 1.4 Package-On-Package Concept ........................................................................................ 1.5 Device Identification ..................................................................................................... Memory Mapping ............................................................................................................. 2.1 Introduction ............................................................................................................... 2.2 L3 Memory Space Mapping ............................................................................................ 2.2.1 L3_EMU Memory Space Mapping ............................................................................ 2.3 L4 Memory Space Mapping ............................................................................................ 2.3.1 L4_CFG Memory Space Mapping ............................................................................ 2.3.2 L4_WKUP Memory Space Mapping .......................................................................... 2.3.3 L4_PER Memory Space Mapping ............................................................................ 2.3.4 L4_ABE Memory Space Mapping ............................................................................ 2.4 Dual Cortex-M3 Subsystem Memory Space Mapping .............................................................. 2.5 DSP Subsystem Memory Space Mapping ............................................................................ 2.6 Display Subsystem Memory Space Mapping ........................................................................ 2.6.1 L3 Interconnect View of the Display Memory Space ....................................................... 2.6.2 L4 Interconnect View of the Display Memory Space ....................................................... Power, Reset and Clock Management ................................................................................ 3.1 Device Power Management Introduction ............................................................................. 3.1.1 Device Power-Management Architecture Building Blocks ................................................. 3.1.1.1 Clock Management ....................................................................................... 3.1.1.1.1 Module Interface and Functional Clocks .......................................................... 3.1.1.1.2 Module-Level Clock Management .................................................................

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3.1.1.1.3 Clock Domain ......................................................................................... 3.1.1.1.4 Clock Domain-Level Clock Management ......................................................... 3.1.1.1.5 Clock Domain HW_AUTO Mode Sequences ..................................................... 3.1.1.1.6 Clock Domain Sleep/Wakeup ...................................................................... 3.1.1.1.7 Clock Domain Dependency ......................................................................... 3.1.1.2 Power Management ...................................................................................... 3.1.1.2.1 Power Domain ........................................................................................ 3.1.1.2.2 Module Logic and Memory Context ................................................................ 3.1.1.2.3 Retention-Till-Access Memory Feature ............................................................ 3.1.1.2.4 Power Domain Management ....................................................................... 3.1.1.3 Voltage Management .................................................................................... 3.1.1.3.1 Voltage Domain ...................................................................................... 3.1.1.3.2 Voltage Domain Management ...................................................................... 3.1.1.3.3 AVS Overview ........................................................................................ 3.1.2 Power-Management Techniques ............................................................................. 3.1.2.1 Standby Leakage Management ......................................................................... 3.1.2.2 Dynamic Voltage and Frequency Scaling ............................................................. 3.1.2.3 Dynamic Power Switching ............................................................................... 3.1.2.4 Adaptive Voltage Scaling ................................................................................ 3.1.2.5 Adaptive Body Bias ....................................................................................... 3.1.2.6 Combining Power-Management Techniques ......................................................... 3.1.2.6.1 DPS Versus SLM ..................................................................................... PRCM Subsystem Overview ........................................................................................... 3.2.1 Introduction ...................................................................................................... 3.2.2 Power-Management Framework Features .................................................................. PRCM Subsystem Environment ....................................................................................... 3.3.1 External Clock Signals ......................................................................................... 3.3.2 External Boot Signals ........................................................................................... 3.3.3 External Reset Signals ......................................................................................... 3.3.4 External Power Control Signals ............................................................................... 3.3.5 External Voltage Inputs ........................................................................................ PRCM Subsystem Integration .......................................................................................... 3.4.1 Device Power-Management Layout .......................................................................... 3.4.2 Power-Management Scheme, Reset, and Interrupt Requests ............................................ 3.4.2.1 Power Domain ............................................................................................ 3.4.2.2 Resets ...................................................................................................... 3.4.2.3 Interrupt Requests ........................................................................................ Reset Management Functional Description .......................................................................... 3.5.1 Overview ......................................................................................................... 3.5.1.1 SCRM Reset Management Functional Description .................................................. 3.5.1.1.1 Power-On Reset ...................................................................................... 3.5.1.1.2 Warm Reset ........................................................................................... 3.5.1.2 PRM Reset Management Functional Description .................................................... 3.5.2 General Characteristics of Reset Signals .................................................................... 3.5.2.1 Scope ....................................................................................................... 3.5.2.2 Occurrence ................................................................................................ 3.5.2.3 Source Type ............................................................................................... 3.5.2.4 Retention Type ............................................................................................ 3.5.3 Reset Sources ................................................................................................... 3.5.3.1 Global Reset Sources .................................................................................... 3.5.3.2 Local Reset Sources ..................................................................................... 3.5.4 Reset Domains .................................................................................................. 3.5.5 Reset Logging ...................................................................................................

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3.5.6.11 Cortex-M3 MPU Subsystem Power-On Reset Sequence ........................................... 3.5.6.12 Cortex-M3 MPU Subsystem Software Warm Reset Sequence .................................... 3.5.6.13 Global Warm Reset Sequence .......................................................................... Clock Management Functional Description ........................................................................... 3.6.1 Overview ......................................................................................................... 3.6.2 External Clock Inputs ........................................................................................... 3.6.2.1 sys_32k Clock Input ...................................................................................... 3.6.2.2 High-Frequency System Clock Input ................................................................... 3.6.3 Internal Clock Sources/Generators ........................................................................... 3.6.3.1 PRM Clock Source ....................................................................................... 3.6.3.2 CM Clock Source ......................................................................................... 3.6.3.2.1 CM1 Clock Generator ............................................................................... 3.6.3.2.2 CM1_USB Clock Generator ........................................................................ 3.6.3.2.3 CM1_ABE Clock Generator ......................................................................... 3.6.3.2.4 CM2 Clock Generator ............................................................................... 3.6.3.3 Generic DPLL Overview ................................................................................. 3.6.3.3.1 DPLLs Output Clocks Parameters ................................................................. 3.6.3.3.2 Enable Control, Status, and Low-Power Operation Mode ...................................... 3.6.3.3.3 DPLL Power Modes .................................................................................. 3.6.3.3.4 DPLL Recalibration .................................................................................. 3.6.3.3.5 DPLL Spread Spectrum Clocking .................................................................. 3.6.3.3.6 DPLL Output Power Down .......................................................................... 3.6.3.4 DPLL_PER Description .................................................................................. 3.6.3.4.1 Overview .............................................................................................. 3.6.3.4.2 Synthesized Clock Parameters ..................................................................... 3.6.3.4.3 Power Modes ......................................................................................... 3.6.3.4.4 Recalibration .......................................................................................... 3.6.3.4.5 Spread Spectrum Clocking ......................................................................... 3.6.3.4.6 Ouput Power Down .................................................................................. 3.6.3.5 DPLL_CORE Description ................................................................................ 3.6.3.5.1 Overview .............................................................................................. 3.6.3.5.2 Synthesized Clock Parameters ..................................................................... 3.6.3.5.3 Power Modes ......................................................................................... 3.6.3.5.4 Recalibration .......................................................................................... 3.6.3.5.5 Spread Spectrum Clocking ......................................................................... 3.6.3.5.6 Ouput Power-Down .................................................................................. 3.6.3.6 DPLL_ABE Description .................................................................................. 3.6.3.6.1 Overview .............................................................................................. 3.6.3.6.2 Synthesized Clock Parameters ..................................................................... 3.6.3.6.3 Power Modes .........................................................................................

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3.5.5.1 PRCM Module Reset Logging Mechanism ............................................................ 3.5.6 Reset Sequences ............................................................................................... 3.5.6.1 SCRM Power-on Reset Sequence ..................................................................... 3.5.6.2 PRCM Module Power-On Reset Sequence ........................................................... 3.5.6.3 Cortex-A9 MPU Subsystem Power-On Reset Sequence ........................................... 3.5.6.4 Cortex-A9 MPU Subsystem Warm Reset Sequence ................................................ 3.5.6.5 Cortex-A9 MPU Subsystem Reset Sequence On Sleep and Wake-Up Transitions From RETENTION or Off STATE ............................................................................. 3.5.6.6 IVAHD Subsystem Power-On Reset Sequence ...................................................... 3.5.6.7 IVAHD Subsystem Software Warm Reset Sequence ............................................... 3.5.6.8 DSP Subsystem Power-On Reset Sequence ......................................................... 3.5.6.9 DSP Subsystem Software Warm Reset Sequence .................................................. 3.5.6.10 DSP Subsystem Reset Sequence On Wake-Up Transitions From OSWR RETENTION State

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3.6.3.6.4 Recalibration .......................................................................................... 3.6.3.6.5 Spread Spectrum Clocking ......................................................................... 3.6.3.7 DPLL_MPU Description .................................................................................. 3.6.3.7.1 Overview .............................................................................................. 3.6.3.7.2 Synthesized Clock Parameters ..................................................................... 3.6.3.7.3 Power Modes ......................................................................................... 3.6.3.7.4 Recalibration .......................................................................................... 3.6.3.7.5 Spread Spectrum Clocking ......................................................................... 3.6.3.8 DPLL_IVA Description ................................................................................... 3.6.3.8.1 Overview .............................................................................................. 3.6.3.8.2 Synthesized Clock Parameters ..................................................................... 3.6.3.8.3 Power Modes ......................................................................................... 3.6.3.8.4 Recalibration .......................................................................................... 3.6.3.8.5 Spread Spectrum Clocking ......................................................................... 3.6.3.8.6 Ouput Power Down .................................................................................. 3.6.3.9 DPLL_USB Description .................................................................................. 3.6.3.9.1 Overview .............................................................................................. 3.6.3.9.2 Synthesized Clock Parameters ..................................................................... 3.6.3.9.3 Power Modes ......................................................................................... 3.6.3.9.4 Spread Spectrum Clocking ......................................................................... 3.6.3.10 DPLLs Cascading ......................................................................................... 3.6.4 CD_WKUP Clock Domain ..................................................................................... 3.6.4.1 Overview ................................................................................................... 3.6.4.2 Clock Domain Modes .................................................................................... 3.6.4.3 Clock Domain Dependency ............................................................................. 3.6.4.3.1 Wake-Up Dependency .............................................................................. 3.6.4.4 Clock Domain Module Attributes ....................................................................... 3.6.5 CD_DSP Clock Domain ........................................................................................ 3.6.5.1 Overview ................................................................................................... 3.6.5.2 Clock Domain Modes .................................................................................... 3.6.5.3 Clock Domain Dependency ............................................................................. 3.6.5.3.1 Static Dependency ................................................................................... 3.6.5.3.2 Dynamic Dependency ............................................................................... 3.6.5.4 Clock Domain Module Attributes ....................................................................... 3.6.6 CD_STD_EFUSE Clock Domain .............................................................................. 3.6.6.1 Overview ................................................................................................... 3.6.6.2 Clock Domain Module Attributes ....................................................................... 3.6.7 CD_CORTEXA9 Clock Domain ............................................................................... 3.6.7.1 Overview ................................................................................................... 3.6.7.2 Clock Domain Modes .................................................................................... 3.6.7.3 Clock Domain Dependency ............................................................................. 3.6.7.3.1 Static Dependency ................................................................................... 3.6.7.3.2 Dynamic Dependency ............................................................................... 3.6.7.4 Clock Domain Module Attributes ....................................................................... 3.6.8 CD_L4_PER Clock Domain ................................................................................... 3.6.8.1 Overview ................................................................................................... 3.6.8.2 Clock Domain Modes .................................................................................... 3.6.8.3 Clock Domain Dependency ............................................................................. 3.6.8.3.1 Dynamic Dependency ............................................................................... 3.6.8.3.2 Wake-Up Dependency .............................................................................. 3.6.8.4 Clock Domain Module Attributes ....................................................................... 3.6.9 CD_L3_INIT Clock Domain .................................................................................... 3.6.9.1 Overview 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3.6.9.2 Clock Domain Modes .................................................................................... 3.6.9.3 Clock Domain Dependency ............................................................................. 3.6.9.3.1 Static Dependency ................................................................................... 3.6.9.3.2 Dynamic Dependency ............................................................................... 3.6.9.3.3 Wake-Up Dependency .............................................................................. 3.6.9.4 Clock Domain Module Attributes ....................................................................... 3.6.10 CD_IVAHD Clock Domain .................................................................................... 3.6.10.1 Overview ................................................................................................... 3.6.10.2 Clock Domain Modes .................................................................................... 3.6.10.3 Clock Domain Dependency ............................................................................. 3.6.10.3.1 Static Dependency ................................................................................... 3.6.10.3.2 Dynamic Dependency ............................................................................... 3.6.10.4 Clock Domain Module Attributes ....................................................................... 3.6.11 CD_SGX Clock Domain ....................................................................................... 3.6.11.1 Overview ................................................................................................... 3.6.11.2 Clock Domain Modes .................................................................................... 3.6.11.3 Clock Domain Dependency ............................................................................. 3.6.11.3.1 Static Dependency ................................................................................... 3.6.11.3.2 Dynamic Dependency ............................................................................... 3.6.11.4 Clock Domain Module Attributes ....................................................................... 3.6.12 CD_EMU Clock Domain ...................................................................................... 3.6.12.1 Overview ................................................................................................... 3.6.12.2 Clock Domain Modes .................................................................................... 3.6.12.3 Clock Domain Dependency ............................................................................. 3.6.12.3.1 Dynamic Dependency ............................................................................... 3.6.12.4 Clock Domain Module Attributes ....................................................................... 3.6.13 CD_DSS Clock Domain ....................................................................................... 3.6.13.1 Overview ................................................................................................... 3.6.13.2 Clock Domain Modes .................................................................................... 3.6.13.3 Clock Domain Dependency ............................................................................. 3.6.13.3.1 Static Dependency ................................................................................... 3.6.13.3.2 Dynamic Dependency ............................................................................... 3.6.13.3.3 Wake-Up Dependency .............................................................................. 3.6.13.4 Clock Domain Module Attributes ....................................................................... 3.6.14 CD_L4_CFG Clock Domain .................................................................................. 3.6.14.1 Overview ................................................................................................... 3.6.14.2 Clock Domain Modes .................................................................................... 3.6.14.3 Clock Domain Dependency ............................................................................. 3.6.14.3.1 Dynamic Dependency ............................................................................... 3.6.14.4 Clock Domain Module Attributes ....................................................................... 3.6.15 CD_L3_INSTR Clock Domain ................................................................................ 3.6.15.1 Overview ................................................................................................... 3.6.15.2 Clock Domain Modes .................................................................................... 3.6.15.3 Clock Domain Dependency ............................................................................. 3.6.15.4 Clock Domain Module Attributes ....................................................................... 3.6.16 CD_L3_2 Clock Domain ...................................................................................... 3.6.16.1 Overview ................................................................................................... 3.6.16.2 Clock Domain Modes .................................................................................... 3.6.16.3 Clock Domain Dependency ............................................................................. 3.6.16.3.1 Dynamic Dependency ............................................................................... 3.6.16.4 Clock Domain Module Attributes ....................................................................... 3.6.17 CD_L3_1 Clock Domain ...................................................................................... 3.6.17.1 Overview ...................................................................................................

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3.6.17.2 Clock Domain Modes .................................................................................... 3.6.17.3 Clock Domain Dependency ............................................................................. 3.6.17.3.1 Dynamic Dependency ............................................................................... 3.6.17.4 Clock Domain Module Attributes ....................................................................... 3.6.18 CD_EMIF Clock Domain ...................................................................................... 3.6.18.1 Overview ................................................................................................... 3.6.18.2 Clock Domain Modes .................................................................................... 3.6.18.3 Clock Domain Dependency ............................................................................. 3.6.18.4 Clock Domain Module Attributes ....................................................................... 3.6.19 CD_CORTEXM3 Clock Domain ............................................................................. 3.6.19.1 Overview ................................................................................................... 3.6.19.2 Clock Domain Modes .................................................................................... 3.6.19.3 Clock Domain Dependency ............................................................................. 3.6.19.3.1 Static Dependency ................................................................................... 3.6.19.3.2 Dynamic Dependency ............................................................................... 3.6.19.4 Clock Domain Module Attributes ....................................................................... 3.6.20 CD_DMA Clock Domain ...................................................................................... 3.6.20.1 Overview ................................................................................................... 3.6.20.2 Clock Domain Modes .................................................................................... 3.6.20.3 Clock Domain Dependency ............................................................................. 3.6.20.4 Clock Domain Module Attributes ....................................................................... 3.6.21 CD_C2C Clock Domain ....................................................................................... 3.6.21.1 Overview ................................................................................................... 3.6.21.2 Clock Domain Modes .................................................................................... 3.6.21.3 Clock Domain Dependency ............................................................................. 3.6.21.3.1 Static Dependency ................................................................................... 3.6.21.3.2 Dynamic Dependency ............................................................................... 3.6.21.4 Clock Domain Module Attributes ....................................................................... 3.6.22 CD_CAM Clock Domain ...................................................................................... 3.6.22.1 Overview ................................................................................................... 3.6.22.2 Clock Domain Modes .................................................................................... 3.6.22.3 Clock Domain Dependency ............................................................................. 3.6.22.3.1 Static Dependency ................................................................................... 3.6.22.3.2 Dynamic Dependency ............................................................................... 3.6.22.4 Clock Domain Module Attributes ....................................................................... 3.6.23 CD_ABE Clock Domain ....................................................................................... 3.6.23.1 Overview ................................................................................................... 3.6.23.2 Clock Domain Modes .................................................................................... 3.6.23.3 Clock Domain Dependency ............................................................................. 3.6.23.3.1 Wake-Up Dependency .............................................................................. 3.6.23.4 Clock Domain Module Attributes ....................................................................... 3.6.24 CD_L4_ALWON_CORE Clock Domain ..................................................................... 3.6.24.1 Overview ................................................................................................... 3.6.24.2 Clock Domain Modes .................................................................................... 3.6.24.3 Clock Domain Dependency ............................................................................. 3.6.24.3.1 Wake-Up Dependency .............................................................................. 3.6.24.4 Clock Domain Module Attributes ....................................................................... Power Management Functional Description .......................................................................... 3.7.1 PD_WKUP Description ......................................................................................... 3.7.1.1 Power Domain Modes .................................................................................... 3.7.2 PD_DSP Description ........................................................................................... 3.7.2.1 Power Domain Modes .................................................................................... 3.7.2.1.1 Logic and Memory Area Power Modes ...........................................................

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3.7.2.1.2 Logic and Memory Area Power Modes Control and Status .................................... 3.7.3 PD_STD_EFUSE Description ................................................................................. 3.7.3.1 Power Domain Modes .................................................................................... 3.7.4 PD_MPU Description ........................................................................................... 3.7.4.1 Power Domain Modes .................................................................................... 3.7.4.1.1 Logic and Memory Area Power Modes ........................................................... 3.7.4.1.2 Logic and Memory Area Power Modes Control and Status .................................... 3.7.5 PD_L4_PER Description ....................................................................................... 3.7.5.1 Power Domain Modes .................................................................................... 3.7.5.1.1 Logic and Memory Area Power Modes ........................................................... 3.7.5.1.2 Logic and Memory Area Power Modes Control and Status .................................... 3.7.6 PD_L3_INIT Description ....................................................................................... 3.7.6.1 Power Domain Modes .................................................................................... 3.7.6.1.1 Logic and Memory Area Power Modes ........................................................... 3.7.6.1.2 Logic and Memory Area Power Modes Control and Status .................................... 3.7.7 PD_IVAHD Description ......................................................................................... 3.7.7.1 Power Domain Modes .................................................................................... 3.7.7.1.1 Logic and Memory Area Power Modes ........................................................... 3.7.7.1.2 Logic and Memory Area Power Modes Control and Status .................................... 3.7.8 PD_SGX Description ........................................................................................... 3.7.8.1 Power Domain Modes .................................................................................... 3.7.8.1.1 Logic and Memory Area Power Modes ........................................................... 3.7.8.1.2 Logic and Memory Area Power Modes Control and Status .................................... 3.7.9 PD_EMU Description ........................................................................................... 3.7.9.1 Power Domain Modes .................................................................................... 3.7.9.1.1 Logic and Memory Area Power Modes ........................................................... 3.7.9.1.2 Logic and Memory Area Power Modes Control and Status .................................... 3.7.10 PD_DSS Description .......................................................................................... 3.7.10.1 Power Domain Modes .................................................................................... 3.7.10.1.1 Logic and Memory Area Power Modes ........................................................... 3.7.10.1.2 Logic and Memory Area Power Modes Control and Status .................................... 3.7.11 PD_CORE Description ........................................................................................ 3.7.11.1 Power Domain Modes .................................................................................... 3.7.11.1.1 Logic and Memory Area Power Modes ........................................................... 3.7.11.1.2 Logic and Memory Area Power Modes Control and Status .................................... 3.7.12 PD_CAM Description .......................................................................................... 3.7.12.1 Power Domain Modes .................................................................................... 3.7.12.1.1 Logic and Memory Area Power Modes ........................................................... 3.7.12.1.2 Logic and Memory Area Power Modes Control and Status .................................... 3.7.13 PD_AUDIO Description ....................................................................................... 3.7.13.1 Power Domain Modes .................................................................................... 3.7.13.1.1 Logic and Memory Area Power Modes ........................................................... 3.7.13.1.2 Logic and Memory Area Power Modes Control and Status .................................... 3.7.14 PD_ALWON_MPU Description .............................................................................. 3.7.14.1 Power Domain Modes .................................................................................... 3.7.15 PD_ALWON_DSP Description ............................................................................... 3.7.15.1 Power Domain Modes .................................................................................... 3.7.16 PD_ALWON_CORE Description ............................................................................. 3.7.16.1 Power Domain Modes .................................................................................... Voltage Management Functional Description ........................................................................ 3.8.1 Overview ......................................................................................................... 3.8.2 Voltage-Control Architecture ................................................................................... 3.8.3 VDD_MPU_L, VDD_CORE_L, and VDD_IVA_L Control ..................................................

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3.8.4 Internal LDOs Control .......................................................................................... 3.8.4.1 Memory LDOs ............................................................................................. 3.8.4.2 LDO_WAKEUP ........................................................................................... 3.8.4.3 ABB LDOs Control ........................................................................................ 3.8.4.4 Bandgap control .......................................................................................... 3.8.5 Voltage Domain State Transitions ............................................................................ 3.8.5.1 VDD_x_L Transitions ..................................................................................... 3.8.5.2 Memory LDOs Transitions ............................................................................... 3.8.5.3 LDO_WAKEUP Transitions ............................................................................. 3.8.6 DVFS ............................................................................................................. 3.8.6.1 EMIF Clocks Frequency Scaling Constraints ......................................................... 3.8.6.2 GPMC Clocks Frequency Scaling Constraints ........................................................ 3.8.6.3 CORE DVFS Versus Subsystem Functionality ....................................................... 3.8.6.3.1 Display Subsystem ................................................................................... 3.8.6.3.2 IVAHD ................................................................................................. 3.8.6.3.3 Imaging Subsystem .................................................................................. 3.8.6.4 DVFS Voting Mechanism (VDD_CORE_L and VDD_IVA_L Voltage Domains) ................. 3.8.6.4.1 CORE OPP Voting Architecture .................................................................... 3.8.6.4.2 IVA OPP Voting Architecture ....................................................................... 3.8.6.4.3 Voting Mechanism ................................................................................... Device Low-Power States .............................................................................................. 3.9.1 Device Wake-Up Source Summary .......................................................................... 3.9.2 Device RETENTION State Management .................................................................... 3.9.3 Device OFF State Management .............................................................................. 3.9.3.1 Device Off Mode Sleep Sequence ..................................................................... 3.9.3.2 Device Off Mode Wake-Up Sequences ................................................................ 3.9.3.2.1 Wake Up From a Wake-Up Event ................................................................. 3.9.3.2.2 Wakeup Upon Global Warm Reset ................................................................ 3.9.3.3 Global Warm Reset During a Device Wake-Up Sequence ......................................... 3.9.4 I/O Management ................................................................................................ 3.9.4.1 Hardware-Controlled I/O Isolation Sequences ........................................................ 3.9.4.2 Software-Controlled I/O Isolation ....................................................................... PRCM Module Programming Guide ................................................................................... 3.10.1 DPLLs Low-Level Programming Models .................................................................... 3.10.1.1 Global Initialization ....................................................................................... 3.10.1.1.1 Surrounding Module Global Initialization .......................................................... 3.10.1.1.2 DPLL Global Initialization ........................................................................... 3.10.1.2 DPLL Output Frequency Change ....................................................................... 3.10.2 Clock Management Low-Level Programming Models .................................................... 3.10.2.1 Global Initialization ....................................................................................... 3.10.2.1.1 Surrounding Module Global Initialization .......................................................... 3.10.2.1.2 Clock Management Global Initialization ........................................................... 3.10.2.2 Clock Domain Sleep Transition and Troubleshooting ...............................................

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3.8.3.1 PRM Dedicated I C Control ............................................................................. 3.8.3.2 Adaptive Voltage Scaling ................................................................................ 3.8.3.2.1 SmartReflex in the Device .......................................................................... 3.8.3.2.2 SmartReflex Module ................................................................................. 3.8.3.2.3 SmartReflex Submodules ........................................................................... 3.8.3.2.4 Status Register ....................................................................................... 3.8.3.2.5 SmartReflex Parameters Set After Silicon Characterization .................................... 3.8.3.2.6 Voltage Processor Module .......................................................................... 3.8.3.2.7 SMPS-Dependent Parameter Configuration ...................................................... 3.8.3.2.8 Communication Between SmartReflex, Voltage Processor, Voltage Controller, and SMPS2

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3.10.2.3 Enable/Disable Software-Programmable Static Dependency ...................................... 3.10.3 Power Management Low-Level Programming Models .................................................... 3.10.3.1 Global Initialization ....................................................................................... 3.10.3.1.1 Surrounding Module Global Initialization .......................................................... 3.10.3.1.2 Power Management Global Initialization .......................................................... 3.10.3.2 Forced Memory Area State Change With Power Domain ON ...................................... 3.10.3.3 Forced Power Domain Low-Power State Transition ................................................. 3.10.4 Voltage Management Low-Level Programming Models .................................................. 3.10.4.1 Global Initialization ....................................................................................... 3.10.4.1.1 Surrounding Module Global Initialization .......................................................... 3.10.4.1.2 Voltage Management Global Initialization ........................................................ 3.10.4.1.3 SmartReflex Module Initialization .................................................................. 3.10.4.1.4 Voltage Processor Initialization .................................................................... 3.10.4.1.5 Voltage Controller Initialization ..................................................................... 3.10.4.2 Changing OPP ............................................................................................ PRCM Register Manual ................................................................................................. 3.11.1 PRM Instance Summary ...................................................................................... 3.11.2 INTRCONN_SOCKET_PRM Registers ..................................................................... 3.11.2.1 INTRCONN_SOCKET_PRM Register Summary ..................................................... 3.11.2.2 INTRCONN_SOCKET_PRM Register Description ................................................... 3.11.3 CKGEN_PRM Registers ...................................................................................... 3.11.3.1 CKGEN_PRM Register Summary ...................................................................... 3.11.3.2 CKGEN_PRM Register Description .................................................................... 3.11.4 MPU_PRM Registers .......................................................................................... 3.11.4.1 MPU_PRM Register Summary ......................................................................... 3.11.4.2 MPU_PRM Register Description ........................................................................ 3.11.5 DSP_PRM Registers .......................................................................................... 3.11.5.1 DSP_PRM Register Summary .......................................................................... 3.11.5.2 DSP_PRM Register Description ........................................................................ 3.11.6 ABE_PRM Registers .......................................................................................... 3.11.6.1 ABE_PRM Register Summary .......................................................................... 3.11.6.2 ABE_PRM Register Description ........................................................................ 3.11.7 ALWAYS_ON_PRM Registers ............................................................................... 3.11.7.1 ALWAYS_ON_PRM Register Summary ............................................................... 3.11.7.2 ALWAYS_ON_PRM Register Description ............................................................. 3.11.8 CORE_PRM Registers ........................................................................................ 3.11.8.1 CORE_PRM Register Summary ........................................................................ 3.11.8.2 CORE_PRM Register Description ...................................................................... 3.11.9 IVAHD_PRM Registers ....................................................................................... 3.11.9.1 IVAHD_PRM Register Summary ....................................................................... 3.11.9.2 IVAHD_PRM Register Description ..................................................................... 3.11.10 CAM_PRM Registers ........................................................................................ 3.11.10.1 CAM_PRM Register Summary ........................................................................ 3.11.10.2 CAM_PRM Register Description ...................................................................... 3.11.11 DSS_PRM Registers ......................................................................................... 3.11.11.1 DSS_PRM Register Summary ......................................................................... 3.11.11.2 DSS_PRM Register Description ....................................................................... 3.11.12 SGX_PRM Registers ........................................................................................ 3.11.12.1 SGX_PRM Register Summary ......................................................................... 3.11.12.2 SGX_PRM Register Description ....................................................................... 3.11.13 L3INIT_PRM Registers ...................................................................................... 3.11.13.1 L3INIT_PRM Register Summary ...................................................................... 3.11.13.2 L3INIT_PRM Register Description ....................................................................

514 515 515 515 515 515 515 516 516 516 516 516 518 519 520 521 521 521 521 521 539 539 539 541 541 541 545 545 546 551 551 551 573 573 573 577 577 578 597 597 597 603 603 604 607 607 607 612 612 612 615 615 61511


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3.11.14 L4PER_PRM Registers ...................................................................................... 3.11.14.1 L4PER_PRM Register Summary ...................................................................... 3.11.14.2 L4PER_PRM Register Description .................................................................... 3.11.15 WKUP_PRM Registers ...................................................................................... 3.11.15.1 WKUP_PRM Register Summary ...................................................................... 3.11.15.2 WKUP_PRM Register Description .................................................................... 3.11.16 WKUP_CM Registers ........................................................................................ 3.11.16.1 WKUP_CM Register Summary ........................................................................ 3.11.16.2 WKUP_CM Register Description ...................................................................... 3.11.17 EMU_PRM Registers ........................................................................................ 3.11.17.1 EMU_PRM Register Summary ........................................................................ 3.11.17.2 EMU_PRM Register Description ...................................................................... 3.11.18 EMU_CM Registers .......................................................................................... 3.11.18.1 EMU_CM Register Summary .......................................................................... 3.11.18.2 EMU_CM Register Description ........................................................................ 3.11.19 DEVICE_PRM Registers .................................................................................... 3.11.19.1 DEVICE_PRM Register Summary .................................................................... 3.11.19.2 DEVICE_PRM Register Description .................................................................. 3.11.20 INSTR_PRM Registers ...................................................................................... 3.11.20.1 INSTR_PRM Register Summary ...................................................................... 3.11.20.2 INSTR_PRM Register Description .................................................................... 3.11.21 CM1 Instance Summary ..................................................................................... 3.11.22 INTRCONN_SOCKET_CM1 Registers .................................................................... 3.11.22.1 INTRCONN_SOCKET_CM1 Register Summary .................................................... 3.11.22.2 INTRCONN_SOCKET_CM1 Register Description .................................................. 3.11.23 CKGEN_CM1 Registers ..................................................................................... 3.11.23.1 CKGEN_CM1 Register Summary ..................................................................... 3.11.23.2 CKGEN_CM1 Register Description ................................................................... 3.11.24 MPU_CM1 Registers ........................................................................................ 3.11.24.1 MPU_CM1 Register Summary ......................................................................... 3.11.24.2 MPU_CM1 Register Description ....................................................................... 3.11.25 DSP_CM1 Registers ......................................................................................... 3.11.25.1 DSP_CM1 Register Summary ......................................................................... 3.11.25.2 DSP_CM1 Register Description ....................................................................... 3.11.26 ABE_CM1 Registers ......................................................................................... 3.11.26.1 ABE_CM1 Register Summary ......................................................................... 3.11.26.2 ABE_CM1 Register Description ....................................................................... 3.11.27 RESTORE_CM1 Registers ................................................................................. 3.11.27.1 RESTORE_CM1 Register Summary ................................................................. 3.11.27.2 RESTORE_CM1 Register Description ................................................................ 3.11.28 INSTR_CM1 Registers ...................................................................................... 3.11.28.1 INSTR_CM1 Register Summary ...................................................................... 3.11.28.2 INSTR_CM1 Register Description .................................................................... 3.11.29 CM2 Instance Summary ..................................................................................... 3.11.30 INTRCONN_SOCKET_CM2 Registers .................................................................... 3.11.30.1 INTRCONN_SOCKET_CM2 Register Summary .................................................... 3.11.30.2 INTRCONN_SOCKET_CM2 Register Description .................................................. 3.11.31 CKGEN_CM2 Registers ..................................................................................... 3.11.31.1 CKGEN_CM2 Register Summary ..................................................................... 3.11.31.2 CKGEN_CM2 Register Description ................................................................... 3.11.32 ALWAYS_ON_CM2 Registers .............................................................................. 3.11.32.1 ALWAYS_ON_CM2 Register Summary .............................................................. 3.11.32.2 ALWAYS_ON_CM2 Register Description ............................................................

629 629 631 677 677 677 684 684 685 692 692 692 695 695 695 698 698 700 747 747 747 750 751 751 751 753 753 754 790 790 790 795 795 795 799 799 799 816 816 817 833 833 833 836 837 837 837 839 839 840 861 861 861

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3.11.33 CORE_CM2 Registers ....................................................................................... 866 3.11.33.1 CORE_CM2 Register Summary ....................................................................... 866 3.11.33.2 CORE_CM2 Register Description ..................................................................... 867 3.11.34 IVAHD_CM2 Registers ...................................................................................... 899 3.11.34.1 IVAHD_CM2 Register Summary ...................................................................... 899 3.11.34.2 IVAHD_CM2 Register Description .................................................................... 900 3.11.35 CAM_CM2 Registers ........................................................................................ 904 3.11.35.1 CAM_CM2 Register Summary ......................................................................... 904 3.11.35.2 CAM_CM2 Register Description ....................................................................... 904 3.11.36 DSS_CM2 Registers ......................................................................................... 909 3.11.36.1 DSS_CM2 Register Summary ......................................................................... 909 3.11.36.2 DSS_CM2 Register Description ....................................................................... 909 3.11.37 SGX_CM2 Registers ......................................................................................... 913 3.11.37.1 SGX_CM2 Register Summary ......................................................................... 913 3.11.37.2 SGX_CM2 Register Description ....................................................................... 913 3.11.38 L3INIT_CM2 Registers ...................................................................................... 917 3.11.38.1 L3INIT_CM2 Register Summary ...................................................................... 917 3.11.38.2 L3INIT_CM2 Register Description .................................................................... 917 3.11.39 L4PER_CM2 Registers ...................................................................................... 931 3.11.39.1 L4PER_CM2 Register Summary ...................................................................... 931 3.11.39.2 L4PER_CM2 Register Description .................................................................... 932 3.11.40 RESTORE_CM2 Registers ................................................................................. 963 3.11.40.1 RESTORE_CM2 Register Summary ................................................................. 963 3.11.40.2 RESTORE_CM2 Register Description ................................................................ 964 3.11.41 INSTR_CM2 Registers ...................................................................................... 991 3.11.41.1 INSTR_CM2 Register Summary ...................................................................... 991 3.11.41.2 INSTR_CM2 Register Description .................................................................... 991 SCRM Register Manual ................................................................................................. 996 3.12.1 SCRM Instance Summary .................................................................................... 996 3.12.2 SCRM Registers ............................................................................................... 996 3.12.2.1 SCRM Register Summary ............................................................................... 996 3.12.2.2 SCRM Register Description ............................................................................. 997 SR Register Manual .................................................................................................... 1020 3.13.1 SR Instance Summary ....................................................................................... 1020 3.13.2 SR Registers .................................................................................................. 1020 3.13.2.1 SR Register Summary .................................................................................. 1020 3.13.2.2 SR Register Description ................................................................................ 1020 Dual Cortex-A9 MPU Subsystem Overview ........................................................................ 4.1.1 Introduction ..................................................................................................... 4.1.2 Features ........................................................................................................ Dual Cortex-A9 MPU Subsystem Integration ....................................................................... 4.2.1 Clock Distribution .............................................................................................. 4.2.2 Reset Distribution .............................................................................................. Dual Cortex-A9 MPU Subsystem Functional Description ......................................................... 4.3.1 Cortex-A9 MPU Subsystem Block Diagram ............................................................... 4.3.2 ARM Core ...................................................................................................... 4.3.3 Local Interconnect ............................................................................................. 4.3.4 Power Management ........................................................................................... 4.3.4.1 Power Domains .......................................................................................... 4.3.4.2 Power States of CPU0 and CPU1 .................................................................... 4.3.4.3 WUGEN .................................................................................................. 4.3.4.4 Power Transition Sequence ...........................................................................Contents 20102011, Texas Instruments Incorporated

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............................................................................................................. 1071 IVA-HD Subsystem ......................................................................................................... 1073 6.1 IVA-HD Overview ....................................................................................................... 1074 6.1.1 IVA-HD Integration ............................................................................................ 1076 6.1.2 IVA-HD Functional Description .............................................................................. 1077 6.1.2.1 IVA-HD Block Diagram ................................................................................. 1077 6.1.2.1.1 SyncBox .............................................................................................. 1078 6.1.2.1.2 iCONTs ............................................................................................... 1078 6.1.2.1.3 vDMA ................................................................................................. 1078 6.1.2.1.4 iME3 .................................................................................................. 1078 6.1.2.1.5 iPE3 .................................................................................................. 1078 6.1.2.1.6 MC3 .................................................................................................. 1078 6.1.2.1.7 CALC3 ............................................................................................... 1079 6.1.2.1.8 iLF3 ................................................................................................... 1079 6.1.2.1.9 ECD3 ................................................................................................. 1079 6.1.2.1.10 SL2 Interface ........................................................................................ 1079 6.1.2.1.11 Message Bus ........................................................................................ 1079 6.1.2.1.12 IVA-HD Local Interconnect ........................................................................ 1079 6.1.2.1.13 MailBox .............................................................................................. 1079 6.1.2.1.14 IVA-HD System Control ............................................................................ 1080 6.1.2.2 IVA-HD Power Management ........................................................................... 1080 6.1.2.3 IVA-HD Memory Mapping .............................................................................. 1080 6.1.3 IVA-HD Register Manual ..................................................................................... 1084 6.1.3.1 IVA-HD Instance Summary ............................................................................ 1084 6.1.3.2 SYSCTRL Registers .................................................................................... 1084 6.1.3.2.1 SYSCTRL Register Summary ..................................................................... 1084 6.1.3.2.2 SYSCTRL Register Description ................................................................... 1085 Dual Cortex-M3 MPU Subsystem ...................................................................................... 1097 7.1 Dual Cortex-M3 MPU Subsystem Overview ........................................................................ 1098 7.1.1 Introduction ..................................................................................................... 1098 7.1.2 Features ........................................................................................................ 1099 7.2 Dual Cortex-M3 MPU Subsystem Integration ...................................................................... 1100 7.2.1 Dual Cortex-M3 MPU Subsystem Clock and Reset Distribution ........................................ 1101DSP SubsystemContents 20102011, Texas Instruments Incorporated

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4.3.4.5 CPU0 and CPU1 Power Domains Description ...................................................... 4.3.4.5.1 Power Domain Modes .............................................................................. Dual Cortex-A9 MPU Subsystem Register Manual ................................................................ 4.4.1 Cortex-A9 MPU Subsystem Instance Summary ........................................................... 4.4.2 SCU Registers ................................................................................................. 4.4.3 Interrupt Controller Registers ................................................................................ 4.4.4 Timer Registers ................................................................................................ 4.4.5 PL310 Registers ............................................................................................... 4.4.6 Local PRCM Revision Register .............................................................................. 4.4.6.1 Local PRCM Revision Register Summary ........................................................... 4.4.6.2 Local PRCM Revision Register Description ......................................................... 4.4.7 Local PRCM Registers ........................................................................................ 4.4.7.1 Local PRCM Registers Summary ..................................................................... 4.4.7.2 Local PRCM Log Register Description ............................................................... 4.4.8 Local PRCM CPU0 and CPU1 Registers .................................................................. 4.4.8.1 Local PRCM CPU0 and CPU1 Register Summary ................................................. 4.4.8.2 Local PRCM CPU0 Register Description ............................................................ 4.4.9 Wake-Up Generator Registers ............................................................................... 4.4.9.1 CORTEXA9_WUGEN Register Summary ........................................................... 4.4.9.2 CORTEXA9_WUGEN Register Description .........................................................

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Imaging Subsystem8.1

ISS Overview ............................................................................................................ 8.1.1 ISS Integration ................................................................................................. 8.1.1.1 ISS PRCM Interface Integration ....................................................................... 8.1.1.1.1 ISS Clock Domains ................................................................................. 8.1.2 ISS Functional Description ................................................................................... 8.1.2.1 ISS Interrupts ............................................................................................ 8.1.2.1.1 ISS Interrupt Merger ................................................................................ 8.1.2.1.2 ISS Submodule Interrupts ......................................................................... 8.1.2.2 ISS Clocks ............................................................................................... 8.1.2.3 ISS Reset ................................................................................................ 8.1.2.4 ISS Power Management ............................................................................... 8.1.2.4.1 ISS Power-Management Infrastructure Overview .............................................. 8.1.2.4.2 ISS STANDBY Mechanism ........................................................................ 8.1.2.4.3 ISS IDLE Mechanism .............................................................................. 8.1.3 ISS Register Manual .......................................................................................... 8.1.3.1 ISS Instance Summary ................................................................................. 8.1.3.2 ISS Registers ............................................................................................ 8.1.3.2.1 ISS TOP Register Summary ...................................................................... 8.1.3.2.2 ISS TOP Register Description ....................................................................Contents 20102011, Texas Instruments Incorporated

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7.2.1.1 Clock Distribution ........................................................................................ 7.2.1.2 Reset Distribution ....................................................................................... Dual Cortex-M3 MPU Subsystem Functional Description ........................................................ 7.3.1 Dual Cortex-M3 MPU Subsystem Block Diagram ......................................................... 7.3.2 Power Management ........................................................................................... 7.3.2.1 Local Power Management ............................................................................. 7.3.2.2 Power Domains .......................................................................................... 7.3.2.3 Voltage Domain ......................................................................................... 7.3.2.4 Power States and Modes .............................................................................. 7.3.2.5 Wake-Up Generator .................................................................................... 7.3.2.5.1 WUGEN Main Features ............................................................................ 7.3.3 Shared Cache .................................................................................................. 7.3.4 Shared Cache MMU .......................................................................................... 7.3.5 L2 MMU ......................................................................................................... 7.3.5.1 L2 MMU Behavior on Page-Fault in Dual Cortex-M3 MPU ........................................ 7.3.6 Interprocessor Communication (IPC) ....................................................................... 7.3.6.1 Use of WFE and SEV .................................................................................. 7.3.6.2 Use of Interrupt for IPC ................................................................................. 7.3.6.3 Use of the Bit-Band Feature for Semaphore Operations .......................................... 7.3.6.4 Private Memory Space ................................................................................. Dual Cortex-M3 MPU Subsystem Register Manual ................................................................ 7.4.1 Dual Cortex-M3 Subsystem Instance Summary ........................................................... 7.4.2 Shared Cache Configuration Registers ..................................................................... 7.4.3 Shared Cache SCTM Registers ............................................................................. 7.4.4 Shared Cache MMU Registers .............................................................................. 7.4.5 Cortex-M3 L2 MMU Registers ............................................................................... 7.4.6 Cortex-M3 NVIC Registers ................................................................................... 7.4.7 Cortex-M3 Wake-Up Generator Registers ................................................................. 7.4.7.1 CORTEXM3_WKUP Register Summary ............................................................. 7.4.7.2 Dual Cortex-M3 MPU Wake-Up Generator Register Description ................................. 7.4.8 Cortex-M3 RW Table Registers ............................................................................. 7.4.8.1 CM3_RW_Table Register Summary .................................................................. 7.4.8.2 Cortex-M3 RW Table Register Description ..........................................................

1101 1102 1104 1104 1105 1106 1106 1106 1107 1108 1108 1109 1110 1110 1111 1111 1111 1112 1112 1112 1114 1114 1114 1114 1114 1115 1115 1115 1115 1115 1119 1119 1119 1122 1125 1127 1127 1128 1128 1128 1129 1138 1139 1140 1140 1140 1142 1143 1143 1143 1143 114315

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ISS Interfaces ........................................................................................................... 8.2.1 ISS Interfaces Overview ...................................................................................... 8.2.1.1 ISS Interface Features .................................................................................. 8.2.2 ISS Interfaces Environment .................................................................................. 8.2.2.1 ISS Interfaces Signal Descriptions .................................................................... 8.2.2.2 ISS Interface Modes .................................................................................... 8.2.3 ISS CSI2 PHY ................................................................................................. 8.2.3.1 ISS CSI2 PHY Overview ............................................................................... 8.2.3.2 ISS CSI2 PHY Functional Description ................................................................ 8.2.3.2.1 ISS CSI2 PHY Functional Configuration ......................................................... 8.2.3.2.2 ISS CSI2 PHY and Link Initialization Sequence ................................................ 8.2.3.2.3 ISS CCP2 and Link Initialization Sequence ..................................................... 8.2.3.2.4 ISS CSI PHY Error Signals ........................................................................ 8.2.3.3 ISS CSI2 PHY Register Manual ....................................................................... 8.2.3.3.1 ISS CSI2 PHY Instance Summary ............................................................... 8.2.3.3.2 ISS CSI2 PHY Registers .......................................................................... 8.2.4 ISS CCP2 ....................................................................................................... 8.2.4.1 ISS CCP2 Environment ................................................................................ 8.2.4.1.1 ISS CCP2 Protocol and Data Formats ........................................................... 8.2.4.2 ISS CCP2 Integration ................................................................................... 8.2.4.3 ISS CCP2 Functional Description ..................................................................... 8.2.4.3.1 ISS CCP2 Overview ................................................................................ 8.2.4.3.2 ISS CCP2 PHY ..................................................................................... 8.2.4.3.3 ISS CCP2 VP Interface ............................................................................ 8.2.4.3.4 ISS CCP2 Data Compression ..................................................................... 8.2.4.3.5 ISS CCP2 Memory Read Channel ............................................................... 8.2.4.4 ISS CCP2 Programming Model ....................................................................... 8.2.4.4.1 ISS CCP2 Hardware Setup/Initialization ......................................................... 8.2.4.4.2 ISS CCP2 Event and Status Checking .......................................................... 8.2.4.4.3 ISS CCP2 Register Accessibility During Frame Processing .................................. 8.2.4.4.4 ISS CCP2 Enable/Disable the Hardware ........................................................ 8.2.4.4.5 ISS CCP2 Select the Signaling Scheme ........................................................ 8.2.4.4.6 ISS CCP2 Select the Mode: MIPI CSI1 or CCP2 .............................................. 8.2.4.4.7 ISS CCP2 Burst Settings .......................................................................... 8.2.4.4.8 ISS CCP2 Debug Mode ............................................................................ 8.2.4.4.9 ISS CCP2 Video Port .............................................................................. 8.2.4.4.10 ISS CCP2 Logical Channels ...................................................................... 8.2.4.4.11 ISS CCP2 Controls ................................................................................. 8.2.4.4.12 ISS CCP2 Region-of-Interest ..................................................................... 8.2.4.4.13 ISS CCP2 CRC ..................................................................................... 8.2.4.4.14 ISS CCP2 Destination Format .................................................................... 8.2.4.4.15 ISS CCP2 Frame Acquisition ..................................................................... 8.2.4.4.16 ISS CCP2 Synchronization Codes ............................................................... 8.2.4.4.17 ISS CCP2 Status Data ............................................................................. 8.2.4.4.18 ISS CCP2 Pixel Data Region ..................................................................... 8.2.4.4.19 ISS CCP2 Memory Read Channel ............................................................... 8.2.4.5 ISS CCP2 Register Manual ............................................................................ 8.2.4.5.1 ISS CCP2 Instance Summary .................................................................... 8.2.4.5.2 ISS CCP2 Registers ................................................................................ 8.2.5 ISS CSI2 ........................................................................................................ 8.2.5.1 ISS CSI2 Environment .................................................................................. 8.2.5.1.1 ISS CSI2 Protocol and Data Format ............................................................. 8.2.5.2 ISS CSI2 Integration ....................................................................................

1158 1158 1159 1162 1162 1163 1166 1166 1167 1167 1168 1172 1172 1173 1173 1173 1176 1176 1176 1189 1191 1191 1191 1192 1194 1194 1202 1202 1202 1203 1203 1204 1204 1204 1204 1205 1206 1206 1206 1206 1207 1207 1207 1207 1208 1210 1211 1211 1212 1245 1245 1245 1280

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8.2.5.3 ISS CSI2 Functional Description ...................................................................... 8.2.5.3.1 ISS CSI2 Overview ................................................................................. 8.2.5.3.2 ISS CSI2 Features .................................................................................. 8.2.5.3.3 ISS CSI2 Functional Description ................................................................. 8.2.5.4 ISS CSI2 Programming Model .........................

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