on-chip inductance issues - nc state university · skin effect impacts resistance and inductance...

1© 2002, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

On-Chip Inductance Issues

Dr. Paul D. Franzon(with Karthik Chandraskar, Dr. Micheal Steer, + more)

Department of Electrical and Computer Engineering Department

North Carolina State UniversityBox 7911

Raleigh, NC 27695-7911Ph. (919) 515-7351Fax (919) 515-7382

[email protected]://www.ece.edu/erl


Outline• Introduction• Review of First Principles

Signal IntegritySignal Propagation and ImpedanceInductanceSkin Effect

• Inductive “Effects”Metal StackupDelay and reflection noiseCrosstalk noiseControl issues

• MeasurementsImportance in modeling Procedures, approaches and examples

• On-Chip Spiral Inductors and TransformersExamples


Novel Systems and capabilities•RF & optical MEMS•Sibgle-chip radio•Ultra-dense packaging•Molecular Computing•Networking & DSP Hardware•IC design methodology

MicroSystems Integration

CMOS VLSI•Full Custom•ASIC•Low Power

MEMS•Bulk•Surface•Emboss•Custom

Advanced Packaging•Seamless integration•Embedded Passives

Paul D. Franzon

Nanotechnologies•Viral•Molecular

S

Au

Au

NO2

(2)(2)


List of Projects

Current Projects:ASIC design for Optical Burst Switching (NSA)Micromachined high density packaging (SRC)High torque precision miniature motors (DARPA)Deep sub-micron IC design (NSF, Cadence, Intarsia)Chip-Package Codesign (SRC, DARPA)SOI low-power radio (NASA)RF MEMS (NSF, DARPA)Molecular Electronics (DARPA)


InfrastructureMicroelectronics Systems Laboratory

> $1M of electronic and photonic test and measurement equipment> $100,000,000M of CAD tools

Electronics Research Laboratory>$7M of RF/microwave test and measurement equipmentTwo Network Analyzers; Probe Station; TDR, etc.

Solid State LaboratoryAbility to perform custom MEMS / micromachining steps


Signal Integrity ObjectivesOverall Design Objective in Digital Circuits:

Obtain timing and noise to avoid transition in excess of noise margin at timed elements during set-up and hold +/- skew and jitterDistribute clock with low skew and jitter + Noise < Noise Margin

Clock

Logic and InterconnectData

Flip-flops Flip-flops

D Q D Q

ClockDQ

tsetup thold Setup ViolationMetastability

Delay = skew + jitter


…Signal Integrity ObjectivesRole of Interconnect Design and Extraction in Signal Integrity:

Signal PathsInterconnect Delay part of path delay

Excessive delay leads to set-up violationsUnderpredicted delay leads to hold violations

Excessive noise can lead to metastability, if intrude on flip-flop during set-up and hold

ClocksInterconnect can:

Increase clock skewIncrease transition time of clock (increasing skew)

Noise in excess of noise margin leads to failure

Clock1Clock2Signal


Signal PropagationPropagating Current and Voltage supported by propagating electric and

magnetic field.

Under reasonable assumptions, transmission line equations apply:

P S G

CjGLjR

YZZ

CjGLjRZY

eVeVZ

I

eVeVV

xx

xx

ωω

ωωγ

γγ

γγ

++==

++==

+=

+=

−−

+

−−

+

0

0

))((

)(1Note:

•Transmission line propagation (approach ~ 0.3 speed of light) if

Rl < 2√(L/C);

•Otherwise RC-like propagation as R > ωL


Transmission Line “Behavior”Zdrv Z0

Vswing Z0/(Zdrv+Z0)t>l/v

T=2l/v

T>2l/v

T>3l/v

l

100% reflection

If Zdrv = Z0No reflection


Switching ScenariosSource impedance matched

Good-size driver

Zdrv = Z0 l

Vswing

l/v 2l/v


Signal PropagationTransmission Line Propagation•√(LC) delay•Model

2-6 segments typical

•Potential for Reflection Noise(Requires large driver,Zdrive ~ √(L/C))

RC Propogation•RC Delay

Source: Qi, et.al.”On-Chip InductanceModeling of VLSI Chips,”ISSCC 2000length < tR vprop/10

Source: Kleveland, et.al. “Line Inductance Modeling And Extraction in a Real Chip with Power/Ground Grid”, IEDM 98.

Non-Physical


Signal Return PathThe signal return path is as important as the signal path

• It exists whether provided for or not

• Think of “return” structures, not just power and ground.• Its an AC path

Decoupling capacitance often provides the path between different reference planes

In an IC, Return Path consists mainly of Power/Ground Grid and Other Signal Paths.


Return Path is Frequency DependentReturn signal seeks the path of least impedance

When frequency is low = path of least resistanceWhen frequency is high = path that minimizes current loop

=> A source of frequency dependanceIf R and jωL are comparable, a frequency dependency referred to as the proximity effect enters into the issue.

LjRZ ω+=

Return current at low frequencyGround Plane

Signal Line

Return current at high frequency


InductanceDefinition

L = N φ/I

Inductance is only properly defined wrt a current loopReturn paths identified

Effect of inductanceV = L di/dt

Impedes changes in current

Partial InductanceMathematical abstraction of “partial inductance” often used by modeling tools to avoid problem of modeling loop

φ


Partial Inductance• Tools model partial inductances

Can be directly input to Spice simulator as inductance between pairs of nodes• Loop inductance “calculated” by

Explicitly identifying the return path, orImplicitly identifying the return path by doing a circuit simulation on a netlist containing partial inductances (+ Ls and Cs)

• ExamplePartial inductance L11 or L22Loop inductance (the ‘real’ inductance). If conductor 2 is a ground, L = L11 + L22 - 2 M12


Skin EffectMinimizing jωL at high frequencies leads to current crowding:

Increasing Frequency

Current Density

Depth

JS0.37 JS

Skin Depth


…Skin EffectSkin depth defined as distance current density is 1/e that of surface.

Skin effect becomes important as δS starts approaching thickness/2.Rough approximate skin effect resistance:

ρ = resistivity, w = width• 1 µm thick IC trace: Skin effect insignificant below ~4 GHz

.typermeabili,/

==

µπµρδ fS

Sskin wR

δρ≈


Skin EffectImpacts Resistance and Inductance

• Tools often only calculate “external” or HF inductance.• Skin effect insignificant for most ICsInductance Data Source : Massoud et.al. “Layout Techniques for Minimizing On-Chip Interconnect Self

Inductance,” 1998 DAC.

Inductance (nH/cm)

1

1.5

2

2.5

3

3.5

4

1.0E+06 1.0E+08 1.0E+10 1.0E+12 1.0E+14

Inductance(nH/cm)

Resistance (W/cm)

0

2000

4000

6000

8000

10000

12000

14000

16000

1.0E+06 1.0E+08 1.0E+10 1.0E+12 1.0E+14

Resistance(W/cm)

G S G1µm

1µm1µm


Proximity EffectMore important than skin effect in determining frequency dependence

Return path resistance function of frequency(However, single frequency modeling usually satisfactory – choose frequency

between 1/(2tr) and 1/(3tr))Note: Can not make signal wire arbitrarily wide to obtain low-R.

G S P G S PIncreasing Frequency

Signal Current Path

Return Current Paths


Outline• Review of First Principles






Typical Conductor Stack-UpSample 6-layer process:

Note : Even one thick metal can be “hard to get”

... 2.1 µm

Min: 1.8 µm

M61.36 µm1.37 µmM5

M4M3M2M1

0.73 µm

Global Power/Ground/Signal

Cell Power/Ground/Signal

Local Power/Ground/Signal


Clock NetsIncluding L is important to accurately predicting clock skew and both L and Rreturn

are important for predicting transition time.

Thin M4 Thick M5Source: P. Restle, “Measurement and Modeling of On-Chip Transmission Line Effects in a 400 MHz Microporocessor,”

IEEE JSSC, 33(4), April 1998.


Data Nets• Delay issues identical to clock nets• Noise Issues:

Common mode noise when signals share power/grounds (R12)Requires return path resistance modeling for full analysisTransmission line noise : Noise different at each end

Source:Deutsch, et.al.“Multiline Crosstalk and Common Mode Noise,” 2000.

Q = Quiet Line= Power or Ground

12 µm pitch, 5 mm lines


Improving Crosstalk NoiseImprove by increasing power/ground density

Worst Case:55 – 150 mV(10% Vswing)

Source:Deutsch, et.al.“Multiline Crosstalk and Common Mode Noise,” 2000.


On-Chip Inductance “Control”• Important for longer lines only

For ~ 100 nm gates; tR ~ 50 psShort Lines

√(LC) l < 0.25 tRR > 1000 Ω/cm; l < 500 µm; C ~ 2-3 pF/cm; L ~ 3-5 nH/cmZdrv >> ZORC dominated

Medium LinesR ~ 200 – 300 Ω/cm; l ~ 1-3 mm; Zdrv < 3 ZORC dominated

Long linesR < 100 Ω/cm; Zdrv ~ 50 Ω (Z0); R, Zdrv low to make fast3 - 10 mmRLC approach essential

Source: Deutsch, “On-Chip Wiring Design Challenges for GHz operation,” Proc. IEEE, April 2001


On-Chip Inductance “Control”For Long Nets:• Make inductive effects easier to predict by explicitly providing return

pathsPower/Ground Shields both sides of clockLow ratio of P/G to signals for buses

• Determine design rulesDriver impedance, wire-widthSpacing, width, P/G density for crosstalk and CM noise

• Must use modeling toolsAt least inductance; preferably resistance also for clocks

• Consider buffer insertion and line “twisting” to reduce inductance impact

Must calibrate models with measurementsNo modeling tool can capture all effects


Measurements1. Use Realistic Test Structures

• Include rich set of parasitic structures, not sparse structures• Range of line lengths

• Short lines hard to remove phase error• Long lines are too lossy

• Include on-chip de-embedding structures (see our web pages)2. Consider Time Domain and Frequency Domain

• Time Domain Reflectometry• Easier but limited by rise-time; no frequency dependance

• E-beam : sampling oscilloscope• On-chip sampling oscilloscope• Frequency Domain : S parameters (Network Analyzer)

• Gives frequency dependance• De-embedding procedure can be difficult

• On-chip calibration structures hard to get 50 Ω match• Off-chip calibration structures lead to inaccurate results

3. Keep extraction physical• Model what can be modeled, then numerically fit


Test StructuresExamples:


Time Domain vs. Frequency Domain• Time Domain Reflectometry

• Easier but limited by rise-time; no frequency dependance • Frequency Domain : S parameters (Network Analyzer)

• Gives frequency dependance• De-embedding procedure can be difficult

• On-chip calibration structures hard to get 50 Ω match• Off-chip calibration structures lead to inaccurate results


NCSU S-parameter Test ResultsAfter De-embedding:

Resistance,Inductance

Characteristic Impedance,

Mag. & Phase


On-Chip Inductors and TransformersModeling Needs• Need accurate models for higher-Q circuits (e.g. frequency synthesizers)

and lower accuracy for broader band circuits• Complexities due to substrate “ground” shields

Tessalated PolysiliconRich wiring grid

Measurement Issues• Still need to calibrate models• S-parameter measurements more reliable in this domain

C/- Dogan, NCAT


OEA-Spiral Inductor Simulation-Measurement

9 turn Inductor ,Width 1.2um, InterTurn Spacing 1.2um,Outer Diameter 50um(Left-Layout ,Right-3D Model)

L(from Spiral)=1.89nH(without PGS); L(from Formulae[7]=2.08nH; L(extracted from S-parameter data=2.6nH(with PGS)

•Calibration still needed (ground shield)[7]Jose M.Cruz et.al,”On Chip Inductors and Transformers”


AC Coupled Interconnect Concept

New IdeasNew Ideas•AC coupled connections down to 70 µm pitch•Short- or long-range capacitive or inductive coupling•Buried solder bumps to bring chips into proximity•High-speed, low-power current switching techniques

(100:1 high-Z probe)

Substrate

DC Connection(Solder Bump)VLSI Chip

AC Connections

TrenchInterconnection

Layer

VLSI Chip

Trench

DC Connection(Solder Bump)

SolderBump C

hip

L-C Pads

SubstrateBumpPad

L-C Pads


Coupled Inductor Measurements

TSMC 0.25µm 5 metal processPolysilicon shieldMetal1/Metal4 50µm diameter spirals


…Coupled Inductor Measurements

TSMC 0.25µm process; 50µm Spiral Inductor; 9 Turns

-10dB

-14dB

-16dB

-18dB

-20dB

-22dB

1GHz 5GHz 10GHz 15GHz 20GHz

chip 2

chip 1


Coupled Inductor ModelCapacitance and Resistance

Calculated from TSMC process parametersInductance calculated from formulas in literatureUse model to match measurements and make predictions


109 1010-28

-26

-24

-22

-20

-18

-16

-14

-12

Mag

S21

(dB

)

Frequency (Hz)

Measurement and Model

Model to Match MeasurementsModel generation

Measure S-parametersOpen circuit - pads only50um x 50um 9 turn coupled inductors

De-embed effects of padsLumped model

Model ValuesCp = 180fFCps = 15fFRp = 65ΩRs = 65ΩLp = 2.8nHLs = 2.8nHK = 0.5

Measurement vs ModelSimple model provides excellent fit


Conclusions• On-chip inductance important in long-range connections

Roughly > 3 mm todayIncludes inductive effect on resistanceDelay, Transition Time, Noise all impacted

• Management StrategyModeling, as calibrated by measurementSimulation of realistic structuresRules-driven design

Driver SizingPower/Ground (return) designWire SizingBuffers, twists, etc.

• Spiral Inductors and TransformersEasier to manage but fidelity needs greaterMeasurement confirmation and calibration still essential

on-chip inductance issues - nc state university · skin effect impacts resistance and inductance...

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