Optimal-Complexity Optical Router

Hadas Kogan, Isaac Hadas Kogan, Isaac KeslassyKeslassy

Technion (Israel)Technion (Israel)

Router – schematic representationRouter – schematic representation

Problem - electronic routers do not scale to optical speeds:

Access to electronic memory is slow and power consuming.

Data conversions are power consuming as well.

Electronicto optic

Electronicto optic

…

Lookup Switching

Optic to electronic

Optic to electronic

…

Buffering

Router

Power consumption per chassisPower consumption per chassis

0

2

4

6

8

10

12

14

16

1990 1993 1996 1999 2002 2003 2004

Po

wer

(kW

)

[Nick McKeown, Stanford]

How about an optical router?How about an optical router? No electronic memory bottleneck No O/E/O conversions

BUT:An optical router is thought to be too complex.

Is it?

Objective: quantify the fundamental complexity of an optical router

Quantifying complexityQuantifying complexity

“Quantify the fundamental complexity of an optical router” reduce into most basic building blocks

Switching – 2x2 switches(and input/output lines)

Basic optical buffering componentBasic optical buffering component

11 1(a) (b) (c)

Buffering – 2x2 switches (and input/output/fiber delay lines)

Mode of operation: (a) Write (b) Circulate (c) Read

The complexity of a system is the minimal number of 2x2 switches

needed to implement it.

Quantifying complexityQuantifying complexity Complexity lower-bound: To get a state-

space of size K in time T, the minimal number C* of 2x2 switches needed is:

Examples: NxN switch:

Time Slot Interchange with time frame N:

* 2logK

CT

12345678

1

2

3

4

5

67

8

* 2log ![Shannon '49]

1

NC

812345678

N

1 2 345 6 78

* 2log ![Jordan et al. '94]

NC

N

Quantifying complexityQuantifying complexity A construction algorithm is said to be

optimal if its number of 2x2 switches grows like the construction complexity.

Examples: NxN switch (“Benes is optimal”):

Time Slot Interchange:

* 2log ( !)( ln )

1

NC N N C

* 2log ( !)(ln )

NC N C

N [Jordan et al. ‘94].

[Benes ‘65]

Optimal buffer emulationOptimal buffer emulation

Emulation definitionEmulation definition

654321

t

Original buffer:

Buffer emulation (with delay D):

654321

tD

Emulation ideaEmulation idea Objectif: emulate buffer of size B

Universal buffer: any policy

Idea: schedule using frames of size B During any frame of B slots, observe which packets

leave the original buffer and color them in blue After some pipeline delay, send these blue packets

in the same order

Opticalbuffer

F - Frame of size BFrame-based scheduling

AlgorithmAlgorithm

B

departureB B

Algorithm is optimal Complexity Θ(ln B) Complexity lower-bound Θ(ln B) (the Time

Slot Interchange is a special case)

6 31

25

4

631 631 254

124 356

Optimal router emulationOptimal router emulation

What we want: an ideal routerWhat we want: an ideal router An output-queued push-in-first-out

(OQ-PIFO) switch.

OQ - Arriving packets are placed immediately in the queue of size B at their destination output.

PIFO – packets departure ordering is according to their priority.

Input 1

Input N

… …

Output 1

Output N

What we want: an ideal routerWhat we want: an ideal router Why it is ideal:

OQ: Work-conserving best throughput and average delay.

PIFO: Enables FIFO, strict priority, WFQ… But – up to N packets could be destined

to the same output: Speed-up for switch Speed-up for queue PIFO is hard to implement.

Finding the complexityFinding the complexity Direct calculation of complexity seems

impossible – what are the states?

Alternative way of finding the complexity: Find a lower bound Find an upper bound via algorithm

Algorithm complexity = Θ (lower bound) algorithm is optimal

Lower bound - intuitionLower bound - intuition

Input 1

Input N

… …

Output 1

Output N

At least Θ(Nln(N)) At least Θ(ln(B))

B

Intuition: the complexity of an OQ-PIFO switch is at least Θ(N ln(N) + N • ln(B)) = Θ(N ln(NB))

Lower boundLower bound A frames switch (time/space switch):

341

625

1278

11910

t=3t=4t=5t=6t=7t=8t=9

456

123

101112

789

t=1t=2t=3t=4t=5t=6

Framesswitch

A frames switch is a special case of an OQ-PIFO switch.

The practical complexity of a frames switch:

Complexity {OQ-PIFO} ≥ Θ(Nln(NB)) Now, find an algorithm that reaches this lower-

bound

ln(( )!)( ) ( ln( ))

NBN NB

B

B

N

Example: Emulating a non-idling OQ-FIFO switch:

Solving the speed-up problemSolving the speed-up problem

Using parallel buffers to resolve conflicts: At most one packet can enter a buffer at each time

slot (N-1 constraints). A packet departing at time T should not enter a

buffer with a packet departing at T (N-1 constraints). 2N-1 buffers are enough.

Input 1

Input N

… Output A

…

A1

C1

A2

Output B

…

C2

D1XX

Leaves output A at time 1

The pigeonhole principleThe pigeonhole principle Proof intuition:

Pigeons ↔ PacketsHoles ↔ Buffers

For emulating PIFO behavior – The departure process is slightly modified 4N-2 parallel buffers are required

Input 1

Input N

… …Output 1

Output N

…

…

Output 1

Output N

…

An optical emulation of an OQ-PIFO An optical emulation of an OQ-PIFO switchswitch

Optical buffer

Optical buffer

The pigeonhole principle+

Our emulation of an optical buffer=

An optical OQ-PIFO switch

πB

B

B

πB

(4N-2)xN switch

πB

B

B

πB

πB

B

B

πB

...

Nx(4N-2) switch

An optical emulation of an OQ-PIFO An optical emulation of an OQ-PIFO switchswitch

Number of 2x2 switches = Θ(NlnN+NlnB) = Θ(Nln(NB))= Θ(lower bound)

algorithm is optimal

ConclusionConclusion

Buffer fundamental complexity = Θ(lnB)

OQ-PIFO router fundamental complexity = Θ(NlnNB)

Both can be reached using given algorithms

Thank you!Thank you!