optimizing a multi- processor system performing: isaac yarom supervised by: mony orbach 15/5/2008...
DESCRIPTION
Tools Hardware: PC system GiDEL StartixII® Development system: Altera SoPC® + QuartusII GiDEL ProcStar® NiosII® based VPU LBS developed Host/Generator softwareTRANSCRIPT
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OPTIMIZING A MULTI-PROCESSOR SYSTEM
Performing: Isaac YaromSupervised by: Mony Orbach15/5/2008
Annual Project – Semester A (2007-1)Mid-term presentation
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Introduction A few teams from HS DSL are developing a
multi-processors system that implements a recognition algorithm from REFAEL.
The system is design as SOPC using on multiple FPGA systems
Area on FPGA is an important constraint, there is a need to decide on system “configuration” that will supply the best performance on a given FPGA system.
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Tools Hardware:
PC system GiDEL StartixII®
Development system: Altera SoPC® + QuartusII GiDEL ProcStar®
NiosII® based VPU LBS developed Host/Generator software
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System overview
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System overview (continued)Current state of system: Nios VPU is implemented with C2H.
Some issues regarding size and speed Switch system is implemented.
No support for asymmetric VPUs yet. MultiFIFO communication between PC and
FPGA has problems. Implementation Generator team has
contacted GiDEL in regards to this problem.
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Project goals – Part A Performance evaluation methods and tools
Define methods and tools to use Implement needed tools
Define optimization constraints and trade offs Software model
Design and Implement Performance simulator Run on several configuration and produce recommendations for configuration to test on actual system.
Build Dummy-system (+ performance study) Learn Tools: PROCWizard, SOPC Learn System: Switch, Software application & VPU Build dummy system and produce performance evaluation
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Performance evaluation methods Performance is evaluated in several
levels: VPU functions VPU latency System throughput
A “Software system” throughput will be measured as well to perceive FPGA system merit.
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FPGA tools Ramp-up Basic tutorials for
PROCStar® Basic NiosII® CPU on
StarTIX card. Integrating PROCStar,
Quratus and SOPC Builder Basic design Basic VPU
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Timeline – Part A
ID Task NameQ2 08
4/5 11/5
1 Define performance methods and tools
2 Implement performance tools
3 Learn FPGA tools
5 Learn system
6 Build dummy system and run performance evaluation
7 Design and implement performance simulator
8 Run and analyze configuration on simulator
4 Define optimization constraints and tradeoffs
18/5 25/5 1/6 8/6 15/6 22/6
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Presentation Notes Profiling algorithm is first prority from
performance tasks Understand algorithm Control C2H If needed push other task to second
semester