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CHAPTER 5

PACKAGING STRATEGIES FOR RF MEMS SWITCHES

5.1 Introduction

The packaging technique for RF MEMS switches is the complex and expensive step,

which will ultimately decide the cost of the switch. MEMS switches are very sensitive to

humidity and contaminants. Packaging contributes to almost 80% of the total cost of the

device and its functioning and reliability strongly depend on the packaging. Therefore,

MEMS packaging tends to be customized to the specific application, with emphasis on the

cost, performance and reliability. Without packaging, the operation of RF MEMS switches

can be severely affected by the presence of water vapor, contaminants, hydrocarbons and

other gases in the atmosphere. As the pull-up forces are very small (50-500 µN) and are not

enough to overcome the adhesive forces of water molecules or puncture through any

contaminants in between the capacitive contact, the performance gets highly affected due to

the presence of above. To avoid the failure of RF MEMS switches, proper RF and hermetic

packaging is required. A lot of general packaging issues make the packaging of RF devices a

quite complex process, such as; package sealing material, sealing curing temperature,

alignment of package with device, package material & external connections etc. The

package can be composed of LTCC, ceramic material, beryllium oxide & aluminum etc. The

hermetic seal can be achieved using seam sealing, roller sealing or laser sealing techniques,

and these methods have been proven to satisfy long-term satellite and defense applications

[1]. The high temperature packaging processes are generally avoided to improve the

mechanical reliability of MEMS switches. Several different technologies can be used for the

RF MEMS switch packaging; such as [2]

• Epoxy Seals

• Metal - to - metal solder bonding

• Glass - to - glass anodic bonding

• Glass frit bonding

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• Gold - to - gold thermo-compression bonding, etc.

There are several problems with these techniques, as most bonding techniques outgas

organic materials inside and outside the MEMS cavity during the bonding or curing

processes due to wetting compounds in the gold, glass or epoxy materials. This out-gassing

has a serious effect on reliability of RF MEMS switches. Also, hermetic bonding process

requires very high temperatures for achieving a good seal contact. For released structures,

high temperature processing can bow the membranes by several microns (for thin and long

membranes), thus damaging the switch. Other bonding techniques like glass - to - glass

bonding and thermo-compression bonding techniques are sensitive to the planarity and

cleanliness of wafer, surface roughness and exact height of gold rings on the wafer. A

number of RF MEMS packaging techniques have been discussed in Ref. [1].

5.2 Levels of RF MEMS Packaging

For RF MEMS switches, packaging can be done in three different levels as zero

level, first level and second level, which is the final level of packaging [3]. The 0-level

packaging creates an on-wafer device scaled sealed cavity for the fragile MEMS device,

carried out on the wafer during wafer processing, prior to dicing or after the pre-dicing. This

is also called as die level packaging. The 1-level package comprises what is usually

interpreted as the package, i.e., the chip capsule (metal can, plastic package, ceramic

package) and/or the leads for interconnecting the chip to the outside world, also termed as

device level packaging. Mounting a 1-level packaged device to a board, for system level use

is termed as 2-level packaging, also termed as system level packaging. The sealing material

proposed for the initial trial is UV-cured non-conducting epoxy. Though the organic

contaminants will degas after the curing of the epoxy and will reduce the reliability, but for

initial trials we can use it. In this work only zero level packaging strategies have been

discussed.

In this chapter two types of packaging techniques have been discussed which will be

followed for initial or zero-level packaging of RF MEMS switches developed for this work.

These are:

• High resistivity Si cavity packaging or LTCC cavity packaging

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• Si or LTCC packaging using via holes for external connections (Top contact or

bottom cont)

5.3 High Resistivity Si / LTCC Cavity Packaging

As described above, zero level package consists of a single cavity capping only the

mechanical device and extending the connections horizontally for external world. Fig. 5.1

shows the schematic view of zero level package for STS. As can be seen from the Fig. 5.1

(a) & (b), the external connections are extended outside the cavity area. The fabrication

process flow is quite simple in this case, as the standard approach for making Si cavities has

been followed. The switch fabrication will be done according to the streamlined process and

the cavity which has been dimensionally optimized will be sealed over the mechanical

membrane of the switch using non-conducting UV epoxy. The cavity can be fabricated

either by using high resistivity substrate or by using LTCC tapes. For silicon cavity

fabrication, bulk etching using TMAH has been done. An etch rate of nearly 0.5 µm has

been achieved with an undercut ratio of 1:40. The difference between them will be reflected

in the terms of insertion losses. Fig. 5.2 (a) - (d) shows the simulated on-state and off-state

response of the switch with high resistivity silicon cavity. High frequency structure

simulator (HFSS) is being used for the electrical designing of RF MEMS switches. As

shown in Fig. 5.2 (a) - (d), different cavity heights show different losses, but loss gets

stabilized above 50 µm cavity height. Above 50 µm, response remains same for all cavity

heights. Thus, 50 µm deep Si cavity is sufficient for zero level packaging and can easily be

MEMS BridgeDC

Contact

DC

Contact

Si/LTCC cavity

Transmission line

Substrate CPW Ground CPW Ground

Signal Line

DC Contact

Pads

RF Contact Pads

Si/LTCC Cavity

(a) (b)

Fig. 5.1: Schematic view of zero level package for RF MEMS Switch, (a) cross sectional view,

(b) top view.

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etched using standard Si bulk etching technology. Fig. 5.3 (a) -(d) shows the electrical

response of zero-level packaged STS with LTCC as the cavity material. As same as the

silicon cavities response, the insertion loss of STS with LTCC cavity gets stabilized above

50 µm cavity height. Thus, with the LTCC cavities also, 50 µm is the optimum height for

zero level packaging. The cavities have been etched using TMAH etchant. The etching was

carried out in a laboratory made assembly consisting of reflex condenser. For agitation of

the liquid, a magnetic stirrer was submerged in the liquid and was kept under a meshed

teflon cap, on top of which a boat containing wafer has been placed.

5.4 Silicon or LTCC packaging using via holes for external connections

Since it is easy to access the electrical and RF connections by extending the

connections outside the cavity sealing area, but the radiation losses outside the cavity will be

quite high. Another method for packaging to reduce the radiation losses has been proposed

in this section. The method is to take the connections vertically out of the package. Vertical

contacts can be taken from top, i.e. through the cavity package as well as from the bottom

-0.24

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rtio

n L

os

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turn

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ss [

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]

On-state On-state

Off-state

Off-state

(a) (b)

(c) (d)

Fig. 5.2: Comparison of STS for different cavity height packages in silicon (a) & (b) on state,

and (c) & (d) off state.

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[4], i.e. through the substrate. For top contact approach we can use the standard packages

available in the market from Kyocera and Hymite. One of the packaging methods using

standard vertical contact package has been described in Fig. 5.4 using Hymite package

available in Coventor Ware [5]. The package sealing is a metal to metal one. As shown in

Fig. 5.4 (a), the metal sealing in gold will be fabricated along with the switch without any

additional masking steps. Fig. 5.4 (b) & (c) shows the bottom view and top view of the RF

package. Bottom view shows the gold seal ring which is grounded with CPW grounds, two

RF connections and two DC connections. Top view shows the access of these connections to

the top side for external world connections. The connection from bottom to top is achieved

through the via holes filled with the metal. Fig. 5.4 (f) shows the proposed view of complete

packaged device using standard available package in market from Hymite. This type of

package can also be made using in-house LTCC technology at CEERI, Pilani. In this type of

packages, to minimize the losses, the design of cavity and via holes have to be optimized.

On-stateIn

sert

ion

Lo

s [d

B]

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(a)

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turn

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ss [

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(b)

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(d)-50

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Iso

lati

on

[d

B]

(c)

Fig. 5.3: Comparison of STS for different cavity height packages in LTCC (a) & (b) on state,

and (c) & (d) off state.

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Though the standard packages are available, but the sealing technology is thermo-

compression or high temperature sealing. This can lead to local heating of the mechanical

membrane to high temperatures, resulting in degradation in device performance. To avoid

this local heating, vertical connections using bottom contact approach has been proposed.

STS with extended DC and RF connections and outer seal ring

Gold Seal RingDC Connection

DC ConnectionRF Connection

Package Bottom view

Package Top view

RF Connections on top

RF Connections on top

DC Connection on top

DC Connection on top

Gold Seal Ring

STS with package, top cover is hidden

Via holes filled with gold Cavity

(a) (b)

(c) (d)

Top Connections, connected to via holes

Complete packaged deviceTop connection of device with top cover hidden

(e) (f)

Fig. 5.4 (a) - (f): Packaging of STS using standard Hymite package available in Coventor

ware library.

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Following this type of approach, high resistivity Si wafers (> 5 kΩ), LTCC or Alumina, any

type of substrate can be used. The simulations have been carried out using high resistivity

silicon substrate. Fig. 5.5 shows the cross sectional view of proposed approach. As shown in

Fig. 5.5 (a), through & through via holes can be etched using Si wet etching or DRIE (Deep

reactive ion etching) [6]. Fig. 5.5 (b) shows the metal filling and contacts on the back side of

wafer. Fig. 5.5 (c) shows the electrode formation on the contacts available on the top side of

the wafer. The inner and outer electrodes are shorted together through polysilicon lines. Fig.

5.5 (d) shows the transmission line formation over the contact & Fig. 5.5 (e) shows the

bridge formation. Fig. 5.5 (f) shows the capping of the device by using epoxy seals. After

capping, the inner contacts are available at the bottom side of the wafer, and the chip can be

soldiered on the PCB and coaxial contact cables for further use in systems.

(a)

(b)

(c)

(d)

(e)

(f)

Fig. 5.5 (a) - (f): Packaging of STS using bottom contact approach.

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References

[1]. G. M. Rebeiz, “RF MEMS Theory, Design and Technology”, 1st ed. Wiley Inter-

Science, 2003.

[2]. Paola Ferinelli, “RF-MEMS Packaging”, presentation at University of Perugia, May

11, 2007.

[3]. A. Jourdain, K. Vaesen, J. M. Scheer, J. W. Weekamp, J. T. M. van Beek & H.A.C.

Tilmans, “From Zero to Second level packaging of RF MEMS devices”.

[4]. Qun Wu, Xun-jun He, Bo-shi Jin, Ming-xin Song & Jing-hua Yin, “Packaging and

feedthrough modes of wafer level for RF MEMS Switches”, 2006 International RF

and Microwave Proceedings, Putrajaya, Malaysia, September 12 – 14, 2006.

[5]. Coventor Ware® 2008 & 2010.

[6]. Alexandros Margomenos, Dimitrios Peroulis, Katherine, J. Herrick and Linda P. B.

Katehi, “Silicon Micromachined packages for RF MEMS Switches”, IEEE Xplore,

31st European Microwave Conference, September 2001, pp. 1 - 4.