page 1 : menu page 6 : dc/dc for arria10-group1->vccr...
TRANSCRIPT
MENU
PAGE 6 : DC/DC FOR ARRIA10-GROUP1->VCCR_GXB,VCCT_GXB
PAGE 8 : DC/DC FOR ARRIA10-GROUP1->VCCRAM
PAGE 12 : MICRO PODS [ ARRIA10 LEFT SIDE ]
PAGE 15 : ARRIA10 POWER AND NON CONNECTED PINS
PAGE 17 : ARRIA10 DECOUPLING CAPACITORS
PAGE 22 : ARRIA10 BANKS BOTTOM:3A,3B-TOP:3G,3H
PAGE 2 : MMC (ATMEGA128)PAGE 3 : MMC (OTHERS)PAGE 4 : VOLTAGE SEQUENCERPAGE 5 : DC/DC FOR ARRIA10-GROUP1-VCC
PAGE 7 : DC/DC FOR ARRIA10-GROUP2
PAGE 9 : MEMORIES : DDR3PAGE 10 : STANDARD CLOCKSPAGE 11 : TTC CLOCKS
PAGE 19 : ARRIA10 LEFT TRANSCEIVERS
PAGE 24 : JTAG CHAINS
PAGE 27 : OTHERS
PAGE 1 : MENU
PAGE 20 : ARRIA10 RIGHT TRANSCEIVERS
DC/DC FOR ARRIA10-GROUP3->VCC_PGM,VCCIO AND 3.3V & 2.5V FOR OTHERS COMPONENTS
PAGE 26 : FPGA CONNECTIONS
PAGE 23 : AMC CONNECTOR
PAGE 21 : ARRIA10 BANKS BOTTOM:2A,2F-TOP:2K,2L
PAGE 18 : ARRIA10 CLOCKS AND CONFIGURATION
PAGE 16 : ARRIA10 GROUND
PAGE 14 : MICRO PODS TO ARRIA10 CONNECTIONSPAGE 13 : MICRO PODS [ ARRIA10 RIGHT SIDE ]
PAGE 25 : LEVEL TRANSLATION
MODIFIE: Fri Jan 30 09:52:36 2015
SHEET: 1 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 1 / 27
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
MENU
PAGE 6 : DC/DC FOR ARRIA10-GROUP1->VCCR_GXB,VCCT_GXB
PAGE 8 : DC/DC FOR ARRIA10-GROUP1->VCCRAM
PAGE 12 : MICRO PODS [ ARRIA10 LEFT SIDE ]
PAGE 15 : ARRIA10 POWER AND NON CONNECTED PINS
PAGE 17 : ARRIA10 DECOUPLING CAPACITORS
PAGE 22 : ARRIA10 BANKS BOTTOM:3A,3B-TOP:3G,3H
PAGE 2 : MMC (ATMEGA128)PAGE 3 : MMC (OTHERS)PAGE 4 : VOLTAGE SEQUENCERPAGE 5 : DC/DC FOR ARRIA10-GROUP1-VCC
PAGE 7 : DC/DC FOR ARRIA10-GROUP2
PAGE 9 : MEMORIES : DDR3PAGE 10 : STANDARD CLOCKSPAGE 11 : TTC CLOCKS
PAGE 19 : ARRIA10 LEFT TRANSCEIVERS
PAGE 24 : JTAG CHAINS
PAGE 27 : OTHERS
PAGE 1 : MENU
PAGE 20 : ARRIA10 RIGHT TRANSCEIVERS
DC/DC FOR ARRIA10-GROUP3->VCC_PGM,VCCIO AND 3.3V & 2.5V FOR OTHERS COMPONENTS
PAGE 26 : FPGA CONNECTIONS
PAGE 23 : AMC CONNECTOR
PAGE 21 : ARRIA10 BANKS BOTTOM:2A,2F-TOP:2K,2L
PAGE 18 : ARRIA10 CLOCKS AND CONFIGURATION
PAGE 16 : ARRIA10 GROUND
PAGE 14 : MICRO PODS TO ARRIA10 CONNECTIONSPAGE 13 : MICRO PODS [ ARRIA10 RIGHT SIDE ]
PAGE 25 : LEVEL TRANSLATION
MODIFIE: Fri Jan 30 09:52:36 2015
SHEET: 1 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 1 / 27
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
PS1/PS0 SCHOTTKY DIODE : 0.6V MAX WHEN 2MA
MMC:ATMEGA128
MODIFIE: Mon Mar 23 09:50:36 2015
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C381
R118R117R116
R122
R123
1 T4
1 T5
R121
R120R119
CA
D8
C382
R186
R187
2324
20
1918433433
5455565758596061
1
98765432
3231302928272625
4241403938373635
1716151413121110
4445464748495051
6462
U31
R115
R112R111R110
R114R113
61U30
43U30
330
390K
33K
33K
0
150K
49.9K
4.7K
1.0N
33K
33
4.7K
100N
3333K
33K
4.7K
150K
MMC_FPGA_RELOADNMMC_FPGA_INIT_DONE
MMC_FPGA_USER_IO0
MMC_LED_RED_N
ATMEGA_RESET
MMC_SCL
MMC_FPGA_USER_IO1
A10_G1_VCC_POKA10_G2_POWER_POKA10_G3_POWER_POKCON_ATMEGA_JTAG_TCK
CON_ATMEGA_JTAG_MISO
AMC_PS0_N
MMC_SDAMMC_TEMP_ALARM_NPOWER_SEQ_DONE_NPOWER_SEQ_FAULT_N
ATMEGA_RESET
AMC_PS1_N
MMC_LED_BLUE_NMMC_LED_GREEN_N
AMC_GA0AMC_GA1
MMC_FPGA_RESETN
MMC_DC_DC_EN
AMC_GA2
AMC_PS1_N
CON_ATMEGA_JTAG_MOSI
CON_ATMEGA_JTAG_TMS
AMC_SCL_L
MMC_MICROSWITCH_NAMC_SDA_L
AMC_PS0_N
MMC_FPGA_INIT_DONE
AMC_ENABLE_N
FPGA_INIT_DONE_LED_N
MMC:ATMEGA128
MMC:ATMEGA128
25D4
5B6 4C2 4C2 8D4 24B4 24B4
24B6 24B6
(GND:53,22,63,65;VCC:21,52)VCC=P3V3_IPMI
24B6 24A3
4B6
BAT165
23B5
3B1
23A7
GND=GND
GND=GND
VCC=P3V3_IPMI
VCC=P3V3_IPMI
3D7
3D7 3D7 3D7
23B7 23B7
4B6 3B1
25E8
4D8
23B7
2A8 25C4
2B5
2D2 23B5
25D4 25D4
24A4
24C6 4C2 8C1
7D3
3D1 3B1 3A6 3D2 3A6
3B6 23A7
2C2
2A3 23B5 2A5 23B5
2D6
2C6 25C4
24B6 23B4
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
p3v3_ipmi
*
GND
p3v3_ipmi
IN
BIIN
IN
OUTBI
**
p3v3_ipmi
*
IN
VP12
**
GND
test_pin
TEST
test_pin
TEST
VP12
p3v3_ipmi
ININ
IN
GND
*
**
INININ
ININ
OUT
SN74LVC2G06DCKR
1Y1A
IN
BIBI
IN
p3v3_ipmi
GND
*
*
SN74LVC2G06DCKR
2Y2A
IN
INININ
THERMAL_PAD : 65,66,67,68
atmga128
VCC : 21,52GND : 53,22,63
PF7PF6PF5
PF3PF4
PF2PF1PF0
PE0PE1PE2PE3PE4PE5
PE7PE6
PD0PD1PD2PD3PD4PD5PD6PD7
AREFAVCC
PC7PC6
PC0PC1PC2PC3PC4PC5
PB5PB6PB7
PB4
PB0PB1PB2PB3
PA2PA3PA4PA5PA6PA7
PA0PA1
XTAL2XTAL1
RESET*
PEN*PG0PG1PG2PG3PG4
OUT
OUTOUT
OUTOUT
IN
IN
OUT
*IN
OUT
OUT
***
*
IN
PS1/PS0 SCHOTTKY DIODE : 0.6V MAX WHEN 2MA
MMC:ATMEGA128
MODIFIE: Mon Mar 23 09:50:36 2015
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330
390K
33K
33K
0
150K
49.9K
4.7K
1.0N
33K
33
4.7K
100N
3333K
33K
4.7K
150K
MMC:ATMEGA128
MMC:ATMEGA128
(GND:53,22,63,65;VCC:21,52)VCC=P3V3_IPMI
BAT165
GND=GND
GND=GND
VCC=P3V3_IPMI
VCC=P3V3_IPMI
C381
R118R117R116
R122
R123
T4
T5
R121
R120R119
D8
C382
R186
R187
U31
R115
R112R111R110
R114R113
U30
U30
25D4
5B6 4C2 4C2 8D4 24B4 24B4
24B6 24B6
24B6 24A3
4B6
23B5
3B1
23A7
3D7
3D7 3D7 3D7
23B7 23B7
4B6 3B1
25E8
4D8
23B7
2A8 25C4
2B5
2D2 23B5
25D4 25D4
24A4
24C6 4C2 8C1
7D3
3D1 3B1 3A6 3D2 3A6
3B6 23A7
2C2
2A3 23B5 2A5 23B5
2D6
2C6 25C4
24B6 23B4
MMC_FPGA_RELOADNMMC_FPGA_INIT_DONE
MMC_FPGA_USER_IO0
MMC_LED_RED_N
ATMEGA_RESET
MMC_SCL
MMC_FPGA_USER_IO1
A10_G1_VCC_POKA10_G2_POWER_POKA10_G3_POWER_POKCON_ATMEGA_JTAG_TCK
CON_ATMEGA_JTAG_MISO
AMC_PS0_N
MMC_SDAMMC_TEMP_ALARM_NPOWER_SEQ_DONE_NPOWER_SEQ_FAULT_N
ATMEGA_RESET
AMC_PS1_N
MMC_LED_BLUE_NMMC_LED_GREEN_N
AMC_GA0AMC_GA1
MMC_FPGA_RESETN
MMC_DC_DC_EN
AMC_GA2
AMC_PS1_N
CON_ATMEGA_JTAG_MOSI
CON_ATMEGA_JTAG_TMS
AMC_SCL_L
MMC_MICROSWITCH_NAMC_SDA_L
AMC_PS0_N
MMC_FPGA_INIT_DONE
AMC_ENABLE_N
FPGA_INIT_DONE_LED_N
1
1
CA
2324
20
1918433433
5455565758596061
1
98765432
3231302928272625
4241403938373635
1716151413121110
4445464748495051
6462
61
43
p3v3_ipmi
*
GND
p3v3_ipmi
IN
BIIN
IN
OUTBI
**
p3v3_ipmi
*
IN
VP12
**
GND
test_pin
TEST
test_pin
TEST
VP12
p3v3_ipmi
ININ
IN
GND
*
**
INININ
ININ
OUT
SN74LVC2G06DCKR
1Y1A
IN
BIBI
IN
p3v3_ipmi
GND
*
*
SN74LVC2G06DCKR
2Y2A
IN
INININ
THERMAL_PAD : 65,66,67,68
atmga128
VCC : 21,52GND : 53,22,63
PF7PF6PF5
PF3PF4
PF2PF1PF0
PE0PE1PE2PE3PE4PE5
PE7PE6
PD0PD1PD2PD3PD4PD5PD6PD7
AREFAVCC
PC7PC6
PC0PC1PC2PC3PC4PC5
PB5PB6PB7
PB4
PB0PB1PB2PB3
PA2PA3PA4PA5PA6PA7
PA0PA1
XTAL2XTAL1
RESET*
PEN*PG0PG1PG2PG3PG4
OUT
OUTOUT
OUTOUT
IN
IN
OUT
*IN
OUT
OUT
***
*
IN
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
DIODE4 CLOSE TO VCC DC/DCDIODE3 CLOSE TO RIGHT UPODDIODE2 CLOSE TO LEFT UPODPLACE 100PF CLOSE TO LM95234
I2C ADD=0X14
I2C ADD=0X56
SDR,FRU EEPROM
MMC:EEPROM, SENSORS, OTHERS
I2C ADD=0X4E
ATCA LED 2
ATCA LED 1
ATCA BLUE LED
GREEN
MODIFIE: Mon Mar 23 09:50:36 2015
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C367
C368
R94
R92
R93
C421
C422
R155C423
23
1
T3C424
R95
R96
R153
R154
2
141110
1213
1 8
3467
5
9U37
28
32
3029
2427
35
72322212019181716151413121110
98
383736
2526
U28
C366R91R90
23
1
T1C419
23
1
T2C420
R188
2 1D1
R189
R1902 1
D2
2 1
D3
R151
R152
C418
R1912 1
D4R4
7
C339DC
BA
SW1
4
8
563
21
U16
C340
DNC
DNC
DNC
DNC
DNC
DNC
DNC
240
240
240
240
10U
10U
10U
330K
100N
1K
100N
100P
33K
100N
00
1K
100P
100P
100P
100N
100P
FPGA_INIT_DONE_LED_N
MMC_LED_GREEN_N
MMC_LED_BLUE_N
MMC_LED_RED_N
FPGA_TEMPDIODE_NMMC_TEMP_ALARM_N
P1V8
P2V5
P1V8_M
P2V5_M
P1V5P1V5_MA10_VCC_RAM
A10_VCCPT_VCCH_GXB_VCCA_PLL
A10_VCC_RAM_M
A10_G2_POWER_M
P3V3_MP3V3
A10_VCC
A10_VCCT_VCCR_GXBA10_VCC_M
A10_VCCT_VCCR_GXB_M MMC_SCL
MMC_MICROSWITCH_N
MMC_SDA
TEMPDIODE4_PTEMPDIODE_N
TEMPDIODE2_P
TEMPDIODE_NTEMPDIODE3_P
MMC_SDAMMC_SCL
TEMPDIODE_N
MMC_SDAMMC_SCL
FPGA_TEMPDIODE_P TEMPDIODE1_PTEMPDIODE2_PTEMPDIODE3_P
TEMPDIODE4_P
TEMPDIODE_N
2C6
8A5
15B2
8C4
8D4 26B8
8D5
7B7
GND=GND
2D2
THERMAL_PAD=GND
mmbt3904mmbt3904
mmbt3904
8D4
2C6
3B1 3A6 2D2 3B1 3A6 2D2
26B8 6B2
26C7 5C2 26C7
15B2 2D6
3D2 3A6 2D2 3D1 3A6 2D2
2C6
2A5
3D2 3B1 2D2 3D1 3B1 2D2
3B4 3A3
3B4
3A3 3A3
3B4 3A3 3A2
3B4
3B4 3A3 3A2
3B4
3A3 3A2 3A2
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
INBI
p3v3_ipmi
BI
GND
p3v3_ipmi
*
GND
*
*
p3v3_ipmi
p3v3_ipmi
IN
INBI
*
OUT
GND
**
GND
GNDp3v3_ipmi
GND
p3v3_ipmi
*
*
GND
lm95234
SMBCLKSMBDAT
TCRIT3_NTCRIT2_NTCRIT1_N
A0
GND
D-D4+D3+D2+D1+
VDD
NC
ltc2495 CAO2CAO1CAO0
F0
REF-REF+
ADCINNADCINP
MUXOUTNMUXOUTP
CH15CH14CH13CH12CH11CH10CH9CH8CH7CH6CH5CH4CH3CH2CH1CH0
COM
SDASCL
VCC
24aa025e48_soic
A2A1A0
VSS
VCC
SDASCL
*
GND
*
p3v3_ipmi
ININ
p3v3_ipmi
ININININ
ININ
ININ
IN
IN
GND
ININ
IN
p3v3_ipmi
*
*
*
IN
IN
IN
p3v3_ipmi
IN
*
*
*
p3v3_ipmi
p3v3_ipmi
IN
IN
*
OUT
GND
IN
20849_209
D
B
C
A
GND
GND
DIODE4 CLOSE TO VCC DC/DCDIODE3 CLOSE TO RIGHT UPODDIODE2 CLOSE TO LEFT UPODPLACE 100PF CLOSE TO LM95234
I2C ADD=0X14
I2C ADD=0X56
SDR,FRU EEPROM
MMC:EEPROM, SENSORS, OTHERS
I2C ADD=0X4E
ATCA LED 2
ATCA LED 1
ATCA BLUE LED
GREEN
MODIFIE: Mon Mar 23 09:50:36 2015
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DNC
DNC
DNC
DNC
DNC
DNC
DNC
240
240
240
240
10U
10U
10U
330K
100N
1K
100N
100P
33K
100N
00
1K
100P
100P
100P
100N
100P
GND=GND
THERMAL_PAD=GND
mmbt3904mmbt3904
mmbt3904
C367
C368
R94
R92
R93
C421
C422
R155C423
T3C424
R95
R96
R153
R154
U37
U28
C366R91R90
T1C419
T2C420
R188D1
R189
R190
D2D3
R151
R152
C418
R191D4R4
7
C339
SW1
U16
C340
2C6
8A5
15B2
8C4
8D4 26B8
8D5
7B7
2D2
8D4
2C6
3B1 3A6 2D2 3B1 3A6 2D2
26B8 6B2
26C7 5C2 26C7
15B2 2D6
3D2 3A6 2D2 3D1 3A6 2D2
2C6
2A5
3D2 3B1 2D2 3D1 3B1 2D2
3B4 3A3
3B4
3A3 3A3
3B4 3A3 3A2
3B4
3B4 3A3 3A2
3B4
3A3 3A2 3A2
FPGA_INIT_DONE_LED_N
MMC_LED_GREEN_N
MMC_LED_BLUE_N
MMC_LED_RED_N
FPGA_TEMPDIODE_NMMC_TEMP_ALARM_N
P1V8
P2V5
P1V8_M
P2V5_M
P1V5P1V5_MA10_VCC_RAM
A10_VCCPT_VCCH_GXB_VCCA_PLL
A10_VCC_RAM_M
A10_G2_POWER_M
P3V3_MP3V3
A10_VCC
A10_VCCT_VCCR_GXBA10_VCC_M
A10_VCCT_VCCR_GXB_M MMC_SCL
MMC_MICROSWITCH_N
MMC_SDA
TEMPDIODE4_PTEMPDIODE_N
TEMPDIODE2_P
TEMPDIODE_NTEMPDIODE3_P
MMC_SDAMMC_SCL
TEMPDIODE_N
MMC_SDAMMC_SCL
FPGA_TEMPDIODE_P TEMPDIODE1_PTEMPDIODE2_PTEMPDIODE3_P
TEMPDIODE4_P
TEMPDIODE_N
23
1
2
141110
1213
1 8
3467
5
9
28
32
3029
2427
35
72322212019181716151413121110
98
383736
2526
23
1
23
1
2 1
2 1
2 1
2 1
DC
BA
4
8
563
21
INBI
p3v3_ipmi
BI
GND
p3v3_ipmi
*
GND
*
*
p3v3_ipmi
p3v3_ipmi
IN
INBI
*
OUT
GND
**
GND
GNDp3v3_ipmi
GND
p3v3_ipmi
*
*
GND
lm95234
SMBCLKSMBDAT
TCRIT3_NTCRIT2_NTCRIT1_N
A0
GND
D-D4+D3+D2+D1+
VDD
NC
ltc2495 CAO2CAO1CAO0
F0
REF-REF+
ADCINNADCINP
MUXOUTNMUXOUTP
CH15CH14CH13CH12CH11CH10CH9CH8CH7CH6CH5CH4CH3CH2CH1CH0
COM
SDASCL
VCC
24aa025e48_soic
A2A1A0
VSS
VCC
SDASCL
*
GND
*
p3v3_ipmi
ININ
p3v3_ipmi
ININININ
ININ
ININ
IN
IN
GND
ININ
IN
p3v3_ipmi
*
*
*
IN
IN
IN
p3v3_ipmi
IN
*
*
*
p3v3_ipmi
p3v3_ipmi
IN
IN
*
OUT
GND
IN
20849_209
D
B
C
A
GND
GND
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
RED
GREEN
REGROUP RES 'DNC' MMC_DC_DC_EN WITH RES 'DNC' FPGA_N_CONFIG (P25)
FIRST : MMC NOT CONNECTED ('DNC'ON MMC_DC_DC_EN)DC/DC ENABLE BY MMC OR EXTERNAL SWITCH
POWER SEQUENCING : DELAY~1MS FOR IN TO OUT;1MS OUT TURNED ONDETECTION ON DC/DC POWER GOOD SIGNALS : VON>=3V AND VOFF<2.7VOUT~8V=>VOUT ENABLE ~2V
ARRIA10 : VOLTAGE SEQUENCER
MODIFIE: Mon Mar 23 09:50:37 2015
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R146R145R144
R132R130R128R126
2
1
J1
R17
R16
R24
R143C385
R140R139
R141R142
R138
R134
R136R135
R137R133R131R129R127
11
1412
8765
164321
15
13
910
U32
C384C383
R125R124
21D5R48
21D6R49
240
240 10K
10K
10K
33
0000
10K
10K
10K
10K
DNC
4.7N
4.7N 49.9K
00
680K
330K
680K
0
0
330K
680K 100N
680K
330K
330K
POWER_SEQ_FAULT_N
MMC_DC_DC_EN POWER_SEQ_EN
POWER_SEQ_ENA10_G3_POWER_POK
A10_G1_VCC_POKA10_G1_POWER_POKA10_G2_POWER_POK
POWER_SEQ_DONE_N
A10_G1_VCC_ENA10_G1_POWER_ENA10_G2_POWER_ENA10_G3_POWER_EN
2C6 4C6
4D6 8C1 8D4 2C3
5B6 2C3 6B6 8C4 7D3 2C3
2D6
2D6
5D8 6C7 8D8 7D3 8C1 8C8
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
*
OUT
OUT
ININ
ININ
p3v3_ipmi
***
***
*
*
GND
OUT
p3v3_ipmi
CO
N2P
2
1
*
*
GND
*
OUT
p3v3_ipmi
*
OUTOUTOUT
GND
*
*
*
*
*
GND
p3v3_ipmi
*
*
*
*
***
*
*
GND
LTC2924
FAULT_NDONE_N
VCC
PGT
GND
TMR HYS_CFG
ONOUT4OUT3OUT2OUT1
IN4IN3IN2IN1
GNDGND
p3v3_ipmi
IN
*
IN
RED
GREEN
REGROUP RES 'DNC' MMC_DC_DC_EN WITH RES 'DNC' FPGA_N_CONFIG (P25)
FIRST : MMC NOT CONNECTED ('DNC'ON MMC_DC_DC_EN)DC/DC ENABLE BY MMC OR EXTERNAL SWITCH
POWER SEQUENCING : DELAY~1MS FOR IN TO OUT;1MS OUT TURNED ONDETECTION ON DC/DC POWER GOOD SIGNALS : VON>=3V AND VOFF<2.7VOUT~8V=>VOUT ENABLE ~2V
ARRIA10 : VOLTAGE SEQUENCER
MODIFIE: Mon Mar 23 09:50:37 2015
SHEET: 4 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 4 / 27
240
240 10K
10K
10K
33
0000
10K
10K
10K
10K
DNC
4.7N
4.7N 49.9K
00
680K
330K
680K
0
0
330K
680K 100N
680K
330K
330K
R146R145R144
R132R130R128R126
J1
R17
R16
R24
R143C385
R140R139
R141R142
R138
R134
R136R135
R137R133R131R129R127
U32
C384C383
R125R124
D5R48
D6R49
2C6 4C6
4D6 8C1 8D4 2C3
5B6 2C3 6B6 8C4 7D3 2C3
2D6
2D6
5D8 6C7 8D8 7D3 8C1 8C8
POWER_SEQ_FAULT_N
MMC_DC_DC_EN POWER_SEQ_EN
POWER_SEQ_ENA10_G3_POWER_POK
A10_G1_VCC_POKA10_G1_POWER_POKA10_G2_POWER_POK
POWER_SEQ_DONE_N
A10_G1_VCC_ENA10_G1_POWER_ENA10_G2_POWER_ENA10_G3_POWER_EN
2
1
11
1412
8765
164321
15
13
910
21
21
*
OUT
OUT
ININ
ININ
p3v3_ipmi
***
***
*
*
GND
OUT
p3v3_ipmi
CO
N2P
2
1
*
*
GND
*
OUT
p3v3_ipmi
*
OUTOUTOUT
GND
*
*
*
*
*
GND
p3v3_ipmi
*
*
*
*
***
*
*
GND
LTC2924
FAULT_NDONE_N
VCC
PGT
GND
TMR HYS_CFG
ONOUT4OUT3OUT2OUT1
IN4IN3IN2IN1
GNDGND
p3v3_ipmi
IN
*
IN
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
DC/DC ARRIA10 : GROUP1->VCC
LOW LEAKAGE MOSFET <300NA
INH MAX=7 V ; INTERNAL PULL UP
SOFT START TIME ~2.8MS
GROUP1:VCC=0.95V@30A
MODIFIE: Mon Mar 23 09:50:37 2015
SHEET: 5 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 5 / 27
C341
1 T6
R56C347C346C345C344
R55R54
R51
R53
6860595857565554535210
152
13
61
3
14
1819
6966444342
712827262524232211
72706765646362515049484746414039383734331751
1667
9
U18C343C342
R52
61
U1743
U17
47U
0.001
100U
100U
100U
100U825
160
10N
4.7K
511 2.00K
47U
LMZ31530_VCC_INH
A10_VCC_M
A10_G1_VCC_POK
A10_G1_VCC_EN
PH_VCC
26C7
VCC=P3V3_IPMI
2C3 4C2
4D4
3D5
GND=GND
GND=GNDVCC=P3V3_IPMI
6B6
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
VP12
*
GN
D
GND
OUT
OUT
GND
SN74LVC2G06DCKR
1Y1A
p3v3_ipmi
a10_vcc
a10_vcc
test_pin
TEST
*
GND
SN74LVC2G06DCKR
2Y2A
**
GND
p3v3_ipmi
*
*
lmz31530
PGND
_22
PGND
_21
PGND
_20
PGND
_19
PGND
_18
PGND
_17
VOUT_10
SS_SELVOUT_9VOUT_8VOUT_7VOUT_6VOUT_5VOUT_4VOUT_3VOUT_2VOUT_1VOUT_0
VIN_1VIN_0
VADJ
V5V
SENSE+
PWRGD_PUPWRGD
PVIN_4PVIN_3PVIN_2PVIN_1PVIN_0
PH_8
PH_7
PH_6
PH_5
PH_4
PH_3
PH_2
PH_1
PH_0
PGND
_16
PGND
_15
PGND
_14
PGND
_13
PGND
_12
PGND
_11
PGND
_10
PGND
_9PG
ND_8
PGND
_7PG
ND_6
PGND
_5PG
ND_4
PGND
_3PG
ND_2
PGND
_1PG
ND_0
INHILIMFREQ_SEL
AGNDp3v3_ipmi
IN
DC/DC ARRIA10 : GROUP1->VCC
LOW LEAKAGE MOSFET <300NA
INH MAX=7 V ; INTERNAL PULL UP
SOFT START TIME ~2.8MS
GROUP1:VCC=0.95V@30A
MODIFIE: Mon Mar 23 09:50:37 2015
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47U
0.001
100U
100U
100U
100U825
160
10N
4.7K
511 2.00K
47U
VCC=P3V3_IPMI
GND=GND
GND=GNDVCC=P3V3_IPMI
C341
T6
R56C347C346C345C344
R55R54
R51
R53
U18C343C342
R52
U17
U17
26C7
2C3 4C2
4D4
3D5
6B6 LMZ31530_VCC_INH
A10_VCC_M
A10_G1_VCC_POK
A10_G1_VCC_EN
PH_VCC 1
6860595857565554535210
152
13
61
3
14
1819
6966444342
712827262524232211
72706765646362515049484746414039383734331751
1667
9
61
43
VP12
*
GN
D
GND
OUT
OUT
GND
SN74LVC2G06DCKR
1Y1A
p3v3_ipmi
a10_vcc
a10_vcc
test_pin
TEST
*
GND
SN74LVC2G06DCKR
2Y2A
**
GND
p3v3_ipmi
*
*
lmz31530
PGND
_22
PGND
_21
PGND
_20
PGND
_19
PGND
_18
PGND
_17
VOUT_10
SS_SELVOUT_9VOUT_8VOUT_7VOUT_6VOUT_5VOUT_4VOUT_3VOUT_2VOUT_1VOUT_0
VIN_1VIN_0
VADJ
V5V
SENSE+
PWRGD_PUPWRGD
PVIN_4PVIN_3PVIN_2PVIN_1PVIN_0
PH_8
PH_7
PH_6
PH_5
PH_4
PH_3
PH_2
PH_1
PH_0
PGND
_16
PGND
_15
PGND
_14
PGND
_13
PGND
_12
PGND
_11
PGND
_10
PGND
_9PG
ND_8
PGND
_7PG
ND_6
PGND
_5PG
ND_4
PGND
_3PG
ND_2
PGND
_1PG
ND_0
INHILIMFREQ_SEL
AGNDp3v3_ipmi
IN
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
GROUP1:VCCT_GXB=1.0V AND VCCR_GXB=1.0V (AT LEAST) FOR 11.3GBPS<DATA RATE<12.5GBPS
INH MAX=7 V ; INTERNAL PULL UP
SOFT START TIME ~2.8MS
LOW LEAKAGE MOSFET <300NA
DC/DC ARRIA10-GROUP1->VCCR,VCCT_GXB
VCCT_GXB AND VCCR_GXB MERGED : 1.0V@30A
MODIFIE: Mon Mar 23 09:50:37 2015
SHEET: 6 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 6 / 27
C516
1
T7
R185
C522C521C520C519
R184R183
R182
R181
C518C517
6860595857565554535210
152
13
61
3
14
1819
6966444342
712827262524232211
72706765646362515049484746414039383734331751
1667
9
U46
R180
43U45
61U45
47U
825
47U
100P
0.001
100U
100U
100U
100U
2.00K196
160
4.7K
LMZ31530_PWR_INH
A10_G1_POWER_EN
PH_PWR
A10_VCCT_VCCR_GXB_M
A10_G1_POWER_POK
GND=GND
VCC=P3V3_IPMI
8D8 4D4
4C2
3D5 26B8
8C4
GND=GND
VCC=P3V3_IPMI
5C6
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
GND
OUT
lmz31530
PGND
_22
PGND
_21
PGND
_20
PGND
_19
PGND
_18
PGND
_17
VOUT_10
SS_SELVOUT_9VOUT_8VOUT_7VOUT_6VOUT_5VOUT_4VOUT_3VOUT_2VOUT_1VOUT_0
VIN_1VIN_0
VADJ
V5V
SENSE+
PWRGD_PUPWRGD
PVIN_4PVIN_3PVIN_2PVIN_1PVIN_0
PH_8
PH_7
PH_6
PH_5
PH_4
PH_3
PH_2
PH_1
PH_0
PGND
_16
PGND
_15
PGND
_14
PGND
_13
PGND
_12
PGND
_11
PGND
_10
PGND
_9PG
ND_8
PGND
_7PG
ND_6
PGND
_5PG
ND_4
PGND
_3PG
ND_2
PGND
_1PG
ND_0
INHILIMFREQ_SEL
AGNDp3v3_ipmi
p3v3_ipmi
*
p3v3_ipmiSN74LVC2G06DCKR
2Y2A
GND
OUT
a10_vcct_vccr_gxb
test_pin
TEST
a10_vcct_vccr_gxb
*
SN74LVC2G06DCKR
1Y1A
GND**
GND
*
*
GN
D
VP12
IN
GROUP1:VCCT_GXB=1.0V AND VCCR_GXB=1.0V (AT LEAST) FOR 11.3GBPS<DATA RATE<12.5GBPS
INH MAX=7 V ; INTERNAL PULL UP
SOFT START TIME ~2.8MS
LOW LEAKAGE MOSFET <300NA
DC/DC ARRIA10-GROUP1->VCCR,VCCT_GXB
VCCT_GXB AND VCCR_GXB MERGED : 1.0V@30A
MODIFIE: Mon Mar 23 09:50:37 2015
SHEET: 6 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 6 / 27
47U
825
47U
100P
0.001
100U
100U
100U
100U
2.00K196
160
4.7K
GND=GND
VCC=P3V3_IPMI
GND=GND
VCC=P3V3_IPMI
C516 T7
R185
C522C521C520C519
R184R183
R182
R181
C518C517 U46
R180
U45
U458D8 4D4
4C2
3D5 26B8
8C4
5C6 LMZ31530_PWR_INH
A10_G1_POWER_EN
PH_PWR
A10_VCCT_VCCR_GXB_M
A10_G1_POWER_POK
1
6860595857565554535210
152
13
61
3
14
1819
6966444342
712827262524232211
72706765646362515049484746414039383734331751
1667
9
43
61
GND
OUT
lmz31530
PGND
_22
PGND
_21
PGND
_20
PGND
_19
PGND
_18
PGND
_17
VOUT_10
SS_SELVOUT_9VOUT_8VOUT_7VOUT_6VOUT_5VOUT_4VOUT_3VOUT_2VOUT_1VOUT_0
VIN_1VIN_0
VADJ
V5V
SENSE+
PWRGD_PUPWRGD
PVIN_4PVIN_3PVIN_2PVIN_1PVIN_0
PH_8
PH_7
PH_6
PH_5
PH_4
PH_3
PH_2
PH_1
PH_0
PGND
_16
PGND
_15
PGND
_14
PGND
_13
PGND
_12
PGND
_11
PGND
_10
PGND
_9PG
ND_8
PGND
_7PG
ND_6
PGND
_5PG
ND_4
PGND
_3PG
ND_2
PGND
_1PG
ND_0
INHILIMFREQ_SEL
AGNDp3v3_ipmi
p3v3_ipmi
*
p3v3_ipmiSN74LVC2G06DCKR
2Y2A
GND
OUT
a10_vcct_vccr_gxb
test_pin
TEST
a10_vcct_vccr_gxb
*
SN74LVC2G06DCKR
1Y1A
GND**
GND
*
*
GN
D
VP12
IN
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
DC/DC ARRIA10->GROUP2
EN2360QI & EN23F0QI : ENABLE CANNO'T BE ASSERTED BEFORE PVIN
FILTER 10A
GROUP2 : VCCPT,VCCH_GXB,VCCA_PLL=1.8V@15A
MODIFIE: Mon Mar 23 09:50:38 2015
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R178
R179C514
C515
C513
C509R177C508R176R175
C510
C511
C512
C504
C505
C506
C507
3534333231302928272625
76
67
78
7069
79
6362616059585756555453525150494847
7146454443424140
65
92 91 90 89 88 87 86 85 84 83
39383781
36
242322212019181716151413121110
987654321
7580 727782
66
68
64
7374
U44
R174
R173
R170
C503
R172
1 T8
R171
21FE1
4.87K
1.0U
0
22U
22U
100U
47U
47U
47U
200K
15K15P
0100K
0.001
22U
100N47
0N
1.0U
4.75K
86.6K
10N100K
A10_G2_POWER_M
A10_G2_POWER_EN
A10_G2_POWER_POK4D4
2C3 4C2
3D5
THERMAL_PAD=GND
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
a10_vccpt_vcch_gxb_vcca_pll
*
a10_vccpt_vcch_gxb_vcca_pll
a10_vccpt_vcch_gxb_vcca_pll
test_pin
TEST
*
OUT
IN
OUT*
*
GNDVP12
GND
GND
***GND
GND
Thermal pad in power group
en23f0qi
NC_2
5
BGNDVDDB
NC_S
W_1
2NC
_SW
_11
NC_S
W_1
0NC
_SW
_9NC
_SW
_8NC
_SW
_7NC
_SW
_6NC
_SW
_5NC
_SW
_4NC
_SW
_3CG
ND
FQAD
JRC
LX SSEA
INVF
BM
_SAG
NDAV
INEN
ABLE
POK
S_OUTS_IN
BTMPPG
AVINOPVIN_16PVIN_15PVIN_14PVIN_13PVIN_12PVIN_11PVIN_10
PVIN_9PVIN_8PVIN_7PVIN_6PVIN_5PVIN_4PVIN_3PVIN_2PVIN_1PVIN_0
PGND
_6PG
ND_5
PGND
_4PG
ND_3
PGND
_2PG
ND_1
PGND
_0NC
_SW
_2NC
_SW
_1NC
_SW
_0NC
_24
VOUT
_10
VOUT
_9VO
UT_8
VOUT
_7VO
UT_6
VOUT
_5VO
UT_4
VOUT
_3VO
UT_2
VOUT
_1VO
UT_0
NC_23NC_22NC_21NC_20NC_19NC_18NC_17NC_16NC_15NC_14NC_13NC_12NC_11NC_10NC_9NC_8NC_7NC_6NC_5NC_4NC_3NC_2NC_1NC_0
*
*
*
a10_vcch_vcca_pll
DC/DC ARRIA10->GROUP2
EN2360QI & EN23F0QI : ENABLE CANNO'T BE ASSERTED BEFORE PVIN
FILTER 10A
GROUP2 : VCCPT,VCCH_GXB,VCCA_PLL=1.8V@15A
MODIFIE: Mon Mar 23 09:50:38 2015
SHEET: 7 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 7 / 27
4.87K
1.0U
0
22U
22U
100U
47U
47U
47U
200K
15K15P
0100K
0.001
22U
100N47
0N
1.0U
4.75K
86.6K
10N100K
THERMAL_PAD=GND
R178
R179C514
C515
C513
C509R177C508R176R175
C510
C511
C512
C504
C505
C506
C507
U44
R174
R173
R170
C503
R172
T8
R171
FE1
4D4
2C3 4C2
3D5
A10_G2_POWER_M
A10_G2_POWER_EN
A10_G2_POWER_POK
3534333231302928272625
76
67
78
7069
79
6362616059585756555453525150494847
7146454443424140
65
92 91 90 89 88 87 86 85 84 83
39383781
36
242322212019181716151413121110
987654321
7580 727782
66
68
64
7374
1
21
a10_vccpt_vcch_gxb_vcca_pll
*
a10_vccpt_vcch_gxb_vcca_pll
a10_vccpt_vcch_gxb_vcca_pll
test_pin
TEST
*
OUT
IN
OUT*
*
GNDVP12
GND
GND
***GND
GND
Thermal pad in power group
en23f0qi
NC_2
5
BGNDVDDB
NC_S
W_1
2NC
_SW
_11
NC_S
W_1
0NC
_SW
_9NC
_SW
_8NC
_SW
_7NC
_SW
_6NC
_SW
_5NC
_SW
_4NC
_SW
_3CG
ND
FQAD
JRC
LX SSEA
INVF
BM
_SAG
NDAV
INEN
ABLE
POK
S_OUTS_IN
BTMPPG
AVINOPVIN_16PVIN_15PVIN_14PVIN_13PVIN_12PVIN_11PVIN_10
PVIN_9PVIN_8PVIN_7PVIN_6PVIN_5PVIN_4PVIN_3PVIN_2PVIN_1PVIN_0
PGND
_6PG
ND_5
PGND
_4PG
ND_3
PGND
_2PG
ND_1
PGND
_0NC
_SW
_2NC
_SW
_1NC
_SW
_0NC
_24
VOUT
_10
VOUT
_9VO
UT_8
VOUT
_7VO
UT_6
VOUT
_5VO
UT_4
VOUT
_3VO
UT_2
VOUT
_1VO
UT_0
NC_23NC_22NC_21NC_20NC_19NC_18NC_17NC_16NC_15NC_14NC_13NC_12NC_11NC_10NC_9NC_8NC_7NC_6NC_5NC_4NC_3NC_2NC_1NC_0
*
*
*
a10_vcch_vcca_pll
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
OTHERS POWER SUPPLY : 3.3V [NB:UPOD~1.6A]GROUP 3:VCCPGM=1.8V ; VCCIO [1.8V-1.5V]
EN2360QI & EN23F0QI : ENABLE CANNO'T BE ASSERTED BEFORE PVIN
DC/DC FOR OTHER POWER SUPPLIESDC/DC ARRIA10 GROUP3 AND VCCRAM
OTHER POWER SUPPLY : 2.5V@6A [NB:UPOD~3.6A]
GROUP 1:VCC_RAM=0.95V
MODIFIE: Mon Mar 23 09:50:38 2015
SHEET: 8 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 8 / 27
1
T13
R35
R34
C190
C189
C186
R33
R32
C188
C182R31R30
C187C183
C184
C185
242322212019181716
54
45
56
4847
57
41403938373635
49343332313029
43
63 62 61
2827
68 67 66 65 64 59
262515
1413121110
987654321
58 505560
44
46
42
5153 52 U13
R25
R28
R29C181
C373 R106
R107
R108
C377
C374
C378
C379
C375
R105
R104
R97
R100
R101
R102
R103
C369
C370
C371
C372
R109
C380
C376
R27R26
R98
R99
J1K2K1
G2G1F1
D2D1C1
A3A2A1
L4L3
H4H3
E4E3
B4B3
K6
G6
D6
A6
F3
L5
H5
E5
B5
F7K7
J6
F6
C6
J2
F2
C2
C3
L6
H6
E6
B6
K5
J4
F4
C4
J7
G7
D7
A7
L7
H7
E7
B7
J3C7
U29
1 T9
1 T10
1 T11
1 T12
P1V8
P1V5
P1V8
P1V5
10U
10U
4.75K
22U
13.3K
2.2N3.57K
1.0U
56K
0
560
47N
1.0U
220N
47U
47U
100U
47U
0
2.2N
2.2N
0
22U
22U
12K
200K
12P
100K10K
10N
100K
0.001
47U
2.2N
0
0.001
0.001
063.4K
0.001
0.001
0
47U
40.2K
47U
30.1K
A10_G3_POWER_POKA10_G3_POWER_EN
A10_G1_POWER_EN
A10_G3_POWER_EN
P2V5_M
P1V8_M
P1V5_M
A10_VCC_RAM_M
P3V3_M
A10_G1_POWER_POK
A10_G3_POWER_POK
4C2 2C3 8D4
4C4 8C8
3D5
6B6 4C2
3D5
8C1 2C3 4C2
3D5
4D4 6C7
4C4 8C1
THERMAL_PAD=GND
3D5
3D5
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
test_pin
TEST
OUT
OUT
OUT
OUT
OUT
P2V5
test_pin
TEST
OUT
IN
*
*
GND
test_pin
TEST
GND
*
*
VP12
**
GND
GND
Thermal pad in power group
en2360qi
NC_1
7
NC_2
2NC
_21
NC_2
0NC
_19
NC_1
8NC
_SW
_4NC
_SW
_3NC
_SW
_2CG
ND
FQAD
JRC
LX SSEA
INVF
BAG
ND_1
AGND
_0AV
INEN
ABLE
POK
S_OUTS_IN
BGNDVDDBBTMP
PGAVINO
PVIN_6PVIN_5PVIN_4PVIN_3PVIN_2PVIN_1PVIN_0
PGND
_5PG
ND_4
PGND
_3PG
ND_2
PGND
_1PG
ND_0
NC_S
W_1
NC_S
W_0
NC_1
6NC
_15
VOUT
_8VO
UT_7
VOUT
_6VO
UT_5
VOUT
_4VO
UT_3
VOUT
_2VO
UT_1
VOUT
_0NC
_14
NC_13NC_12NC_11NC_10NC_9NC_8NC_7NC_6NC_5NC_4NC_3NC_2NC_1NC_0
*
P2V5
*
*
a10_vcc_ram
OUT
a10_vcc_ram
*
*
*
test_pin
TEST
*
*
*
*
*
*
*
P3V3
VP12
IN
OUTP3V3
*
GND
test_pin
TEST**
GND
*
*
GND
GND in power group
LTM4644
SGND
TEM
P
CLKO
UT
CLKI
N
INTVCC4
INTVCC3
INTVCC2
INTVCC1
FB4
FB3
FB2
FB1
RUN4
RUN3
RUN2
RUN1
PGOOD4
PGOOD3
PGOOD2
PGOOD1
COMP4
COMP3
COMP2
COMP1
MODE4
MODE3
MODE2
MODE1
SVIN4
SVIN3
SVIN2
SVIN1
VIN4_1VIN4_0
VIN3_1VIN3_0
VIN2_1VIN2_0
VIN1_1VIN1_0
TRACK_SS4
TRACK_SS3
TRACK_SS2
TRACK_SS1
VOUT4_2VOUT4_1VOUT4_0
VOUT3_2VOUT3_1VOUT3_0
VOUT2_2VOUT2_1VOUT2_0
VOUT1_2VOUT1_1VOUT1_0
IN
GND
OTHERS POWER SUPPLY : 3.3V [NB:UPOD~1.6A]GROUP 3:VCCPGM=1.8V ; VCCIO [1.8V-1.5V]
EN2360QI & EN23F0QI : ENABLE CANNO'T BE ASSERTED BEFORE PVIN
DC/DC FOR OTHER POWER SUPPLIESDC/DC ARRIA10 GROUP3 AND VCCRAM
OTHER POWER SUPPLY : 2.5V@6A [NB:UPOD~3.6A]
GROUP 1:VCC_RAM=0.95V
MODIFIE: Mon Mar 23 09:50:38 2015
SHEET: 8 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 8 / 27
P1V8
P1V5
P1V8
P1V5
10U
10U
4.75K
22U
13.3K
2.2N3.57K
1.0U
56K
0
560
47N
1.0U
220N
47U
47U
100U
47U
0
2.2N
2.2N
0
22U
22U
12K
200K
12P
100K10K
10N
100K
0.001
47U
2.2N
0
0.001
0.001
063.4K
0.001
0.001
0
47U
40.2K
47U
30.1K
THERMAL_PAD=GND
T13
R35
R34
C190
C189
C186
R33
R32
C188
C182R31R30
C187C183
C184
C185
U13
R25
R28
R29C181
C373 R106
R107
R108
C377
C374
C378
C379
C375
R105
R104
R97
R100
R101
R102
R103
C369
C370
C371
C372
R109
C380
C376
R27R26
R98
R99
U29
T9
T10
T11
T12
4C2 2C3 8D4
4C4 8C8
3D5
6B6 4C2
3D5
8C1 2C3 4C2
3D5
4D4 6C7
4C4 8C1
3D5
3D5
A10_G3_POWER_POKA10_G3_POWER_EN
A10_G1_POWER_EN
A10_G3_POWER_EN
P2V5_M
P1V8_M
P1V5_M
A10_VCC_RAM_M
P3V3_M
A10_G1_POWER_POK
A10_G3_POWER_POK
1
242322212019181716
54
45
56
4847
57
41403938373635
49343332313029
43
63 62 61
2827
68 67 66 65 64 59
262515
1413121110
987654321
58 505560
44
46
42
5153 52
J1K2K1
G2G1F1
D2D1C1
A3A2A1
L4L3
H4H3
E4E3
B4B3
K6
G6
D6
A6
F3
L5
H5
E5
B5
F7K7
J6
F6
C6
J2
F2
C2
C3
L6
H6
E6
B6
K5
J4
F4
C4
J7
G7
D7
A7
L7
H7
E7
B7
J3C7
1
1
1
1
test_pin
TEST
OUT
OUT
OUT
OUT
OUT
P2V5
test_pin
TEST
OUT
IN
*
*
GND
test_pin
TEST
GND
*
*
VP12
**
GND
GND
Thermal pad in power group
en2360qi
NC_1
7
NC_2
2NC
_21
NC_2
0NC
_19
NC_1
8NC
_SW
_4NC
_SW
_3NC
_SW
_2CG
ND
FQAD
JRC
LX SSEA
INVF
BAG
ND_1
AGND
_0AV
INEN
ABLE
POK
S_OUTS_IN
BGNDVDDBBTMP
PGAVINO
PVIN_6PVIN_5PVIN_4PVIN_3PVIN_2PVIN_1PVIN_0
PGND
_5PG
ND_4
PGND
_3PG
ND_2
PGND
_1PG
ND_0
NC_S
W_1
NC_S
W_0
NC_1
6NC
_15
VOUT
_8VO
UT_7
VOUT
_6VO
UT_5
VOUT
_4VO
UT_3
VOUT
_2VO
UT_1
VOUT
_0NC
_14
NC_13NC_12NC_11NC_10NC_9NC_8NC_7NC_6NC_5NC_4NC_3NC_2NC_1NC_0
*
P2V5
*
*
a10_vcc_ram
OUT
a10_vcc_ram
*
*
*
test_pin
TEST
*
*
*
*
*
*
*
P3V3
VP12
IN
OUTP3V3
*
GND
test_pin
TEST**
GND
*
*
GND
GND in power group
LTM4644
SGND
TEM
P
CLKO
UT
CLKI
N
INTVCC4
INTVCC3
INTVCC2
INTVCC1
FB4
FB3
FB2
FB1
RUN4
RUN3
RUN2
RUN1
PGOOD4
PGOOD3
PGOOD2
PGOOD1
COMP4
COMP3
COMP2
COMP1
MODE4
MODE3
MODE2
MODE1
SVIN4
SVIN3
SVIN2
SVIN1
VIN4_1VIN4_0
VIN3_1VIN3_0
VIN2_1VIN2_0
VIN1_1VIN1_0
TRACK_SS4
TRACK_SS3
TRACK_SS2
TRACK_SS1
VOUT4_2VOUT4_1VOUT4_0
VOUT3_2VOUT3_1VOUT3_0
VOUT2_2VOUT2_1VOUT2_0
VOUT1_2VOUT1_1VOUT1_0
IN
GND
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
DDR3 2GBITS : A13 CONNECTEDDDR3 1GBITS : A13 NOT CONNECTED
ARRIA10 CONNECTIONS : BANK ON TOP [3G,3H,2L,2K]
MEMORIES : DDR3
MODIFIE: Mon Mar 23 09:50:39 2015
SHEET: 9 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 9 / 27
C142
C141
C144
C143 C145
C146 C148
C147 C149
C150 C152
C151
C154 C156
C153 C155
C158
C157 C159 C160
C180C179C177
C178
C175C173
C176C174
L8
L3
H1M8
C7B7
D3
T2
J3
K1
F3G3E7
L2
K9J7K7
K3
T3N7R7L7
U12
C171C169
C172C170
C167C165
C168C166
C163C161
C164C162
R22
R20
R23
1 T14
L8
L3
H1M8
C7B7
D3
T2
J3
K1
F3G3E7
L2
K9J7K7
K3
T3N7R7L7
U11
R21
532
10
619
4 8
7U10
R18
C138R19
C140C139C137C136C135
P1V5
P1V5
P1V5
P1V5
P1V5
P1V5
10U
10U
1.0U
1.0U
100N
1.0N10K
10K
100N
100N
100
100N
100N
1.0U
100N
100N
100N
1.0U
1.0U
1.0U
240
1.0U
100N
100N
100N
100N
100N
1.0U
100N
1.0U
100N
100
100N
100N
100N
1.0U
240
1.0U
1.0U
1.0U
1.0U
1.0U
1.0U
100N
100N
100N
100N
100N
1.0U
1.0U
100N
100N
DDR3_0_ZQDDR3_0_ODTDDR3_0_RESETNDDR3_0_BA<2..0>DDR3_0_CASN
DDR3_0_WENDDR3_0_RASN
DDR3_0_CSN
DDR3_0_CKEDDR3_0_A<13>DDR3_0_A<12>
DDR3_0_CKP
DDR3_0_A<11>
DDR3_1_RASNDDR3_1_CASNDDR3_1_BA<2..0>
DDR3_1_RESETNDDR3_1_ODTDDR3_1_ZQ
DDR3_0_DQS1_NDDR3_0_DQS1_PDDR3_0_DQS0_NDDR3_0_DQS0_P
DDR3_0_DQ<15..0>
DDR3_1_A<10>DDR3_1_A<9..0>
DDR3_1_A<11>DDR3_1_A<12>DDR3_1_A<13>DDR3_1_CKE
DDR3_1_DM0
DDR3_1_WENDDR3_1_CSNDDR3_1_DM1
DDR3_1_CKNDDR3_1_CKP
DDR3_1_DQ<15..0>
DDR3_1_DQS1_NDDR3_1_DQS1_PDDR3_1_DQS0_NDDR3_1_DQS0_P
DDR3_0_CKNDDR3_0_DM0DDR3_0_DM1
DDR3_0_A<10>DDR3_0_A<9..0>
THERMAL_PAD=GND
21A4 21A1
21B4 21B1
21B1
21A1 21B1
21B4
21B4
18B4 21B4
21B1
18B7
22B4 22B2
22B4 22B2 22A2 22B2
21B5 21B5 18B4 18B4
21B7 21B5 21A7 21A5 18B8
18A7 22B4 22B2 18A4
18A7 22B4 18A4
22B4
22B5
22A2 22A4
18A7
22B2
22B2
22C8 22C5 22B8 22B5 18A8 18A4
22B5 22B5 22B5 22B5
21B1
18B7 21A5
18B7 21B4 21B1 18B4
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
VTT_REF
GND
GND
GND
mt41jxxm16
BA[2..0]
A[9..0]
DQ[15..0]
VSSQ[8..0]VDDQ[8..0]VSS[11..0]VDD[8..0]
A13/NC
ZQ
VREFDQVREFCA
UDQS_NUDQS_PLDQS_NLDQS_P
UDM
RESETN
WEN
CASNRASN
ODT
LDM
CSN
CKE
CK_NCK_P
A12/BCNA11A10/AP
VTT_REF
*
*
*
GND
GND
GND
VTT_REF
P2V5
VTT
GND
VTT_REF
GND
test_pin
TEST
mt41jxxm16
BA[2..0]
A[9..0]
DQ[15..0]
VSSQ[8..0]VDDQ[8..0]VSS[11..0]VDD[8..0]
A13/NC
ZQ
VREFDQVREFCA
UDQS_NUDQS_PLDQS_NLDQS_P
UDM
RESETN
WEN
CASNRASN
ODT
LDM
CSN
CKE
CK_NCK_P
A12/BCNA11A10/AP
VTT_REF
VTT
*
GND
tps51200
VINPGOOD
GND
EN
REFOUT
VOSNSPGND
VOVLDOINREFIN
P2V5
GND
VTT_REF
GND
*
ININ
ININ
ININININININ
IN
IN IN
ININININININ
IN*
IN IN
INININININ
INININ
GND
ININ
IN
IN
BIBI
BIBI
BI
VTT_REF
BI
BI
BI
BI
BI
GND
P2V5
GND
DDR3 2GBITS : A13 CONNECTEDDDR3 1GBITS : A13 NOT CONNECTED
ARRIA10 CONNECTIONS : BANK ON TOP [3G,3H,2L,2K]
MEMORIES : DDR3
MODIFIE: Mon Mar 23 09:50:39 2015
SHEET: 9 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 9 / 27
P1V5
P1V5
P1V5
P1V5
P1V5
P1V5
10U
10U
1.0U
1.0U
100N
1.0N10K
10K
100N
100N
100
100N
100N
1.0U
100N
100N
100N
1.0U
1.0U
1.0U
240
1.0U
100N
100N
100N
100N
100N
1.0U
100N
1.0U
100N
100
100N
100N
100N
1.0U
240
1.0U
1.0U
1.0U
1.0U
1.0U
1.0U
100N
100N
100N
100N
100N
1.0U
1.0U
100N
100N
THERMAL_PAD=GND
C142
C141
C144
C143 C145
C146 C148
C147 C149
C150 C152
C151
C154 C156
C153 C155
C158
C157 C159 C160
C180C179C177
C178
C175C173
C176C174
U12
C171C169
C172C170
C167C165
C168C166
C163C161
C164C162
R22
R20
R23
T14
U11
R21
U10R18
C138R19
C140C139C137C136C135
21A4 21A1
21B4 21B1
21B1
21A1 21B1
21B4
21B4
18B4 21B4
21B1
18B7
22B4 22B2
22B4 22B2 22A2 22B2
21B5 21B5 18B4 18B4
21B7 21B5 21A7 21A5 18B8
18A7 22B4 22B2 18A4
18A7 22B4 18A4
22B4
22B5
22A2 22A4
18A7
22B2
22B2
22C8 22C5 22B8 22B5 18A8 18A4
22B5 22B5 22B5 22B5
21B1
18B7 21A5
18B7 21B4 21B1 18B4
DDR3_0_ZQDDR3_0_ODTDDR3_0_RESETNDDR3_0_BA<2..0>DDR3_0_CASN
DDR3_0_WENDDR3_0_RASN
DDR3_0_CSN
DDR3_0_CKEDDR3_0_A<13>DDR3_0_A<12>
DDR3_0_CKP
DDR3_0_A<11>
DDR3_1_RASNDDR3_1_CASNDDR3_1_BA<2..0>
DDR3_1_RESETNDDR3_1_ODTDDR3_1_ZQ
DDR3_0_DQS1_NDDR3_0_DQS1_PDDR3_0_DQS0_NDDR3_0_DQS0_P
DDR3_0_DQ<15..0>
DDR3_1_A<10>DDR3_1_A<9..0>
DDR3_1_A<11>DDR3_1_A<12>DDR3_1_A<13>DDR3_1_CKE
DDR3_1_DM0
DDR3_1_WENDDR3_1_CSNDDR3_1_DM1
DDR3_1_CKNDDR3_1_CKP
DDR3_1_DQ<15..0>
DDR3_1_DQS1_NDDR3_1_DQS1_PDDR3_1_DQS0_NDDR3_1_DQS0_P
DDR3_0_CKNDDR3_0_DM0DDR3_0_DM1
DDR3_0_A<10>DDR3_0_A<9..0>
L8
L3
H1M8
C7B7
D3
T2
J3
K1
F3G3E7
L2
K9J7K7
K3
T3N7R7L7
1
L8
L3
H1M8
C7B7
D3
T2
J3
K1
F3G3E7
L2
K9J7K7
K3
T3N7R7L7
532
10
619
4 8
7VTT_REF
GND
GND
GND
mt41jxxm16
BA[2..0]
A[9..0]
DQ[15..0]
VSSQ[8..0]VDDQ[8..0]VSS[11..0]VDD[8..0]
A13/NC
ZQ
VREFDQVREFCA
UDQS_NUDQS_PLDQS_NLDQS_P
UDM
RESETN
WEN
CASNRASN
ODT
LDM
CSN
CKE
CK_NCK_P
A12/BCNA11A10/AP
VTT_REF
*
*
*
GND
GND
GND
VTT_REF
P2V5
VTT
GND
VTT_REF
GND
test_pin
TEST
mt41jxxm16
BA[2..0]
A[9..0]
DQ[15..0]
VSSQ[8..0]VDDQ[8..0]VSS[11..0]VDD[8..0]
A13/NC
ZQ
VREFDQVREFCA
UDQS_NUDQS_PLDQS_NLDQS_P
UDM
RESETN
WEN
CASNRASN
ODT
LDM
CSN
CKE
CK_NCK_P
A12/BCNA11A10/AP
VTT_REF
VTT
*
GND
tps51200
VINPGOOD
GND
EN
REFOUT
VOSNSPGND
VOVLDOINREFIN
P2V5
GND
VTT_REF
GND
*
ININ
ININ
ININININININ
IN
IN IN
ININININININ
IN*
IN IN
INININININ
INININ
GND
ININ
IN
IN
BIBI
BIBI
BI
VTT_REF
BI
BI
BI
BI
BI
GND
P2V5
GND
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
156.25MHZ REF CLOCK FOR XAUI GXB
100MHZ CLOCK FOR SYSTEM CLOCK
100MHZ CLOCK FOR TRANSCEIVER CALIBRATION
R=PARALLEL EQUIVALENT RESISTANCE1/(2XPIXRC)~500MHZ VOLTAGE DIVIDER FOR 1.5V APPLICATION
RISE TIME=800PS MAX => ARRIA10 REF CLK RISE TIME=250PS MAX !!!AC COUPLING ON REF CLOCK
100MHZ CLOCK FOR DDR3_1
CHANGE 69.8 BY 33 AND REMOVE 374
C=ARRIA10 INPUT CAPACITANCE (5PF FOR CALCUL)R=PARALLEL EQUIVALENT RESISTANCE
1/(2XPIXRC)~500MHZ VOLTAGE DIVIDER FOR 1.5V APPLICATION
C=ARRIA10 INPUT CAPACITANCE (5PF FOR CALCUL)
IF 1.5V OSCILLATOR FOUNDCHANGE 69.8 BY 33 AND REMOVE 374
STANDARD CLOCKS
100MHZ CLOCK FOR DDR3_0
AC COUPLING ON REF CLOCK100/125MHZ REF CLOCK FOR PCIE/1GBE GXB
IF 1.5V OSCILLATOR FOUND
MODIFIE: Mon Mar 23 09:50:39 2015
SHEET: 10 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 10 / 27
R11
R94
1 2
3U6C132
R10
R8C131 4
1 2
3U7
621
354
U2
C127
621
354
U3
C128
R193
R1924
1 2
3U4
C129
4
1 2
3
U5C130
P1V8
P1V8
P1V8 P1V8
P1V8P1V8
P1V8
P1V8
1.0N
69.8
374
100N
69.810N
100N
100N
33
100N
33
374
XAUI_REF_CLK_NXAUI_REF_CLK_P
PCIE_1GBE_REF_CLK_PPCIE_1GBE_REF_CLK_N
SYS_CLK
DDR3_0_CLK
CLKUSR
DDR3_1_CLK
CLK
CLK
18C8
20B8 20B8
19B8 19B8
18B8
21D4
18A8
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
GND
OUT
*
*
GND
si501CLK
OE GND
VDD
GND
GND
OUT
*
GND
*
si501CLK
OE GND
VDD
GND
GND
si501CLK
OE GND
VDD
OUTOUT
OUT
GND
OUT
P2V5
si510_6pins
CLK+CLK-
GND
VDDNCOE
GNDGND
P2V5
P2V5
si510_6pins
CLK+CLK-
GND
VDDNCOE
GND
P2V5
OUT
OUT*
GND
GND
*
si501CLK
OE GND
VDD
GND
156.25MHZ REF CLOCK FOR XAUI GXB
100MHZ CLOCK FOR SYSTEM CLOCK
100MHZ CLOCK FOR TRANSCEIVER CALIBRATION
R=PARALLEL EQUIVALENT RESISTANCE1/(2XPIXRC)~500MHZ VOLTAGE DIVIDER FOR 1.5V APPLICATION
RISE TIME=800PS MAX => ARRIA10 REF CLK RISE TIME=250PS MAX !!!AC COUPLING ON REF CLOCK
100MHZ CLOCK FOR DDR3_1
CHANGE 69.8 BY 33 AND REMOVE 374
C=ARRIA10 INPUT CAPACITANCE (5PF FOR CALCUL)R=PARALLEL EQUIVALENT RESISTANCE
1/(2XPIXRC)~500MHZ VOLTAGE DIVIDER FOR 1.5V APPLICATION
C=ARRIA10 INPUT CAPACITANCE (5PF FOR CALCUL)
IF 1.5V OSCILLATOR FOUNDCHANGE 69.8 BY 33 AND REMOVE 374
STANDARD CLOCKS
100MHZ CLOCK FOR DDR3_0
AC COUPLING ON REF CLOCK100/125MHZ REF CLOCK FOR PCIE/1GBE GXB
IF 1.5V OSCILLATOR FOUND
MODIFIE: Mon Mar 23 09:50:39 2015
SHEET: 10 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 10 / 27
P1V8
P1V8
P1V8 P1V8
P1V8P1V8
P1V8
P1V8
1.0N
69.8
374
100N
69.810N
100N
100N
33
100N
33
374
CLK
CLK
R11
R9U6C132
R10
R8C131
U7
U2
C127
U3
C128
R193
R192U4C129
U5C130
18C8
20B8 20B8
19B8 19B8
18B8
21D4
18A8
XAUI_REF_CLK_NXAUI_REF_CLK_P
PCIE_1GBE_REF_CLK_PPCIE_1GBE_REF_CLK_N
SYS_CLK
DDR3_0_CLK
CLKUSR
DDR3_1_CLK
4
1 2
3
4
1 2
3
621
354
621
354
4
1 2
3
4
1 2
3
GND
OUT
*
*
GND
si501CLK
OE GND
VDD
GND
GND
OUT
*
GND
*
si501CLK
OE GND
VDD
GND
GND
si501CLK
OE GND
VDD
OUTOUT
OUT
GND
OUT
P2V5
si510_6pins
CLK+CLK-
GND
VDDNCOE
GNDGND
P2V5
P2V5
si510_6pins
CLK+CLK-
GND
VDDNCOE
GND
P2V5
OUT
OUT*
GND
GND
*
si501CLK
OE GND
VDD
GND
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
VDDO=2.5V=>1.1<VOCM<1.350.247<VOD<0.454 (SINGLE ENDED OUTPUT SWING)RISE TIME=350PS MAX
SI535(7X5MM)=> COULD BE REPLACED BY SI530 FOR MORE FREQUENCY CHOICE
TTC CLOCKS
1.125<VOCM<1.275;0.5<VOD<0.9
CLK_SEL:INTERNAL PULL DOWN
MODIFIE: Mon Mar 23 09:50:44 2015
SHEET: 11 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 11 / 27
C445
C444C435
C443
C433
C434
C442
C446C427C426
C428C437
C438
C439C440
C441
C429
C430
C432
C431
C436
R156
R157
17
34
44
12
3231
23
25242726302936353837
414043425487109
18
16
2811
21
13
3922
6
33
1
23
1920
1415
U39
621
354
U38
C425
TTC_REF_CLK3_CN TTC_REF_CLK3_NTTC_REF_CLK3_PTTC_REF_CLK3_CP
TTC_REF_CLK2_CNTTC_REF_CLK2_CPTTC_REF_CLK0_CNTTC_REF_CLK0_CP
TTC_CORE_CLK_N
TTC_REF_CLK8_CNTTC_REF_CLK7_CPTTC_REF_CLK7_CNTTC_REF_CLK5_CP
100N
TTC_CORE_CLK_P
100N
100N
100N
100N
100N
100N
1.0U
100
100
TTC_REF_CLK4_P
TTC_CLK_SEL
LOCAL_TTC_CLK_NLOCAL_TTC_CLK_P
GND_PAD=GND
19C8 19B4
20C8
20D4
25D8
11E6
11E6
11C7 11C7
23C6 25C8
23C6
25C8
20C8
19E8
20B4
19B4
20C4
19D4
20B4
19D8
19E8
19D4 20D4
20C4
100N
100N
AMC_TTC_CLK_LOSAMC_TTC_CLK_N
AMC_TTC_CLK_P
LOCAL_TTC_CLK_LOSLOCAL_TTC_CLK_N
LOCAL_TTC_CLK_P
100N100N
1.0U
TTC_REF_CLK4_CP
100N
100N
100N
100N
100N
TTC_REF_CLK2_NTTC_REF_CLK2_P
I77I78
I79100NI75
18C8 18C8
100NI82
TTC_REF_CLK0_PI76100N TTC_REF_CLK0_NI74100N 20E8
20E8
TTC_REF_CLK6_CN
TTC_REF_CLK4_N
TTC_REF_CLK7_PTTC_REF_CLK7_N
TTC_REF_CLK6_N
TTC_REF_CLK8_N
TTC_REF_CLK6_P
TTC_REF_CLK8_P
TTC_REF_CLK6_CP
TTC_REF_CLK1_CNTTC_REF_CLK1_CP
TTC_REF_CLK5_N
TTC_REF_CLK1_NTTC_REF_CLK1_P
TTC_REF_CLK5_PTTC_REF_CLK5_CN
TTC_REF_CLK8_CPTTC_REF_CLK4_CN
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
IN
OUTOUT
OUT
OUTOUT
OUT
OUT
OUT
OUT
OUTOUTOUT
OUTOUT
OUTOUT
P2V5
OUTOUTOUTOUTOUTOUT
GND
P2V5
GND
si535
CLK+CLK-VDD
GNDOENC
P2V5
GND
P2V5
P2V
5
GN
D
P2V5
OUTOUT
GND
GND
P2V5
P2V
5
GN
D
*
*
si53302
GND_2GND_1GND_0
NC_1NC_0
VDDOA
Q3_PQ3_N
Q4_PQ4_N
Q5_PQ5_N
Q6_PQ6_N
VDDOBDIVB
SFOUTA1SFOUTA0
SFOUTB1SFOUTB0
Q7_PQ7_N
Q8_NQ8_P
Q9_PQ9_N
CLK_SEL
LOS1CLK1_NCLK1_P OEB
VREF
OEA
CLK0_NCLK0_P
LOS0
VDD
Q0_PQ0_N
Q1_PQ1_N
Q2_PQ2_N
DIVA
GND
IN
IN
IN
IN
VDDO=2.5V=>1.1<VOCM<1.350.247<VOD<0.454 (SINGLE ENDED OUTPUT SWING)RISE TIME=350PS MAX
SI535(7X5MM)=> COULD BE REPLACED BY SI530 FOR MORE FREQUENCY CHOICE
TTC CLOCKS
1.125<VOCM<1.275;0.5<VOD<0.9
CLK_SEL:INTERNAL PULL DOWN
MODIFIE: Mon Mar 23 09:50:44 2015
SHEET: 11 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 11 / 27
100N
100N
100N
100N
100N
100N
100N
1.0U
100
100
GND_PAD=GND
100N
100N
100N100N
1.0U
100N
100N
100N
100N
100N
I77I78
I79100NI75
100NI82
I76100NI74100N
C445
C444C435
C443
C433
C434
C442
C446C427C426
C428C437
C438
C439C440
C441
C429
C430
C432
C431
C436
R156
R157
U39
U38
C425
19C8 19B4
20C8
20D4
25D8
11E6
11E6
11C7 11C7
23C6 25C8
23C6
25C8
20C8
19E8
20B4
19B4
20C4
19D4
20B4
19D8
19E8
19D4 20D4
20C4
18C8 18C8
20E8 20E8
TTC_REF_CLK3_CN TTC_REF_CLK3_NTTC_REF_CLK3_PTTC_REF_CLK3_CP
TTC_REF_CLK2_CNTTC_REF_CLK2_CPTTC_REF_CLK0_CNTTC_REF_CLK0_CP
TTC_CORE_CLK_N
TTC_REF_CLK8_CNTTC_REF_CLK7_CPTTC_REF_CLK7_CNTTC_REF_CLK5_CP
TTC_CORE_CLK_P
TTC_REF_CLK4_P
TTC_CLK_SEL
LOCAL_TTC_CLK_NLOCAL_TTC_CLK_P
AMC_TTC_CLK_LOSAMC_TTC_CLK_N
AMC_TTC_CLK_P
LOCAL_TTC_CLK_LOSLOCAL_TTC_CLK_N
LOCAL_TTC_CLK_P
TTC_REF_CLK4_CP
TTC_REF_CLK2_NTTC_REF_CLK2_P
TTC_REF_CLK0_PTTC_REF_CLK0_N
TTC_REF_CLK6_CN
TTC_REF_CLK4_N
TTC_REF_CLK7_PTTC_REF_CLK7_N
TTC_REF_CLK6_N
TTC_REF_CLK8_N
TTC_REF_CLK6_P
TTC_REF_CLK8_P
TTC_REF_CLK6_CP
TTC_REF_CLK1_CNTTC_REF_CLK1_CP
TTC_REF_CLK5_N
TTC_REF_CLK1_NTTC_REF_CLK1_P
TTC_REF_CLK5_PTTC_REF_CLK5_CN
TTC_REF_CLK8_CPTTC_REF_CLK4_CN
17
34
44
12
3231
23
25242726302936353837
414043425487109
18
16
2811
21
13
3922
6
33
1
23
1920
1415
621
354
IN
OUTOUT
OUT
OUTOUT
OUT
OUT
OUT
OUT
OUTOUTOUT
OUTOUT
OUTOUT
P2V5
OUTOUTOUTOUTOUTOUT
GND
P2V5
GND
si535
CLK+CLK-VDD
GNDOENC
P2V5
GND
P2V5
P2V
5
GN
D
P2V5
OUTOUT
GND
GND
P2V5
P2V
5
GN
D
*
*
si53302
GND_2GND_1GND_0
NC_1NC_0
VDDOA
Q3_PQ3_N
Q4_PQ4_N
Q5_PQ5_N
Q6_PQ6_N
VDDOBDIVB
SFOUTA1SFOUTA0
SFOUTB1SFOUTB0
Q7_PQ7_N
Q8_NQ8_P
Q9_PQ9_N
CLK_SEL
LOS1CLK1_NCLK1_P OEB
VREF
OEA
CLK0_NCLK0_P
LOS0
VDD
Q0_PQ0_N
Q1_PQ1_N
Q2_PQ2_N
DIVA
GND
IN
IN
IN
IN
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
UPOD_TX_L1
UPOD_RX_L1
UPOD_RX_L0
RESETN:INTERNAL PULL UPI2C_ADD=0X34
I2C_ADD=0X35
I2C ADD=0X29
UPOD_TX_L0
I2C ADD=0X28
MICRO PODS [ ARRIA10 LEFT SIDE ]
MODIFIE: Mon Mar 23 09:50:40 2015
SHEET: 12 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 12 / 27
L11
C541 C543
R209
C544C542
L12
R210
C124
C123
C121C108
L9
C106
R207
C122C109
L10
C107
R208
C489
L3
C487
R164
C485
C490
L4
C488
R165
C486
R147
C392C393C390C391
R148
D6
D4
E6
E4
F4F5D5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
U33
C401C400C399C398
D6
D4
E6
E4
F4F5D5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
U34
C397
C388C389C386C387
C483
C484
L1
C481C479
R162
C482
L2
C480
C453C454
R158
C452C451C449C450C447C448
C396C395C394
R163
C462C461
R159
C460C459C458C457C456C455
D6
D4
E6
E4
F4D5F5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
U40
D6
D4
E6
E4
F4D5F5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
U41
0.5
22U
4.7U
13E3
RX_UPOD_L0_P<0>RX_UPOD_L0_N<0>RX_UPOD_L0_P<1>RX_UPOD_L0_N<1>RX_UPOD_L0_P<2>
RX_UPOD_L0_P<3>RX_UPOD_L0_N<3>RX_UPOD_L0_P<4>
4.7U4.7U RX_UPOD_L0_N<10>RX_UPOD_L0_P<10>RX_UPOD_L0_N<9>RX_UPOD_L0_P<9>RX_UPOD_L0_N<8>RX_UPOD_L0_P<8>RX_UPOD_L0_N<7>
13C3 12E3
13C3 12E3 12E3
4.7K25B4
14E8 14E8
14E8
14E8 14E8 14E8
14E8 14E8
14E8 14E8 14E8 14E8 14E8
14D8
14D8
14D8 14D8 14D8
14D8
14D8
14D8 14D8 14D8
14D8
RX_UPOD_L0_INTN
RX_UPOD_L0_P<11>
RX_UPOD_L0_N<2>
RX_UPOD_L0_N<4>RX_UPOD_L0_P<5>RX_UPOD_L0_N<5>RX_UPOD_L0_P<6>RX_UPOD_L0_N<6>RX_UPOD_L0_P<7>
RX_UPOD_L0_N<11>
RX_UPOD_SDARX_UPOD_SCLRX_UPOD_SDARX_UPOD_SCL
RX_UPOD_RESETN
12B3 12C3
25E8
12C3 12E3
1.0U
100N
1.0U
100N
1.0U
100N
1.0U
100N
12E3 13C3
12C3
13B3 25A4
13C3
13C3 13E3
13E3 25A4
22U
100N
4.7U
100N22
U0.5
TX_UPOD_L0_P<6>
TX_UPOD_L0_N<7>TX_UPOD_L0_P<8>TX_UPOD_L0_N<8>TX_UPOD_L0_P<9>TX_UPOD_L0_N<9>TX_UPOD_L0_P<10>TX_UPOD_L0_N<10>
RX_UPOD_L1_P<8>RX_UPOD_L1_N<8>RX_UPOD_L1_P<9>RX_UPOD_L1_N<9>RX_UPOD_L1_P<10>RX_UPOD_L1_N<10>RX_UPOD_L1_P<11>RX_UPOD_L1_N<11>
RX_UPOD_L1_INTNRX_UPOD_SDARX_UPOD_SCL
RX_UPOD_RESETN25E8 13E3
4.7K
14D8 14D8 14D8
25B4
14D8
14D8 14D8 14D8 14D8
14C8 14C8 14C8 14C8 14C8 14C8 14C8
14C8 14C8 14C8 14C8
14C8
14C8 14C8 14C8
14C8
RX_UPOD_L1_N<4>RX_UPOD_L1_P<5>RX_UPOD_L1_N<5>
RX_UPOD_L1_P<4>
RX_UPOD_L1_P<2>RX_UPOD_L1_N<2>RX_UPOD_L1_P<3>RX_UPOD_L1_N<3>
RX_UPOD_L1_N<1>
RX_UPOD_L1_P<0>RX_UPOD_L1_N<0>RX_UPOD_L1_P<1>
RX_UPOD_L1_P<6>RX_UPOD_L1_N<6>RX_UPOD_L1_P<7>RX_UPOD_L1_N<7>
RX_UPOD_SCLRX_UPOD_SDA12C3
12C3
100N
1.0U
100N
1.0U
1.0U
1.0U
100N
100N
13B3 13E3 13C3
25A4 13E3 25A4
4.7U
100N22U
0.5
4.7U
22U
100N
0.5
0.5
1.0U
100N
1.0U
100N
100N
4.7U
4.7K25A4
22U
100N
1.0U
100N
100N
4.7U
22U
100N
0.5
TX_UPOD_L1_INTNTX_UPOD_RESETN12E7 13C7 13E7 25E8
1.0U
100N
TX_UPOD_L1_P<2>
TX_UPOD_L1_P<3>
TX_UPOD_L1_P<4>
TX_UPOD_SDATX_UPOD_SCL
TX_UPOD_SCLTX_UPOD_SDA
TX_UPOD_L1_P<8>TX_UPOD_L1_N<8>
TX_UPOD_L1_N<7>TX_UPOD_L1_P<7>TX_UPOD_L1_N<6>TX_UPOD_L1_P<6>TX_UPOD_L1_N<5>
TX_UPOD_L1_N<4>TX_UPOD_L1_P<5>
TX_UPOD_L1_P<0>TX_UPOD_L1_N<0>TX_UPOD_L1_P<1>TX_UPOD_L1_N<1>
TX_UPOD_L1_N<2>
TX_UPOD_L1_N<3>
TX_UPOD_L1_N<10>TX_UPOD_L1_P<11>TX_UPOD_L1_N<11>
TX_UPOD_L1_P<10>TX_UPOD_L1_N<9>TX_UPOD_L1_P<9>
12B7 12B7
12E7 12E7
14D3
14D3 14D3 14D3
14C3
14C3
14C3
14D3
14C3
14D3
14D3
14C3 14C3
14C3 14C3 14C3 14C3
14C3 14C3
14C3 14C3
14C3 14C3 14C3
13B7 13B7 25B4
25B4 13E7 13E7
TX_UPOD_L0_INTN4.7K
25A4
100N
100N
100N
0.5
1.0U
1.0U
100N
100N
1.0U
22U
100N
0.5
100N
TX_UPOD_SDATX_UPOD_SCL
TX_UPOD_SCLTX_UPOD_SDA
TX_UPOD_RESETN25E8
12B7 12B7
12E7 12E7
1.0U
100N
TX_UPOD_L0_P<7>
TX_UPOD_L0_P<4>
TX_UPOD_L0_P<0>
TX_UPOD_L0_N<11>TX_UPOD_L0_P<11>
TX_UPOD_L0_N<0>TX_UPOD_L0_P<1>TX_UPOD_L0_N<1>
TX_UPOD_L0_N<6>
TX_UPOD_L0_N<2>TX_UPOD_L0_P<2>
TX_UPOD_L0_N<5>TX_UPOD_L0_P<5>TX_UPOD_L0_N<4>
TX_UPOD_L0_N<3>TX_UPOD_L0_P<3>
14E3
14E3
14E3
14E3
14E3
14E3
14D3
14E3
14D3
14D3
14D3
14E3 14E3
14E3 14E3 14E3
14D3
14D3 14D3 14D3 14D3
14D3 14D3 14D3
13B7 13B7
12C7 13E7
25B4 13E7
13C7
25B4 13E7
100N
100N
100N
100N
25A4 13E3
12C3 12B3
12E3 12C3 12E3
13C3 13B3 13E3
13C3 25A4
13E3 25A4
12C3 12E3 13C3 13E3 12B3 25A4 13B3 12E3 13C3
12B7 12B7
12E7 12E7
13B7 13B7 13E7
13E7 25B4 25B4
12B7 12B7 12E7
12E7 13B7 13B7
25B4 13E7 25B4 13E7
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
*
GND
p3v3_left_tx1
ININ
*
OUT
GND
p3v3_left_tx1
IN
GND
p2v5_left_tx1
afbr_77d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]VCC25[3..0]
VCC33[3..0]
RESETL
DIN11-
DIN10-
DIN9-
DIN8-
DIN7-
DIN6-
DIN5-
DIN4-
DIN3-
DIN2-
DIN1-
DIN0-
DIN11+
DIN10+
DIN9+
DIN8+
DIN7+
DIN6+
DIN5+
DIN4+
DIN3+
DIN2+
DIN1+
DIN0+
ADDR2ADDR1ADDR0
GND
afbr_77d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]VCC25[3..0]
VCC33[3..0]
RESETL
DIN11-
DIN10-
DIN9-
DIN8-
DIN7-
DIN6-
DIN5-
DIN4-
DIN3-
DIN2-
DIN1-
DIN0-
DIN11+
DIN10+
DIN9+
DIN8+
DIN7+
DIN6+
DIN5+
DIN4+
DIN3+
DIN2+
DIN1+
DIN0+
ADDR2ADDR1ADDR0
IN
BI
IN
BI
ININ
GND
ININININININ
IN
ININININININININININ
IN
ININININININ
p2v5_left_tx0p3v3_left_tx0
IN
BI
IN
BI
p3v3_left_tx1
IN
p3v3_left_rx1P3V3
*
p2v5_left_rx1
IN
GND
GND
*
P2V5
p3v3_left_rx0
IN
P3V3
*
GND
p2v5_left_rx0P2V5
IN
*
GND
p2v5_left_tx1
p3v3_left_tx1P3V3
*
IN
GND
P2V5
*
GND
IN
p3v3_left_rx0
*
OUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
GND
p2v5_left_tx1
OUTOUTOUTOUTOUTOUT
OUT
p3v3_left_rx0
IN
p3v3_left_rx0
p3v3_left_rx1
*
OUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUT
OUT
IN
GND
afbr_78d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]
VCC25[3..0]VCC33[3..0]
RESETL
DOUT11-
DOUT10-
DOUT9-
DOUT8-
DOUT7-
DOUT6-
DOUT5-
DOUT4-
DOUT3-
DOUT2-
DOUT1-
DOUT0-
DOUT11+
DOUT10+
DOUT9+
DOUT8+
DOUT7+
DOUT6+
DOUT5+
DOUT4+
DOUT3+
DOUT2+
DOUT1+
DOUT0+
ADDR2ADDR1ADDR0
p3v3_left_rx1
GND
GND
afbr_78d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]
VCC25[3..0]VCC33[3..0]
RESETL
DOUT11-
DOUT10-
DOUT9-
DOUT8-
DOUT7-
DOUT6-
DOUT5-
DOUT4-
DOUT3-
DOUT2-
DOUT1-
DOUT0-
DOUT11+
DOUT10+
DOUT9+
DOUT8+
DOUT7+
DOUT6+
DOUT5+
DOUT4+
DOUT3+
DOUT2+
DOUT1+
DOUT0+
ADDR2ADDR1ADDR0
IN
p3v3_left_rx1
p2v5_left_rx0
p2v5_left_rx1
IN
BIBI
GND
p3v3_left_rx0
IN
p2v5_left_rx0
GND
p3v3_left_tx0
p2v5_left_tx0
p3v3_left_tx0
IN
P3V3
*
GND
P2V5
IN
*
OUT
p3v3_left_tx0
GND
IN
p2v5_left_tx0
IN
BI
p3v3_left_rx1BI
GND
p2v5_left_rx1
IN
p3v3_left_tx1
UPOD_TX_L1
UPOD_RX_L1
UPOD_RX_L0
RESETN:INTERNAL PULL UPI2C_ADD=0X34
I2C_ADD=0X35
I2C ADD=0X29
UPOD_TX_L0
I2C ADD=0X28
MICRO PODS [ ARRIA10 LEFT SIDE ]
MODIFIE: Mon Mar 23 09:50:40 2015
SHEET: 12 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 12 / 27
0.5
22U
4.7U
4.7U4.7U
4.7K
1.0U
100N
1.0U
100N
1.0U
100N
1.0U
100N
22U
100N
4.7U
100N22
U0.5
4.7K
100N
1.0U
100N
1.0U
1.0U
1.0U
100N
100N
4.7U
100N22U
0.5
4.7U
22U
100N
0.5
0.5
1.0U
100N
1.0U
100N
100N
4.7U
4.7K
22U
100N
1.0U
100N
100N
4.7U
22U
100N
0.5
1.0U
100N
4.7K
100N
100N
100N
0.5
1.0U
1.0U
100N
100N
1.0U
22U
100N
0.5
100N
1.0U
100N
100N
100N
100N
100N
L11
C541 C543
R209
C544C542
L12
R210
C124
C123
C121C108
L9
C106
R207
C122C109
L10
C107
R208
C489
L3
C487
R164
C485
C490
L4
C488
R165
C486
R147
C392C393C390C391
R148
U33
C401C400C399C398
U34
C397
C388C389C386C387
C483
C484
L1
C481C479
R162
C482
L2
C480
C453C454
R158
C452C451C449C450C447C448
C396C395C394
R163
C462C461
R159
C460C459C458C457C456C455
U40
U41
13E3
13C3 12E3
13C3 12E3 12E3
25B4
14E8 14E8
14E8
14E8 14E8 14E8
14E8 14E8
14E8 14E8 14E8 14E8 14E8
14D8
14D8
14D8 14D8 14D8
14D8
14D8
14D8 14D8 14D8
14D8
12B3 12C3
25E8
12C3 12E3
12E3 13C3
12C3
13B3 25A4
13C3
13C3 13E3
13E3 25A4
25E8 13E3
14D8 14D8 14D8
25B4
14D8
14D8 14D8 14D8 14D8
14C8 14C8 14C8 14C8 14C8 14C8 14C8
14C8 14C8 14C8 14C8
14C8
14C8 14C8 14C8
14C8
12C3 12C3 13B3
13E3 13C3
25A4 13E3 25A4
25A4
12E7 13C7 13E7 25E8
12B7 12B7
12E7 12E7
14D3
14D3 14D3 14D3
14C3
14C3
14C3
14D3
14C3
14D3
14D3
14C3 14C3
14C3 14C3 14C3 14C3
14C3 14C3
14C3 14C3
14C3 14C3 14C3
13B7 13B7 25B4
25B4 13E7 13E7
25A4
25E8
12B7 12B7
12E7 12E7
14E3
14E3
14E3
14E3
14E3
14E3
14D3
14E3
14D3
14D3
14D3
14E3 14E3
14E3 14E3 14E3
14D3
14D3 14D3 14D3 14D3
14D3 14D3 14D3
13B7 13B7
12C7 13E7
25B4 13E7
13C7
25B4 13E7
25A4 13E3
12C3 12B3
12E3 12C3 12E3
13C3 13B3 13E3
13C3 25A4
13E3 25A4
12C3 12E3 13C3 13E3 12B3 25A4 13B3 12E3 13C3
12B7 12B7
12E7 12E7
13B7 13B7 13E7
13E7 25B4 25B4
12B7 12B7 12E7
12E7 13B7 13B7
25B4 13E7 25B4 13E7
RX_UPOD_L0_P<0>RX_UPOD_L0_N<0>RX_UPOD_L0_P<1>RX_UPOD_L0_N<1>RX_UPOD_L0_P<2>
RX_UPOD_L0_P<3>RX_UPOD_L0_N<3>RX_UPOD_L0_P<4>
RX_UPOD_L0_N<10>RX_UPOD_L0_P<10>RX_UPOD_L0_N<9>RX_UPOD_L0_P<9>RX_UPOD_L0_N<8>RX_UPOD_L0_P<8>RX_UPOD_L0_N<7>
RX_UPOD_L0_INTN
RX_UPOD_L0_P<11>
RX_UPOD_L0_N<2>
RX_UPOD_L0_N<4>RX_UPOD_L0_P<5>RX_UPOD_L0_N<5>RX_UPOD_L0_P<6>RX_UPOD_L0_N<6>RX_UPOD_L0_P<7>
RX_UPOD_L0_N<11>
RX_UPOD_SDARX_UPOD_SCLRX_UPOD_SDARX_UPOD_SCL
RX_UPOD_RESETN
TX_UPOD_L0_P<6>
TX_UPOD_L0_N<7>TX_UPOD_L0_P<8>TX_UPOD_L0_N<8>TX_UPOD_L0_P<9>TX_UPOD_L0_N<9>TX_UPOD_L0_P<10>TX_UPOD_L0_N<10>
RX_UPOD_L1_P<8>RX_UPOD_L1_N<8>RX_UPOD_L1_P<9>RX_UPOD_L1_N<9>RX_UPOD_L1_P<10>RX_UPOD_L1_N<10>RX_UPOD_L1_P<11>RX_UPOD_L1_N<11>
RX_UPOD_L1_INTNRX_UPOD_SDARX_UPOD_SCL
RX_UPOD_RESETN
RX_UPOD_L1_N<4>RX_UPOD_L1_P<5>RX_UPOD_L1_N<5>
RX_UPOD_L1_P<4>
RX_UPOD_L1_P<2>RX_UPOD_L1_N<2>RX_UPOD_L1_P<3>RX_UPOD_L1_N<3>
RX_UPOD_L1_N<1>
RX_UPOD_L1_P<0>RX_UPOD_L1_N<0>RX_UPOD_L1_P<1>
RX_UPOD_L1_P<6>RX_UPOD_L1_N<6>RX_UPOD_L1_P<7>RX_UPOD_L1_N<7>
RX_UPOD_SCLRX_UPOD_SDATX_UPOD_L1_INTN
TX_UPOD_RESETN
TX_UPOD_L1_P<2>
TX_UPOD_L1_P<3>
TX_UPOD_L1_P<4>
TX_UPOD_SDATX_UPOD_SCL
TX_UPOD_SCLTX_UPOD_SDA
TX_UPOD_L1_P<8>TX_UPOD_L1_N<8>
TX_UPOD_L1_N<7>TX_UPOD_L1_P<7>TX_UPOD_L1_N<6>TX_UPOD_L1_P<6>TX_UPOD_L1_N<5>
TX_UPOD_L1_N<4>TX_UPOD_L1_P<5>
TX_UPOD_L1_P<0>TX_UPOD_L1_N<0>TX_UPOD_L1_P<1>TX_UPOD_L1_N<1>
TX_UPOD_L1_N<2>
TX_UPOD_L1_N<3>
TX_UPOD_L1_N<10>TX_UPOD_L1_P<11>TX_UPOD_L1_N<11>
TX_UPOD_L1_P<10>TX_UPOD_L1_N<9>TX_UPOD_L1_P<9>
TX_UPOD_L0_INTN
TX_UPOD_SDATX_UPOD_SCL
TX_UPOD_SCLTX_UPOD_SDA
TX_UPOD_RESETN
TX_UPOD_L0_P<7>
TX_UPOD_L0_P<4>
TX_UPOD_L0_P<0>
TX_UPOD_L0_N<11>TX_UPOD_L0_P<11>
TX_UPOD_L0_N<0>TX_UPOD_L0_P<1>TX_UPOD_L0_N<1>
TX_UPOD_L0_N<6>
TX_UPOD_L0_N<2>TX_UPOD_L0_P<2>
TX_UPOD_L0_N<5>TX_UPOD_L0_P<5>TX_UPOD_L0_N<4>
TX_UPOD_L0_N<3>TX_UPOD_L0_P<3>
D6
D4
E6
E4
F4F5D5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
D6
D4
E6
E4
F4F5D5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
D6
D4
E6
E4
F4D5F5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
D6
D4
E6
E4
F4D5F5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
*
GND
p3v3_left_tx1
ININ
*
OUT
GND
p3v3_left_tx1
IN
GND
p2v5_left_tx1
afbr_77d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]VCC25[3..0]
VCC33[3..0]
RESETL
DIN11-
DIN10-
DIN9-
DIN8-
DIN7-
DIN6-
DIN5-
DIN4-
DIN3-
DIN2-
DIN1-
DIN0-
DIN11+
DIN10+
DIN9+
DIN8+
DIN7+
DIN6+
DIN5+
DIN4+
DIN3+
DIN2+
DIN1+
DIN0+
ADDR2ADDR1ADDR0
GND
afbr_77d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]VCC25[3..0]
VCC33[3..0]
RESETL
DIN11-
DIN10-
DIN9-
DIN8-
DIN7-
DIN6-
DIN5-
DIN4-
DIN3-
DIN2-
DIN1-
DIN0-
DIN11+
DIN10+
DIN9+
DIN8+
DIN7+
DIN6+
DIN5+
DIN4+
DIN3+
DIN2+
DIN1+
DIN0+
ADDR2ADDR1ADDR0
IN
BI
IN
BI
ININ
GND
ININININININ
IN
ININININININININININ
IN
ININININININ
p2v5_left_tx0p3v3_left_tx0
IN
BI
IN
BI
p3v3_left_tx1
IN
p3v3_left_rx1P3V3
*
p2v5_left_rx1
IN
GND
GND
*
P2V5
p3v3_left_rx0
IN
P3V3
*
GND
p2v5_left_rx0P2V5
IN
*
GND
p2v5_left_tx1
p3v3_left_tx1P3V3
*
IN
GND
P2V5
*
GND
IN
p3v3_left_rx0
*
OUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
GND
p2v5_left_tx1
OUTOUTOUTOUTOUTOUT
OUT
p3v3_left_rx0
IN
p3v3_left_rx0
p3v3_left_rx1
*
OUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUT
OUT
IN
GND
afbr_78d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]
VCC25[3..0]VCC33[3..0]
RESETL
DOUT11-
DOUT10-
DOUT9-
DOUT8-
DOUT7-
DOUT6-
DOUT5-
DOUT4-
DOUT3-
DOUT2-
DOUT1-
DOUT0-
DOUT11+
DOUT10+
DOUT9+
DOUT8+
DOUT7+
DOUT6+
DOUT5+
DOUT4+
DOUT3+
DOUT2+
DOUT1+
DOUT0+
ADDR2ADDR1ADDR0
p3v3_left_rx1
GND
GND
afbr_78d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]
VCC25[3..0]VCC33[3..0]
RESETL
DOUT11-
DOUT10-
DOUT9-
DOUT8-
DOUT7-
DOUT6-
DOUT5-
DOUT4-
DOUT3-
DOUT2-
DOUT1-
DOUT0-
DOUT11+
DOUT10+
DOUT9+
DOUT8+
DOUT7+
DOUT6+
DOUT5+
DOUT4+
DOUT3+
DOUT2+
DOUT1+
DOUT0+
ADDR2ADDR1ADDR0
IN
p3v3_left_rx1
p2v5_left_rx0
p2v5_left_rx1
IN
BIBI
GND
p3v3_left_rx0
IN
p2v5_left_rx0
GND
p3v3_left_tx0
p2v5_left_tx0
p3v3_left_tx0
IN
P3V3
*
GND
P2V5
IN
*
OUT
p3v3_left_tx0
GND
IN
p2v5_left_tx0
IN
BI
p3v3_left_rx1BI
GND
p2v5_left_rx1
IN
p3v3_left_tx1
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
I2C ADD=0X37
MICRO PODS [ ARRIA10 RIGHT SIDE ]
I2C ADD=0X2A
I2C ADD=0X2B
INDUCTANCE>4A
I2C ADD=0X36UPOD_TX_R0
UPOD_TX_R1
UPOD_RX_R1
UPOD_RX_R0
MODIFIE: Mon Mar 23 09:50:44 2015
SHEET: 13 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 13 / 27
C555C553
L15
C551
C556
R213
L16
C554
R214
C552
C546
R212
L14
C548 C550
C545
R211
L13
C547 C549
C495C493
L5
C491
R166
C496C494
L6
C492
R167
L7
C499 C501
R168
C502C500
L8
R169
C498
C497
R149
C409C408C407C406C405C404C403C402
R150
D6
D4
E6
E4
F4F5D5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
U35
C417C416C415C414C413C412C411C410
D6
D4
E6
E4
F4F5D5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
U36
C470
R160
C469C468C467C466C465C464C463
R161
C478C477C476C475C474C473C472C471
D6
D4
E6
E4
F4D5F5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
U42
D6
D4
E6
E4
F4D5F5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
U43
14B8 14A8 14A8
14B8
14B8
14B8 14B8
14B8
14B8 14B8
14B8 14B8
14B8 14B8
14B8
14B8
14B8
14B8 14B8
14C8 14C8 14B8 14B8 14B8
100N
100N
25B4 25B4
13E7 13E7
13B7
14E1
12C7 12E7
14E1 14E1
14D1 14D1
14E1
14E1 14E1
14E1
14E1 14D1
14E1
14D1
14D1
14E1
25E8
12E7
14E1
12E7
14E1
14E1
14D1 14D1 14D1 14D1
14D1 14D1
TX_UPOD_R0_N<8>
TX_UPOD_R0_N<9>
TX_UPOD_R0_P<11>
TX_UPOD_R0_N<7>TX_UPOD_R0_P<7>
TX_UPOD_R0_P<8>
TX_UPOD_R0_N<11>
TX_UPOD_R0_N<10>
TX_UPOD_R0_P<9>
TX_UPOD_R0_N<6>
12B7 12B7
TX_UPOD_R0_N<5>
TX_UPOD_R0_P<2>TX_UPOD_R0_N<2>TX_UPOD_R0_P<3>TX_UPOD_R0_N<3>TX_UPOD_R0_P<4>TX_UPOD_R0_N<4>TX_UPOD_R0_P<5>
TX_UPOD_R0_P<6>
TX_UPOD_R0_N<1>
TX_UPOD_R0_N<0>TX_UPOD_R0_P<0>
TX_UPOD_R0_P<1>
TX_UPOD_SDATX_UPOD_RESETN
100N
1.0U
100N
1.0U
100N
0.5
4.7U
22U
100N
1.0U
100N
100N
1.0U
25A4
0.5
100N
4.7U
22U
4.7K
13C7
13B7 TX_UPOD_SCLTX_UPOD_SDATX_UPOD_SCL
14C1
14C1
14C1 14C1 14C1 14C1 14C1 14C1
14C1
14C1 14C1 14C1 14C1 14C1 14C1
TX_UPOD_R1_N<7>
TX_UPOD_R1_N<8>
TX_UPOD_R1_N<11>TX_UPOD_R1_P<11>TX_UPOD_R1_N<10>
TX_UPOD_R1_N<9>TX_UPOD_R1_P<9>
TX_UPOD_R1_P<8>
100N
1.0U
100N
1.0U
14C1
14D1 14D1
12C7 12E7 13E7
13B7
25E8
12E7
14C1
14D1
14D1
14D1
14D1
12B7 TX_UPOD_SCL
TX_UPOD_R1_INTN
100N
1.0U
100N
1.0U
100N
0.5
100N22
U
4.7U
4.7K25A4
100N
0.5
22U
100N
4.7U
TX_UPOD_R1_P<10>
TX_UPOD_R0_P<10>
0.5
22U
4.7U
100N
RX_UPOD_R1_N<6>RX_UPOD_R1_P<7>
RX_UPOD_R1_P<6>RX_UPOD_R1_N<5>
RX_UPOD_R1_P<9>RX_UPOD_R1_N<9>
RX_UPOD_R1_N<8>
RX_UPOD_R1_N<7>RX_UPOD_R1_P<8>
RX_UPOD_R1_N<11>RX_UPOD_R1_P<11>
RX_UPOD_R1_P<10>RX_UPOD_R1_N<10>
14A8 14A8 14A8
14A8 14A8
14A8 14A8
14A8
14A8 14A8
14A8 14A8
14A8
0.5
100N
1.0U
100N
1.0U
100N
1.0U
14A8
22U
4.7U
25A4 25A4 13E3
100N
13E3 13C3 12E3
13C3 12C3 12E3
13E3 25E8 12C3 12E3
12B3 12C3 RX_UPOD_SDA
RX_UPOD_SCL
RX_UPOD_SCLRX_UPOD_SDA
RX_UPOD_RESETN
RX_UPOD_R1_N<2>RX_UPOD_R1_P<2>RX_UPOD_R1_N<1>RX_UPOD_R1_P<1>
RX_UPOD_R1_P<0>RX_UPOD_R1_N<0>
RX_UPOD_R1_N<4>RX_UPOD_R1_P<4>RX_UPOD_R1_N<3>RX_UPOD_R1_P<3>
RX_UPOD_R1_P<5>
RX_UPOD_R1_INTN4.7K
25C4
14A8 14A8 14A8 14A8 14A8 14A8
14A8 14A8
14A8 14A8
100N
1.0U
0.5
100N 22U
4.7U
100N
100N
0.5
22U
4.7U
100N
100N
12E3 12C3 13B3 13C3 25A4 13E3
13C3
25A4
12E3
13E3
12C3
13C3
25E8
12E3 12C3 12B3
1.0U
100N
1.0U
100N
1.0U
100N
1.0U
RX_UPOD_SCL
RX_UPOD_RESETNRX_UPOD_SDA
RX_UPOD_SDARX_UPOD_SCL
RX_UPOD_R0_P<2>
RX_UPOD_R0_P<0>RX_UPOD_R0_N<0>RX_UPOD_R0_P<1>RX_UPOD_R0_N<1>
RX_UPOD_R0_N<2>RX_UPOD_R0_P<3>RX_UPOD_R0_N<3>
RX_UPOD_R0_N<11>
RX_UPOD_R0_P<4>
RX_UPOD_R0_N<6>RX_UPOD_R0_P<6>
RX_UPOD_R0_N<4>RX_UPOD_R0_P<5>RX_UPOD_R0_N<5>
RX_UPOD_R0_N<9>
RX_UPOD_R0_N<8>RX_UPOD_R0_P<9>
RX_UPOD_R0_P<8>
RX_UPOD_R0_P<7>RX_UPOD_R0_N<7>
RX_UPOD_R0_P<11>
RX_UPOD_R0_P<10>RX_UPOD_R0_N<10>
RX_UPOD_R0_INTN4.7K
25C4
100N
TX_UPOD_R0_INTN
TX_UPOD_R1_N<5>
TX_UPOD_R1_P<7>TX_UPOD_R1_N<6>TX_UPOD_R1_P<6>
TX_UPOD_R1_P<5>TX_UPOD_R1_N<4>TX_UPOD_R1_P<4>TX_UPOD_R1_N<3>TX_UPOD_R1_P<3>TX_UPOD_R1_N<2>TX_UPOD_R1_P<2>TX_UPOD_R1_N<1>TX_UPOD_R1_P<1>TX_UPOD_R1_N<0>TX_UPOD_R1_P<0>
TX_UPOD_SCLTX_UPOD_SDA
TX_UPOD_RESETN
TX_UPOD_SDA
14D1
25B4 12B7 12E7 13B7 13E7 13E7 25B4
25B4 25B4 13E7
13B7 13E7 13B7
12B7 12E7 12B7
25B4 25B4
13B7 13E7 13B7 13E7
12E7 12E7
25A4 13E3 25A4 13E3
13B3 13C3 12E3
12C3 12E3 12B3 12C3
13E3 25A4 25A4 13C3
13E3 13B3 12E3
13C3 12C3 12B3 12E3 12C3
12E7
12B7 12B7
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
INININ
INININININ
GND
IN
IN
p3v3_right_tx1
GND
GND
*
OUT
IN
p3v3_right_tx1p2v5_right_tx1
IN
GND
IN
GND
afbr_77d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]VCC25[3..0]
VCC33[3..0]
RESETL
DIN11-
DIN10-
DIN9-
DIN8-
DIN7-
DIN6-
DIN5-
DIN4-
DIN3-
DIN2-
DIN1-
DIN0-
DIN11+
DIN10+
DIN9+
DIN8+
DIN7+
DIN6+
DIN5+
DIN4+
DIN3+
DIN2+
DIN1+
DIN0+
ADDR2ADDR1ADDR0
IN
ININININ
ININ
IN
INININININ
p2v5_right_tx0p3v3_right_tx0
IN
BIBI
IN
p3v3_right_tx1
p3v3_right_rx1P3V3
p2v5_right_rx1
IN
*
GND
P2V5
*
GND
P2V5
IN
*
GND
p2v5_right_rx0
P3V3
*
GND
GND
p3v3_right_rx0
p3v3_right_tx0
p2v5_right_tx0
p2v5_right_tx1
p3v3_right_tx1
IN
P3V3
*
GND
P2V5
IN
*
GND
*
IN
GND
GND
*
P2V5
P3V3
IN
p3v3_right_rx0
*
OUT
OUTOUTOUTOUTOUTOUTOUT
IN
OUTOUT
OUTOUTOUT
OUTOUT
IN
BIBI
afbr_77d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]VCC25[3..0]
VCC33[3..0]
RESETL
DIN11-
DIN10-
DIN9-
DIN8-
DIN7-
DIN6-
DIN5-
DIN4-
DIN3-
DIN2-
DIN1-
DIN0-
DIN11+
DIN10+
DIN9+
DIN8+
DIN7+
DIN6+
DIN5+
DIN4+
DIN3+
DIN2+
DIN1+
DIN0+
ADDR2ADDR1ADDR0
p2v5_right_tx1
GND
p3v3_right_rx0
p3v3_right_rx0
p2v5_right_rx0
IN
p3v3_right_rx1
OUTOUTOUT
OUTOUT
OUTOUT
IN
OUTOUTOUT
GND
*
OUT
OUTOUT
OUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUT
OUT
INOUT
OUTOUTOUT
OUTOUT
OUTOUTOUTOUT
IN
GND
afbr_78d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]
VCC25[3..0]VCC33[3..0]
RESETL
DOUT11-
DOUT10-
DOUT9-
DOUT8-
DOUT7-
DOUT6-
DOUT5-
DOUT4-
DOUT3-
DOUT2-
DOUT1-
DOUT0-
DOUT11+
DOUT10+
DOUT9+
DOUT8+
DOUT7+
DOUT6+
DOUT5+
DOUT4+
DOUT3+
DOUT2+
DOUT1+
DOUT0+
ADDR2ADDR1ADDR0
p3v3_right_rx0p2v5_right_rx0
GND
IN
BI
p3v3_right_rx1BI
IN
p3v3_right_rx1p2v5_right_rx1
afbr_78d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]
VCC25[3..0]VCC33[3..0]
RESETL
DOUT11-
DOUT10-
DOUT9-
DOUT8-
DOUT7-
DOUT6-
DOUT5-
DOUT4-
DOUT3-
DOUT2-
DOUT1-
DOUT0-
DOUT11+
DOUT10+
DOUT9+
DOUT8+
DOUT7+
DOUT6+
DOUT5+
DOUT4+
DOUT3+
DOUT2+
DOUT1+
DOUT0+
ADDR2ADDR1ADDR0
IN
p3v3_right_rx1p2v5_right_rx1
GNDIN
p3v3_right_tx0
*
OUT
p3v3_right_tx0
IN
p2v5_right_tx0
IN
BIBI
p3v3_right_tx0
INININ
IN
IN
p3v3_right_tx1
I2C ADD=0X37
MICRO PODS [ ARRIA10 RIGHT SIDE ]
I2C ADD=0X2A
I2C ADD=0X2B
INDUCTANCE>4A
I2C ADD=0X36UPOD_TX_R0
UPOD_TX_R1
UPOD_RX_R1
UPOD_RX_R0
MODIFIE: Mon Mar 23 09:50:44 2015
SHEET: 13 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 13 / 27
100N
100N
100N
1.0U
100N
1.0U
100N
0.5
4.7U
22U
100N
1.0U
100N
100N
1.0U
0.5
100N
4.7U
22U
4.7K
100N
1.0U
100N
1.0U
100N
1.0U
100N
1.0U
100N
0.5
100N22
U
4.7U
4.7K
100N
0.5
22U
100N
4.7U
0.5
22U
4.7U
100N
0.5
100N
1.0U
100N
1.0U
100N
1.0U
22U
4.7U
100N
4.7K
100N
1.0U
0.5
100N 22U
4.7U
100N
100N
0.5
22U
4.7U
100N
100N
1.0U
100N
1.0U
100N
1.0U
100N
1.0U
4.7K
100N
C555C553
L15
C551
C556
R213
L16
C554
R214
C552
C546
R212
L14
C548 C550
C545
R211
L13
C547 C549
C495C493
L5
C491
R166
C496C494
L6
C492
R167
L7
C499 C501
R168
C502C500
L8
R169
C498
C497
R149
C409C408C407C406C405C404C403C402
R150
U35
C417C416C415C414C413C412C411C410
U36
C470
R160
C469C468C467C466C465C464C463
R161
C478C477C476C475C474C473C472C471
U42
U43
14B8 14A8 14A8
14B8
14B8
14B8 14B8
14B8
14B8 14B8
14B8 14B8
14B8 14B8
14B8
14B8
14B8
14B8 14B8
14C8 14C8 14B8 14B8 14B8
25B4 25B4
13E7 13E7
13B7
14E1
12C7 12E7
14E1 14E1
14D1 14D1
14E1
14E1 14E1
14E1
14E1 14D1
14E1
14D1
14D1
14E1
25E8
12E7
14E1
12E7
14E1
14E1
14D1 14D1 14D1 14D1
14D1 14D1
12B7 12B7 25A4
13C7
13B7
14C1
14C1
14C1 14C1 14C1 14C1 14C1 14C1
14C1
14C1 14C1 14C1 14C1 14C1 14C1 14C1
14D1 14D1
12C7 12E7 13E7
13B7
25E8
12E7
14C1
14D1
14D1
14D1
14D1
12B7 25A4
14A8 14A8 14A8
14A8 14A8
14A8 14A8
14A8
14A8 14A8
14A8 14A8
14A8
14A8
25A4 25A4 13E3
13E3 13C3 12E3
13C3 12C3 12E3
13E3 25E8 12C3 12E3
12B3 12C3 25C4
14A8 14A8 14A8 14A8 14A8 14A8
14A8 14A8
14A8 14A8
12E3 12C3 13B3 13C3 25A4 13E3
13C3
25A4
12E3
13E3
12C3
13C3
25E8
12E3 12C3 12B3 25C4
14D1
25B4 12B7 12E7 13B7 13E7 13E7 25B4
25B4 25B4 13E7
13B7 13E7 13B7
12B7 12E7 12B7
25B4 25B4
13B7 13E7 13B7 13E7
12E7 12E7
25A4 13E3 25A4 13E3
13B3 13C3 12E3
12C3 12E3 12B3 12C3
13E3 25A4 25A4 13C3
13E3 13B3 12E3
13C3 12C3 12B3 12E3 12C3
12E7
12B7 12B7
TX_UPOD_R0_N<8>
TX_UPOD_R0_N<9>
TX_UPOD_R0_P<11>
TX_UPOD_R0_N<7>TX_UPOD_R0_P<7>
TX_UPOD_R0_P<8>
TX_UPOD_R0_N<11>
TX_UPOD_R0_N<10>
TX_UPOD_R0_P<9>
TX_UPOD_R0_N<6>
TX_UPOD_R0_N<5>
TX_UPOD_R0_P<2>TX_UPOD_R0_N<2>TX_UPOD_R0_P<3>TX_UPOD_R0_N<3>TX_UPOD_R0_P<4>TX_UPOD_R0_N<4>TX_UPOD_R0_P<5>
TX_UPOD_R0_P<6>
TX_UPOD_R0_N<1>
TX_UPOD_R0_N<0>TX_UPOD_R0_P<0>
TX_UPOD_R0_P<1>
TX_UPOD_SDATX_UPOD_RESETN
TX_UPOD_SCLTX_UPOD_SDATX_UPOD_SCL
TX_UPOD_R1_N<7>
TX_UPOD_R1_N<8>
TX_UPOD_R1_N<11>TX_UPOD_R1_P<11>TX_UPOD_R1_N<10>
TX_UPOD_R1_N<9>TX_UPOD_R1_P<9>
TX_UPOD_R1_P<8>
TX_UPOD_SCL
TX_UPOD_R1_INTN
TX_UPOD_R1_P<10>
TX_UPOD_R0_P<10>
RX_UPOD_R1_N<6>RX_UPOD_R1_P<7>
RX_UPOD_R1_P<6>RX_UPOD_R1_N<5>
RX_UPOD_R1_P<9>RX_UPOD_R1_N<9>
RX_UPOD_R1_N<8>
RX_UPOD_R1_N<7>RX_UPOD_R1_P<8>
RX_UPOD_R1_N<11>RX_UPOD_R1_P<11>
RX_UPOD_R1_P<10>RX_UPOD_R1_N<10>
RX_UPOD_SDARX_UPOD_SCL
RX_UPOD_SCLRX_UPOD_SDA
RX_UPOD_RESETN
RX_UPOD_R1_N<2>RX_UPOD_R1_P<2>RX_UPOD_R1_N<1>RX_UPOD_R1_P<1>
RX_UPOD_R1_P<0>RX_UPOD_R1_N<0>
RX_UPOD_R1_N<4>RX_UPOD_R1_P<4>RX_UPOD_R1_N<3>RX_UPOD_R1_P<3>
RX_UPOD_R1_P<5>
RX_UPOD_R1_INTN
RX_UPOD_SCL
RX_UPOD_RESETNRX_UPOD_SDA
RX_UPOD_SDARX_UPOD_SCL
RX_UPOD_R0_P<2>
RX_UPOD_R0_P<0>RX_UPOD_R0_N<0>RX_UPOD_R0_P<1>RX_UPOD_R0_N<1>
RX_UPOD_R0_N<2>RX_UPOD_R0_P<3>RX_UPOD_R0_N<3>
RX_UPOD_R0_N<11>
RX_UPOD_R0_P<4>
RX_UPOD_R0_N<6>RX_UPOD_R0_P<6>
RX_UPOD_R0_N<4>RX_UPOD_R0_P<5>RX_UPOD_R0_N<5>
RX_UPOD_R0_N<9>
RX_UPOD_R0_N<8>RX_UPOD_R0_P<9>
RX_UPOD_R0_P<8>
RX_UPOD_R0_P<7>RX_UPOD_R0_N<7>
RX_UPOD_R0_P<11>
RX_UPOD_R0_P<10>RX_UPOD_R0_N<10>
RX_UPOD_R0_INTN
TX_UPOD_R0_INTN
TX_UPOD_R1_N<5>
TX_UPOD_R1_P<7>TX_UPOD_R1_N<6>TX_UPOD_R1_P<6>
TX_UPOD_R1_P<5>TX_UPOD_R1_N<4>TX_UPOD_R1_P<4>TX_UPOD_R1_N<3>TX_UPOD_R1_P<3>TX_UPOD_R1_N<2>TX_UPOD_R1_P<2>TX_UPOD_R1_N<1>TX_UPOD_R1_P<1>TX_UPOD_R1_N<0>TX_UPOD_R1_P<0>
TX_UPOD_SCLTX_UPOD_SDA
TX_UPOD_RESETN
TX_UPOD_SDA
D6
D4
E6
E4
F4F5D5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
D6
D4
E6
E4
F4F5D5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
D6
D4
E6
E4
F4D5F5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
D6
D4
E6
E4
F4D5F5
F8F9D8D9H8J8B8A8H6J6B6A6H4J4B4A4H2J2B2A2F2F1D2D1
C3E3G3
INININ
INININININ
GND
IN
IN
p3v3_right_tx1
GND
GND
*
OUT
IN
p3v3_right_tx1p2v5_right_tx1
IN
GND
IN
GND
afbr_77d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]VCC25[3..0]
VCC33[3..0]
RESETL
DIN11-
DIN10-
DIN9-
DIN8-
DIN7-
DIN6-
DIN5-
DIN4-
DIN3-
DIN2-
DIN1-
DIN0-
DIN11+
DIN10+
DIN9+
DIN8+
DIN7+
DIN6+
DIN5+
DIN4+
DIN3+
DIN2+
DIN1+
DIN0+
ADDR2ADDR1ADDR0
IN
ININININ
ININ
IN
INININININ
p2v5_right_tx0p3v3_right_tx0
IN
BIBI
IN
p3v3_right_tx1
p3v3_right_rx1P3V3
p2v5_right_rx1
IN
*
GND
P2V5
*
GND
P2V5
IN
*
GND
p2v5_right_rx0
P3V3
*
GND
GND
p3v3_right_rx0
p3v3_right_tx0
p2v5_right_tx0
p2v5_right_tx1
p3v3_right_tx1
IN
P3V3
*
GND
P2V5
IN
*
GND
*
IN
GND
GND
*
P2V5
P3V3
IN
p3v3_right_rx0
*
OUT
OUTOUTOUTOUTOUTOUTOUT
IN
OUTOUT
OUTOUTOUT
OUTOUT
IN
BIBI
afbr_77d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]VCC25[3..0]
VCC33[3..0]
RESETL
DIN11-
DIN10-
DIN9-
DIN8-
DIN7-
DIN6-
DIN5-
DIN4-
DIN3-
DIN2-
DIN1-
DIN0-
DIN11+
DIN10+
DIN9+
DIN8+
DIN7+
DIN6+
DIN5+
DIN4+
DIN3+
DIN2+
DIN1+
DIN0+
ADDR2ADDR1ADDR0
p2v5_right_tx1
GND
p3v3_right_rx0
p3v3_right_rx0
p2v5_right_rx0
IN
p3v3_right_rx1
OUTOUTOUT
OUTOUT
OUTOUT
IN
OUTOUTOUT
GND
*
OUT
OUTOUT
OUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUT
OUT
INOUT
OUTOUTOUT
OUTOUT
OUTOUTOUTOUT
IN
GND
afbr_78d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]
VCC25[3..0]VCC33[3..0]
RESETL
DOUT11-
DOUT10-
DOUT9-
DOUT8-
DOUT7-
DOUT6-
DOUT5-
DOUT4-
DOUT3-
DOUT2-
DOUT1-
DOUT0-
DOUT11+
DOUT10+
DOUT9+
DOUT8+
DOUT7+
DOUT6+
DOUT5+
DOUT4+
DOUT3+
DOUT2+
DOUT1+
DOUT0+
ADDR2ADDR1ADDR0
p3v3_right_rx0p2v5_right_rx0
GND
IN
BI
p3v3_right_rx1BI
IN
p3v3_right_rx1p2v5_right_rx1
afbr_78d2sz
INTL_1INTL_0
SCL_1SDA_1SCL_0SDA_0
GND[31..0]NC[6..0]
VCC25[3..0]VCC33[3..0]
RESETL
DOUT11-
DOUT10-
DOUT9-
DOUT8-
DOUT7-
DOUT6-
DOUT5-
DOUT4-
DOUT3-
DOUT2-
DOUT1-
DOUT0-
DOUT11+
DOUT10+
DOUT9+
DOUT8+
DOUT7+
DOUT6+
DOUT5+
DOUT4+
DOUT3+
DOUT2+
DOUT1+
DOUT0+
ADDR2ADDR1ADDR0
IN
p3v3_right_rx1p2v5_right_rx1
GNDIN
p3v3_right_tx0
*
OUT
p3v3_right_tx0
IN
p2v5_right_tx0
IN
BIBI
p3v3_right_tx0
INININ
IN
IN
p3v3_right_tx1
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
UPOD TO ARRIA10 CONNECTIONS
MODIFIE: Mon Mar 23 09:50:45 2015
SHEET: 14 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 14 / 27
C90C33
C1
C91C34
C2
C92C35
C36
C3
C4
C93
C37C94
C5
C6C38
C95
C96C39
C7
C8C40
C65
C9C66C41
C42 C67C10
C11C43 C68
C69C44C12
C45 C70C13
C14C46 C71
C47 C72C15
C16C73C48
C17C74
C49
C75C50C18
C76C51C19
C20C52 C77
C53 C78C21
C22C79C54
C80C55C23
C24C56 C81
C25C82C57
C58C26
C83
C84C59C27
C28C60 C85
C61 C86C29
C30C62 C87
C63 C88C31
C32C89C64
100N
100N
100N100N
100N
100N
100N
100N
100N100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N100N
100N
100N
100N
100N100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N100N
100N
100N
100N
100N
100N
100N100N
100N
100N100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N100N
100N
100N
100N
100N
100N
100N100NRX_UPOD_L0_P<0>
RX_UPOD_L0_N<0>RX_UPOD_L0_P<1>RX_UPOD_L0_N<1>RX_UPOD_L0_P<2>RX_UPOD_L0_N<2>RX_UPOD_L0_P<3>RX_UPOD_L0_N<3>RX_UPOD_L0_P<4>RX_UPOD_L0_N<4>RX_UPOD_L0_P<5>RX_UPOD_L0_N<5>RX_UPOD_L0_P<6>RX_UPOD_L0_N<6>
RX_UPOD_L0_N<7>RX_UPOD_L0_P<8>RX_UPOD_L0_N<8>RX_UPOD_L0_P<9>RX_UPOD_L0_N<9>RX_UPOD_L0_P<10>RX_UPOD_L0_N<10>RX_UPOD_L0_P<11>RX_UPOD_L0_N<11> RX_GXB_L0_N<11>
RX_GXB_L0_P<1>RX_GXB_L0_N<0>RX_GXB_L0_P<0>
RX_UPOD_L1_P<0> RX_GXB_L1_P<0>
RX_GXB_L0_N<6>RX_GXB_L0_P<6>RX_GXB_L0_N<5>RX_GXB_L0_P<5>
RX_UPOD_L0_P<7>
RX_GXB_L0_P<11>
RX_GXB_L0_P<7>RX_GXB_L0_N<7>RX_GXB_L0_P<8>RX_GXB_L0_N<8>RX_GXB_L0_P<9>RX_GXB_L0_N<9>RX_GXB_L0_P<10>RX_GXB_L0_N<10>
RX_GXB_L1_P<2>RX_GXB_L1_N<2>
RX_GXB_L0_N<1>RX_GXB_L0_P<2>RX_GXB_L0_N<2>RX_GXB_L0_P<3>
RX_UPOD_R0_P<3>
RX_UPOD_R0_P<5>
RX_GXB_R0_N<8>RX_GXB_R0_P<9>RX_GXB_R0_N<9>
RX_GXB_L1_P<3>RX_GXB_L1_N<3>
RX_GXB_L0_N<4>RX_GXB_L0_P<4>RX_GXB_L0_N<3>
RX_UPOD_L1_P<10>RX_UPOD_L1_N<10>
RX_UPOD_L1_N<8>RX_UPOD_L1_P<8>RX_UPOD_L1_N<7>RX_UPOD_L1_P<7>
RX_UPOD_L1_P<2>RX_UPOD_L1_N<2>RX_UPOD_L1_P<3>RX_UPOD_L1_N<3>RX_UPOD_L1_P<4>RX_UPOD_L1_N<4>RX_UPOD_L1_P<5>RX_UPOD_L1_N<5>
RX_UPOD_R0_P<6>RX_UPOD_R0_N<5>
TX_GXB_L1_P<3>TX_GXB_L1_N<2>TX_GXB_L1_P<2>TX_GXB_L1_N<1>TX_GXB_L1_P<1>TX_GXB_L1_N<0>TX_GXB_L1_P<0>
TX_GXB_L0_N<11>TX_GXB_L0_P<11>
TX_GXB_L0_P<10>
TX_GXB_L0_P<8>TX_GXB_L0_N<7>
RX_GXB_R1_P<10>
RX_GXB_L1_N<0>RX_GXB_L1_P<1>RX_GXB_L1_N<1>
RX_GXB_L1_P<4>
RX_GXB_L1_P<5>RX_GXB_L1_N<4>
RX_GXB_L1_N<5>
RX_GXB_L1_N<6>RX_GXB_L1_P<6>
RX_GXB_L1_N<7>RX_GXB_L1_P<7>
RX_GXB_L1_P<8>RX_GXB_L1_N<8>RX_GXB_L1_P<9>
RX_GXB_L1_P<10>RX_GXB_L1_N<9>
RX_GXB_L1_N<10>RX_GXB_L1_P<11>RX_GXB_L1_N<11>
RX_GXB_R0_P<0>RX_GXB_R0_N<0>RX_GXB_R0_P<1>
RX_GXB_R0_N<2>
RX_GXB_R0_N<1>RX_GXB_R0_P<2>
RX_GXB_R0_P<3>RX_GXB_R0_N<3>
RX_GXB_R0_P<5>
RX_GXB_R0_P<4>RX_GXB_R0_N<4>
RX_GXB_R0_P<6>RX_GXB_R0_N<5>
RX_GXB_R0_N<6>
RX_GXB_R0_N<7>RX_GXB_R0_P<7>
RX_GXB_R0_P<8>
RX_GXB_R0_P<10>RX_GXB_R0_N<10>RX_GXB_R0_P<11>RX_GXB_R0_N<11>
RX_GXB_R1_P<0>RX_GXB_R1_N<0>RX_GXB_R1_P<1>
RX_GXB_R1_N<2>
RX_GXB_R1_N<1>RX_GXB_R1_P<2>
RX_GXB_R1_P<3>RX_GXB_R1_N<3>RX_GXB_R1_P<4>
RX_GXB_R1_P<5>RX_GXB_R1_N<4>
RX_GXB_R1_P<6>RX_GXB_R1_N<5>
RX_GXB_R1_N<6>
RX_GXB_R1_N<7>RX_GXB_R1_P<7>
RX_GXB_R1_P<8>RX_GXB_R1_N<8>RX_GXB_R1_P<9>RX_GXB_R1_N<9>
RX_GXB_R1_N<10>RX_GXB_R1_P<11>RX_GXB_R1_N<11>
RX_UPOD_L1_N<11>
RX_UPOD_L1_N<9>
RX_UPOD_L1_P<11>
RX_UPOD_R0_P<0>
RX_UPOD_L1_N<1>
RX_UPOD_L1_N<0>
TX_GXB_L1_N<11> TX_UPOD_R1_N<11>
TX_UPOD_L1_P<8>
TX_UPOD_L1_P<7>
TX_UPOD_L1_P<6>
TX_UPOD_L1_P<5>
TX_UPOD_L1_P<4>
TX_UPOD_L1_N<2>TX_UPOD_L1_P<2>
TX_UPOD_L1_P<1>
TX_UPOD_L0_P<10>TX_GXB_L0_N<10>
RX_UPOD_R1_P<2>
RX_UPOD_R1_N<0>RX_UPOD_R1_P<0>
RX_UPOD_R0_N<11>RX_UPOD_R0_P<11>
TX_UPOD_L1_P<3>TX_UPOD_L1_N<3>
TX_GXB_L0_P<1>
TX_GXB_L0_P<0>
TX_GXB_L1_P<11>TX_GXB_L1_N<10>TX_GXB_L1_P<10>TX_GXB_L1_N<9>TX_GXB_L1_P<9>TX_GXB_L1_N<8>TX_GXB_L1_P<8>
TX_GXB_L1_N<3>TX_GXB_L1_P<4>TX_GXB_L1_N<4>TX_GXB_L1_P<5>
TX_GXB_R1_N<11>TX_GXB_R1_P<11>TX_GXB_R1_N<10>
RX_UPOD_L1_P<9>
TX_UPOD_L1_P<11>TX_UPOD_L1_N<10>TX_UPOD_L1_P<10>TX_UPOD_L1_N<9>
TX_GXB_R1_P<9>TX_GXB_R1_N<8>
TX_UPOD_R1_N<7>TX_UPOD_R1_P<7>TX_UPOD_R1_N<6>TX_UPOD_R1_P<6>TX_UPOD_R1_N<5>
RX_UPOD_R1_P<1>RX_UPOD_R1_N<1>
RX_UPOD_R1_N<2>RX_UPOD_R1_P<3>RX_UPOD_R1_N<3>RX_UPOD_R1_P<4>
RX_UPOD_R1_N<10>
RX_UPOD_R1_P<9>
RX_UPOD_R1_N<7>
RX_UPOD_R1_P<6>
RX_UPOD_R1_N<4>
RX_UPOD_R0_N<10>
RX_UPOD_R1_P<5>
RX_UPOD_R0_P<9>
RX_UPOD_R0_N<7>
RX_UPOD_R0_N<4>
RX_UPOD_R0_N<1>RX_UPOD_R0_P<1>RX_UPOD_R0_N<0>
RX_UPOD_R0_P<2>RX_UPOD_R0_N<2>
RX_UPOD_R0_N<3>RX_UPOD_R0_P<4>
RX_UPOD_L1_P<1>
RX_UPOD_L1_P<6>
RX_UPOD_R1_N<6>
RX_UPOD_R1_P<8>
RX_UPOD_R1_N<9>
RX_UPOD_R1_P<11>
RX_UPOD_R0_N<9>
RX_UPOD_R0_P<8>
RX_UPOD_R0_N<6>
RX_UPOD_L1_N<6>
RX_UPOD_R0_P<7>
RX_UPOD_R0_N<8>
RX_UPOD_R0_P<10>
RX_UPOD_R1_N<5>
RX_UPOD_R1_P<7>
RX_UPOD_R1_N<8>
RX_UPOD_R1_P<10>
RX_UPOD_R1_N<11>
TX_UPOD_L1_P<0>
TX_UPOD_L0_N<11>TX_UPOD_L0_P<11>TX_UPOD_L0_N<10>
TX_UPOD_L0_N<9>TX_UPOD_L0_P<9>
TX_UPOD_L0_N<7>
TX_UPOD_L0_N<0>TX_UPOD_L0_P<1>
TX_GXB_L0_P<2>TX_GXB_L0_N<2>
TX_GXB_L1_P<7>TX_GXB_L1_N<7>
TX_GXB_L1_N<6>TX_GXB_L1_P<6>TX_GXB_L1_N<5>
TX_UPOD_L1_N<11>
TX_UPOD_L1_P<9>TX_UPOD_L1_N<8>
TX_UPOD_L1_N<7>
TX_UPOD_L1_N<6>
TX_UPOD_L1_N<5>
TX_UPOD_L1_N<4>
TX_UPOD_L1_N<1>
TX_GXB_L0_N<9>TX_GXB_L0_P<9>TX_GXB_L0_N<8>
TX_GXB_L0_P<7>TX_GXB_L0_N<6>TX_GXB_L0_P<6>TX_GXB_L0_N<5>TX_GXB_L0_P<5>TX_GXB_L0_N<4>TX_GXB_L0_P<4>
TX_GXB_L0_P<3>TX_GXB_L0_N<3>
TX_GXB_L0_N<1>
TX_GXB_L0_N<0>
TX_UPOD_L1_N<0>
TX_UPOD_L0_P<8>TX_UPOD_L0_N<8>
TX_UPOD_L0_N<6>TX_UPOD_L0_P<7>
TX_UPOD_L0_P<6>TX_UPOD_L0_N<5>TX_UPOD_L0_P<5>
TX_UPOD_L0_P<4>TX_UPOD_L0_N<4>
TX_UPOD_L0_P<3>TX_UPOD_L0_N<3>
TX_UPOD_L0_N<2>TX_UPOD_L0_P<2>TX_UPOD_L0_N<1>
TX_UPOD_L0_P<0>
TX_GXB_R1_P<7>TX_GXB_R1_N<6>
TX_UPOD_R0_P<2>
TX_UPOD_R0_N<3>TX_UPOD_R0_P<4>TX_UPOD_R0_N<4>TX_UPOD_R0_P<5>
TX_UPOD_R0_P<6>TX_UPOD_R0_N<5>
TX_UPOD_R0_N<6>TX_UPOD_R0_P<7>TX_UPOD_R0_N<7>TX_UPOD_R0_P<8>TX_UPOD_R0_N<8>
TX_UPOD_R0_N<9>TX_UPOD_R0_P<10>
TX_UPOD_R0_P<9>
TX_UPOD_R0_P<11>TX_UPOD_R0_N<10>
TX_UPOD_R0_N<11>
TX_UPOD_R1_P<0>
TX_UPOD_R1_P<1>TX_UPOD_R1_N<0>
TX_UPOD_R1_N<1>TX_UPOD_R1_P<2>TX_UPOD_R1_N<2>TX_UPOD_R1_P<3>TX_UPOD_R1_N<3>TX_UPOD_R1_P<4>TX_UPOD_R1_N<4>TX_UPOD_R1_P<5>
TX_UPOD_R1_P<10>
TX_UPOD_R1_P<9>TX_UPOD_R1_N<8>TX_UPOD_R1_P<8>
TX_UPOD_R1_N<9>
TX_UPOD_R1_P<11>TX_UPOD_R1_N<10>
TX_UPOD_R0_P<3>TX_UPOD_R0_N<2>
TX_GXB_R1_N<4>TX_GXB_R1_P<4>
TX_GXB_R1_P<5>TX_GXB_R1_N<5>TX_GXB_R1_P<6>
TX_GXB_R1_N<1>TX_GXB_R1_P<2>TX_GXB_R1_N<2>
TX_GXB_R1_N<3>TX_GXB_R1_P<3>
TX_GXB_R1_N<0>TX_GXB_R1_P<1>
TX_GXB_R0_N<4>TX_GXB_R0_P<4>
TX_GXB_R0_P<5>TX_GXB_R0_N<5>
TX_GXB_R0_P<2>TX_GXB_R0_N<1>
TX_GXB_R0_N<2>TX_GXB_R0_P<3>TX_GXB_R0_N<3>
TX_GXB_R0_P<0>TX_GXB_R0_N<0>TX_GXB_R0_P<1>
TX_GXB_R1_P<10>TX_GXB_R1_N<9>
TX_GXB_R1_P<8>TX_GXB_R1_N<7>
TX_UPOD_R0_P<0>TX_UPOD_R0_N<0>TX_UPOD_R0_P<1>TX_UPOD_R0_N<1>
TX_GXB_R0_P<9>TX_GXB_R0_N<9>TX_GXB_R0_P<10>TX_GXB_R0_N<10>TX_GXB_R0_P<11>TX_GXB_R0_N<11>
TX_GXB_R1_P<0>
TX_GXB_R0_P<6>
TX_GXB_R0_P<7>TX_GXB_R0_N<7>TX_GXB_R0_P<8>TX_GXB_R0_N<8>
TX_GXB_R0_N<6>
12C1
19C4
19E8 12B1
12B1
19C4 19C4
19B4 19B4
13D1
20A4
12B1 12B1 12A1 12A1
19C8
19A4
19C8 19C8 19C8
19C5 19C5 19D5
19C4 19C4
19C4 19C4 19C4 19C4 19C4 19C4 19C4
19B4 19B4
19B4 19B4 19B4 19B4 19A4 19A4 19A4
20C8
19E8 19E8 19E8
19E8 19D8
19D8 19D8 19D8
19D8 19D8
19D8
19C8 19C8
19C8 19C8
19C8 19C8 19C8
19C8
20C4 20C4 20C4
20C4
20C4 20C4
20C4 20C4
20C4
20C4 20C4
20B4 20C4
20B4
20B4 20B4
20B4 20B4 20A4 20A4
20A4 20A4 20A4
20E8 20E8 20D8
20D8
20E8 20D8
20D8 20D8 20D8
20D8 20D8
20C8 20D8
20C8
20C8 20C8
20C8 20C8 20C8 20C8
20C8 20C8 20C8
19E5 19E5
12B1
12B1 12B1
12B1 12B1
12A1
12D1
19C5
12C7
19A1
19B1 19A1
12B7 20D4
19B1
19B1
19B1
19C1 19C1 19C1 19C1 19C1 19C1
19C1 19C1
19B1
19C5
20C4 20C4
19C5 12A7 12A7 12A7 12A7
20C4 20C4
13A7 13A7 13A7 13A7 13B7
13B1 13B1 13B1 13B1 13B1 13B1 13B1
13A1
13A1
13A1
13B1
13B1
13B1
13C1
13B1
13B1
12A1
13D1
13D1
13D1
13D1
13D1
13D1
13D1
12A1
13D1
13D1 13D1
13D1 13D1
13D1 13D1
12B1 12B1
12B1 12B1
12C1 12C1
12C1 12D1
12D1
12D1 12D1
12D1 12D1
12A1
13B1
13A1
13A1
13A1
13C1
13D1
13D1
13D1
12A1
12B1
12A1
12A1
12A1
13D1
13D1
13C1
13C1
13B1
13A1
13A1
13A1
13A1
12D1 12D1 12D1 12D1 12D1 12D1 12D1
12D1 12D1
12D1 12D1
12D1
12D1
19C5
19C5 19C5
19E5 19D5 19E5
12B7
12C7 12C7 12C7
12C7 12C7
12D7
12D7 12D7
19C5 19C5
19C5 19C5
19D5 19D5 19D5
19D5 19D5
12A7
12A7 12A7 12A7 12A7 12A7 12A7
12B7 12A7
12B7 12B7
12B7 12B7 12B7 12B7 12B7
19E5
19A1 19A1
19B1
19B1
19B1 19C1 19C1 19C1
19C1
12B7 12B7
12D7 12D7
12D7 12D7
12D7 12D7 12D7
12D7 12D7
12D7 12D7
12D7 12D7 12D7
12D7
20C4
13D7
13D7 13D7 13D7 13D7
13D7 13D7
13D7 13D7 13D7 13D7 13D7
13C7 13C7
13C7
13C7 13C7
13C7
13B7
13B7 13B7
13B7 13B7 13B7 13B7 13B7 13B7 13B7 13B7
13A7
13A7 13A7 13A7
13A7
13A7 13A7
13A7
13D7 13D7
20D4 20D4
20D4 20C4
20E4 20D4 20D4
20D4 20D4
20E4 20D4
20C1 20C1
20C1 20C1
20C1 20C1
20C1 20C1 20C1
20C1 20C1 20C1
20C4 20C4 20C4 20C4 20C4
20C4
13D7 13D7 13D7 13D7
20A1 20A1 20A1 20A1 20A1 20A1
20E4
20B1
20B1 20B1 20B1 20B1
20B1
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
INININININININ
IN
INININININ
ININININ
IN
IN
ININININ
IN
ININ
ININ
IN
IN
ININ
ININ
INININ
INININ
IN
ININ
IN
ININININ
IN
IN
IN
INININ
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
ININ
IN
ININ
IN
ININ
ALIAS
ALIASALIASALIAS
ALIASALIAS
ALIASALIAS
IN
ALIASALIASALIAS
ALIASALIASALIAS
ALIASALIAS
ALIAS
ALIAS
IN
ALIAS
ALIASALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIASALIAS
ALIAS
IN
ALIASALIAS
OUTOUTOUT
OUTOUT
OUTOUTOUT
IN
OUTOUT
ININININININ
ININ
IN
IN
IN
ININ
OUTOUTOUTOUT
OUTOUT
OUT
IN
OUTOUT
OUTOUT
OUTOUTOUT
OUTOUTOUT
IN
OUTOUT
ININININININININ
IN
INININININ
ININININ
IN
IN
ININ
ININININ
IN
IN
IN
IN
IN
IN
IN
ININ
IN
IN
IN
IN
ININ
IN
ALIASALIASALIASALIASALIAS
ALIASALIAS
ALIAS
ALIASALIAS
IN
ALIASALIAS
ALIAS
ALIASALIAS
ALIASALIASALIAS
OUT
OUT
IN
OUT
OUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUT
OUTOUT
OUTOUT
OUT
IN
ININ
IN
IN
IN
ININ
IN
ININ
IN
IN
ININ
IN
IN
IN
IN
ININ
ALIASALIASALIASALIASALIAS
IN
ALIAS
ALIASALIASALIAS
ALIASALIAS
ALIAS
ALIASALIAS
ALIAS
IN
ALIAS
ALIAS
ALIASALIAS
ALIASALIAS
ALIASALIASALIAS
ALIAS
IN
ALIAS
ALIASALIAS
ALIASALIAS
OUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUT
OUT
IN
OUTOUT
OUTOUT
OUT
OUT
OUTOUT
OUT
OUT
IN
OUT
OUTOUT
OUTOUTOUTOUT
OUTOUT
OUT
IN
OUT
OUT
OUTOUT
OUTOUTOUT
OUTOUT
OUT
IN
IN
OUTOUTOUT
OUTOUT
IN
IN
IN
ALIAS
ALIASALIAS
ALIAS
IN
ALIAS
ALIAS
ALIASALIAS
ALIASALIAS
ALIAS
ALIASALIAS
ALIAS
IN
ALIAS
ALIASALIASALIAS
OUTOUTOUTOUTOUTOUT
IN
OUTOUT
OUTOUT
OUT
OUT
OUT
OUTOUT
OUT
IN
OUT
OUT
OUTOUTOUT
OUTOUT
OUT
OUTOUT
IN
OUTOUT
OUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUT
OUTOUT
OUTOUTOUT
OUT
IN
IN
OUT
OUTOUT
OUTOUTOUTOUTOUTOUTOUT
IN
OUT
IN
IN
ININ
OUTOUTOUT
OUTOUTOUTOUT
OUTOUT
OUT
IN
OUTOUT
OUTOUT
OUTOUT
OUT
OUTOUT
OUT
IN
OUTOUTOUTOUTOUTOUTOUT
IN
ININ
INUPOD TO ARRIA10 CONNECTIONS
MODIFIE: Mon Mar 23 09:50:45 2015
SHEET: 14 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 14 / 27
100N
100N
100N100N
100N
100N
100N
100N
100N100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N100N
100N
100N
100N
100N100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N100N
100N
100N
100N
100N
100N
100N100N
100N
100N100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N100N
100N
100N
100N
100N
100N
100N100N
C90C33
C1
C91C34
C2
C92C35
C36
C3
C4
C93
C37C94
C5
C6C38
C95
C96C39
C7
C8C40
C65
C9C66C41
C42 C67C10
C11C43 C68
C69C44C12
C45 C70C13
C14C46 C71
C47 C72C15
C16C73C48
C17C74
C49
C75C50C18
C76C51C19
C20C52 C77
C53 C78C21
C22C79C54
C80C55C23
C24C56 C81
C25C82C57
C58C26
C83
C84C59C27
C28C60 C85
C61 C86C29
C30C62 C87
C63 C88C31
C32C89C64
12C1
19C4
19E8 12B1
12B1
19C4 19C4
19B4 19B4
13D1
20A4
12B1 12B1 12A1 12A1
19C8
19A4
19C8 19C8 19C8
19C5 19C5 19D5
19C4 19C4
19C4 19C4 19C4 19C4 19C4 19C4 19C4
19B4 19B4
19B4 19B4 19B4 19B4 19A4 19A4 19A4
20C8
19E8 19E8 19E8
19E8 19D8
19D8 19D8 19D8
19D8 19D8
19D8
19C8 19C8
19C8 19C8
19C8 19C8 19C8
19C8
20C4 20C4 20C4
20C4
20C4 20C4
20C4 20C4
20C4
20C4 20C4
20B4 20C4
20B4
20B4 20B4
20B4 20B4 20A4 20A4
20A4 20A4 20A4
20E8 20E8 20D8
20D8
20E8 20D8
20D8 20D8 20D8
20D8 20D8
20C8 20D8
20C8
20C8 20C8
20C8 20C8 20C8 20C8
20C8 20C8 20C8
19E5 19E5
12B1
12B1 12B1
12B1 12B1
12A1
12D1
19C5
12C7
19A1
19B1 19A1
12B7 20D4
19B1
19B1
19B1
19C1 19C1 19C1 19C1 19C1 19C1
19C1 19C1
19B1
19C5
20C4 20C4
19C5 12A7 12A7 12A7 12A7
20C4 20C4
13A7 13A7 13A7 13A7 13B7
13B1 13B1 13B1 13B1 13B1 13B1 13B1
13A1
13A1
13A1
13B1
13B1
13B1
13C1
13B1
13B1
12A1
13D1
13D1
13D1
13D1
13D1
13D1
13D1
12A1
13D1
13D1 13D1
13D1 13D1
13D1 13D1
12B1 12B1
12B1 12B1
12C1 12C1
12C1 12D1
12D1
12D1 12D1
12D1 12D1
12A1
13B1
13A1
13A1
13A1
13C1
13D1
13D1
13D1
12A1
12B1
12A1
12A1
12A1
13D1
13D1
13C1
13C1
13B1
13A1
13A1
13A1
13A1
12D1 12D1 12D1 12D1 12D1 12D1 12D1
12D1 12D1
12D1 12D1
12D1
12D1
19C5
19C5 19C5
19E5 19D5 19E5
12B7
12C7 12C7 12C7
12C7 12C7
12D7
12D7 12D7
19C5 19C5
19C5 19C5
19D5 19D5 19D5
19D5 19D5
12A7
12A7 12A7 12A7 12A7 12A7 12A7
12B7 12A7
12B7 12B7
12B7 12B7 12B7 12B7 12B7
19E5
19A1 19A1
19B1
19B1
19B1 19C1 19C1 19C1
19C1
12B7 12B7
12D7 12D7
12D7 12D7
12D7 12D7 12D7
12D7 12D7
12D7 12D7
12D7 12D7 12D7
12D7
20C4
13D7
13D7 13D7 13D7 13D7
13D7 13D7
13D7 13D7 13D7 13D7 13D7
13C7 13C7
13C7
13C7 13C7
13C7
13B7
13B7 13B7
13B7 13B7 13B7 13B7 13B7 13B7 13B7 13B7
13A7
13A7 13A7 13A7
13A7
13A7 13A7
13A7
13D7 13D7
20D4 20D4
20D4 20C4
20E4 20D4 20D4
20D4 20D4
20E4 20D4
20C1 20C1
20C1 20C1
20C1 20C1
20C1 20C1 20C1
20C1 20C1 20C1
20C4 20C4 20C4 20C4 20C4
20C4
13D7 13D7 13D7 13D7
20A1 20A1 20A1 20A1 20A1 20A1
20E4
20B1
20B1 20B1 20B1 20B1
20B1
RX_UPOD_L0_P<0>RX_UPOD_L0_N<0>RX_UPOD_L0_P<1>RX_UPOD_L0_N<1>RX_UPOD_L0_P<2>RX_UPOD_L0_N<2>RX_UPOD_L0_P<3>RX_UPOD_L0_N<3>RX_UPOD_L0_P<4>RX_UPOD_L0_N<4>RX_UPOD_L0_P<5>RX_UPOD_L0_N<5>RX_UPOD_L0_P<6>RX_UPOD_L0_N<6>
RX_UPOD_L0_N<7>RX_UPOD_L0_P<8>RX_UPOD_L0_N<8>RX_UPOD_L0_P<9>RX_UPOD_L0_N<9>RX_UPOD_L0_P<10>RX_UPOD_L0_N<10>RX_UPOD_L0_P<11>RX_UPOD_L0_N<11> RX_GXB_L0_N<11>
RX_GXB_L0_P<1>RX_GXB_L0_N<0>RX_GXB_L0_P<0>
RX_UPOD_L1_P<0> RX_GXB_L1_P<0>
RX_GXB_L0_N<6>RX_GXB_L0_P<6>RX_GXB_L0_N<5>RX_GXB_L0_P<5>
RX_UPOD_L0_P<7>
RX_GXB_L0_P<11>
RX_GXB_L0_P<7>RX_GXB_L0_N<7>RX_GXB_L0_P<8>RX_GXB_L0_N<8>RX_GXB_L0_P<9>RX_GXB_L0_N<9>RX_GXB_L0_P<10>RX_GXB_L0_N<10>
RX_GXB_L1_P<2>RX_GXB_L1_N<2>
RX_GXB_L0_N<1>RX_GXB_L0_P<2>RX_GXB_L0_N<2>RX_GXB_L0_P<3>
RX_UPOD_R0_P<3>
RX_UPOD_R0_P<5>
RX_GXB_R0_N<8>RX_GXB_R0_P<9>RX_GXB_R0_N<9>
RX_GXB_L1_P<3>RX_GXB_L1_N<3>
RX_GXB_L0_N<4>RX_GXB_L0_P<4>RX_GXB_L0_N<3>
RX_UPOD_L1_P<10>RX_UPOD_L1_N<10>
RX_UPOD_L1_N<8>RX_UPOD_L1_P<8>RX_UPOD_L1_N<7>RX_UPOD_L1_P<7>
RX_UPOD_L1_P<2>RX_UPOD_L1_N<2>RX_UPOD_L1_P<3>RX_UPOD_L1_N<3>RX_UPOD_L1_P<4>RX_UPOD_L1_N<4>RX_UPOD_L1_P<5>RX_UPOD_L1_N<5>
RX_UPOD_R0_P<6>RX_UPOD_R0_N<5>
TX_GXB_L1_P<3>TX_GXB_L1_N<2>TX_GXB_L1_P<2>TX_GXB_L1_N<1>TX_GXB_L1_P<1>TX_GXB_L1_N<0>TX_GXB_L1_P<0>
TX_GXB_L0_N<11>TX_GXB_L0_P<11>
TX_GXB_L0_P<10>
TX_GXB_L0_P<8>TX_GXB_L0_N<7>
RX_GXB_R1_P<10>
RX_GXB_L1_N<0>RX_GXB_L1_P<1>RX_GXB_L1_N<1>
RX_GXB_L1_P<4>
RX_GXB_L1_P<5>RX_GXB_L1_N<4>
RX_GXB_L1_N<5>
RX_GXB_L1_N<6>RX_GXB_L1_P<6>
RX_GXB_L1_N<7>RX_GXB_L1_P<7>
RX_GXB_L1_P<8>RX_GXB_L1_N<8>RX_GXB_L1_P<9>
RX_GXB_L1_P<10>RX_GXB_L1_N<9>
RX_GXB_L1_N<10>RX_GXB_L1_P<11>RX_GXB_L1_N<11>
RX_GXB_R0_P<0>RX_GXB_R0_N<0>RX_GXB_R0_P<1>
RX_GXB_R0_N<2>
RX_GXB_R0_N<1>RX_GXB_R0_P<2>
RX_GXB_R0_P<3>RX_GXB_R0_N<3>
RX_GXB_R0_P<5>
RX_GXB_R0_P<4>RX_GXB_R0_N<4>
RX_GXB_R0_P<6>RX_GXB_R0_N<5>
RX_GXB_R0_N<6>
RX_GXB_R0_N<7>RX_GXB_R0_P<7>
RX_GXB_R0_P<8>
RX_GXB_R0_P<10>RX_GXB_R0_N<10>RX_GXB_R0_P<11>RX_GXB_R0_N<11>
RX_GXB_R1_P<0>RX_GXB_R1_N<0>RX_GXB_R1_P<1>
RX_GXB_R1_N<2>
RX_GXB_R1_N<1>RX_GXB_R1_P<2>
RX_GXB_R1_P<3>RX_GXB_R1_N<3>RX_GXB_R1_P<4>
RX_GXB_R1_P<5>RX_GXB_R1_N<4>
RX_GXB_R1_P<6>RX_GXB_R1_N<5>
RX_GXB_R1_N<6>
RX_GXB_R1_N<7>RX_GXB_R1_P<7>
RX_GXB_R1_P<8>RX_GXB_R1_N<8>RX_GXB_R1_P<9>RX_GXB_R1_N<9>
RX_GXB_R1_N<10>RX_GXB_R1_P<11>RX_GXB_R1_N<11>
RX_UPOD_L1_N<11>
RX_UPOD_L1_N<9>
RX_UPOD_L1_P<11>
RX_UPOD_R0_P<0>
RX_UPOD_L1_N<1>
RX_UPOD_L1_N<0>
TX_GXB_L1_N<11> TX_UPOD_R1_N<11>
TX_UPOD_L1_P<8>
TX_UPOD_L1_P<7>
TX_UPOD_L1_P<6>
TX_UPOD_L1_P<5>
TX_UPOD_L1_P<4>
TX_UPOD_L1_N<2>TX_UPOD_L1_P<2>
TX_UPOD_L1_P<1>
TX_UPOD_L0_P<10>TX_GXB_L0_N<10>
RX_UPOD_R1_P<2>
RX_UPOD_R1_N<0>RX_UPOD_R1_P<0>
RX_UPOD_R0_N<11>RX_UPOD_R0_P<11>
TX_UPOD_L1_P<3>TX_UPOD_L1_N<3>
TX_GXB_L0_P<1>
TX_GXB_L0_P<0>
TX_GXB_L1_P<11>TX_GXB_L1_N<10>TX_GXB_L1_P<10>TX_GXB_L1_N<9>TX_GXB_L1_P<9>TX_GXB_L1_N<8>TX_GXB_L1_P<8>
TX_GXB_L1_N<3>TX_GXB_L1_P<4>TX_GXB_L1_N<4>TX_GXB_L1_P<5>
TX_GXB_R1_N<11>TX_GXB_R1_P<11>TX_GXB_R1_N<10>
RX_UPOD_L1_P<9>
TX_UPOD_L1_P<11>TX_UPOD_L1_N<10>TX_UPOD_L1_P<10>TX_UPOD_L1_N<9>
TX_GXB_R1_P<9>TX_GXB_R1_N<8>
TX_UPOD_R1_N<7>TX_UPOD_R1_P<7>TX_UPOD_R1_N<6>TX_UPOD_R1_P<6>TX_UPOD_R1_N<5>
RX_UPOD_R1_P<1>RX_UPOD_R1_N<1>
RX_UPOD_R1_N<2>RX_UPOD_R1_P<3>RX_UPOD_R1_N<3>RX_UPOD_R1_P<4>
RX_UPOD_R1_N<10>
RX_UPOD_R1_P<9>
RX_UPOD_R1_N<7>
RX_UPOD_R1_P<6>
RX_UPOD_R1_N<4>
RX_UPOD_R0_N<10>
RX_UPOD_R1_P<5>
RX_UPOD_R0_P<9>
RX_UPOD_R0_N<7>
RX_UPOD_R0_N<4>
RX_UPOD_R0_N<1>RX_UPOD_R0_P<1>RX_UPOD_R0_N<0>
RX_UPOD_R0_P<2>RX_UPOD_R0_N<2>
RX_UPOD_R0_N<3>RX_UPOD_R0_P<4>
RX_UPOD_L1_P<1>
RX_UPOD_L1_P<6>
RX_UPOD_R1_N<6>
RX_UPOD_R1_P<8>
RX_UPOD_R1_N<9>
RX_UPOD_R1_P<11>
RX_UPOD_R0_N<9>
RX_UPOD_R0_P<8>
RX_UPOD_R0_N<6>
RX_UPOD_L1_N<6>
RX_UPOD_R0_P<7>
RX_UPOD_R0_N<8>
RX_UPOD_R0_P<10>
RX_UPOD_R1_N<5>
RX_UPOD_R1_P<7>
RX_UPOD_R1_N<8>
RX_UPOD_R1_P<10>
RX_UPOD_R1_N<11>
TX_UPOD_L1_P<0>
TX_UPOD_L0_N<11>TX_UPOD_L0_P<11>TX_UPOD_L0_N<10>
TX_UPOD_L0_N<9>TX_UPOD_L0_P<9>
TX_UPOD_L0_N<7>
TX_UPOD_L0_N<0>TX_UPOD_L0_P<1>
TX_GXB_L0_P<2>TX_GXB_L0_N<2>
TX_GXB_L1_P<7>TX_GXB_L1_N<7>
TX_GXB_L1_N<6>TX_GXB_L1_P<6>TX_GXB_L1_N<5>
TX_UPOD_L1_N<11>
TX_UPOD_L1_P<9>TX_UPOD_L1_N<8>
TX_UPOD_L1_N<7>
TX_UPOD_L1_N<6>
TX_UPOD_L1_N<5>
TX_UPOD_L1_N<4>
TX_UPOD_L1_N<1>
TX_GXB_L0_N<9>TX_GXB_L0_P<9>TX_GXB_L0_N<8>
TX_GXB_L0_P<7>TX_GXB_L0_N<6>TX_GXB_L0_P<6>TX_GXB_L0_N<5>TX_GXB_L0_P<5>TX_GXB_L0_N<4>TX_GXB_L0_P<4>
TX_GXB_L0_P<3>TX_GXB_L0_N<3>
TX_GXB_L0_N<1>
TX_GXB_L0_N<0>
TX_UPOD_L1_N<0>
TX_UPOD_L0_P<8>TX_UPOD_L0_N<8>
TX_UPOD_L0_N<6>TX_UPOD_L0_P<7>
TX_UPOD_L0_P<6>TX_UPOD_L0_N<5>TX_UPOD_L0_P<5>
TX_UPOD_L0_P<4>TX_UPOD_L0_N<4>
TX_UPOD_L0_P<3>TX_UPOD_L0_N<3>
TX_UPOD_L0_N<2>TX_UPOD_L0_P<2>TX_UPOD_L0_N<1>
TX_UPOD_L0_P<0>
TX_GXB_R1_P<7>TX_GXB_R1_N<6>
TX_UPOD_R0_P<2>
TX_UPOD_R0_N<3>TX_UPOD_R0_P<4>TX_UPOD_R0_N<4>TX_UPOD_R0_P<5>
TX_UPOD_R0_P<6>TX_UPOD_R0_N<5>
TX_UPOD_R0_N<6>TX_UPOD_R0_P<7>TX_UPOD_R0_N<7>TX_UPOD_R0_P<8>TX_UPOD_R0_N<8>
TX_UPOD_R0_N<9>TX_UPOD_R0_P<10>
TX_UPOD_R0_P<9>
TX_UPOD_R0_P<11>TX_UPOD_R0_N<10>
TX_UPOD_R0_N<11>
TX_UPOD_R1_P<0>
TX_UPOD_R1_P<1>TX_UPOD_R1_N<0>
TX_UPOD_R1_N<1>TX_UPOD_R1_P<2>TX_UPOD_R1_N<2>TX_UPOD_R1_P<3>TX_UPOD_R1_N<3>TX_UPOD_R1_P<4>TX_UPOD_R1_N<4>TX_UPOD_R1_P<5>
TX_UPOD_R1_P<10>
TX_UPOD_R1_P<9>TX_UPOD_R1_N<8>TX_UPOD_R1_P<8>
TX_UPOD_R1_N<9>
TX_UPOD_R1_P<11>TX_UPOD_R1_N<10>
TX_UPOD_R0_P<3>TX_UPOD_R0_N<2>
TX_GXB_R1_N<4>TX_GXB_R1_P<4>
TX_GXB_R1_P<5>TX_GXB_R1_N<5>TX_GXB_R1_P<6>
TX_GXB_R1_N<1>TX_GXB_R1_P<2>TX_GXB_R1_N<2>
TX_GXB_R1_N<3>TX_GXB_R1_P<3>
TX_GXB_R1_N<0>TX_GXB_R1_P<1>
TX_GXB_R0_N<4>TX_GXB_R0_P<4>
TX_GXB_R0_P<5>TX_GXB_R0_N<5>
TX_GXB_R0_P<2>TX_GXB_R0_N<1>
TX_GXB_R0_N<2>TX_GXB_R0_P<3>TX_GXB_R0_N<3>
TX_GXB_R0_P<0>TX_GXB_R0_N<0>TX_GXB_R0_P<1>
TX_GXB_R1_P<10>TX_GXB_R1_N<9>
TX_GXB_R1_P<8>TX_GXB_R1_N<7>
TX_UPOD_R0_P<0>TX_UPOD_R0_N<0>TX_UPOD_R0_P<1>TX_UPOD_R0_N<1>
TX_GXB_R0_P<9>TX_GXB_R0_N<9>TX_GXB_R0_P<10>TX_GXB_R0_N<10>TX_GXB_R0_P<11>TX_GXB_R0_N<11>
TX_GXB_R1_P<0>
TX_GXB_R0_P<6>
TX_GXB_R0_P<7>TX_GXB_R0_N<7>TX_GXB_R0_P<8>TX_GXB_R0_N<8>
TX_GXB_R0_N<6>
INININININININ
IN
INININININ
ININININ
IN
IN
ININININ
IN
ININ
ININ
IN
IN
ININ
ININ
INININ
INININ
IN
ININ
IN
ININININ
IN
IN
IN
INININ
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
ININ
IN
ININ
IN
ININ
ALIAS
ALIASALIASALIAS
ALIASALIAS
ALIASALIAS
IN
ALIASALIASALIAS
ALIASALIASALIAS
ALIASALIAS
ALIAS
ALIAS
IN
ALIAS
ALIASALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIASALIAS
ALIAS
IN
ALIASALIAS
OUTOUTOUT
OUTOUT
OUTOUTOUT
IN
OUTOUT
ININININININ
ININ
IN
IN
IN
ININ
OUTOUTOUTOUT
OUTOUT
OUT
IN
OUTOUT
OUTOUT
OUTOUTOUT
OUTOUTOUT
IN
OUTOUT
ININININININININ
IN
INININININ
ININININ
IN
IN
ININ
ININININ
IN
IN
IN
IN
IN
IN
IN
ININ
IN
IN
IN
IN
ININ
IN
ALIASALIASALIASALIASALIAS
ALIASALIAS
ALIAS
ALIASALIAS
IN
ALIASALIAS
ALIAS
ALIASALIAS
ALIASALIASALIAS
OUT
OUT
IN
OUT
OUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUT
OUTOUT
OUTOUT
OUT
IN
ININ
IN
IN
IN
ININ
IN
ININ
IN
IN
ININ
IN
IN
IN
IN
ININ
ALIASALIASALIASALIASALIAS
IN
ALIAS
ALIASALIASALIAS
ALIASALIAS
ALIAS
ALIASALIAS
ALIAS
IN
ALIAS
ALIAS
ALIASALIAS
ALIASALIAS
ALIASALIASALIAS
ALIAS
IN
ALIAS
ALIASALIAS
ALIASALIAS
OUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUT
OUT
IN
OUTOUT
OUTOUT
OUT
OUT
OUTOUT
OUT
OUT
IN
OUT
OUTOUT
OUTOUTOUTOUT
OUTOUT
OUT
IN
OUT
OUT
OUTOUT
OUTOUTOUT
OUTOUT
OUT
IN
IN
OUTOUTOUT
OUTOUT
IN
IN
IN
ALIAS
ALIASALIAS
ALIAS
IN
ALIAS
ALIAS
ALIASALIAS
ALIASALIAS
ALIAS
ALIASALIAS
ALIAS
IN
ALIAS
ALIASALIASALIAS
OUTOUTOUTOUTOUTOUT
IN
OUTOUT
OUTOUT
OUT
OUT
OUT
OUTOUT
OUT
IN
OUT
OUT
OUTOUTOUT
OUTOUT
OUT
OUTOUT
IN
OUTOUT
OUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUT
OUTOUT
OUTOUTOUT
OUT
IN
IN
OUT
OUTOUT
OUTOUTOUTOUTOUTOUTOUT
IN
OUT
IN
IN
ININ
OUTOUTOUT
OUTOUTOUTOUT
OUTOUT
OUT
IN
OUTOUT
OUTOUT
OUTOUT
OUT
OUTOUT
OUT
IN
OUTOUTOUTOUTOUTOUTOUT
IN
ININ
IN
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
VSIG : EXTERNAL VOLTAGE SENSOR IF NEEDED
ASSUMPTION : BANK 2AF[1.8V]=IO
ARRIA10 : POWER AND NC
ASSUMPTION : BANK 2KL[1.5V]=DDR3_0 ASSUMPTION : BANK 3GH[1.5V]=DDR3_1 ASSUMPTION : BANK 3AB[1.8V]=OUTPUT TEST PINS,AMC_ID
VREFNADC:INTERNAL REF WHEN TIED TO GNDTIED TO GND IF NOT USED=DEFAULT CONFIGDO NOT DRIVE UNTIL VCCA_PLL HAS REACHED 1.62V
MODIFIE: Mon Mar 23 09:50:40 2015
SHEET: 15 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 15 / 27
AE20AE19AC24
P25AC16AC13
P15P20
AC17AC22AC18AC23AD17AD16AD20AD19AC21AC19
J33AF16AE17AF18AE18
U26G30J30K30M30L30
W27V27V26W26P30R30
AA27AA28W29W30Y27
AA26AC29
AB30U29V29Y28Y29AB28AB29U28V28T28T27T26AA11AC11AB11W11W10AM9AB10V11U11V12AM10T11R10R12T12AK10AF11AF10AD11AC27AD27AL10AF30AC28AD29AM31AM30AL30AJ30AE15
U14
P10Y22Y20
AF17AV12AV13AG16AH16AH17AG15AC26AE14AF15AD26AF13AG18AE13AH18AH13AG13AH19AF21AG21AG14
AL15AH21AL11AJ11AK13AH14AJ12AK12AK15AL12AJ15Y12W12AH12AA12AG11AH11AC12AD12AK14AJ14AF12AE12AV28AV27
U14
J8L10
J7
K10J10G10
P24P22N24P19P16N16AD15AD14AC14AD25AD24AD22AD21
AF20AG20
W21
AB18AA23AA22AA18AA17
AG19
AB24AB16AB13
R14P21R25
AB14AB25AB15AB26
N17P17
Y21
J32
U14
R15
M19R13
AL13AN17
M24P26
AE27AF23
J18G17F19E16J13G12F14
AT14AP13AR16AP18
K21J23G22F24M27K26G27F29
AP28AM27AK26AH25AE26AP23AM22AL24AJ23
U14
R38
R39
R13
R14R12
K9L9P9R9V9W9AB9AC9AF9AG9AK9AL9
K31L31P31R31V31W31
AB31AC31AF31AG31AK31AL31
K8K7P8P7V8V7AB8AB7AF8AF7AK8AK7
K32K33P32P33V32V33
AB32AB33AF32AF33AK32AK33
H9M9T9Y9AD9AH9
H31M31T31Y31
AD31AH31
A12A28AW12AW28
U14
R36
R37
Y25Y24Y23Y19Y18Y17Y15Y14Y13W25W24W22AA20W20W19W17W16W15W14V24V23V22V21V19V18V17V16V14V13U25U24U23U21U20U19
U18U16U15U14U13T25T23T22T21T20T18T17T16T15T13R24R23R22R20R19R18R17R15
AA25AA13AA16AA15
N23N22N21N19N18
AB23AB21AB20AB19
U14
P1V8
P1V8
P1V8
P1V5
00
DNC
DNC
2.00K
2.00K 2.00K
2.00K
A10_VCCT_VCCR_GXB_CURRENTA10_VCC_CURRENT
FPGA_TEMPDIODE_PFPGA_TEMPDIODE_N
26C5 26B5
3B5 3B5
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
ININ
POWER : TRANSCEIVERS10ax115f40
VCCT_GXBR4J_1VCCT_GXBR4J_0VCCT_GXBR4I_1VCCT_GXBR4I_0
VCCT_GXBR4H_1VCCT_GXBR4H_0VCCT_GXBR4G_1VCCT_GXBR4G_0VCCT_GXBR4F_1VCCT_GXBR4F_0VCCT_GXBR4E_1VCCT_GXBR4E_0
VCCT_GXBL1H_1VCCT_GXBL1H_0VCCT_GXBL1G_1VCCT_GXBL1G_0VCCT_GXBL1F_1VCCT_GXBL1F_0VCCT_GXBL1E_1VCCT_GXBL1E_0VCCT_GXBL1D_1VCCT_GXBL1D_0VCCT_GXBL1C_1VCCT_GXBL1C_0
VCCR_GXBR4J_1VCCR_GXBR4J_0VCCR_GXBR4I_1VCCR_GXBR4I_0
VCCR_GXBR4H_1VCCR_GXBR4H_0VCCR_GXBR4G_1VCCR_GXBR4G_0VCCR_GXBR4F_1VCCR_GXBR4F_0VCCR_GXBR4E_1VCCR_GXBR4E_0
VCCR_GXBL1H_1VCCR_GXBL1H_0VCCR_GXBL1G_1VCCR_GXBL1G_0VCCR_GXBL1F_1VCCR_GXBL1F_0VCCR_GXBL1E_1VCCR_GXBL1E_0VCCR_GXBL1D_1VCCR_GXBL1D_0VCCR_GXBL1C_1VCCR_GXBL1C_0
VCCH_GXBR_5VCCH_GXBR_4VCCH_GXBR_3VCCH_GXBR_2VCCH_GXBR_1VCCH_GXBR_0
VCCH_GXBL_5VCCH_GXBL_4VCCH_GXBL_3VCCH_GXBL_2VCCH_GXBL_1VCCH_GXBL_0
RREF_TRRREF_TLRREF_BRRREF_BL
a10_vcc
a10_vcch_vcca_pll
*
VTT_REF
Non Connected10ax115f40
NC_83NC_82NC_81NC_80NC_79NC_78NC_77NC_76NC_75NC_74NC_73NC_72NC_71NC_70NC_69NC_68NC_67NC_66NC_65NC_64NC_63NC_62NC_61NC_60NC_59NC_58NC_57NC_56NC_55NC_54NC_53NC_52NC_51NC_50NC_49NC_48NC_47NC_46NC_45NC_44NC_43NC_42
NC_41NC_40NC_39NC_38NC_37NC_36NC_35NC_34NC_33NC_32NC_31NC_30NC_29NC_28NC_27NC_26NC_25NC_24NC_23NC_22NC_21NC_20NC_19NC_18NC_17NC_16NC_15NC_14NC_13NC_12NC_11NC_10
NC_9NC_8NC_7NC_6NC_5NC_4NC_3NC_2NC_1NC_0
Do Not Use10ax115f40
DNU_48DNU_47DNU_46DNU_45DNU_44DNU_43DNU_42DNU_41DNU_40DNU_39DNU_38DNU_37DNU_36DNU_35DNU_34DNU_33DNU_32DNU_31DNU_30DNU_29DNU_28DNU_27DNU_26DNU_25
DNU_24DNU_23DNU_22DNU_21DNU_20DNU_19DNU_18DNU_17DNU_16DNU_15DNU_14DNU_13DNU_12DNU_11DNU_10
DNU_9DNU_8DNU_7DNU_6DNU_5DNU_4DNU_3DNU_2DNU_1DNU_0
a10_vccpt_vcch_gxb_vcca_pll
OUTOUT
GND
POWER : OTHERS
10ax115f40
VCCLSENSEVSIGP_1VSIGP_0VSIGN_1
VSIGN_0
VCCERAM_4VCCERAM_3VCCERAM_2VCCERAM_1VCCERAM_0
VCCA_FPLL_9VCCA_FPLL_8VCCA_FPLL_7VCCA_FPLL_6VCCA_FPLL_5VCCA_FPLL_4VCCA_FPLL_3VCCA_FPLL_2VCCA_FPLL_1VCCA_FPLL_0
VREFP_ADCVREFN_ADC
VCCBATTEMPDIODEPTEMPDIODEN
VCCPGM_1VCCPGM_0
VCCPT_2_12VCCPT_2_11VCCPT_2_10
VCCPT_2_9VCCPT_2_8VCCPT_2_7VCCPT_2_6VCCPT_2_5VCCPT_2_4VCCPT_2_3VCCPT_2_2VCCPT_2_1VCCPT_2_0
GNDSENSE
ADCGND
*
*
GND
a10_vcch_vcca_pll
a10_vcct_vccr_gxb
a10_vcct_vccr_gxba10_vcct_vccr_gxb
a10_vcct_vccr_gxb
POWER : VCCIO10ax115f40
VREFB3HN0VREFB3GN0
VREFB3BN0VREFB3AN0
VREFB2LN0VREFB2KN0
VREFB2FN0VREFB2AN0
VCCIO_3GH_6VCCIO_3GH_5VCCIO_3GH_4VCCIO_3GH_3VCCIO_3GH_2VCCIO_3GH_1VCCIO_3GH_0
VCCIO_3AB_3VCCIO_3AB_2VCCIO_3AB_1VCCIO_3AB_0
VCCIO_2KL_7VCCIO_2KL_6VCCIO_2KL_5VCCIO_2KL_4VCCIO_2KL_3VCCIO_2KL_2VCCIO_2KL_1VCCIO_2KL_0
VCCIO_2AF_8VCCIO_2AF_7VCCIO_2AF_6VCCIO_2AF_5VCCIO_2AF_4VCCIO_2AF_3VCCIO_2AF_2VCCIO_2AF_1VCCIO_2AF_0
GND
GND
a10_vcc_ram
a10_vcch_vcca_pll
*
*
GND
a10_vcc
*
*
*
POWER : VCC10ax115f40
VCC_70VCC_69VCC_68VCC_67VCC_66VCC_65VCC_64VCC_63VCC_62VCC_61VCC_60VCC_59VCC_58VCC_57VCC_56VCC_55VCC_54VCC_53VCC_52VCC_51VCC_50VCC_49VCC_48VCC_47VCC_46VCC_45VCC_44VCC_43VCC_42VCC_41VCC_40VCC_39VCC_38VCC_37VCC_36
VCC_35VCC_34VCC_33VCC_32VCC_31VCC_30VCC_29VCC_28VCC_27VCC_26VCC_25VCC_24VCC_23VCC_22VCC_21VCC_20VCC_19VCC_18VCC_17VCC_16VCC_15VCC_14VCC_13VCC_12VCC_11VCC_10VCC_9VCC_8VCC_7VCC_6VCC_5VCC_4VCC_3VCC_2VCC_1VCC_0
VSIG : EXTERNAL VOLTAGE SENSOR IF NEEDED
ASSUMPTION : BANK 2AF[1.8V]=IO
ARRIA10 : POWER AND NC
ASSUMPTION : BANK 2KL[1.5V]=DDR3_0 ASSUMPTION : BANK 3GH[1.5V]=DDR3_1 ASSUMPTION : BANK 3AB[1.8V]=OUTPUT TEST PINS,AMC_ID
VREFNADC:INTERNAL REF WHEN TIED TO GNDTIED TO GND IF NOT USED=DEFAULT CONFIGDO NOT DRIVE UNTIL VCCA_PLL HAS REACHED 1.62V
MODIFIE: Mon Mar 23 09:50:40 2015
SHEET: 15 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 15 / 27
P1V8
P1V8
P1V8
P1V5
00
DNC
DNC
2.00K
2.00K 2.00K
2.00K
U14
U14
U14
R15
U14
R38
R39
R13
R14R12
U14
R36
R37
U14
26C5 26B5
3B5 3B5
A10_VCCT_VCCR_GXB_CURRENTA10_VCC_CURRENT
FPGA_TEMPDIODE_PFPGA_TEMPDIODE_N
AE20AE19AC24
P25AC16AC13
P15P20
AC17AC22AC18AC23AD17AD16AD20AD19AC21AC19
J33AF16AE17AF18AE18
U26G30J30K30M30L30
W27V27V26W26P30R30
AA27AA28W29W30Y27
AA26AC29
AB30U29V29Y28Y29AB28AB29U28V28T28T27T26AA11AC11AB11W11W10AM9AB10V11U11V12AM10T11R10R12T12AK10AF11AF10AD11AC27AD27AL10AF30AC28AD29AM31AM30AL30AJ30AE15
P10Y22Y20
AF17AV12AV13AG16AH16AH17AG15AC26AE14AF15AD26AF13AG18AE13AH18AH13AG13AH19AF21AG21AG14
AL15AH21AL11AJ11AK13AH14AJ12AK12AK15AL12AJ15Y12W12AH12AA12AG11AH11AC12AD12AK14AJ14AF12AE12AV28AV27
J8L10
J7
K10J10G10
P24P22N24P19P16N16AD15AD14AC14AD25AD24AD22AD21
AF20AG20
W21
AB18AA23AA22AA18AA17
AG19
AB24AB16AB13
R14P21R25
AB14AB25AB15AB26
N17P17
Y21
J32
M19R13
AL13AN17
M24P26
AE27AF23
J18G17F19E16J13G12F14
AT14AP13AR16AP18
K21J23G22F24M27K26G27F29
AP28AM27AK26AH25AE26AP23AM22AL24AJ23K9
L9P9R9V9W9AB9AC9AF9AG9AK9AL9
K31L31P31R31V31W31
AB31AC31AF31AG31AK31AL31
K8K7P8P7V8V7AB8AB7AF8AF7AK8AK7
K32K33P32P33V32V33
AB32AB33AF32AF33AK32AK33
H9M9T9Y9AD9AH9
H31M31T31Y31
AD31AH31
A12A28AW12AW28
Y25Y24Y23Y19Y18Y17Y15Y14Y13W25W24W22AA20W20W19W17W16W15W14V24V23V22V21V19V18V17V16V14V13U25U24U23U21U20U19
U18U16U15U14U13T25T23T22T21T20T18T17T16T15T13R24R23R22R20R19R18R17R15
AA25AA13AA16AA15
N23N22N21N19N18
AB23AB21AB20AB19
ININ
POWER : TRANSCEIVERS10ax115f40
VCCT_GXBR4J_1VCCT_GXBR4J_0VCCT_GXBR4I_1VCCT_GXBR4I_0
VCCT_GXBR4H_1VCCT_GXBR4H_0VCCT_GXBR4G_1VCCT_GXBR4G_0VCCT_GXBR4F_1VCCT_GXBR4F_0VCCT_GXBR4E_1VCCT_GXBR4E_0
VCCT_GXBL1H_1VCCT_GXBL1H_0VCCT_GXBL1G_1VCCT_GXBL1G_0VCCT_GXBL1F_1VCCT_GXBL1F_0VCCT_GXBL1E_1VCCT_GXBL1E_0VCCT_GXBL1D_1VCCT_GXBL1D_0VCCT_GXBL1C_1VCCT_GXBL1C_0
VCCR_GXBR4J_1VCCR_GXBR4J_0VCCR_GXBR4I_1VCCR_GXBR4I_0
VCCR_GXBR4H_1VCCR_GXBR4H_0VCCR_GXBR4G_1VCCR_GXBR4G_0VCCR_GXBR4F_1VCCR_GXBR4F_0VCCR_GXBR4E_1VCCR_GXBR4E_0
VCCR_GXBL1H_1VCCR_GXBL1H_0VCCR_GXBL1G_1VCCR_GXBL1G_0VCCR_GXBL1F_1VCCR_GXBL1F_0VCCR_GXBL1E_1VCCR_GXBL1E_0VCCR_GXBL1D_1VCCR_GXBL1D_0VCCR_GXBL1C_1VCCR_GXBL1C_0
VCCH_GXBR_5VCCH_GXBR_4VCCH_GXBR_3VCCH_GXBR_2VCCH_GXBR_1VCCH_GXBR_0
VCCH_GXBL_5VCCH_GXBL_4VCCH_GXBL_3VCCH_GXBL_2VCCH_GXBL_1VCCH_GXBL_0
RREF_TRRREF_TLRREF_BRRREF_BL
a10_vcc
a10_vcch_vcca_pll
*
VTT_REF
Non Connected10ax115f40
NC_83NC_82NC_81NC_80NC_79NC_78NC_77NC_76NC_75NC_74NC_73NC_72NC_71NC_70NC_69NC_68NC_67NC_66NC_65NC_64NC_63NC_62NC_61NC_60NC_59NC_58NC_57NC_56NC_55NC_54NC_53NC_52NC_51NC_50NC_49NC_48NC_47NC_46NC_45NC_44NC_43NC_42
NC_41NC_40NC_39NC_38NC_37NC_36NC_35NC_34NC_33NC_32NC_31NC_30NC_29NC_28NC_27NC_26NC_25NC_24NC_23NC_22NC_21NC_20NC_19NC_18NC_17NC_16NC_15NC_14NC_13NC_12NC_11NC_10
NC_9NC_8NC_7NC_6NC_5NC_4NC_3NC_2NC_1NC_0
Do Not Use10ax115f40
DNU_48DNU_47DNU_46DNU_45DNU_44DNU_43DNU_42DNU_41DNU_40DNU_39DNU_38DNU_37DNU_36DNU_35DNU_34DNU_33DNU_32DNU_31DNU_30DNU_29DNU_28DNU_27DNU_26DNU_25
DNU_24DNU_23DNU_22DNU_21DNU_20DNU_19DNU_18DNU_17DNU_16DNU_15DNU_14DNU_13DNU_12DNU_11DNU_10
DNU_9DNU_8DNU_7DNU_6DNU_5DNU_4DNU_3DNU_2DNU_1DNU_0
a10_vccpt_vcch_gxb_vcca_pll
OUTOUT
GND
POWER : OTHERS
10ax115f40
VCCLSENSEVSIGP_1VSIGP_0VSIGN_1
VSIGN_0
VCCERAM_4VCCERAM_3VCCERAM_2VCCERAM_1VCCERAM_0
VCCA_FPLL_9VCCA_FPLL_8VCCA_FPLL_7VCCA_FPLL_6VCCA_FPLL_5VCCA_FPLL_4VCCA_FPLL_3VCCA_FPLL_2VCCA_FPLL_1VCCA_FPLL_0
VREFP_ADCVREFN_ADC
VCCBATTEMPDIODEPTEMPDIODEN
VCCPGM_1VCCPGM_0
VCCPT_2_12VCCPT_2_11VCCPT_2_10
VCCPT_2_9VCCPT_2_8VCCPT_2_7VCCPT_2_6VCCPT_2_5VCCPT_2_4VCCPT_2_3VCCPT_2_2VCCPT_2_1VCCPT_2_0
GNDSENSE
ADCGND
*
*
GND
a10_vcch_vcca_pll
a10_vcct_vccr_gxb
a10_vcct_vccr_gxba10_vcct_vccr_gxb
a10_vcct_vccr_gxb
POWER : VCCIO10ax115f40
VREFB3HN0VREFB3GN0
VREFB3BN0VREFB3AN0
VREFB2LN0VREFB2KN0
VREFB2FN0VREFB2AN0
VCCIO_3GH_6VCCIO_3GH_5VCCIO_3GH_4VCCIO_3GH_3VCCIO_3GH_2VCCIO_3GH_1VCCIO_3GH_0
VCCIO_3AB_3VCCIO_3AB_2VCCIO_3AB_1VCCIO_3AB_0
VCCIO_2KL_7VCCIO_2KL_6VCCIO_2KL_5VCCIO_2KL_4VCCIO_2KL_3VCCIO_2KL_2VCCIO_2KL_1VCCIO_2KL_0
VCCIO_2AF_8VCCIO_2AF_7VCCIO_2AF_6VCCIO_2AF_5VCCIO_2AF_4VCCIO_2AF_3VCCIO_2AF_2VCCIO_2AF_1VCCIO_2AF_0
GND
GND
a10_vcc_ram
a10_vcch_vcca_pll
*
*
GND
a10_vcc
*
*
*
POWER : VCC10ax115f40
VCC_70VCC_69VCC_68VCC_67VCC_66VCC_65VCC_64VCC_63VCC_62VCC_61VCC_60VCC_59VCC_58VCC_57VCC_56VCC_55VCC_54VCC_53VCC_52VCC_51VCC_50VCC_49VCC_48VCC_47VCC_46VCC_45VCC_44VCC_43VCC_42VCC_41VCC_40VCC_39VCC_38VCC_37VCC_36
VCC_35VCC_34VCC_33VCC_32VCC_31VCC_30VCC_29VCC_28VCC_27VCC_26VCC_25VCC_24VCC_23VCC_22VCC_21VCC_20VCC_19VCC_18VCC_17VCC_16VCC_15VCC_14VCC_13VCC_12VCC_11VCC_10VCC_9VCC_8VCC_7VCC_6VCC_5VCC_4VCC_3VCC_2VCC_1VCC_0
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
ARRIA10:GROUND
MODIFIE: Mon Mar 23 09:50:46 2015
SHEET: 16 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 16 / 27
Y8Y7Y4Y3W6W5W2W1V4V3U9U6U5U2U10U1T8T7T4T3R6R5R2R1P4P3N9N6N5N2N1M8M7M4M3M10L6L5L2L1K4K3J9J6J5J2J1H8H7H4
H3G9G8G7G6G5G2G1F8F7F4F3E9E6E5E2E1D9D8D7D4D3C9C6C5C2
C11C10
C1B8B7B4B3
B13B12B11
AW9AW6AW5AW2
AW13AW11AW10
AV8AV7AV4AV3
AV11AU9AU6
U14
AU5AU2AU11AU10AU1AT9AT8AT7AT4AT3AR9AR6AR5AR2AR1AP9AP8AP7AP4AP3AN8AN7AN6AN5AN2AN1AM8AM7AM4AM3AL6AL5AL2AL1AK4AK3AJ9AJ6AJ5AJ2AJ1AH8AH7AH4AH3AG6AG5AG2AG1AF4
AF3AE9AE6AE5AE2AE1AD8AD7AD4AD3AC6AC5AC2AC1AB4AB3AA9AA6AA5AA2AA1
A9A6A5A2
A13A11A10Y37Y36Y33Y32W39W38W35W34V37V36U39U38U35U34U31U30T37T36T33T32R39R38
U14
R35R34P37P36N39N38N35N34N31M37M36M33M32L39L38L35L34K37K36J39J38J35J34J31H37H36H33H32G39G38G35G34G33G32G31F37F36F33F32E39E38E35E34E31D37D36D33D32D31C39
C38C35C34C31C30C29B37B36B33B32B29B28B27
AW38AW35AW34AW31AW30AW29AW27AV37AV36AV33AV32AV29AU39AU38AU35AU34AU31AU30AU29AT37AT36AT33AT32AT31AR39AR38AR35AR34AR31AP37AP36AP33AP32AP31AN39AN38AN35
U14
AN34AN33AN32AM37AM36AM33AM32AL39AL38AL35AL34AK37AK36AJ39AJ38AJ35AJ34AJ31AH37AH36AH33AH32AG39AG38AG35AG34AF37AF36AE39AE38AE35AE34AE31AD37AD36AD33AD32AC39AC38AC35AC34AB37AB36AA39AA38AA35AA34AA31AA30A38
A35A34A31A30A29A27Y30Y26
AA21Y16Y11Y10W28W23W18W13V30V25V20V15V10U27U22U17U12T30T29T24T19T14T10R26R21R16R11P28P23P18P13N30N25N20N15N10M22M17M12L29L24L19
U14
L14K16K11J28H30H25H20H15H10F9F31E26E21E11D28D23D18D13C25C20C15B22B17AW23AW18AV25AV20AV15AU27AU22AU17AU12AT29AT24AT19AR26AR21AR11AN30AN25AN20AN15AN10AM17AM12AL29AL19AL14AK30AK21
AK16AK11AJ28AJ18AJ13AJ10AH30AH20AH15AH10AG30AG27AG22AG17AG12AG10AF29AF24AF19AF14AE30AE21AE16AE11AE10AD30AD28AD23AD18AD13AD10AC30AC25AC20AC15AC10AB27AB22AB17AB12AA29AA24AA19AA14AA10
A24A19A14
AK20AN18
U14
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
GND_210ax115f40
GND_299GND_298GND_297GND_296GND_295GND_294GND_293GND_292GND_291GND_290GND_289GND_288GND_287GND_286GND_285GND_284GND_283GND_282GND_281GND_280GND_279GND_278GND_277GND_276GND_275GND_274GND_273GND_272GND_271GND_270GND_269GND_268GND_267GND_266GND_265GND_264GND_263GND_262GND_261GND_260GND_259GND_258GND_257GND_256GND_255GND_254GND_253GND_252GND_251GND_250
GND_249GND_248GND_247GND_246GND_245GND_244GND_243GND_242GND_241GND_240GND_239GND_238GND_237GND_236GND_235GND_234GND_233GND_232GND_231GND_230GND_229GND_228GND_227GND_226GND_225GND_224GND_223GND_222GND_221GND_220GND_219GND_218GND_217GND_216GND_215GND_214GND_213GND_212GND_211GND_210GND_209GND_208GND_207GND_206GND_205GND_204GND_203GND_202GND_201GND_200
GNDGND GND
GND_110ax115f40
GND_199GND_198GND_197GND_196GND_195GND_194GND_193GND_192GND_191GND_190GND_189GND_188GND_187GND_186GND_185GND_184GND_183GND_182GND_181GND_180GND_179GND_178GND_177GND_176GND_175GND_174GND_173GND_172GND_171GND_170GND_169GND_168GND_167GND_166GND_165GND_164GND_163GND_162GND_161GND_160GND_159GND_158GND_157GND_156GND_155GND_154GND_153GND_152GND_151GND_150
GND_149GND_148GND_147GND_146GND_145GND_144GND_143GND_142GND_141GND_140GND_139GND_138GND_137GND_136GND_135GND_134GND_133GND_132GND_131GND_130GND_129GND_128GND_127GND_126GND_125GND_124GND_123GND_122GND_121GND_120GND_119GND_118GND_117GND_116GND_115GND_114GND_113GND_112GND_111GND_110GND_109GND_108GND_107GND_106GND_105GND_104GND_103GND_102GND_101GND_100
GND_010ax115f40
GND_99GND_98GND_97GND_96GND_95GND_94GND_93GND_92GND_91GND_90GND_89GND_88GND_87GND_86GND_85GND_84GND_83GND_82GND_81GND_80GND_79GND_78GND_77GND_76GND_75GND_74GND_73GND_72GND_71GND_70GND_69GND_68GND_67GND_66GND_65GND_64GND_63GND_62GND_61GND_60GND_59GND_58GND_57GND_56GND_55GND_54GND_53GND_52GND_51GND_50
GND_49GND_48GND_47GND_46GND_45GND_44GND_43GND_42GND_41GND_40GND_39GND_38GND_37GND_36GND_35GND_34GND_33GND_32GND_31GND_30GND_29GND_28GND_27GND_26GND_25GND_24GND_23GND_22GND_21GND_20GND_19GND_18GND_17GND_16GND_15GND_14GND_13GND_12GND_11GND_10GND_9GND_8GND_7GND_6GND_5GND_4GND_3GND_2GND_1GND_0
GND GND GND
GND_410ax115f40
GND_499GND_498GND_497GND_496GND_495GND_494GND_493GND_492GND_491GND_490GND_489GND_488GND_487GND_486GND_485GND_484GND_483GND_482GND_481GND_480GND_479GND_478GND_477GND_476GND_475GND_474GND_473GND_472GND_471GND_470GND_469GND_468GND_467GND_466GND_465GND_464GND_463GND_462GND_461GND_460GND_459GND_458GND_457GND_456GND_455GND_454GND_453GND_452GND_451GND_450
GND_449GND_448GND_447GND_446GND_445GND_444GND_443GND_442GND_441GND_440GND_439GND_438GND_437GND_436GND_435GND_434GND_433GND_432GND_431GND_430GND_429GND_428GND_427GND_426GND_425GND_424GND_423GND_422GND_421GND_420GND_419GND_418GND_417GND_416GND_415GND_414GND_413GND_412GND_411GND_410GND_409GND_408GND_407GND_406GND_405GND_404GND_403GND_402GND_401GND_400
GND_310ax115f40
GND_399GND_398GND_397GND_396GND_395GND_394GND_393GND_392GND_391GND_390GND_389GND_388GND_387GND_386GND_385GND_384GND_383GND_382GND_381GND_380GND_379GND_378GND_377GND_376GND_375GND_374GND_373GND_372GND_371GND_370GND_369GND_368GND_367GND_366GND_365GND_364GND_363GND_362GND_361GND_360GND_359GND_358GND_357GND_356GND_355GND_354GND_353GND_352GND_351GND_350
GND_349GND_348GND_347GND_346GND_345GND_344GND_343GND_342GND_341GND_340GND_339GND_338GND_337GND_336GND_335GND_334GND_333GND_332GND_331GND_330GND_329GND_328GND_327GND_326GND_325GND_324GND_323GND_322GND_321GND_320GND_319GND_318GND_317GND_316GND_315GND_314GND_313GND_312GND_311GND_310GND_309GND_308GND_307GND_306GND_305GND_304GND_303GND_302GND_301GND_300
GNDGNDGNDGND
ARRIA10:GROUND
MODIFIE: Mon Mar 23 09:50:46 2015
SHEET: 16 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 16 / 27
U14U14U14U14U14
Y8Y7Y4Y3W6W5W2W1V4V3U9U6U5U2U10U1T8T7T4T3R6R5R2R1P4P3N9N6N5N2N1M8M7M4M3M10L6L5L2L1K4K3J9J6J5J2J1H8H7H4
H3G9G8G7G6G5G2G1F8F7F4F3E9E6E5E2E1D9D8D7D4D3C9C6C5C2
C11C10
C1B8B7B4B3
B13B12B11
AW9AW6AW5AW2
AW13AW11AW10
AV8AV7AV4AV3
AV11AU9AU6
AU5AU2AU11AU10AU1AT9AT8AT7AT4AT3AR9AR6AR5AR2AR1AP9AP8AP7AP4AP3AN8AN7AN6AN5AN2AN1AM8AM7AM4AM3AL6AL5AL2AL1AK4AK3AJ9AJ6AJ5AJ2AJ1AH8AH7AH4AH3AG6AG5AG2AG1AF4
AF3AE9AE6AE5AE2AE1AD8AD7AD4AD3AC6AC5AC2AC1AB4AB3AA9AA6AA5AA2AA1
A9A6A5A2
A13A11A10Y37Y36Y33Y32W39W38W35W34V37V36U39U38U35U34U31U30T37T36T33T32R39R38
R35R34P37P36N39N38N35N34N31M37M36M33M32L39L38L35L34K37K36J39J38J35J34J31H37H36H33H32G39G38G35G34G33G32G31F37F36F33F32E39E38E35E34E31D37D36D33D32D31C39
C38C35C34C31C30C29B37B36B33B32B29B28B27
AW38AW35AW34AW31AW30AW29AW27AV37AV36AV33AV32AV29AU39AU38AU35AU34AU31AU30AU29AT37AT36AT33AT32AT31AR39AR38AR35AR34AR31AP37AP36AP33AP32AP31AN39AN38AN35
AN34AN33AN32AM37AM36AM33AM32AL39AL38AL35AL34AK37AK36AJ39AJ38AJ35AJ34AJ31AH37AH36AH33AH32AG39AG38AG35AG34AF37AF36AE39AE38AE35AE34AE31AD37AD36AD33AD32AC39AC38AC35AC34AB37AB36AA39AA38AA35AA34AA31AA30A38
A35A34A31A30A29A27Y30Y26
AA21Y16Y11Y10W28W23W18W13V30V25V20V15V10U27U22U17U12T30T29T24T19T14T10R26R21R16R11P28P23P18P13N30N25N20N15N10M22M17M12L29L24L19
L14K16K11J28H30H25H20H15H10F9F31E26E21E11D28D23D18D13C25C20C15B22B17AW23AW18AV25AV20AV15AU27AU22AU17AU12AT29AT24AT19AR26AR21AR11AN30AN25AN20AN15AN10AM17AM12AL29AL19AL14AK30AK21
AK16AK11AJ28AJ18AJ13AJ10AH30AH20AH15AH10AG30AG27AG22AG17AG12AG10AF29AF24AF19AF14AE30AE21AE16AE11AE10AD30AD28AD23AD18AD13AD10AC30AC25AC20AC15AC10AB27AB22AB17AB12AA29AA24AA19AA14AA10
A24A19A14
AK20AN18
GND_210ax115f40
GND_299GND_298GND_297GND_296GND_295GND_294GND_293GND_292GND_291GND_290GND_289GND_288GND_287GND_286GND_285GND_284GND_283GND_282GND_281GND_280GND_279GND_278GND_277GND_276GND_275GND_274GND_273GND_272GND_271GND_270GND_269GND_268GND_267GND_266GND_265GND_264GND_263GND_262GND_261GND_260GND_259GND_258GND_257GND_256GND_255GND_254GND_253GND_252GND_251GND_250
GND_249GND_248GND_247GND_246GND_245GND_244GND_243GND_242GND_241GND_240GND_239GND_238GND_237GND_236GND_235GND_234GND_233GND_232GND_231GND_230GND_229GND_228GND_227GND_226GND_225GND_224GND_223GND_222GND_221GND_220GND_219GND_218GND_217GND_216GND_215GND_214GND_213GND_212GND_211GND_210GND_209GND_208GND_207GND_206GND_205GND_204GND_203GND_202GND_201GND_200
GNDGND GND
GND_110ax115f40
GND_199GND_198GND_197GND_196GND_195GND_194GND_193GND_192GND_191GND_190GND_189GND_188GND_187GND_186GND_185GND_184GND_183GND_182GND_181GND_180GND_179GND_178GND_177GND_176GND_175GND_174GND_173GND_172GND_171GND_170GND_169GND_168GND_167GND_166GND_165GND_164GND_163GND_162GND_161GND_160GND_159GND_158GND_157GND_156GND_155GND_154GND_153GND_152GND_151GND_150
GND_149GND_148GND_147GND_146GND_145GND_144GND_143GND_142GND_141GND_140GND_139GND_138GND_137GND_136GND_135GND_134GND_133GND_132GND_131GND_130GND_129GND_128GND_127GND_126GND_125GND_124GND_123GND_122GND_121GND_120GND_119GND_118GND_117GND_116GND_115GND_114GND_113GND_112GND_111GND_110GND_109GND_108GND_107GND_106GND_105GND_104GND_103GND_102GND_101GND_100
GND_010ax115f40
GND_99GND_98GND_97GND_96GND_95GND_94GND_93GND_92GND_91GND_90GND_89GND_88GND_87GND_86GND_85GND_84GND_83GND_82GND_81GND_80GND_79GND_78GND_77GND_76GND_75GND_74GND_73GND_72GND_71GND_70GND_69GND_68GND_67GND_66GND_65GND_64GND_63GND_62GND_61GND_60GND_59GND_58GND_57GND_56GND_55GND_54GND_53GND_52GND_51GND_50
GND_49GND_48GND_47GND_46GND_45GND_44GND_43GND_42GND_41GND_40GND_39GND_38GND_37GND_36GND_35GND_34GND_33GND_32GND_31GND_30GND_29GND_28GND_27GND_26GND_25GND_24GND_23GND_22GND_21GND_20GND_19GND_18GND_17GND_16GND_15GND_14GND_13GND_12GND_11GND_10GND_9GND_8GND_7GND_6GND_5GND_4GND_3GND_2GND_1GND_0
GND GND GND
GND_410ax115f40
GND_499GND_498GND_497GND_496GND_495GND_494GND_493GND_492GND_491GND_490GND_489GND_488GND_487GND_486GND_485GND_484GND_483GND_482GND_481GND_480GND_479GND_478GND_477GND_476GND_475GND_474GND_473GND_472GND_471GND_470GND_469GND_468GND_467GND_466GND_465GND_464GND_463GND_462GND_461GND_460GND_459GND_458GND_457GND_456GND_455GND_454GND_453GND_452GND_451GND_450
GND_449GND_448GND_447GND_446GND_445GND_444GND_443GND_442GND_441GND_440GND_439GND_438GND_437GND_436GND_435GND_434GND_433GND_432GND_431GND_430GND_429GND_428GND_427GND_426GND_425GND_424GND_423GND_422GND_421GND_420GND_419GND_418GND_417GND_416GND_415GND_414GND_413GND_412GND_411GND_410GND_409GND_408GND_407GND_406GND_405GND_404GND_403GND_402GND_401GND_400
GND_310ax115f40
GND_399GND_398GND_397GND_396GND_395GND_394GND_393GND_392GND_391GND_390GND_389GND_388GND_387GND_386GND_385GND_384GND_383GND_382GND_381GND_380GND_379GND_378GND_377GND_376GND_375GND_374GND_373GND_372GND_371GND_370GND_369GND_368GND_367GND_366GND_365GND_364GND_363GND_362GND_361GND_360GND_359GND_358GND_357GND_356GND_355GND_354GND_353GND_352GND_351GND_350
GND_349GND_348GND_347GND_346GND_345GND_344GND_343GND_342GND_341GND_340GND_339GND_338GND_337GND_336GND_335GND_334GND_333GND_332GND_331GND_330GND_329GND_328GND_327GND_326GND_325GND_324GND_323GND_322GND_321GND_320GND_319GND_318GND_317GND_316GND_315GND_314GND_313GND_312GND_311GND_310GND_309GND_308GND_307GND_306GND_305GND_304GND_303GND_302GND_301GND_300
GNDGNDGNDGND
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
A10 VCCPT VCCH_GXB VCCA_PLL DECOUPLING
A10 VCC DECOUPLING
A10 P1V8 DECOUPLING
A10 VCCRAM DECOUPLING
ARRIA10 DECOUPLING
A10 P1V5 DECOUPLING
A10 VCCT_GXB AND VCCR_GXB DECOUPLING
MODIFIE: Mon Mar 23 09:50:46 2015
SHEET: 17 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 17 / 27
C337C336C335C334C333C332C329
C330
C326C323C320C317
C327C324C321C318
C314C311C308C305
C315C312C309C306
C331C325C328C319C322C313C316C307C310C302
C303
C304
C300
C301
C295C290C285
C296C291C286
C280
C281
C275C270C265
C276C271C266
C260
C261
C256
C257
C254C252C250
C255C253C251
C248
C249
C245C242C239
C246C243C240
C236
C237
C231C226C221
C232C227C222C217
C216C211C206C201C196
C212C207C202C197
C191
C192
C297C292C287C282C277C272C267
C298C293C288C283C278C273C268
C262
C263
C540C539C538C537
C258
C299C294C289C284C279C274C269C264C259
C536C535C534C533C532C531C530C529
C247C244C241C238
C233C228C218C223
C234C229
C235C230
C224C219
C225C220
C528C527C526C525C524C523
C213C208C203C198
C214C209
C215C210
C204C199
C205C200
C193
C194
C195
P1V8
P1V5
1.0N
1.0N
1.0N
1.0N
1.0N
1.0N
1.0N
1.0N
1.0N
100N
100N
10N
10N
100N
100N
100N
100N
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
100U
100U
100N
1.0U
1.0U
1.0U
100N
100N
100N
100U
100N
100N
100N
100N
100N
100N
100N
100N
100U
100U
100U
100N
100N
10N
10N
100N
100N
100N
100N
100N
100N
100N
10N
10N
100U
100U
100N
100N
100N
100U
100U
100U
100N
100N
1.0N
1.0N
1.0N
1.0N
1.0N
10N
1.0U
1.0U
1.0U
10N
10N
10N
10N
10N
1.0N
1.0U
1.0U
1.0N
1.0N
1.0N
10N
100N
1.0U
100N
10N
100N
1.0U
1.0U
100N
100N
10N
10N
100N
10N
10N
100N
10N
10N
100N
100N
10N
10N
10N
10N
100N
100N
10N
10N
100N
100N
100N
10N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100U
100N
100N
100U
100U
100N
100U
100N
100U
100N
100N
100N
100N
100N
100N
100N
1.0U
100N
100N
100N
FPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLING
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
a10_vcc
GND
a10_vccpt_vcch_gxb_vcca_pll
GND
a10_vcc_ram
a10_vcch_vcca_pllGND
GND
GND
a10_vcct_vccr_gxb
GND
A10 VCCPT VCCH_GXB VCCA_PLL DECOUPLING
A10 VCC DECOUPLING
A10 P1V8 DECOUPLING
A10 VCCRAM DECOUPLING
ARRIA10 DECOUPLING
A10 P1V5 DECOUPLING
A10 VCCT_GXB AND VCCR_GXB DECOUPLING
MODIFIE: Mon Mar 23 09:50:46 2015
SHEET: 17 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 17 / 27
P1V8
P1V5
1.0N
1.0N
1.0N
1.0N
1.0N
1.0N
1.0N
1.0N
1.0N
100N
100N
10N
10N
100N
100N
100N
100N
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
10U
100U
100U
100N
1.0U
1.0U
1.0U
100N
100N
100N
100U
100N
100N
100N
100N
100N
100N
100N
100N
100U
100U
100U
100N
100N
10N
10N
100N
100N
100N
100N
100N
100N
100N
10N
10N
100U
100U
100N
100N
100N
100U
100U
100U
100N
100N
1.0N
1.0N
1.0N
1.0N
1.0N
10N
1.0U
1.0U
1.0U
10N
10N
10N
10N
10N
1.0N
1.0U
1.0U
1.0N
1.0N
1.0N
10N
100N
1.0U
100N
10N
100N
1.0U
1.0U
100N
100N
10N
10N
100N
10N
10N
100N
10N
10N
100N
100N
10N
10N
10N
10N
100N
100N
10N
10N
100N
100N
100N
10N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100U
100N
100N
100U
100U
100N
100U
100N
100U
100N
100N
100N
100N
100N
100N
100N
1.0U
100N
100N
100N
FPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLINGFPGA DECOUPLING
C337C336C335C334C333C332C329
C330
C326C323C320C317
C327C324C321C318
C314C311C308C305
C315C312C309C306
C331C325C328C319C322C313C316C307C310C302
C303
C304
C300
C301
C295C290C285
C296C291C286
C280
C281
C275C270C265
C276C271C266
C260
C261
C256
C257
C254C252C250
C255C253C251
C248
C249
C245C242C239
C246C243C240
C236
C237
C231C226C221
C232C227C222C217
C216C211C206C201C196
C212C207C202C197
C191
C192
C297C292C287C282C277C272C267
C298C293C288C283C278C273C268
C262
C263
C540C539C538C537
C258
C299C294C289C284C279C274C269C264C259
C536C535C534C533C532C531C530C529
C247C244C241C238
C233C228C218C223
C234C229
C235C230
C224C219
C225C220
C528C527C526C525C524C523
C213C208C203C198
C214C209
C215C210
C204C199
C205C200
C193
C194
C195
a10_vcc
GND
a10_vccpt_vcch_gxb_vcca_pll
GND
a10_vcc_ram
a10_vcch_vcca_pllGND
GND
GND
a10_vcct_vccr_gxb
GND
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
AS STANDARD CONFIGMSEL=011 =>STANDARDMSEL=010 =>FAST
ARRIA10 CLOCKS AND CONFIGURATION
DDR3 REF CLOCKS COME FROM INTERNAL FPGA PLL (IO 1.5V)DDR3 REF CLOCKS SHOULD HAVE THE FREQUENCY GIVEN BYMGWZ
LVDS IO : 0.247<VOD<0.6 1.125<VOCM<1.375 VOCM=1.25 TYPICAL
MODIFIE: Mon Mar 23 09:50:41 2015
SHEET: 18 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 18 / 27
R194
R195
R43
AL20
AJ20 AM21AK18AP20
AL17
AN19
AM18AJ16AR20
AJ17AK19
AJ21AL21AJ19
AM19
AK17
AM20AN21AL18AP21
U14
B4 C2
B3
B2
D4C4D2D3
U15
C338
R42R41R40
B16A16B15A15M14M15J14J15AN14AM14AV14AU14AP16AU16B25A25K24K23F27E27H26J25AR29AP29AG25AG24AV26AU26AR24AP24
G19H19D16C16N13N12K15L15
AT10AR10AU13AT13
AW19AT16
A21B21E24D24M28N28G26F26
AL27AK27AR27AR28AE22AF22
AW25AW26
U14
DDR3_0_A<7> 9E7
DDR3_0_DQS0_N 9D5 DDR3_0_DQS0_P
DDR3_0_A<6>
P1V8
P1V8
P1V8
P1V8
0
DNC
100N
10K
1K10K
10K
FPGA_JTAG_MOSIFPGA_JTAG_MISO
FPGA_CONFDONE
EPCQL_DATA3EPCQL_DCLKEPCQL_NCS
EPCQL_DATA3EPCQL_DATA2
EPCQL_DCLKEPCQL_DATA0EPCQL_DATA1
DDR3_1_DQ<10>DDR3_1_DQ<12>
DDR3_1_A<7>DDR3_1_A<6>
DDR3_1_A<13>DDR3_1_CLK
TTC_CORE_CLK_N
SYS_CLK
DDR3_1_A<10>
DDR3_0_DM0DDR3_0_A<11>DDR3_0_A<10>
DDR3_0_CLK
DDR3_1_DM1
DDR3_0_DQ<0>
DDR3_1_DQ<8>
DDR3_1_A<11>
DDR3_0_A<13>
EPCQL_NCS
TTC_CORE_CLK_P
EPCQL_DATA0EPCQL_DATA1EPCQL_DATA2
FPGA_NCONFIG
FPGA_NSTATUS
FPGA_JTAG_TCKFPGA_JTAG_TMS
FPGA_JTAG_TRST
FPGA
FPGA
18D5 18D5
18D5 18D5
18D5 9D5
9E7
9C2 9C2
9C4 9C4
9C4 10C1
11B2
10C6
9C4
9D7
9D7 9E7
10E1
9C4
9D5
9C2
9C4
9D7
18D5
11B2
18B1 18B1 18B1 18B1
18B1
25D1
18B1
24C1 24C1
24C1 24C1
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
OUTOUT
IN
OUT
OUTIN
*
*
*
ININ
GND
BI
ININ
BIOUTOUTOUT
AS CONFIG
JTAG
CONFIGURATION
10ax115f40
TRST
TMSTDOTDI
TCK
NSTATUS
NIO_PULLUP
NCSO2NCSO1NCSO0
NCONFIGNCE
MSEL2MSEL1MSEL0
DCLK
CONF_DONE
ASDATA3ASDATA2ASDATA1ASDATA0_ASDO
epcq_l
GND
VCC
DATA3DATA2DATA1DATA0
DCLKNCS
CLOCKS & PLL10ax115f40
PLL_3B_CLKOUT0P
PLL_3H_CLKOUT1PPLL_3H_CLKOUT1N
PLL_3H_CLKOUT0PPLL_3H_CLKOUT0N
PLL_3G_CLKOUT1PPLL_3G_CLKOUT1N
PLL_3G_CLKOUT0PPLL_3G_CLKOUT0N
PLL_3B_CLKOUT1PPLL_3B_CLKOUT1N
PLL_3B_CLKOUT0N
PLL_3A_CLKOUT1NPLL_3A_CLKOUT0N
PLL_2L_CLKOUT1PPLL_2L_CLKOUT1N
PLL_2L_CLKOUT0PPLL_2L_CLKOUT0N
PLL_2K_CLKOUT1PPLL_2K_CLKOUT1N
PLL_2K_CLKOUT0PPLL_2K_CLKOUT0N
PLL_2F_CLKOUT1PPLL_2F_CLKOUT1N
PLL_2F_CLKOUT0PPLL_2F_CLKOUT0N
PLL_2A_CLKOUT1P_DATA19PLL_2A_CLKOUT1N_DATA18
PLL_2A_CLKOUT0P_DATA27PLL_2A_CLKOUT0N_DATA26
CLK_3H_1PCLK_3H_1N
CLK_3H_0PCLK_3H_0N
CLK_3G_1PCLK_3G_1N
CLK_3G_0PCLK_3G_0N
CLK_3B_1PCLK_3B_1N
CLK_3B_0PCLK_3B_0N
CLK_3A_1NCLK_3A_0N
CLK_2L_1PCLK_2L_1N
CLK_2L_0PCLK_2L_0N
CLK_2K_1PCLK_2K_1N
CLK_2K_0PCLK_2K_0N
CLK_2F_1PCLK_2F_1N
CLK_2F_0PCLK_2F_0N
CLK_2A_1P_DATA21CLK_2A_1N_DATA20
CLK_2A_0P_DATA23CLK_2A_0N_DATA22
GND
GN
D
BIINININ
OUTOUT
GND
OUT***
BI
BIBI
OUTOUT
OUT
OUT
BIBI
OUTOUT
OUT
IN
ININ
OUTBI
IN
AS STANDARD CONFIGMSEL=011 =>STANDARDMSEL=010 =>FAST
ARRIA10 CLOCKS AND CONFIGURATION
DDR3 REF CLOCKS COME FROM INTERNAL FPGA PLL (IO 1.5V)DDR3 REF CLOCKS SHOULD HAVE THE FREQUENCY GIVEN BYMGWZ
LVDS IO : 0.247<VOD<0.6 1.125<VOCM<1.375 VOCM=1.25 TYPICAL
MODIFIE: Mon Mar 23 09:50:41 2015
SHEET: 18 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 18 / 27
P1V8
P1V8
P1V8
P1V8
0
DNC
100N
10K
1K10K
10K
FPGA
FPGAR194
R195
R43
U14
U15
C338
R42R41R40
U14
9E7
9D5
18D5 18D5
18D5 18D5
18D5 9D5
9E7
9C2 9C2
9C4 9C4
9C4 10C1
11B2
10C6
9C4
9D7
9D7 9E7
10E1
9C4
9D5
9C2
9C4
9D7
18D5
11B2
18B1 18B1 18B1 18B1
18B1
25D1
18B1
24C1 24C1
24C1 24C1
DDR3_0_A<7>
DDR3_0_DQS0_NDDR3_0_DQS0_P
DDR3_0_A<6>
FPGA_JTAG_MOSIFPGA_JTAG_MISO
FPGA_CONFDONE
EPCQL_DATA3EPCQL_DCLKEPCQL_NCS
EPCQL_DATA3EPCQL_DATA2
EPCQL_DCLKEPCQL_DATA0EPCQL_DATA1
DDR3_1_DQ<10>DDR3_1_DQ<12>
DDR3_1_A<7>DDR3_1_A<6>
DDR3_1_A<13>DDR3_1_CLK
TTC_CORE_CLK_N
SYS_CLK
DDR3_1_A<10>
DDR3_0_DM0DDR3_0_A<11>DDR3_0_A<10>
DDR3_0_CLK
DDR3_1_DM1
DDR3_0_DQ<0>
DDR3_1_DQ<8>
DDR3_1_A<11>
DDR3_0_A<13>
EPCQL_NCS
TTC_CORE_CLK_P
EPCQL_DATA0EPCQL_DATA1EPCQL_DATA2
FPGA_NCONFIG
FPGA_NSTATUS
FPGA_JTAG_TCKFPGA_JTAG_TMS
FPGA_JTAG_TRST AL20
AJ20 AM21AK18AP20
AL17
AN19
AM18AJ16AR20
AJ17AK19
AJ21AL21AJ19
AM19
AK17
AM20AN21AL18AP21
B4 C2
B3
B2
D4C4D2D3
B16A16B15A15M14M15J14J15AN14AM14AV14AU14AP16AU16B25A25K24K23F27E27H26J25AR29AP29AG25AG24AV26AU26AR24AP24
G19H19D16C16N13N12K15L15
AT10AR10AU13AT13
AW19AT16
A21B21E24D24M28N28G26F26
AL27AK27AR27AR28AE22AF22
AW25AW26
OUTOUT
IN
OUT
OUTIN
*
*
*
ININ
GND
BI
ININ
BIOUTOUTOUT
AS CONFIG
JTAG
CONFIGURATION
10ax115f40
TRST
TMSTDOTDI
TCK
NSTATUS
NIO_PULLUP
NCSO2NCSO1NCSO0
NCONFIGNCE
MSEL2MSEL1MSEL0
DCLK
CONF_DONE
ASDATA3ASDATA2ASDATA1ASDATA0_ASDO
epcq_l
GND
VCC
DATA3DATA2DATA1DATA0
DCLKNCS
CLOCKS & PLL10ax115f40
PLL_3B_CLKOUT0P
PLL_3H_CLKOUT1PPLL_3H_CLKOUT1N
PLL_3H_CLKOUT0PPLL_3H_CLKOUT0N
PLL_3G_CLKOUT1PPLL_3G_CLKOUT1N
PLL_3G_CLKOUT0PPLL_3G_CLKOUT0N
PLL_3B_CLKOUT1PPLL_3B_CLKOUT1N
PLL_3B_CLKOUT0N
PLL_3A_CLKOUT1NPLL_3A_CLKOUT0N
PLL_2L_CLKOUT1PPLL_2L_CLKOUT1N
PLL_2L_CLKOUT0PPLL_2L_CLKOUT0N
PLL_2K_CLKOUT1PPLL_2K_CLKOUT1N
PLL_2K_CLKOUT0PPLL_2K_CLKOUT0N
PLL_2F_CLKOUT1PPLL_2F_CLKOUT1N
PLL_2F_CLKOUT0PPLL_2F_CLKOUT0N
PLL_2A_CLKOUT1P_DATA19PLL_2A_CLKOUT1N_DATA18
PLL_2A_CLKOUT0P_DATA27PLL_2A_CLKOUT0N_DATA26
CLK_3H_1PCLK_3H_1N
CLK_3H_0PCLK_3H_0N
CLK_3G_1PCLK_3G_1N
CLK_3G_0PCLK_3G_0N
CLK_3B_1PCLK_3B_1N
CLK_3B_0PCLK_3B_0N
CLK_3A_1NCLK_3A_0N
CLK_2L_1PCLK_2L_1N
CLK_2L_0PCLK_2L_0N
CLK_2K_1PCLK_2K_1N
CLK_2K_0PCLK_2K_0N
CLK_2F_1PCLK_2F_1N
CLK_2F_0PCLK_2F_0N
CLK_2A_1P_DATA21CLK_2A_1N_DATA20
CLK_2A_0P_DATA23CLK_2A_0N_DATA22
GND
GN
D
BIINININ
OUTOUT
GND
OUT***
BI
BIBI
OUTOUT
OUT
OUT
BIBI
OUTOUT
OUT
IN
ININ
OUTBI
IN
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
PCIE (OPTION): SHALL START AT CHANNEL NUMBER 4BANK 1C WITH CVP
DEDICATED REF CLOCK : VMAX=1.6V 0.2V<PEAK TO PEAK DIFF INPUT<1.6V
ARRIA10 LEFT TRANSCEIVERS
MODIFIE: Mon Mar 23 09:50:47 2015
SHEET: 19 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 19 / 27
L33L32
A33A32B35B34A37A36
B31B30C33C32E33E32
U14
AA33AA32
AC33AC32
V39V38Y39Y38AB39AB38AD39AD38AF39AF38AH39AH38
W37W36Y35Y34
AA37AA36AB35AB34AC37AC36AD35AD34
U14
N33N32
R33R32
B39B38C37C36D39D38E37E36F39F38G37G36
D35D34F35F34H35H34K35K34L37L36M35M34
U14
U33U32
W33W32
H39H38J37J36K39K38M39M38P39P38T39T38
N37N36P35P34R37R36T35T34U37U36V35V34
U14
AE33AE32
AG33AG32
AK39AK38AL37AL36AM39AM38AN37AN36AP39AP38AR37AR36
AE37AE36AF35AF34AG37AG36AH35AH34AJ37AJ36AK35AK34
U14
AJ33AJ32
AL33AL32
AT39AT38AU37AU36AV39AV38AW37AW36AV35AV34AW33AW32
AM35AM34AP35AP34AT35AT34AR33AR32AU33AU32AV31AV30
U14
14C6 RX_GXB_L1_P<6>RX_GXB_L1_N<6>RX_GXB_L1_P<10>RX_GXB_L1_N<10>
11C2
TX_GXB_L0_P<9>
TX_GXB_L0_P<7>
TX_GXB_L0_N<9>
TX_GXB_L0_N<7>
TX_GXB_L0_P<11>TX_GXB_L0_N<11>TX_GXB_L0_P<10>TX_GXB_L0_N<10>TX_GXB_L0_P<8>TX_GXB_L0_N<8>TX_GXB_L0_P<6>
TTC_REF_CLK0_NTTC_REF_CLK0_P
RX_PCIE_P<0>RX_PCIE_N<0>
RX_PCIE_P<1>RX_PCIE_N<1>
TX_GXB_L1_P<6>TX_GXB_L1_N<6>
TX_PCIE_N<1>TX_PCIE_P<1>
TX_1GBE_P<0>
TX_PCIE_P<0>TX_PCIE_N<0>
TX_1GBE_N<0>
PCIE_1GBE_REF_CLK_NPCIE_1GBE_REF_CLK_P
RX_1GBE_N<0>RX_1GBE_P<0>
11C2
14D6
14D6
14D6
11C2
14D6
14D6 14D6
14D6
14C6 14C6
14C6 14C6
14C6 14C6
14C6
14C6 14C6
14C6
23E6 23E6
23D6 23D6
14C5
14C5
14C5
14C5
14C5
14C5
14C5
14D5
14D5
14C5
14D5
14D5 14D5
14D5
14C5
23D2 23D2
23E2
23E2
23E2
14C6
14C5
23E6 23E6
10D6 10D6
14D6
14E5 14E5
14E5 14E5
14E5 14E5
14E5 14E5
14E5
14E5
14E5
14E5
11C2 11C2
14E6 14E6
14E6
14E6
14E6
14E6
14E6
14E6
14E6
14D5 14D5
14D5 14D5
14D5 14D5
14D5 14D5
14D5 14D5
14D5 14D5
14D6
14E6
14D6
14D6 14D6
14D6 14D6
11C2
14D6 TX_GXB_L0_N<6>
TX_GXB_L0_P<5>TX_GXB_L0_N<3>TX_GXB_L0_P<3>TX_GXB_L0_N<1>TX_GXB_L0_P<1>TX_GXB_L0_N<0>TX_GXB_L0_P<0>
TX_GXB_L0_N<4>
TX_GXB_L0_N<2>
TX_GXB_L0_P<4>
TX_GXB_L0_P<2>
TX_GXB_L0_N<5>
TX_GXB_L1_N<8>TX_GXB_L1_P<8>TX_GXB_L1_N<10>TX_GXB_L1_P<10>TX_GXB_L1_N<11>TX_GXB_L1_P<11>
TX_GXB_L1_N<7>
TX_GXB_L1_N<9>
TX_GXB_L1_P<7>
TX_GXB_L1_P<9>
TX_GXB_L1_N<4>TX_GXB_L1_P<4> 14C5
14C5
14C5 14C5
14D5
TX_GXB_L1_P<5>TX_GXB_L1_N<5>
TX_GXB_L1_N<3>
TX_GXB_L1_N<2>TX_GXB_L1_P<2>
TX_GXB_L1_P<3>TX_GXB_L1_N<1>
TX_GXB_L1_N<0>TX_GXB_L1_P<1>
TX_GXB_L1_P<0>
14E6
TTC_REF_CLK3_NTTC_REF_CLK3_P
14E6
14E6
14C5
14C5 14C5
RX_GXB_L0_N<5>RX_GXB_L0_P<5>
RX_GXB_L0_N<2>RX_GXB_L0_P<2>RX_GXB_L0_N<4>RX_GXB_L0_P<4>
RX_GXB_L0_N<0>RX_GXB_L0_P<0>
RX_GXB_L0_N<3>
RX_GXB_L0_N<1>RX_GXB_L0_P<3>
RX_GXB_L0_P<1>
14D6 14D6
14D6 14D6
23E2
11C2
RX_GXB_L0_P<6>RX_GXB_L0_N<6>
TTC_REF_CLK2_PTTC_REF_CLK2_N
RX_GXB_L0_N<8>RX_GXB_L0_P<8>RX_GXB_L0_N<10>RX_GXB_L0_P<10>RX_GXB_L0_N<11>RX_GXB_L0_P<11>
RX_GXB_L0_N<7>
RX_GXB_L0_N<9>
RX_GXB_L0_P<7>
RX_GXB_L0_P<9>
RX_GXB_L1_N<4>RX_GXB_L1_P<4>
RX_GXB_L1_N<2>RX_GXB_L1_P<2>
RX_GXB_L1_N<0>RX_GXB_L1_P<0>
RX_GXB_L1_N<1>RX_GXB_L1_P<1>
RX_GXB_L1_N<5>
RX_GXB_L1_N<3>RX_GXB_L1_P<5>
RX_GXB_L1_P<3>
RX_GXB_L1_N<7>RX_GXB_L1_P<7>
RX_GXB_L1_N<9>RX_GXB_L1_P<9>
14C6
TTC_REF_CLK1_N
14C6
14C6
TTC_REF_CLK1_P
RX_GXB_L1_N<11>RX_GXB_L1_P<11>14C6
11C2
RX_GXB_L1_N<8>RX_GXB_L1_P<8>
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
OUTOUTOUTOUTOUTOUT
BANK1E : Transceivers10ax115f40
REFCLK_GXBL1E_CHBNREFCLK_GXBL1E_CHBP
REFCLK_GXBL1E_CHTPREFCLK_GXBL1E_CHTN
GXBL1E_TX_CH5PGXBL1E_TX_CH5N
GXBL1E_TX_CH4PGXBL1E_TX_CH4N
GXBL1E_TX_CH3PGXBL1E_TX_CH3N
GXBL1E_TX_CH2PGXBL1E_TX_CH2N
GXBL1E_TX_CH1PGXBL1E_TX_CH1N
GXBL1E_TX_CH0PGXBL1E_TX_CH0N
GXBL1E_RX_CH5P_GXBL1E_REFCLK5PGXBL1E_RX_CH5N_GXBL1E_REFCLK5N
GXBL1E_RX_CH4P_GXBL1E_REFCLK4PGXBL1E_RX_CH4N_GXBL1E_REFCLK4N
GXBL1E_RX_CH3P_GXBL1E_REFCLK3PGXBL1E_RX_CH3N_GXBL1E_REFCLK3N
GXBL1E_RX_CH2P_GXBL1E_REFCLK2PGXBL1E_RX_CH2N_GXBL1E_REFCLK2N
GXBL1E_RX_CH1P_GXBL1E_REFCLK1PGXBL1E_RX_CH1N_GXBL1E_REFCLK1N
GXBL1E_RX_CH0P_GXBL1E_REFCLK0PGXBL1E_RX_CH0N_GXBL1E_REFCLK0N
BANK1G : Transceivers10ax115f40
REFCLK_GXBL1G_CHTPREFCLK_GXBL1G_CHTN
REFCLK_GXBL1G_CHBPREFCLK_GXBL1G_CHBN
GXBL1G_TX_CH5PGXBL1G_TX_CH5N
GXBL1G_TX_CH4PGXBL1G_TX_CH4N
GXBL1G_TX_CH3PGXBL1G_TX_CH3N
GXBL1G_TX_CH2PGXBL1G_TX_CH2N
GXBL1G_TX_CH1PGXBL1G_TX_CH1N
GXBL1G_TX_CH0PGXBL1G_TX_CH0N
GXBL1G_RX_CH5P_GXBL1G_REFCLK5PGXBL1G_RX_CH5N_GXBL1G_REFCLK5N
GXBL1G_RX_CH4P_GXBL1G_REFCLK4PGXBL1G_RX_CH4N_GXBL1G_REFCLK4N
GXBL1G_RX_CH3P_GXBL1G_REFCLK3PGXBL1G_RX_CH3N_GXBL1G_REFCLK3N
GXBL1G_RX_CH2P_GXBL1G_REFCLK2PGXBL1G_RX_CH2N_GXBL1G_REFCLK2N
GXBL1G_RX_CH1P_GXBL1G_REFCLK1PGXBL1G_RX_CH1N_GXBL1G_REFCLK1N
GXBL1G_RX_CH0P_GXBL1G_REFCLK0PGXBL1G_RX_CH0N_GXBL1G_REFCLK0N
ININ
IN
ININININININININININ
IN
ININ
GND
ININ
INININININ
IN
ININ
OUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUT
OUTOUT
BANK1F : Transceivers10ax115f40
REFCLK_GXBL1F_CHTPREFCLK_GXBL1F_CHTN
REFCLK_GXBL1F_CHBPREFCLK_GXBL1F_CHBN
GXBL1F_TX_CH5PGXBL1F_TX_CH5N
GXBL1F_TX_CH4PGXBL1F_TX_CH4N
GXBL1F_TX_CH3PGXBL1F_TX_CH3N
GXBL1F_TX_CH2PGXBL1F_TX_CH2N
GXBL1F_TX_CH1PGXBL1F_TX_CH1N
GXBL1F_TX_CH0PGXBL1F_TX_CH0N
GXBL1F_RX_CH5P_GXBL1F_REFCLK5PGXBL1F_RX_CH5N_GXBL1F_REFCLK5N
GXBL1F_RX_CH4P_GXBL1F_REFCLK4PGXBL1F_RX_CH4N_GXBL1F_REFCLK4N
GXBL1F_RX_CH3P_GXBL1F_REFCLK3PGXBL1F_RX_CH3N_GXBL1F_REFCLK3N
GXBL1F_RX_CH2P_GXBL1F_REFCLK2PGXBL1F_RX_CH2N_GXBL1F_REFCLK2N
GXBL1F_RX_CH1P_GXBL1F_REFCLK1PGXBL1F_RX_CH1N_GXBL1F_REFCLK1N
GXBL1F_RX_CH0P_GXBL1F_REFCLK0PGXBL1F_RX_CH0N_GXBL1F_REFCLK0N
IN
IN
IN
IN
ININ
GND
OUTOUTOUTOUT
BANK1D : Transceivers
10ax115f40
REFCLK_GXBL1D_CHTPREFCLK_GXBL1D_CHTN
REFCLK_GXBL1D_CHBPREFCLK_GXBL1D_CHBN
GXBL1D_TX_CH5PGXBL1D_TX_CH5N
GXBL1D_TX_CH4PGXBL1D_TX_CH4N
GXBL1D_TX_CH3PGXBL1D_TX_CH3N
GXBL1D_TX_CH2PGXBL1D_TX_CH2N
GXBL1D_TX_CH1PGXBL1D_TX_CH1N
GXBL1D_TX_CH0PGXBL1D_TX_CH0N
GXBL1D_RX_CH5P_GXBL1D_REFCLK5PGXBL1D_RX_CH5N_GXBL1D_REFCLK5N
GXBL1D_RX_CH4P_GXBL1D_REFCLK4PGXBL1D_RX_CH4N_GXBL1D_REFCLK4N
GXBL1D_RX_CH3P_GXBL1D_REFCLK3PGXBL1D_RX_CH3N_GXBL1D_REFCLK3N
GXBL1D_RX_CH2P_GXBL1D_REFCLK2PGXBL1D_RX_CH2N_GXBL1D_REFCLK2N
GXBL1D_RX_CH1P_GXBL1D_REFCLK1PGXBL1D_RX_CH1N_GXBL1D_REFCLK1N
GXBL1D_RX_CH0P_GXBL1D_REFCLK0PGXBL1D_RX_CH0N_GXBL1D_REFCLK0N
BANK1C : Transceivers10ax115f40
REFCLK_GXBL1C_CHTPREFCLK_GXBL1C_CHTN
REFCLK_GXBL1C_CHBPREFCLK_GXBL1C_CHBN
GXBL1C_TX_CH5PGXBL1C_TX_CH5N
GXBL1C_TX_CH4PGXBL1C_TX_CH4N
GXBL1C_TX_CH3PGXBL1C_TX_CH3N
GXBL1C_TX_CH2PGXBL1C_TX_CH2N
GXBL1C_TX_CH1PGXBL1C_TX_CH1N
GXBL1C_TX_CH0PGXBL1C_TX_CH0N
GXBL1C_RX_CH5P_GXBL1C_REFCLK5PGXBL1C_RX_CH5N_GXBL1C_REFCLK5N
GXBL1C_RX_CH4P_GXBL1C_REFCLK4PGXBL1C_RX_CH4N_GXBL1C_REFCLK4N
GXBL1C_RX_CH3P_GXBL1C_REFCLK3PGXBL1C_RX_CH3N_GXBL1C_REFCLK3N
GXBL1C_RX_CH2P_GXBL1C_REFCLK2PGXBL1C_RX_CH2N_GXBL1C_REFCLK2N
GXBL1C_RX_CH1P_GXBL1C_REFCLK1PGXBL1C_RX_CH1N_GXBL1C_REFCLK1N
GXBL1C_RX_CH0P_GXBL1C_REFCLK0PGXBL1C_RX_CH0N_GXBL1C_REFCLK0N
GND
IN
ININ
ININ
IN
INININININ
IN
INININ
GND
IN
ININ
INININ
IN
ININININININ
OUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUT
OUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUT
BANK1H : Transceivers10ax115f40
REFCLK_GXBL1H_CHBPREFCLK_GXBL1H_CHBN
GXBL1H_TX_CH2PGXBL1H_TX_CH2N
GXBL1H_TX_CH1PGXBL1H_TX_CH1N
GXBL1H_TX_CH0PGXBL1H_TX_CH0N
GXBL1H_RX_CH2P_GXBL1H_REFCLK2PGXBL1H_RX_CH2N_GXBL1H_REFCLK2N
GXBL1H_RX_CH1P_GXBL1H_REFCLK1PGXBL1H_RX_CH1N_GXBL1H_REFCLK1N
GXBL1H_RX_CH0P_GXBL1H_REFCLK0PGXBL1H_RX_CH0N_GXBL1H_REFCLK0N
GND
GND
OUTOUTOUTOUTOUTOUT
GND
GND
PCIE (OPTION): SHALL START AT CHANNEL NUMBER 4BANK 1C WITH CVP
DEDICATED REF CLOCK : VMAX=1.6V 0.2V<PEAK TO PEAK DIFF INPUT<1.6V
ARRIA10 LEFT TRANSCEIVERS
MODIFIE: Mon Mar 23 09:50:47 2015
SHEET: 19 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 19 / 27
U14U14
U14
U14
U14
U14
14C6
11C2
11C2
14D6
14D6
14D6
11C2
14D6
14D6 14D6
14D6
14C6 14C6
14C6 14C6
14C6 14C6
14C6
14C6 14C6
14C6
23E6 23E6
23D6 23D6
14C5
14C5
14C5
14C5
14C5
14C5
14C5
14D5
14D5
14C5
14D5
14D5 14D5
14D5
14C5
23D2 23D2
23E2
23E2
23E2
14C6
14C5
23E6 23E6
10D6 10D6
14D6
14E5 14E5
14E5 14E5
14E5 14E5
14E5 14E5
14E5
14E5
14E5
14E5
11C2 11C2
14E6 14E6
14E6
14E6
14E6
14E6
14E6
14E6
14E6
14D5 14D5
14D5 14D5
14D5 14D5
14D5 14D5
14D5 14D5
14D5 14D5
14D6
14E6
14D6
14D6 14D6
14D6 14D6
11C2
14D6
14C5 14C5
14C5 14C5
14D5
14E6
14E6
14E6
14C5
14C5 14C5
14D6 14D6
14D6 14D6
23E2
11C2
14C6 14C6
14C6 14C6
11C2
RX_GXB_L1_P<6>RX_GXB_L1_N<6>RX_GXB_L1_P<10>RX_GXB_L1_N<10>
TX_GXB_L0_P<9>
TX_GXB_L0_P<7>
TX_GXB_L0_N<9>
TX_GXB_L0_N<7>
TX_GXB_L0_P<11>TX_GXB_L0_N<11>TX_GXB_L0_P<10>TX_GXB_L0_N<10>TX_GXB_L0_P<8>TX_GXB_L0_N<8>TX_GXB_L0_P<6>
TTC_REF_CLK0_NTTC_REF_CLK0_P
RX_PCIE_P<0>RX_PCIE_N<0>
RX_PCIE_P<1>RX_PCIE_N<1>
TX_GXB_L1_P<6>TX_GXB_L1_N<6>
TX_PCIE_N<1>TX_PCIE_P<1>
TX_1GBE_P<0>
TX_PCIE_P<0>TX_PCIE_N<0>
TX_1GBE_N<0>
PCIE_1GBE_REF_CLK_NPCIE_1GBE_REF_CLK_P
RX_1GBE_N<0>RX_1GBE_P<0>
TX_GXB_L0_N<6>
TX_GXB_L0_P<5>TX_GXB_L0_N<3>TX_GXB_L0_P<3>TX_GXB_L0_N<1>TX_GXB_L0_P<1>TX_GXB_L0_N<0>TX_GXB_L0_P<0>
TX_GXB_L0_N<4>
TX_GXB_L0_N<2>
TX_GXB_L0_P<4>
TX_GXB_L0_P<2>
TX_GXB_L0_N<5>
TX_GXB_L1_N<8>TX_GXB_L1_P<8>TX_GXB_L1_N<10>TX_GXB_L1_P<10>TX_GXB_L1_N<11>TX_GXB_L1_P<11>
TX_GXB_L1_N<7>
TX_GXB_L1_N<9>
TX_GXB_L1_P<7>
TX_GXB_L1_P<9>
TX_GXB_L1_N<4>TX_GXB_L1_P<4>
TX_GXB_L1_P<5>TX_GXB_L1_N<5>
TX_GXB_L1_N<3>
TX_GXB_L1_N<2>TX_GXB_L1_P<2>
TX_GXB_L1_P<3>TX_GXB_L1_N<1>
TX_GXB_L1_N<0>TX_GXB_L1_P<1>
TX_GXB_L1_P<0>
TTC_REF_CLK3_NTTC_REF_CLK3_P
RX_GXB_L0_N<5>RX_GXB_L0_P<5>
RX_GXB_L0_N<2>RX_GXB_L0_P<2>RX_GXB_L0_N<4>RX_GXB_L0_P<4>
RX_GXB_L0_N<0>RX_GXB_L0_P<0>
RX_GXB_L0_N<3>
RX_GXB_L0_N<1>RX_GXB_L0_P<3>
RX_GXB_L0_P<1>
RX_GXB_L0_P<6>RX_GXB_L0_N<6>
TTC_REF_CLK2_PTTC_REF_CLK2_N
RX_GXB_L0_N<8>RX_GXB_L0_P<8>RX_GXB_L0_N<10>RX_GXB_L0_P<10>RX_GXB_L0_N<11>RX_GXB_L0_P<11>
RX_GXB_L0_N<7>
RX_GXB_L0_N<9>
RX_GXB_L0_P<7>
RX_GXB_L0_P<9>
RX_GXB_L1_N<4>RX_GXB_L1_P<4>
RX_GXB_L1_N<2>RX_GXB_L1_P<2>
RX_GXB_L1_N<0>RX_GXB_L1_P<0>
RX_GXB_L1_N<1>RX_GXB_L1_P<1>
RX_GXB_L1_N<5>
RX_GXB_L1_N<3>RX_GXB_L1_P<5>
RX_GXB_L1_P<3>
RX_GXB_L1_N<7>RX_GXB_L1_P<7>
RX_GXB_L1_N<9>RX_GXB_L1_P<9>
TTC_REF_CLK1_NTTC_REF_CLK1_P
RX_GXB_L1_N<11>RX_GXB_L1_P<11>
RX_GXB_L1_N<8>RX_GXB_L1_P<8>
L33L32
A33A32B35B34A37A36
B31B30C33C32E33E32
AA33AA32
AC33AC32
V39V38Y39Y38AB39AB38AD39AD38AF39AF38AH39AH38
W37W36Y35Y34
AA37AA36AB35AB34AC37AC36AD35AD34
N33N32
R33R32
B39B38C37C36D39D38E37E36F39F38G37G36
D35D34F35F34H35H34K35K34L37L36M35M34
U33U32
W33W32
H39H38J37J36K39K38M39M38P39P38T39T38
N37N36P35P34R37R36T35T34U37U36V35V34
AE33AE32
AG33AG32
AK39AK38AL37AL36AM39AM38AN37AN36AP39AP38AR37AR36
AE37AE36AF35AF34AG37AG36AH35AH34AJ37AJ36AK35AK34
AJ33AJ32
AL33AL32
AT39AT38AU37AU36AV39AV38AW37AW36AV35AV34AW33AW32
AM35AM34AP35AP34AT35AT34AR33AR32AU33AU32AV31AV30
OUTOUTOUTOUTOUTOUT
BANK1E : Transceivers10ax115f40
REFCLK_GXBL1E_CHBNREFCLK_GXBL1E_CHBP
REFCLK_GXBL1E_CHTPREFCLK_GXBL1E_CHTN
GXBL1E_TX_CH5PGXBL1E_TX_CH5N
GXBL1E_TX_CH4PGXBL1E_TX_CH4N
GXBL1E_TX_CH3PGXBL1E_TX_CH3N
GXBL1E_TX_CH2PGXBL1E_TX_CH2N
GXBL1E_TX_CH1PGXBL1E_TX_CH1N
GXBL1E_TX_CH0PGXBL1E_TX_CH0N
GXBL1E_RX_CH5P_GXBL1E_REFCLK5PGXBL1E_RX_CH5N_GXBL1E_REFCLK5N
GXBL1E_RX_CH4P_GXBL1E_REFCLK4PGXBL1E_RX_CH4N_GXBL1E_REFCLK4N
GXBL1E_RX_CH3P_GXBL1E_REFCLK3PGXBL1E_RX_CH3N_GXBL1E_REFCLK3N
GXBL1E_RX_CH2P_GXBL1E_REFCLK2PGXBL1E_RX_CH2N_GXBL1E_REFCLK2N
GXBL1E_RX_CH1P_GXBL1E_REFCLK1PGXBL1E_RX_CH1N_GXBL1E_REFCLK1N
GXBL1E_RX_CH0P_GXBL1E_REFCLK0PGXBL1E_RX_CH0N_GXBL1E_REFCLK0N
BANK1G : Transceivers10ax115f40
REFCLK_GXBL1G_CHTPREFCLK_GXBL1G_CHTN
REFCLK_GXBL1G_CHBPREFCLK_GXBL1G_CHBN
GXBL1G_TX_CH5PGXBL1G_TX_CH5N
GXBL1G_TX_CH4PGXBL1G_TX_CH4N
GXBL1G_TX_CH3PGXBL1G_TX_CH3N
GXBL1G_TX_CH2PGXBL1G_TX_CH2N
GXBL1G_TX_CH1PGXBL1G_TX_CH1N
GXBL1G_TX_CH0PGXBL1G_TX_CH0N
GXBL1G_RX_CH5P_GXBL1G_REFCLK5PGXBL1G_RX_CH5N_GXBL1G_REFCLK5N
GXBL1G_RX_CH4P_GXBL1G_REFCLK4PGXBL1G_RX_CH4N_GXBL1G_REFCLK4N
GXBL1G_RX_CH3P_GXBL1G_REFCLK3PGXBL1G_RX_CH3N_GXBL1G_REFCLK3N
GXBL1G_RX_CH2P_GXBL1G_REFCLK2PGXBL1G_RX_CH2N_GXBL1G_REFCLK2N
GXBL1G_RX_CH1P_GXBL1G_REFCLK1PGXBL1G_RX_CH1N_GXBL1G_REFCLK1N
GXBL1G_RX_CH0P_GXBL1G_REFCLK0PGXBL1G_RX_CH0N_GXBL1G_REFCLK0N
ININ
IN
ININININININININININ
IN
ININ
GND
ININ
INININININ
IN
ININ
OUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUT
OUTOUT
BANK1F : Transceivers10ax115f40
REFCLK_GXBL1F_CHTPREFCLK_GXBL1F_CHTN
REFCLK_GXBL1F_CHBPREFCLK_GXBL1F_CHBN
GXBL1F_TX_CH5PGXBL1F_TX_CH5N
GXBL1F_TX_CH4PGXBL1F_TX_CH4N
GXBL1F_TX_CH3PGXBL1F_TX_CH3N
GXBL1F_TX_CH2PGXBL1F_TX_CH2N
GXBL1F_TX_CH1PGXBL1F_TX_CH1N
GXBL1F_TX_CH0PGXBL1F_TX_CH0N
GXBL1F_RX_CH5P_GXBL1F_REFCLK5PGXBL1F_RX_CH5N_GXBL1F_REFCLK5N
GXBL1F_RX_CH4P_GXBL1F_REFCLK4PGXBL1F_RX_CH4N_GXBL1F_REFCLK4N
GXBL1F_RX_CH3P_GXBL1F_REFCLK3PGXBL1F_RX_CH3N_GXBL1F_REFCLK3N
GXBL1F_RX_CH2P_GXBL1F_REFCLK2PGXBL1F_RX_CH2N_GXBL1F_REFCLK2N
GXBL1F_RX_CH1P_GXBL1F_REFCLK1PGXBL1F_RX_CH1N_GXBL1F_REFCLK1N
GXBL1F_RX_CH0P_GXBL1F_REFCLK0PGXBL1F_RX_CH0N_GXBL1F_REFCLK0N
IN
IN
IN
IN
ININ
GND
OUTOUTOUTOUT
BANK1D : Transceivers
10ax115f40
REFCLK_GXBL1D_CHTPREFCLK_GXBL1D_CHTN
REFCLK_GXBL1D_CHBPREFCLK_GXBL1D_CHBN
GXBL1D_TX_CH5PGXBL1D_TX_CH5N
GXBL1D_TX_CH4PGXBL1D_TX_CH4N
GXBL1D_TX_CH3PGXBL1D_TX_CH3N
GXBL1D_TX_CH2PGXBL1D_TX_CH2N
GXBL1D_TX_CH1PGXBL1D_TX_CH1N
GXBL1D_TX_CH0PGXBL1D_TX_CH0N
GXBL1D_RX_CH5P_GXBL1D_REFCLK5PGXBL1D_RX_CH5N_GXBL1D_REFCLK5N
GXBL1D_RX_CH4P_GXBL1D_REFCLK4PGXBL1D_RX_CH4N_GXBL1D_REFCLK4N
GXBL1D_RX_CH3P_GXBL1D_REFCLK3PGXBL1D_RX_CH3N_GXBL1D_REFCLK3N
GXBL1D_RX_CH2P_GXBL1D_REFCLK2PGXBL1D_RX_CH2N_GXBL1D_REFCLK2N
GXBL1D_RX_CH1P_GXBL1D_REFCLK1PGXBL1D_RX_CH1N_GXBL1D_REFCLK1N
GXBL1D_RX_CH0P_GXBL1D_REFCLK0PGXBL1D_RX_CH0N_GXBL1D_REFCLK0N
BANK1C : Transceivers10ax115f40
REFCLK_GXBL1C_CHTPREFCLK_GXBL1C_CHTN
REFCLK_GXBL1C_CHBPREFCLK_GXBL1C_CHBN
GXBL1C_TX_CH5PGXBL1C_TX_CH5N
GXBL1C_TX_CH4PGXBL1C_TX_CH4N
GXBL1C_TX_CH3PGXBL1C_TX_CH3N
GXBL1C_TX_CH2PGXBL1C_TX_CH2N
GXBL1C_TX_CH1PGXBL1C_TX_CH1N
GXBL1C_TX_CH0PGXBL1C_TX_CH0N
GXBL1C_RX_CH5P_GXBL1C_REFCLK5PGXBL1C_RX_CH5N_GXBL1C_REFCLK5N
GXBL1C_RX_CH4P_GXBL1C_REFCLK4PGXBL1C_RX_CH4N_GXBL1C_REFCLK4N
GXBL1C_RX_CH3P_GXBL1C_REFCLK3PGXBL1C_RX_CH3N_GXBL1C_REFCLK3N
GXBL1C_RX_CH2P_GXBL1C_REFCLK2PGXBL1C_RX_CH2N_GXBL1C_REFCLK2N
GXBL1C_RX_CH1P_GXBL1C_REFCLK1PGXBL1C_RX_CH1N_GXBL1C_REFCLK1N
GXBL1C_RX_CH0P_GXBL1C_REFCLK0PGXBL1C_RX_CH0N_GXBL1C_REFCLK0N
GND
IN
ININ
ININ
IN
INININININ
IN
INININ
GND
IN
ININ
INININ
IN
ININININININ
OUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUT
OUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUT
BANK1H : Transceivers10ax115f40
REFCLK_GXBL1H_CHBPREFCLK_GXBL1H_CHBN
GXBL1H_TX_CH2PGXBL1H_TX_CH2N
GXBL1H_TX_CH1PGXBL1H_TX_CH1N
GXBL1H_TX_CH0PGXBL1H_TX_CH0N
GXBL1H_RX_CH2P_GXBL1H_REFCLK2PGXBL1H_RX_CH2N_GXBL1H_REFCLK2N
GXBL1H_RX_CH1P_GXBL1H_REFCLK1PGXBL1H_RX_CH1N_GXBL1H_REFCLK1N
GXBL1H_RX_CH0P_GXBL1H_REFCLK0PGXBL1H_RX_CH0N_GXBL1H_REFCLK0N
GND
GND
OUTOUTOUTOUTOUTOUT
GND
GND
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
ARRIA10 RIGHT TRANSCEIVERS
XAUI PORT : SEE THE ORDER OF THE CHANNELS
GBT PORT : ARE INDEPENDENT
MODIFIE: Mon Mar 23 09:50:47 2015
SHEET: 20 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 20 / 27
L7L8
A7A8B5B6A3A4
B9B10C7C8E7E8
U14
N7N8
R7R8
B1B2C3C4D1D2E3E4F1F2G3G4
D5D6F5F6H5H6K5K6L3L4M5M6
U14
U7U8
W7W8
H1H2J3J4K1K2M1M2P1P2T1T2
N3N4P5P6R3R4T5T6U3U4V5V6
U14
AA7AA8
AC7AC8
V1V2Y1Y2AB1AB2AD1AD2AF1AF2AH1AH2
W3W4Y5Y6
AA3AA4AB5AB6AC3AC4AD5AD6
U14
AE7AE8
AG7AG8
AK1AK2AL3AL4AM1AM2AN3AN4AP1AP2AR3AR4
AE3AE4AF5AF6AG3AG4AH5AH6AJ3AJ4AK5AK6
U14
AJ7AJ8
AL7AL8
AT1AT2AU3AU4AV1AV2AW3AW4AV5AV6AW7AW8
AM5AM6AP5AP6AT5AT6AR7AR8AU7AU8AV9
AV10
U14
RX_GXB_R1_P<2>
RX_GXB_R1_P<4>RX_GXB_R1_N<2>
RX_GXB_R1_N<4>
RX_GXB_R1_P<0>RX_GXB_R1_N<0>
TTC_REF_CLK6_NTTC_REF_CLK6_P
14A6
11B2 11B2
14A6
14A6
TX_GXB_R0_P<8>
TX_GXB_R0_P<6>TX_GXB_R0_N<8>
TX_GXB_R0_N<6>
TX_GXB_R0_P<7>
TX_GXB_R0_P<10>TX_GXB_R0_N<10>
TX_GXB_R0_N<9>
TX_GXB_R0_N<7>
TX_GXB_R0_P<9>TX_GXB_R0_N<11>TX_GXB_R0_P<11>
TX_GXB_R0_P<1>
TX_GXB_R0_P<3>
TX_GXB_R0_N<1>
TX_GXB_R0_N<3>
TX_GXB_R0_P<0>TX_GXB_R0_N<0>
TX_GXB_R0_N<4>
TX_GXB_R0_N<2>TX_GXB_R0_P<2>
TX_GXB_R0_P<4>
TX_GXB_R0_N<5>
14C3 14B6 14B6
14C3
14C3 14B6
RX_GXB_R0_P<6>RX_GXB_R0_N<6>RX_GXB_R0_P<8>
RX_GXB_R0_N<4>
RX_GXB_R0_P<9>
RX_GXB_R0_P<7>RX_GXB_R0_N<9>
RX_GXB_R0_N<7>
TX_GXB_R1_P<8> 14C3 23D6 RX_GBT_P<2>
TTC_REF_CLK4_NTTC_REF_CLK4_P
TTC_REF_CLK8_P
RX_GXB_R0_N<11>RX_GXB_R0_P<11>RX_GXB_R0_N<10>
RX_GXB_R0_N<8>
TTC_REF_CLK8_N
TX_GXB_R1_P<1>
14C3
14B6 14B6
14C3 RX_GXB_R0_P<10>
TTC_REF_CLK7_PTTC_REF_CLK7_N
RX_GXB_R0_P<4>RX_GXB_R0_N<2>
RX_GXB_R0_N<1>
RX_GXB_R0_N<0>
RX_GXB_R0_P<1>
RX_GXB_R0_P<0>
RX_GXB_R0_N<3>RX_GXB_R0_P<3>
RX_GXB_R0_P<2>TX_XAUI_P<0>TX_XAUI_N<1>
11B2
TX_GXB_R0_P<5>
14B6
10E6 10D6
14A6
14A6
14A6
23D6
23D6 23D6
23D6 23D6
14A6
14A6
23D6
23D6
23D6
23D2 23D2
23D2 23D2
23D2
23D2 23D2
14C3
14C3
14C3 14C3
14C3 14C3
14C3 14C3
14C3
14D3
14D3 14D3
14D3 14D3
14D3 14D3
14B6
14B6 14B6
14C6 14C6
11B2
14B6
14B6
14B6
14A6 14A6
23D6
23D6
11C2 11C2
11B3
14B6
14B6
14B6
14B6
14B6
14B6
11B2
14B6
23C6
23D2
23C2 23C2
23D2
23D2 23D2
14E3 14E3
14E3 14E3
14E3 14E3
14E3 14E3
14E3 14E3
14E3 14E3
14D3 14D3
14E3 14D3
14D3 14D3
14D3 14D3
14D3 14D3
14D3 14D3
XAUI_REF_CLK_NXAUI_REF_CLK_P
RX_XAUI_P<1>RX_XAUI_N<2>RX_XAUI_P<2>RX_XAUI_N<3>RX_XAUI_P<3>
RX_XAUI_P<0>RX_XAUI_N<1>
RX_XAUI_N<0>
TX_XAUI_P<3>TX_XAUI_N<3>TX_XAUI_P<2>TX_XAUI_N<2>TX_XAUI_P<1>
TX_XAUI_N<0>
RX_GBT_N<2>RX_GBT_P<1>RX_GBT_N<1>RX_GBT_P<0>RX_GBT_N<0>
TX_GBT_N<1>TX_GBT_P<0>TX_GBT_N<0>
TX_GBT_P<1>TX_GBT_N<2>TX_GBT_P<2>
14C3 23C6
14C3
23D6
14A6 TX_GXB_R1_P<5>TX_GXB_R1_N<5>
TX_GXB_R1_P<2>TX_GXB_R1_N<2>TX_GXB_R1_P<4>TX_GXB_R1_N<4>
TX_GXB_R1_N<0>TX_GXB_R1_P<0>
TX_GXB_R1_N<3>
TX_GXB_R1_N<1>
TX_GXB_R1_P<3>
TX_GXB_R1_N<6>TX_GXB_R1_P<6>
TX_GXB_R1_N<11>
TX_GXB_R1_P<7>
TX_GXB_R1_P<9>TX_GXB_R1_N<9>
TX_GXB_R1_P<11>TX_GXB_R1_N<10>TX_GXB_R1_P<10>TX_GXB_R1_N<8>
TX_GXB_R1_N<7>
14A6
14A6
14A6
14A6
14A6
14A6
14A6
14A6
RX_GXB_R1_N<7>RX_GXB_R1_P<7>RX_GXB_R1_N<9>
RX_GXB_R1_P<6>
RX_GXB_R1_P<5>RX_GXB_R1_N<5>RX_GXB_R1_P<3>RX_GXB_R1_N<3>RX_GXB_R1_P<1>RX_GXB_R1_N<1>
14A6
14A6 14A6
11B2 TTC_REF_CLK5_NTTC_REF_CLK5_P
RX_GXB_R1_P<11>RX_GXB_R1_N<11>RX_GXB_R1_P<9>
14A6
11B2
RX_GXB_R1_N<6>RX_GXB_R1_P<8>RX_GXB_R1_N<8>RX_GXB_R1_P<10>RX_GXB_R1_N<10>
14A6 14A6
14A6
23D2
14B6
RX_GXB_R0_N<5>RX_GXB_R0_P<5>
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
IN
OUT
BANK4I : Transceivers10ax115f40
REFCLK_GXBR4I_CHTPREFCLK_GXBR4I_CHTN
REFCLK_GXBR4I_CHBPREFCLK_GXBR4I_CHBN
GXBR4I_TX_CH5PGXBR4I_TX_CH5N
GXBR4I_TX_CH4PGXBR4I_TX_CH4N
GXBR4I_TX_CH3PGXBR4I_TX_CH3N
GXBR4I_TX_CH2PGXBR4I_TX_CH2N
GXBR4I_TX_CH1PGXBR4I_TX_CH1N
GXBR4I_TX_CH0PGXBR4I_TX_CH0N
GXBR4I_RX_CH5P_GXBR4I_REFCLK5PGXBR4I_RX_CH5N_GXBR4I_REFCLK5N
GXBR4I_RX_CH4P_GXBR4I_REFCLK4PGXBR4I_RX_CH4N_GXBR4I_REFCLK4N
GXBR4I_RX_CH3P_GXBR4I_REFCLK3PGXBR4I_RX_CH3N_GXBR4I_REFCLK3N
GXBR4I_RX_CH2P_GXBR4I_REFCLK2PGXBR4I_RX_CH2N_GXBR4I_REFCLK2N
GXBR4I_RX_CH1P_GXBR4I_REFCLK1PGXBR4I_RX_CH1N_GXBR4I_REFCLK1N
GXBR4I_RX_CH0P_GXBR4I_REFCLK0PGXBR4I_RX_CH0N_GXBR4I_REFCLK0N
GND
INININININ
ININ
IN
IN
IN
ININ
IN
INININ
ININ
IN
INININ
INININ
BANK4H : Transceivers10ax115f40
REFCLK_GXBR4H_CHTPREFCLK_GXBR4H_CHTN
REFCLK_GXBR4H_CHBPREFCLK_GXBR4H_CHBN
GXBR4H_TX_CH5PGXBR4H_TX_CH5N
GXBR4H_TX_CH4PGXBR4H_TX_CH4N
GXBR4H_TX_CH3PGXBR4H_TX_CH3N
GXBR4H_TX_CH2PGXBR4H_TX_CH2N
GXBR4H_TX_CH1PGXBR4H_TX_CH1N
GXBR4H_TX_CH0PGXBR4H_TX_CH0N
GXBR4H_RX_CH5P_GXBR4H_REFCLK5PGXBR4H_RX_CH5N_GXBR4H_REFCLK5N
GXBR4H_RX_CH4P_GXBR4H_REFCLK4PGXBR4H_RX_CH4N_GXBR4H_REFCLK4N
GXBR4H_RX_CH3P_GXBR4H_REFCLK3PGXBR4H_RX_CH3N_GXBR4H_REFCLK3N
GXBR4H_RX_CH2P_GXBR4H_REFCLK2PGXBR4H_RX_CH2N_GXBR4H_REFCLK2N
GXBR4H_RX_CH1P_GXBR4H_REFCLK1PGXBR4H_RX_CH1N_GXBR4H_REFCLK1N
GXBR4H_RX_CH0P_GXBR4H_REFCLK0PGXBR4H_RX_CH0N_GXBR4H_REFCLK0N
GND
OUTOUT
IN
OUTOUT
OUT
OUTOUT
OUTOUT
OUTOUTOUT
IN
OUTOUTOUTOUTOUT
BANK4G : Transceivers10ax115f40
REFCLK_GXBR4G_CHTPREFCLK_GXBR4G_CHTN
REFCLK_GXBR4G_CHBPREFCLK_GXBR4G_CHBN
GXBR4G_TX_CH5PGXBR4G_TX_CH5N
GXBR4G_TX_CH4PGXBR4G_TX_CH4N
GXBR4G_TX_CH3PGXBR4G_TX_CH3N
GXBR4G_TX_CH2PGXBR4G_TX_CH2N
GXBR4G_TX_CH1PGXBR4G_TX_CH1N
GXBR4G_TX_CH0PGXBR4G_TX_CH0N
GXBR4G_RX_CH5P_GXBR4G_REFCLK5PGXBR4G_RX_CH5N_GXBR4G_REFCLK5N
GXBR4G_RX_CH4P_GXBR4G_REFCLK4PGXBR4G_RX_CH4N_GXBR4G_REFCLK4N
GXBR4G_RX_CH3P_GXBR4G_REFCLK3PGXBR4G_RX_CH3N_GXBR4G_REFCLK3N
GXBR4G_RX_CH2P_GXBR4G_REFCLK2PGXBR4G_RX_CH2N_GXBR4G_REFCLK2N
GXBR4G_RX_CH1P_GXBR4G_REFCLK1PGXBR4G_RX_CH1N_GXBR4G_REFCLK1N
GXBR4G_RX_CH0P_GXBR4G_REFCLK0PGXBR4G_RX_CH0N_GXBR4G_REFCLK0N
GND
IN
IN
IN
IN
IN
ININININ
ININININ
IN
IN
IN
ININ
ININ
IN
BANK4F : Transceivers10ax115f40
REFCLK_GXBR4F_CHTPREFCLK_GXBR4F_CHTN
REFCLK_GXBR4F_CHBPREFCLK_GXBR4F_CHBN
GXBR4F_TX_CH5PGXBR4F_TX_CH5N
GXBR4F_TX_CH4PGXBR4F_TX_CH4N
GXBR4F_TX_CH3PGXBR4F_TX_CH3N
GXBR4F_TX_CH2PGXBR4F_TX_CH2N
GXBR4F_TX_CH1PGXBR4F_TX_CH1N
GXBR4F_TX_CH0PGXBR4F_TX_CH0N
GXBR4F_RX_CH5P_GXBR4F_REFCLK5PGXBR4F_RX_CH5N_GXBR4F_REFCLK5N
GXBR4F_RX_CH4P_GXBR4F_REFCLK4PGXBR4F_RX_CH4N_GXBR4F_REFCLK4N
GXBR4F_RX_CH3P_GXBR4F_REFCLK3PGXBR4F_RX_CH3N_GXBR4F_REFCLK3N
GXBR4F_RX_CH2P_GXBR4F_REFCLK2PGXBR4F_RX_CH2N_GXBR4F_REFCLK2N
GXBR4F_RX_CH1P_GXBR4F_REFCLK1PGXBR4F_RX_CH1N_GXBR4F_REFCLK1N
GXBR4F_RX_CH0P_GXBR4F_REFCLK0PGXBR4F_RX_CH0N_GXBR4F_REFCLK0N
GND
IN
IN
BANK4E : Transceivers10ax115f40
REFCLK_GXBR4E_CHTPREFCLK_GXBR4E_CHTN
REFCLK_GXBR4E_CHBPREFCLK_GXBR4E_CHBN
GXBR4E_TX_CH5PGXBR4E_TX_CH5N
GXBR4E_TX_CH4PGXBR4E_TX_CH4N
GXBR4E_TX_CH3PGXBR4E_TX_CH3N
GXBR4E_TX_CH2PGXBR4E_TX_CH2N
GXBR4E_TX_CH1PGXBR4E_TX_CH1N
GXBR4E_TX_CH0PGXBR4E_TX_CH0N
GXBR4E_RX_CH5P_GXBR4E_REFCLK5PGXBR4E_RX_CH5N_GXBR4E_REFCLK5N
GXBR4E_RX_CH4P_GXBR4E_REFCLK4PGXBR4E_RX_CH4N_GXBR4E_REFCLK4N
GXBR4E_RX_CH3P_GXBR4E_REFCLK3PGXBR4E_RX_CH3N_GXBR4E_REFCLK3N
GXBR4E_RX_CH2P_GXBR4E_REFCLK2PGXBR4E_RX_CH2N_GXBR4E_REFCLK2N
GXBR4E_RX_CH1P_GXBR4E_REFCLK1PGXBR4E_RX_CH1N_GXBR4E_REFCLK1N
GXBR4E_RX_CH0P_GXBR4E_REFCLK0PGXBR4E_RX_CH0N_GXBR4E_REFCLK0N
IN
ININ
ININ
OUTOUTOUTOUT
OUTOUT
OUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUT
BANK4J : Transceivers10ax115f40
REFCLK_GXBR4J_CHBPREFCLK_GXBR4J_CHBN
GXBR4J_TX_CH2PGXBR4J_TX_CH2N
GXBR4J_TX_CH1PGXBR4J_TX_CH1N
GXBR4J_TX_CH0PGXBR4J_TX_CH0N
GXBR4J_RX_CH2P_GXBR4J_REFCLK2PGXBR4J_RX_CH2N_GXBR4J_REFCLK2N
GXBR4J_RX_CH1P_GXBR4J_REFCLK1PGXBR4J_RX_CH1N_GXBR4J_REFCLK1N
GXBR4J_RX_CH0P_GXBR4J_REFCLK0PGXBR4J_RX_CH0N_GXBR4J_REFCLK0N
ININININ
ININ
IN
IN
IN
ININ
INININ
OUTOUT
OUTOUT
IN
GND
ARRIA10 RIGHT TRANSCEIVERS
XAUI PORT : SEE THE ORDER OF THE CHANNELS
GBT PORT : ARE INDEPENDENT
MODIFIE: Mon Mar 23 09:50:47 2015
SHEET: 20 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 20 / 27
U14
U14
U14
U14
U14
U14
14A6
11B2 11B2
14A6
14A6
14C3 14B6 14B6
14C3
14C3 14B6
14C3 23D6
14C3
14B6 14B6
14C3
11B2
14B6
10E6 10D6
14A6
14A6
14A6
23D6
23D6 23D6
23D6 23D6
14A6
14A6
23D6
23D6
23D6
23D2 23D2
23D2 23D2
23D2
23D2 23D2
14C3
14C3
14C3 14C3
14C3 14C3
14C3 14C3
14C3
14D3
14D3 14D3
14D3 14D3
14D3 14D3
14B6
14B6 14B6
14C6 14C6
11B2
14B6
14B6
14B6
14A6 14A6
23D6
23D6
11C2 11C2
11B3
14B6
14B6
14B6
14B6
14B6
14B6
11B2
14B6
23C6
23D2
23C2 23C2
23D2
23D2 23D2
14E3 14E3
14E3 14E3
14E3 14E3
14E3 14E3
14E3 14E3
14E3 14E3
14D3 14D3
14E3 14D3
14D3 14D3
14D3 14D3
14D3 14D3
14D3 14D3
14C3 23C6
14C3
23D6
14A6
14A6
14A6
14A6
14A6
14A6
14A6
14A6
14A6
14A6
14A6 14A6
11B2
14A6
11B2
14A6 14A6
14A6
23D2
14B6
RX_GXB_R1_P<2>
RX_GXB_R1_P<4>RX_GXB_R1_N<2>
RX_GXB_R1_N<4>
RX_GXB_R1_P<0>RX_GXB_R1_N<0>
TTC_REF_CLK6_NTTC_REF_CLK6_P
TX_GXB_R0_P<8>
TX_GXB_R0_P<6>TX_GXB_R0_N<8>
TX_GXB_R0_N<6>
TX_GXB_R0_P<7>
TX_GXB_R0_P<10>TX_GXB_R0_N<10>
TX_GXB_R0_N<9>
TX_GXB_R0_N<7>
TX_GXB_R0_P<9>TX_GXB_R0_N<11>TX_GXB_R0_P<11>
TX_GXB_R0_P<1>
TX_GXB_R0_P<3>
TX_GXB_R0_N<1>
TX_GXB_R0_N<3>
TX_GXB_R0_P<0>TX_GXB_R0_N<0>
TX_GXB_R0_N<4>
TX_GXB_R0_N<2>TX_GXB_R0_P<2>
TX_GXB_R0_P<4>
TX_GXB_R0_N<5>
RX_GXB_R0_P<6>RX_GXB_R0_N<6>RX_GXB_R0_P<8>
RX_GXB_R0_N<4>
RX_GXB_R0_P<9>
RX_GXB_R0_P<7>RX_GXB_R0_N<9>
RX_GXB_R0_N<7>
TX_GXB_R1_P<8>RX_GBT_P<2>
TTC_REF_CLK4_NTTC_REF_CLK4_P
TTC_REF_CLK8_P
RX_GXB_R0_N<11>RX_GXB_R0_P<11>RX_GXB_R0_N<10>
RX_GXB_R0_N<8>
TTC_REF_CLK8_N
TX_GXB_R1_P<1>RX_GXB_R0_P<10>
TTC_REF_CLK7_PTTC_REF_CLK7_N
RX_GXB_R0_P<4>RX_GXB_R0_N<2>
RX_GXB_R0_N<1>
RX_GXB_R0_N<0>
RX_GXB_R0_P<1>
RX_GXB_R0_P<0>
RX_GXB_R0_N<3>RX_GXB_R0_P<3>
RX_GXB_R0_P<2>TX_XAUI_P<0>TX_XAUI_N<1>
TX_GXB_R0_P<5>
XAUI_REF_CLK_NXAUI_REF_CLK_P
RX_XAUI_P<1>RX_XAUI_N<2>RX_XAUI_P<2>RX_XAUI_N<3>RX_XAUI_P<3>
RX_XAUI_P<0>RX_XAUI_N<1>
RX_XAUI_N<0>
TX_XAUI_P<3>TX_XAUI_N<3>TX_XAUI_P<2>TX_XAUI_N<2>TX_XAUI_P<1>
TX_XAUI_N<0>
RX_GBT_N<2>RX_GBT_P<1>RX_GBT_N<1>RX_GBT_P<0>RX_GBT_N<0>
TX_GBT_N<1>TX_GBT_P<0>TX_GBT_N<0>
TX_GBT_P<1>TX_GBT_N<2>TX_GBT_P<2>
TX_GXB_R1_P<5>TX_GXB_R1_N<5>
TX_GXB_R1_P<2>TX_GXB_R1_N<2>TX_GXB_R1_P<4>TX_GXB_R1_N<4>
TX_GXB_R1_N<0>TX_GXB_R1_P<0>
TX_GXB_R1_N<3>
TX_GXB_R1_N<1>
TX_GXB_R1_P<3>
TX_GXB_R1_N<6>TX_GXB_R1_P<6>
TX_GXB_R1_N<11>
TX_GXB_R1_P<7>
TX_GXB_R1_P<9>TX_GXB_R1_N<9>
TX_GXB_R1_P<11>TX_GXB_R1_N<10>TX_GXB_R1_P<10>TX_GXB_R1_N<8>
TX_GXB_R1_N<7>RX_GXB_R1_N<7>RX_GXB_R1_P<7>RX_GXB_R1_N<9>
RX_GXB_R1_P<6>
RX_GXB_R1_P<5>RX_GXB_R1_N<5>RX_GXB_R1_P<3>RX_GXB_R1_N<3>RX_GXB_R1_P<1>RX_GXB_R1_N<1>
TTC_REF_CLK5_NTTC_REF_CLK5_P
RX_GXB_R1_P<11>RX_GXB_R1_N<11>RX_GXB_R1_P<9>
RX_GXB_R1_N<6>RX_GXB_R1_P<8>RX_GXB_R1_N<8>RX_GXB_R1_P<10>RX_GXB_R1_N<10>
RX_GXB_R0_N<5>RX_GXB_R0_P<5>
L7L8
A7A8B5B6A3A4
B9B10C7C8E7E8
N7N8
R7R8
B1B2C3C4D1D2E3E4F1F2G3G4
D5D6F5F6H5H6K5K6L3L4M5M6
U7U8
W7W8
H1H2J3J4K1K2M1M2P1P2T1T2
N3N4P5P6R3R4T5T6U3U4V5V6
AA7AA8
AC7AC8
V1V2Y1Y2AB1AB2AD1AD2AF1AF2AH1AH2
W3W4Y5Y6
AA3AA4AB5AB6AC3AC4AD5AD6
AE7AE8
AG7AG8
AK1AK2AL3AL4AM1AM2AN3AN4AP1AP2AR3AR4
AE3AE4AF5AF6AG3AG4AH5AH6AJ3AJ4AK5AK6
AJ7AJ8
AL7AL8
AT1AT2AU3AU4AV1AV2AW3AW4AV5AV6AW7AW8
AM5AM6AP5AP6AT5AT6AR7AR8AU7AU8AV9
AV10
OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
IN
OUT
BANK4I : Transceivers10ax115f40
REFCLK_GXBR4I_CHTPREFCLK_GXBR4I_CHTN
REFCLK_GXBR4I_CHBPREFCLK_GXBR4I_CHBN
GXBR4I_TX_CH5PGXBR4I_TX_CH5N
GXBR4I_TX_CH4PGXBR4I_TX_CH4N
GXBR4I_TX_CH3PGXBR4I_TX_CH3N
GXBR4I_TX_CH2PGXBR4I_TX_CH2N
GXBR4I_TX_CH1PGXBR4I_TX_CH1N
GXBR4I_TX_CH0PGXBR4I_TX_CH0N
GXBR4I_RX_CH5P_GXBR4I_REFCLK5PGXBR4I_RX_CH5N_GXBR4I_REFCLK5N
GXBR4I_RX_CH4P_GXBR4I_REFCLK4PGXBR4I_RX_CH4N_GXBR4I_REFCLK4N
GXBR4I_RX_CH3P_GXBR4I_REFCLK3PGXBR4I_RX_CH3N_GXBR4I_REFCLK3N
GXBR4I_RX_CH2P_GXBR4I_REFCLK2PGXBR4I_RX_CH2N_GXBR4I_REFCLK2N
GXBR4I_RX_CH1P_GXBR4I_REFCLK1PGXBR4I_RX_CH1N_GXBR4I_REFCLK1N
GXBR4I_RX_CH0P_GXBR4I_REFCLK0PGXBR4I_RX_CH0N_GXBR4I_REFCLK0N
GND
INININININ
ININ
IN
IN
IN
ININ
IN
INININ
ININ
IN
INININ
INININ
BANK4H : Transceivers10ax115f40
REFCLK_GXBR4H_CHTPREFCLK_GXBR4H_CHTN
REFCLK_GXBR4H_CHBPREFCLK_GXBR4H_CHBN
GXBR4H_TX_CH5PGXBR4H_TX_CH5N
GXBR4H_TX_CH4PGXBR4H_TX_CH4N
GXBR4H_TX_CH3PGXBR4H_TX_CH3N
GXBR4H_TX_CH2PGXBR4H_TX_CH2N
GXBR4H_TX_CH1PGXBR4H_TX_CH1N
GXBR4H_TX_CH0PGXBR4H_TX_CH0N
GXBR4H_RX_CH5P_GXBR4H_REFCLK5PGXBR4H_RX_CH5N_GXBR4H_REFCLK5N
GXBR4H_RX_CH4P_GXBR4H_REFCLK4PGXBR4H_RX_CH4N_GXBR4H_REFCLK4N
GXBR4H_RX_CH3P_GXBR4H_REFCLK3PGXBR4H_RX_CH3N_GXBR4H_REFCLK3N
GXBR4H_RX_CH2P_GXBR4H_REFCLK2PGXBR4H_RX_CH2N_GXBR4H_REFCLK2N
GXBR4H_RX_CH1P_GXBR4H_REFCLK1PGXBR4H_RX_CH1N_GXBR4H_REFCLK1N
GXBR4H_RX_CH0P_GXBR4H_REFCLK0PGXBR4H_RX_CH0N_GXBR4H_REFCLK0N
GND
OUTOUT
IN
OUTOUT
OUT
OUTOUT
OUTOUT
OUTOUTOUT
IN
OUTOUTOUTOUTOUT
BANK4G : Transceivers10ax115f40
REFCLK_GXBR4G_CHTPREFCLK_GXBR4G_CHTN
REFCLK_GXBR4G_CHBPREFCLK_GXBR4G_CHBN
GXBR4G_TX_CH5PGXBR4G_TX_CH5N
GXBR4G_TX_CH4PGXBR4G_TX_CH4N
GXBR4G_TX_CH3PGXBR4G_TX_CH3N
GXBR4G_TX_CH2PGXBR4G_TX_CH2N
GXBR4G_TX_CH1PGXBR4G_TX_CH1N
GXBR4G_TX_CH0PGXBR4G_TX_CH0N
GXBR4G_RX_CH5P_GXBR4G_REFCLK5PGXBR4G_RX_CH5N_GXBR4G_REFCLK5N
GXBR4G_RX_CH4P_GXBR4G_REFCLK4PGXBR4G_RX_CH4N_GXBR4G_REFCLK4N
GXBR4G_RX_CH3P_GXBR4G_REFCLK3PGXBR4G_RX_CH3N_GXBR4G_REFCLK3N
GXBR4G_RX_CH2P_GXBR4G_REFCLK2PGXBR4G_RX_CH2N_GXBR4G_REFCLK2N
GXBR4G_RX_CH1P_GXBR4G_REFCLK1PGXBR4G_RX_CH1N_GXBR4G_REFCLK1N
GXBR4G_RX_CH0P_GXBR4G_REFCLK0PGXBR4G_RX_CH0N_GXBR4G_REFCLK0N
GND
IN
IN
IN
IN
IN
ININININ
ININININ
IN
IN
IN
ININ
ININ
IN
BANK4F : Transceivers10ax115f40
REFCLK_GXBR4F_CHTPREFCLK_GXBR4F_CHTN
REFCLK_GXBR4F_CHBPREFCLK_GXBR4F_CHBN
GXBR4F_TX_CH5PGXBR4F_TX_CH5N
GXBR4F_TX_CH4PGXBR4F_TX_CH4N
GXBR4F_TX_CH3PGXBR4F_TX_CH3N
GXBR4F_TX_CH2PGXBR4F_TX_CH2N
GXBR4F_TX_CH1PGXBR4F_TX_CH1N
GXBR4F_TX_CH0PGXBR4F_TX_CH0N
GXBR4F_RX_CH5P_GXBR4F_REFCLK5PGXBR4F_RX_CH5N_GXBR4F_REFCLK5N
GXBR4F_RX_CH4P_GXBR4F_REFCLK4PGXBR4F_RX_CH4N_GXBR4F_REFCLK4N
GXBR4F_RX_CH3P_GXBR4F_REFCLK3PGXBR4F_RX_CH3N_GXBR4F_REFCLK3N
GXBR4F_RX_CH2P_GXBR4F_REFCLK2PGXBR4F_RX_CH2N_GXBR4F_REFCLK2N
GXBR4F_RX_CH1P_GXBR4F_REFCLK1PGXBR4F_RX_CH1N_GXBR4F_REFCLK1N
GXBR4F_RX_CH0P_GXBR4F_REFCLK0PGXBR4F_RX_CH0N_GXBR4F_REFCLK0N
GND
IN
IN
BANK4E : Transceivers10ax115f40
REFCLK_GXBR4E_CHTPREFCLK_GXBR4E_CHTN
REFCLK_GXBR4E_CHBPREFCLK_GXBR4E_CHBN
GXBR4E_TX_CH5PGXBR4E_TX_CH5N
GXBR4E_TX_CH4PGXBR4E_TX_CH4N
GXBR4E_TX_CH3PGXBR4E_TX_CH3N
GXBR4E_TX_CH2PGXBR4E_TX_CH2N
GXBR4E_TX_CH1PGXBR4E_TX_CH1N
GXBR4E_TX_CH0PGXBR4E_TX_CH0N
GXBR4E_RX_CH5P_GXBR4E_REFCLK5PGXBR4E_RX_CH5N_GXBR4E_REFCLK5N
GXBR4E_RX_CH4P_GXBR4E_REFCLK4PGXBR4E_RX_CH4N_GXBR4E_REFCLK4N
GXBR4E_RX_CH3P_GXBR4E_REFCLK3PGXBR4E_RX_CH3N_GXBR4E_REFCLK3N
GXBR4E_RX_CH2P_GXBR4E_REFCLK2PGXBR4E_RX_CH2N_GXBR4E_REFCLK2N
GXBR4E_RX_CH1P_GXBR4E_REFCLK1PGXBR4E_RX_CH1N_GXBR4E_REFCLK1N
GXBR4E_RX_CH0P_GXBR4E_REFCLK0PGXBR4E_RX_CH0N_GXBR4E_REFCLK0N
IN
ININ
ININ
OUTOUTOUTOUT
OUTOUT
OUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
IN
OUTOUT
BANK4J : Transceivers10ax115f40
REFCLK_GXBR4J_CHBPREFCLK_GXBR4J_CHBN
GXBR4J_TX_CH2PGXBR4J_TX_CH2N
GXBR4J_TX_CH1PGXBR4J_TX_CH1N
GXBR4J_TX_CH0PGXBR4J_TX_CH0N
GXBR4J_RX_CH2P_GXBR4J_REFCLK2PGXBR4J_RX_CH2N_GXBR4J_REFCLK2N
GXBR4J_RX_CH1P_GXBR4J_REFCLK1PGXBR4J_RX_CH1N_GXBR4J_REFCLK1N
GXBR4J_RX_CH0P_GXBR4J_REFCLK0PGXBR4J_RX_CH0N_GXBR4J_REFCLK0N
ININININ
ININ
IN
IN
IN
ININ
INININ
OUTOUT
OUTOUT
IN
GND
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
SOFT CDR ON RX LVDS ONLY ON PINS WITH EVEN NUMBER
BOTTOM BANK 1.8V
ARRIA10 : BANK 2A,2F,2K,2L
LVDS<3:2> IN OPTION
A/C PIN PLACEMENT IS FIXEDBANK 2L : DDR3_0 ADRESS/COMMAND PINS
DDR3 PLACEMENT CONFIRMED WITH QUARTUS (PCB CONSTRAINTS PG.74....)SEE ARRIA 10EMIF GUIDELINES FOR PLACEMENT RULES
DQS AND DQ IN SAME IO LANE : COULD BE CHANGEDBANK 2K : DDR3_0 DATA PINS
BOTTOM BANK 1.8V
PUT PRREQUEST AT 0 IF NOT USED
TOP BANK 1.5V TOP BANK 1.5V
MODIFIE: Mon Mar 23 09:50:41 2015
SHEET: 21 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 21 / 27
AT30AR30
AH26AJ26
AG26AF26
AN28AM28
AE29AE28
AM29AN29
AL26AM26
AF25AE25
AN31AP30AN27AP27
AF28AF27AN26AP26
AJ27AH27
AT28AU28
AL28AK28
AG28AH28
AH24AJ24
AJ25AK25
AK29AJ29
AH29AG29
U14
R45
L22K22
B23C23
E23F23
J22H22
E22F22
C22D22
G23H23
M23L23A22A23
B24C24
C21D21H24J24
M21L21
A26B26
J21H21
G21F21
E25F25
G24G25
A20B20
D20E20
U14
AE24
AN24
AT23AH23
AN22
AG23 AL23
AN23AR23
AE23
AL22AK22 AH22
AU24AU23
AK23AK24AV24AW24
AV22AV23
AU25AT25
AR25AP25
AR22AP22
AT21AT22
AU21AV21
AT26AT27
AM25AL25
AW22AW21
AM23
AJ22
AM24
U14
R44
K29J29
M26N26
D25D26
L28K28
M29N29
G29H29
C26C27
D27C28
P29R29L25M25
K27L27J26J27
F30E30
K25L26
H28H27
G28F28
N27P27
R27R28
E29E28
D29D30
U14
P1V8
10K
240
FPGA_TEST_LED_N_1.8V
MMC_FPGA_RESETN_1.8V
DDR3_0_ODT
DDR3_0_DQS1_N
DDR3_0_DQ<3>
DDR3_0_DQ<13>DDR3_0_DQ<12>
DDR3_0_DQS1_P
DDR3_0_DM1
DDR3_0_DQ<9>DDR3_0_DQ<8>
DDR3_0_DQ<1>
DDR3_0_DQ<10>
DDR3_0_DQ<2>
DDR3_0_DQ<7>DDR3_0_DQ<5>DDR3_0_DQ<6>
DDR3_0_DQ<11>DDR3_0_DQ<15>
DDR3_0_DQ<4>
FPGA_INIT_DONE
TTC_CLK_SEL_1.8V
RX_UPOD_RESETN_1.8V
TX_UPOD_RESETN_1.8V
HARD_FPGA_RESET_NAMC_TTC_CLK_LOS_1.8VLOCAL_TTC_CLK_LOS_1.8V
TX_LVDS_P<1>RX_LVDS_N<1>
TX_LVDS_P<0>
RX_LVDS_P<0>TX_LVDS_N<1>
RX_LVDS_N<0>
RX_LVDS_P<1>
TX_LVDS_N<0>
TX_LVDS_N<2>TX_LVDS_P<2>RX_LVDS_N<2>RX_LVDS_P<2>TX_LVDS_N<3>TX_LVDS_P<3>
UPOD_SDA_1.8VUPOD_SCL_1.8V
DDR3_0_A<4>DDR3_0_A<1>
DDR3_0_CKNDDR3_0_CKP
DDR3_0_CASNDDR3_0_RASN
DDR3_0_RESETN
DDR3_0_A<5>DDR3_0_A<8>DDR3_0_A<9>
DDR3_0_BA<0>
DDR3_0_WEN
DDR3_0_A<0>
RX_LVDS_P<3>RX_LVDS_N<3>
DDR3_0_CKE
DDR3_0_BA<2>DDR3_0_BA<1>DDR3_0_A<12>
DDR3_0_CSN
DDR3_0_DQ<14>
CLKUSR
TX_UPOD_L0_INTN_1.8V
RX_UPOD_R0_INTN_1.8VRX_UPOD_R1_INTN_1.8VRX_UPOD_L0_INTN_1.8VRX_UPOD_L1_INTN_1.8V
MMC_FPGA_USER_IO0_1.8VMMC_FPGA_USER_IO1_1.8V
TX_UPOD_R1_INTN_1.8V
TX_UPOD_L1_INTN_1.8V
TX_UPOD_R0_INTN_1.8V
DDR3_0_A<2>DDR3_0_A<3>
9D7
9E7
9D7
9D5
9D5
9D5 9D5
9D5
9D7
9D5 9D7 9D5
9D5
9D5
9D5 9D5
9D5
9D5
9D5
9D5
9D5
9D5
26D5
25B1
25C1
25C5 25C5
25D5
25D5
23C2
23C6
23C2
23C6
23C2
23C6
23C6
23C2
23C2 23C2
23C6 23C6
23C2 23C2
25B7 25A7 25B7 25A7
9E7
9E7
9D8 9D8
9D7
9D7
9D7
9E7
9E7 9E7
9D7
9D7
9E7
23C6 23C6
9D7
9D7
9D7
10B6
25A1
25C1
25B1
25D1 25D1
25E5
25E5 25C1
25E5 25A1
25A1
25A1
9E7
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
BI
OUTOUT
ININ
OUTOUT
BI
ININ
OUTOUT
ININ
OUTOUT
ININ
BI
OUTOUTOUT
OUTOUTOUTOUTOUTOUTOUTBIOUTOUTOUT
IO BANK 2F10ax115f40
IO47_LVDS2F_1NIO46_LVDS2F_1P
IO45_LVDS2F_2NIO44_LVDS2F_2P
IO43_LVDS2F_3NIO42_LVDS2F_3P
IO41_LVDS2F_4NIO40_LVDS2F_4P
IO39_LVDS2F_5NIO38_LVDS2F_5P
IO37_LVDS2F_6NIO36_LVDS2F_6P
IO35_LVDS2F_7NIO34_LVDS2F_7P
IO33_LVDS2F_8NIO32_LVDS2F_8P
IO31_LVDS2F_9NIO30_LVDS2F_9P
IO27_LVDS2F_11NIO26_RZQ2F_LVDS2F_11P
IO21_LVDS2F_14NIO20_LVDS2F_14P
IO17_LVDS2F_16NIO16_LVDS2F_16P
IO15_LVDS2F_17NIO14_LVDS2F_17P
IO13_LVDS2F_18NIO12_LVDS2F_18P
IO11_LVDS2F_19NIO10_LVDS2F_19P
IO9_LVDS2F_20NIO8_LVDS2F_20P
IO7_LVDS2F_21NIO6_LVDS2F_21P
IO5_LVDS2F_22NIO4_LVDS2F_22P
IO3_LVDS2F_23NIO2_LVDS2F_23P
IO1_LVDS2F_24NIO0_LVDS2F_24P
*
OUTOUTOUT
OUTOUT
IO BANK 2K10ax115f40
IO47_LVDS2K_1NIO46_LVDS2K_1P
IO45_LVDS2K_2NIO44_LVDS2K_2P
IO43_LVDS2K_3NIO42_LVDS2K_3P
IO41_LVDS2K_4NIO40_LVDS2K_4P
IO39_LVDS2K_5NIO38_LVDS2K_5P
IO37_LVDS2K_6NIO36_LVDS2K_6P
IO35_LVDS2K_7NIO34_LVDS2K_7P
IO33_LVDS2K_8NIO32_LVDS2K_8P
IO31_LVDS2K_9NIO30_LVDS2K_9P
IO27_LVDS2K_11NIO26_RZQ2K_LVDS2K_11P
IO21_LVDS2K_14NIO20_LVDS2K_14P
IO17_LVDS2K_16NIO16_LVDS2K_16P
IO15_LVDS2K_17NIO14_LVDS2K_17P
IO13_LVDS2K_18NIO12_LVDS2K_18P
IO11_LVDS2K_19NIO10_LVDS2K_19P
IO9_LVDS2K_20NIO8_LVDS2K_20P
IO7_LVDS2K_21NIO6_LVDS2K_21P
IO5_LVDS2K_22NIO4_LVDS2K_22P
IO3_LVDS2K_23NIO2_LVDS2K_23P
IO1_LVDS2K_24NIO0_LVDS2K_24P
OUT
IO BANK 2L10ax115f40
IO47_LVDS2L_1NIO46_LVDS2L_1P
IO45_LVDS2L_2NIO44_LVDS2L_2P
IO43_LVDS2L_3NIO42_LVDS2L_3P
IO41_LVDS2L_4NIO40_LVDS2L_4P
IO39_LVDS2L_5NIO38_LVDS2L_5P
IO37_LVDS2L_6NIO36_LVDS2L_6P
IO35_LVDS2L_7NIO34_LVDS2L_7P
IO33_LVDS2L_8NIO32_LVDS2L_8P
IO31_LVDS2L_9NIO30_LVDS2L_9P
IO27_LVDS2L_11NIO26_RZQ2L_LVDS2L_11P
IO21_LVDS2L_14NIO20_LVDS2L_14P
IO17_LVDS2L_16NIO16_LVDS2L_16P
IO15_LVDS2L_17NIO14_LVDS2L_17P
IO13_LVDS2L_18NIO12_LVDS2L_18P
IO11_LVDS2L_19NIO10_LVDS2L_19P
IO9_LVDS2L_20NIO8_LVDS2L_20P
IO7_LVDS2L_21NIO6_LVDS2L_21P
IO5_LVDS2L_22NIO4_LVDS2L_22P
IO3_LVDS2L_23NIO2_LVDS2L_23P
IO1_LVDS2L_24NIO0_LVDS2L_24P
OUT
OUT
BIBI
ININININ
BI
IN
INININ
ININ
OUT
OUT
OUT
IN
BI
INININ
IN
GND
BI
BIBI
OUT
BI
BI
BI
OUT
IO BANK 2A10ax115f40
RZQ2A_LVDS2A_11P
PRREQUEST_LVDS2A_18P
PRREADY_LVDS2A_19N
PRERROR_LVDS2A_21N
PRDONE_LVDS2A_20N
NPERSTR1_LVDS2A_21PNPERSTR0_LVDS2A_22P
NPERSTL1_LVDS2A_20PNPERSTL0_LVDS2A_19P
NCEO_LVDS2A_11N
INITDONE_LVDS2A_23NDEVOE_LVDS2A_23P DEVCLRN_LVDS2A_24P
DATA31_LVDS2A_17PDATA30_LVDS2A_17N
DATA29_LVDS2A_16PDATA28_LVDS2A_16N
DATA25_LVDS2A_14PDATA24_LVDS2A_14N
DATA17_LVDS2A_9PDATA16_LVDS2A_9N
DATA15_LVDS2A_8PDATA14_LVDS2A_8N
DATA13_LVDS2A_7PDATA12_LVDS2A_7N
DATA11_LVDS2A_6PDATA10_LVDS2A_6N
DATA9_LVDS2A_5PDATA8_LVDS2A_5N
DATA7_LVDS2A_4PDATA6_LVDS2A_4N
DATA5_LVDS2A_3PDATA4_LVDS2A_3N
DATA3_LVDS2A_2PDATA2_LVDS2A_2N
DATA1_LVDS2A_1PDATA0_LVDS2A_1N
CVPCONFDONE_LVDS2A_22N
CRCERROR_LVDS2A_24N
CLKUSR_LVDS2A_18N
OUT
OUT
*
BIBIBI
BI
SOFT CDR ON RX LVDS ONLY ON PINS WITH EVEN NUMBER
BOTTOM BANK 1.8V
ARRIA10 : BANK 2A,2F,2K,2L
LVDS<3:2> IN OPTION
A/C PIN PLACEMENT IS FIXEDBANK 2L : DDR3_0 ADRESS/COMMAND PINS
DDR3 PLACEMENT CONFIRMED WITH QUARTUS (PCB CONSTRAINTS PG.74....)SEE ARRIA 10EMIF GUIDELINES FOR PLACEMENT RULES
DQS AND DQ IN SAME IO LANE : COULD BE CHANGEDBANK 2K : DDR3_0 DATA PINS
BOTTOM BANK 1.8V
PUT PRREQUEST AT 0 IF NOT USED
TOP BANK 1.5V TOP BANK 1.5V
MODIFIE: Mon Mar 23 09:50:41 2015
SHEET: 21 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 21 / 27
P1V8
10K
240
U14
R45
U14
U14
R44
U14
9D7
9E7
9D7
9D5
9D5
9D5 9D5
9D5
9D7
9D5 9D7 9D5
9D5
9D5
9D5 9D5
9D5
9D5
9D5
9D5
9D5
9D5
26D5
25B1
25C1
25C5 25C5
25D5
25D5
23C2
23C6
23C2
23C6
23C2
23C6
23C6
23C2
23C2 23C2
23C6 23C6
23C2 23C2
25B7 25A7 25B7 25A7
9E7
9E7
9D8 9D8
9D7
9D7
9D7
9E7
9E7 9E7
9D7
9D7
9E7
23C6 23C6
9D7
9D7
9D7
10B6
25A1
25C1
25B1
25D1 25D1
25E5
25E5 25C1
25E5 25A1
25A1
25A1
9E7
FPGA_TEST_LED_N_1.8V
MMC_FPGA_RESETN_1.8V
DDR3_0_ODT
DDR3_0_DQS1_N
DDR3_0_DQ<3>
DDR3_0_DQ<13>DDR3_0_DQ<12>
DDR3_0_DQS1_P
DDR3_0_DM1
DDR3_0_DQ<9>DDR3_0_DQ<8>
DDR3_0_DQ<1>
DDR3_0_DQ<10>
DDR3_0_DQ<2>
DDR3_0_DQ<7>DDR3_0_DQ<5>DDR3_0_DQ<6>
DDR3_0_DQ<11>DDR3_0_DQ<15>
DDR3_0_DQ<4>
FPGA_INIT_DONE
TTC_CLK_SEL_1.8V
RX_UPOD_RESETN_1.8V
TX_UPOD_RESETN_1.8V
HARD_FPGA_RESET_NAMC_TTC_CLK_LOS_1.8VLOCAL_TTC_CLK_LOS_1.8V
TX_LVDS_P<1>RX_LVDS_N<1>
TX_LVDS_P<0>
RX_LVDS_P<0>TX_LVDS_N<1>
RX_LVDS_N<0>
RX_LVDS_P<1>
TX_LVDS_N<0>
TX_LVDS_N<2>TX_LVDS_P<2>RX_LVDS_N<2>RX_LVDS_P<2>TX_LVDS_N<3>TX_LVDS_P<3>
UPOD_SDA_1.8VUPOD_SCL_1.8V
DDR3_0_A<4>DDR3_0_A<1>
DDR3_0_CKNDDR3_0_CKP
DDR3_0_CASNDDR3_0_RASN
DDR3_0_RESETN
DDR3_0_A<5>DDR3_0_A<8>DDR3_0_A<9>
DDR3_0_BA<0>
DDR3_0_WEN
DDR3_0_A<0>
RX_LVDS_P<3>RX_LVDS_N<3>
DDR3_0_CKE
DDR3_0_BA<2>DDR3_0_BA<1>DDR3_0_A<12>
DDR3_0_CSN
DDR3_0_DQ<14>
CLKUSR
TX_UPOD_L0_INTN_1.8V
RX_UPOD_R0_INTN_1.8VRX_UPOD_R1_INTN_1.8VRX_UPOD_L0_INTN_1.8VRX_UPOD_L1_INTN_1.8V
MMC_FPGA_USER_IO0_1.8VMMC_FPGA_USER_IO1_1.8V
TX_UPOD_R1_INTN_1.8V
TX_UPOD_L1_INTN_1.8V
TX_UPOD_R0_INTN_1.8V
DDR3_0_A<2>DDR3_0_A<3>
AT30AR30
AH26AJ26
AG26AF26
AN28AM28
AE29AE28
AM29AN29
AL26AM26
AF25AE25
AN31AP30AN27AP27
AF28AF27AN26AP26
AJ27AH27
AT28AU28
AL28AK28
AG28AH28
AH24AJ24
AJ25AK25
AK29AJ29
AH29AG29
L22K22
B23C23
E23F23
J22H22
E22F22
C22D22
G23H23
M23L23A22A23
B24C24
C21D21H24J24
M21L21
A26B26
J21H21
G21F21
E25F25
G24G25
A20B20
D20E20
AE24
AN24
AT23AH23
AN22
AG23 AL23
AN23AR23
AE23
AL22AK22 AH22
AU24AU23
AK23AK24AV24AW24
AV22AV23
AU25AT25
AR25AP25
AR22AP22
AT21AT22
AU21AV21
AT26AT27
AM25AL25
AW22AW21
AM23
AJ22
AM24
K29J29
M26N26
D25D26
L28K28
M29N29
G29H29
C26C27
D27C28
P29R29L25M25
K27L27J26J27
F30E30
K25L26
H28H27
G28F28
N27P27
R27R28
E29E28
D29D30
BI
OUTOUT
ININ
OUTOUT
BI
ININ
OUTOUT
ININ
OUTOUT
ININ
BI
OUTOUTOUT
OUTOUTOUTOUTOUTOUTOUTBIOUTOUTOUT
IO BANK 2F10ax115f40
IO47_LVDS2F_1NIO46_LVDS2F_1P
IO45_LVDS2F_2NIO44_LVDS2F_2P
IO43_LVDS2F_3NIO42_LVDS2F_3P
IO41_LVDS2F_4NIO40_LVDS2F_4P
IO39_LVDS2F_5NIO38_LVDS2F_5P
IO37_LVDS2F_6NIO36_LVDS2F_6P
IO35_LVDS2F_7NIO34_LVDS2F_7P
IO33_LVDS2F_8NIO32_LVDS2F_8P
IO31_LVDS2F_9NIO30_LVDS2F_9P
IO27_LVDS2F_11NIO26_RZQ2F_LVDS2F_11P
IO21_LVDS2F_14NIO20_LVDS2F_14P
IO17_LVDS2F_16NIO16_LVDS2F_16P
IO15_LVDS2F_17NIO14_LVDS2F_17P
IO13_LVDS2F_18NIO12_LVDS2F_18P
IO11_LVDS2F_19NIO10_LVDS2F_19P
IO9_LVDS2F_20NIO8_LVDS2F_20P
IO7_LVDS2F_21NIO6_LVDS2F_21P
IO5_LVDS2F_22NIO4_LVDS2F_22P
IO3_LVDS2F_23NIO2_LVDS2F_23P
IO1_LVDS2F_24NIO0_LVDS2F_24P
*
OUTOUTOUT
OUTOUT
IO BANK 2K10ax115f40
IO47_LVDS2K_1NIO46_LVDS2K_1P
IO45_LVDS2K_2NIO44_LVDS2K_2P
IO43_LVDS2K_3NIO42_LVDS2K_3P
IO41_LVDS2K_4NIO40_LVDS2K_4P
IO39_LVDS2K_5NIO38_LVDS2K_5P
IO37_LVDS2K_6NIO36_LVDS2K_6P
IO35_LVDS2K_7NIO34_LVDS2K_7P
IO33_LVDS2K_8NIO32_LVDS2K_8P
IO31_LVDS2K_9NIO30_LVDS2K_9P
IO27_LVDS2K_11NIO26_RZQ2K_LVDS2K_11P
IO21_LVDS2K_14NIO20_LVDS2K_14P
IO17_LVDS2K_16NIO16_LVDS2K_16P
IO15_LVDS2K_17NIO14_LVDS2K_17P
IO13_LVDS2K_18NIO12_LVDS2K_18P
IO11_LVDS2K_19NIO10_LVDS2K_19P
IO9_LVDS2K_20NIO8_LVDS2K_20P
IO7_LVDS2K_21NIO6_LVDS2K_21P
IO5_LVDS2K_22NIO4_LVDS2K_22P
IO3_LVDS2K_23NIO2_LVDS2K_23P
IO1_LVDS2K_24NIO0_LVDS2K_24P
OUT
IO BANK 2L10ax115f40
IO47_LVDS2L_1NIO46_LVDS2L_1P
IO45_LVDS2L_2NIO44_LVDS2L_2P
IO43_LVDS2L_3NIO42_LVDS2L_3P
IO41_LVDS2L_4NIO40_LVDS2L_4P
IO39_LVDS2L_5NIO38_LVDS2L_5P
IO37_LVDS2L_6NIO36_LVDS2L_6P
IO35_LVDS2L_7NIO34_LVDS2L_7P
IO33_LVDS2L_8NIO32_LVDS2L_8P
IO31_LVDS2L_9NIO30_LVDS2L_9P
IO27_LVDS2L_11NIO26_RZQ2L_LVDS2L_11P
IO21_LVDS2L_14NIO20_LVDS2L_14P
IO17_LVDS2L_16NIO16_LVDS2L_16P
IO15_LVDS2L_17NIO14_LVDS2L_17P
IO13_LVDS2L_18NIO12_LVDS2L_18P
IO11_LVDS2L_19NIO10_LVDS2L_19P
IO9_LVDS2L_20NIO8_LVDS2L_20P
IO7_LVDS2L_21NIO6_LVDS2L_21P
IO5_LVDS2L_22NIO4_LVDS2L_22P
IO3_LVDS2L_23NIO2_LVDS2L_23P
IO1_LVDS2L_24NIO0_LVDS2L_24P
OUT
OUT
BIBI
ININININ
BI
IN
INININ
ININ
OUT
OUT
OUT
IN
BI
INININ
IN
GND
BI
BIBI
OUT
BI
BI
BI
OUT
IO BANK 2A10ax115f40
RZQ2A_LVDS2A_11P
PRREQUEST_LVDS2A_18P
PRREADY_LVDS2A_19N
PRERROR_LVDS2A_21N
PRDONE_LVDS2A_20N
NPERSTR1_LVDS2A_21PNPERSTR0_LVDS2A_22P
NPERSTL1_LVDS2A_20PNPERSTL0_LVDS2A_19P
NCEO_LVDS2A_11N
INITDONE_LVDS2A_23NDEVOE_LVDS2A_23P DEVCLRN_LVDS2A_24P
DATA31_LVDS2A_17PDATA30_LVDS2A_17N
DATA29_LVDS2A_16PDATA28_LVDS2A_16N
DATA25_LVDS2A_14PDATA24_LVDS2A_14N
DATA17_LVDS2A_9PDATA16_LVDS2A_9N
DATA15_LVDS2A_8PDATA14_LVDS2A_8N
DATA13_LVDS2A_7PDATA12_LVDS2A_7N
DATA11_LVDS2A_6PDATA10_LVDS2A_6N
DATA9_LVDS2A_5PDATA8_LVDS2A_5N
DATA7_LVDS2A_4PDATA6_LVDS2A_4N
DATA5_LVDS2A_3PDATA4_LVDS2A_3N
DATA3_LVDS2A_2PDATA2_LVDS2A_2N
DATA1_LVDS2A_1PDATA0_LVDS2A_1N
CVPCONFDONE_LVDS2A_22N
CRCERROR_LVDS2A_24N
CLKUSR_LVDS2A_18N
OUT
OUT
*
BIBIBI
BI
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
TOP BANK 1.5V
BOTTOM BANK 1.8V
DDR3 PLACEMENT CONFIRMED WITH QUARTUS (PCB CONSTRAINTS PG.74....)
SEE ARRIA 10EMIF GUIDELINES FOR PLACEMENT RULES
BANK 3G : DDR3_0 DATA PINS
TOP BANK 1.5V
DQS AND DQ IN SAME IO LANE : COULD BE CHANGED A/C PIN PLACEMENT IS FIXEDBANK 3H : DDR3_0 ADRESS/COMMAND PINS
BOTTOM BANK 1.8V
MODIFIE: Mon Mar 23 09:50:42 2015
SHEET: 22 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 22 / 27
AR13 AR12AM13 AN13AT11AT12AP14AR14
AP12AN12AW14
AP11AW15
AN11AP10
AU15AT15
AN9AM11
U14
R46
M18L18
K18J17
E17F17
H18G18
E18F18
A18A17
K17L17
D17C17
K19J19H17G16
E19D19F16E15
C18B18
F15G15
C19B19
F20G20
H16J16
M16L16
J20K20
L20M20
U14
AP19 AM15AL16 AR19AT20 AU20AM16 AN16AW20AP15AR15
AR18AV16
AT18
AW16
AU19
AV19
AW17AV17
AR17AT17AU18AV18AP17
U14
M11L11
D15D14
C14B14
J11J12
K12L12
G11H11
E14E13
G14H14
L13M13N14P14
H12H13F13G13
K13K14
C13C12
P11N11
F10F11
E12F12
D12D11
E10D10
P12
U14
26B3
9C4
9B4
9C4 9C4
9C4
9B4
9B4 9B4
9C5
9B4
9C4
9B4
9C4 9C4
9B4
9C4 9C4
9C5
9C4
9B4
9C2
9C2
9C2
9C2
9C2
9C2
9C2
9C2
9C2
9C2
9C4
9C2
9C2
9C2 9C2
9C2 9C2
9C2
26C2 26C2
26C2 26C2 26C2
26C2
26C2 26C2
26C2 26C2
9C4
26B2 26B2
26B3
26B3 26B3 26B3 26B3
26B2
26B3
AMC_ID<3>
DDR3_1_CKE
DDR3_1_BA<1>
DDR3_1_A<2>DDR3_1_A<3>
DDR3_1_A<12>
DDR3_1_RASN
DDR3_1_BA<2> DDR3_1_BA<0>
DDR3_1_CKP
DDR3_1_ODT
DDR3_1_A<0>
DDR3_1_WEN
DDR3_1_A<8>DDR3_1_A<9>DDR3_1_CASN
DDR3_1_A<5>DDR3_1_A<4>
DDR3_1_CKN
DDR3_1_A<1>
DDR3_1_RESETN
DDR3_1_DQS0_P
DDR3_1_DQ<14>
DDR3_1_DQS1_N
DDR3_1_DQ<11>
DDR3_1_DQS0_N
DDR3_1_DQ<6>
DDR3_1_DQ<7>
DDR3_1_DQ<15>
DDR3_1_DQ<13>
DDR3_1_DQS1_P
DDR3_1_DM0
DDR3_1_DQ<3>
DDR3_1_DQ<9>
DDR3_1_DQ<1>DDR3_1_DQ<4>DDR3_1_DQ<5>DDR3_1_DQ<2>DDR3_1_DQ<0>
A10_TEST_IO<9>A10_TEST_IO<8>
A10_TEST_IO<5>A10_TEST_IO<6>A10_TEST_IO<7>
A10_TEST_IO<4>A10_TEST_IO<3>A10_TEST_IO<2>A10_TEST_IO<1>A10_TEST_IO<0>
DDR3_1_CSN
AMC_ID<2>AMC_ID<1>
AMC_ID<8>AMC_ID<7>AMC_ID<6>AMC_ID<5>AMC_ID<4>
AMC_ID<0>
AMC_ID<9>
240
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
IO BANK 3A10ax115f40
IO26_RZQ3A_LVDS3A_11P
IO1_LVDS3A_24N
IO2_LVDS3A_23PIO3_LVDS3A_23N
IO4_LVDS3A_22PIO5_LVDS3A_22N
IO6_LVDS3A_21PIO7_LVDS3A_21N
IO9_LVDS3A_20N
IO11_LVDS3A_19N
IO13_LVDS3A_18N
IO15_LVDS3A_17N
IO17_LVDS3A_16NIO21_LVDS3A_14N
IO27_LVDS3A_11N
IO31_LVDS3A_9NIO33_LVDS3A_8NIO35_LVDS3A_7NIO37_LVDS3A_6NIO39_LVDS3A_5NIO41_LVDS3A_4NIO43_LVDS3A_3NIO45_LVDS3A_2NIO47_LVDS3A_1N
BIBI
BIBIBIBIBI
OUT
BI
OUTOUTOUTOUTOUTOUTOUT
IO BANK 3B10ax115f40
IO1_LVDS3B_24N
IO3_LVDS3B_23N
IO5_LVDS3B_22N
IO7_LVDS3B_21N
IO9_LVDS3B_20N
IO11_LVDS3B_19N
IO13_LVDS3B_18N
IO15_LVDS3B_17N
IO17_LVDS3B_16N
IO20_LVDS3B_14PIO21_LVDS3B_14N
IO26_RZQ3B_LVDS3B_11PIO27_LVDS3B_11N
IO30_LVDS3B_9PIO31_LVDS3B_9N
IO33_LVDS3B_8NIO35_LVDS3B_7NIO37_LVDS3B_6NIO39_LVDS3B_5N
*
OUT
BI
OUT
OUTOUTOUT
IO BANK 3H10ax115f40
IO0_LVDS3H_24PIO1_LVDS3H_24N
IO2_LVDS3H_23PIO3_LVDS3H_23N
IO4_LVDS3H_22PIO5_LVDS3H_22N
IO6_LVDS3H_21PIO7_LVDS3H_21N
IO8_LVDS3H_20PIO9_LVDS3H_20N
IO10_LVDS3H_19PIO11_LVDS3H_19N
IO12_LVDS3H_18PIO13_LVDS3H_18N
IO14_LVDS3H_17PIO15_LVDS3H_17N
IO16_LVDS3H_16PIO17_LVDS3H_16N
IO20_LVDS3H_14PIO21_LVDS3H_14N
IO26_RZQ3H_LVDS3H_11PIO27_LVDS3H_11N
IO30_LVDS3H_9PIO31_LVDS3H_9N
IO32_LVDS3H_8PIO33_LVDS3H_8N
IO34_LVDS3H_7PIO35_LVDS3H_7N
IO36_LVDS3H_6PIO37_LVDS3H_6N
IO38_LVDS3H_5PIO39_LVDS3H_5N
IO40_LVDS3H_4PIO41_LVDS3H_4N
IO42_LVDS3H_3PIO43_LVDS3H_3N
IO44_LVDS3H_2PIO45_LVDS3H_2N
IO46_LVDS3H_1PIO47_LVDS3H_1N
INININININ
BI
INININ
BIBIBIBIBI
ININ
BIOUTOUTOUT
OUT
OUTOUT
GND
BI
BIBI
BI
BIOUT
BIBIBIBI
BIBI
BI
BI
IO BANK 3G10ax115f40
IO1_LVDS3G_24NIO2_LVDS3G_23PIO3_LVDS3G_23N
IO4_LVDS3G_22PIO5_LVDS3G_22N
IO6_LVDS3G_21PIO7_LVDS3G_21N
IO8_LVDS3G_20PIO9_LVDS3G_20N
IO10_LVDS3G_19PIO11_LVDS3G_19N
IO12_LVDS3G_18PIO13_LVDS3G_18N
IO14_LVDS3G_17PIO15_LVDS3G_17N
IO16_LVDS3G_16PIO17_LVDS3G_16N
IO20_LVDS3G_14PIO21_LVDS3G_14N
IO26_RZQ3G_LVDS3G_11PIO27_LVDS3G_11N
IO30_LVDS3G_9PIO31_LVDS3G_9N
IO32_LVDS3G_8PIO33_LVDS3G_8N
IO34_LVDS3G_7PIO35_LVDS3G_7N
IO36_LVDS3G_6PIO37_LVDS3G_6N
IO38_LVDS3G_5PIO39_LVDS3G_5N
IO40_LVDS3G_4PIO41_LVDS3G_4N
IO42_LVDS3G_3PIO43_LVDS3G_3N
IO44_LVDS3G_2PIO45_LVDS3G_2N
IO46_LVDS3G_1PIO47_LVDS3G_1N
TOP BANK 1.5V
BOTTOM BANK 1.8V
DDR3 PLACEMENT CONFIRMED WITH QUARTUS (PCB CONSTRAINTS PG.74....)
SEE ARRIA 10EMIF GUIDELINES FOR PLACEMENT RULES
BANK 3G : DDR3_0 DATA PINS
TOP BANK 1.5V
DQS AND DQ IN SAME IO LANE : COULD BE CHANGED A/C PIN PLACEMENT IS FIXEDBANK 3H : DDR3_0 ADRESS/COMMAND PINS
BOTTOM BANK 1.8V
MODIFIE: Mon Mar 23 09:50:42 2015
SHEET: 22 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 22 / 27
240
U14
R46
U14
U14
U14
26B3
9C4
9B4
9C4 9C4
9C4
9B4
9B4 9B4
9C5
9B4
9C4
9B4
9C4 9C4
9B4
9C4 9C4
9C5
9C4
9B4
9C2
9C2
9C2
9C2
9C2
9C2
9C2
9C2
9C2
9C2
9C4
9C2
9C2
9C2 9C2
9C2 9C2
9C2
26C2 26C2
26C2 26C2 26C2
26C2
26C2 26C2
26C2 26C2
9C4
26B2 26B2
26B3
26B3 26B3 26B3 26B3
26B2
26B3
AMC_ID<3>
DDR3_1_CKE
DDR3_1_BA<1>
DDR3_1_A<2>DDR3_1_A<3>
DDR3_1_A<12>
DDR3_1_RASN
DDR3_1_BA<2> DDR3_1_BA<0>
DDR3_1_CKP
DDR3_1_ODT
DDR3_1_A<0>
DDR3_1_WEN
DDR3_1_A<8>DDR3_1_A<9>DDR3_1_CASN
DDR3_1_A<5>DDR3_1_A<4>
DDR3_1_CKN
DDR3_1_A<1>
DDR3_1_RESETN
DDR3_1_DQS0_P
DDR3_1_DQ<14>
DDR3_1_DQS1_N
DDR3_1_DQ<11>
DDR3_1_DQS0_N
DDR3_1_DQ<6>
DDR3_1_DQ<7>
DDR3_1_DQ<15>
DDR3_1_DQ<13>
DDR3_1_DQS1_P
DDR3_1_DM0
DDR3_1_DQ<3>
DDR3_1_DQ<9>
DDR3_1_DQ<1>DDR3_1_DQ<4>DDR3_1_DQ<5>DDR3_1_DQ<2>DDR3_1_DQ<0>
A10_TEST_IO<9>A10_TEST_IO<8>
A10_TEST_IO<5>A10_TEST_IO<6>A10_TEST_IO<7>
A10_TEST_IO<4>A10_TEST_IO<3>A10_TEST_IO<2>A10_TEST_IO<1>A10_TEST_IO<0>
DDR3_1_CSN
AMC_ID<2>AMC_ID<1>
AMC_ID<8>AMC_ID<7>AMC_ID<6>AMC_ID<5>AMC_ID<4>
AMC_ID<0>
AMC_ID<9>
AR13 AR12AM13 AN13AT11AT12AP14AR14
AP12AN12AW14
AP11AW15
AN11AP10
AU15AT15
AN9AM11
M18L18
K18J17
E17F17
H18G18
E18F18
A18A17
K17L17
D17C17
K19J19H17G16
E19D19F16E15
C18B18
F15G15
C19B19
F20G20
H16J16
M16L16
J20K20
L20M20
AP19 AM15AL16 AR19AT20 AU20AM16 AN16AW20AP15AR15
AR18AV16
AT18
AW16
AU19
AV19
AW17AV17
AR17AT17AU18AV18AP17
M11L11
D15D14
C14B14
J11J12
K12L12
G11H11
E14E13
G14H14
L13M13N14P14
H12H13F13G13
K13K14
C13C12
P11N11
F10F11
E12F12
D12D11
E10D10
P12
IO BANK 3A10ax115f40
IO26_RZQ3A_LVDS3A_11P
IO1_LVDS3A_24N
IO2_LVDS3A_23PIO3_LVDS3A_23N
IO4_LVDS3A_22PIO5_LVDS3A_22N
IO6_LVDS3A_21PIO7_LVDS3A_21N
IO9_LVDS3A_20N
IO11_LVDS3A_19N
IO13_LVDS3A_18N
IO15_LVDS3A_17N
IO17_LVDS3A_16NIO21_LVDS3A_14N
IO27_LVDS3A_11N
IO31_LVDS3A_9NIO33_LVDS3A_8NIO35_LVDS3A_7NIO37_LVDS3A_6NIO39_LVDS3A_5NIO41_LVDS3A_4NIO43_LVDS3A_3NIO45_LVDS3A_2NIO47_LVDS3A_1N
BIBI
BIBIBIBIBI
OUT
BI
OUTOUTOUTOUTOUTOUTOUT
IO BANK 3B10ax115f40
IO1_LVDS3B_24N
IO3_LVDS3B_23N
IO5_LVDS3B_22N
IO7_LVDS3B_21N
IO9_LVDS3B_20N
IO11_LVDS3B_19N
IO13_LVDS3B_18N
IO15_LVDS3B_17N
IO17_LVDS3B_16N
IO20_LVDS3B_14PIO21_LVDS3B_14N
IO26_RZQ3B_LVDS3B_11PIO27_LVDS3B_11N
IO30_LVDS3B_9PIO31_LVDS3B_9N
IO33_LVDS3B_8NIO35_LVDS3B_7NIO37_LVDS3B_6NIO39_LVDS3B_5N
*
OUT
BI
OUT
OUTOUTOUT
IO BANK 3H10ax115f40
IO0_LVDS3H_24PIO1_LVDS3H_24N
IO2_LVDS3H_23PIO3_LVDS3H_23N
IO4_LVDS3H_22PIO5_LVDS3H_22N
IO6_LVDS3H_21PIO7_LVDS3H_21N
IO8_LVDS3H_20PIO9_LVDS3H_20N
IO10_LVDS3H_19PIO11_LVDS3H_19N
IO12_LVDS3H_18PIO13_LVDS3H_18N
IO14_LVDS3H_17PIO15_LVDS3H_17N
IO16_LVDS3H_16PIO17_LVDS3H_16N
IO20_LVDS3H_14PIO21_LVDS3H_14N
IO26_RZQ3H_LVDS3H_11PIO27_LVDS3H_11N
IO30_LVDS3H_9PIO31_LVDS3H_9N
IO32_LVDS3H_8PIO33_LVDS3H_8N
IO34_LVDS3H_7PIO35_LVDS3H_7N
IO36_LVDS3H_6PIO37_LVDS3H_6N
IO38_LVDS3H_5PIO39_LVDS3H_5N
IO40_LVDS3H_4PIO41_LVDS3H_4N
IO42_LVDS3H_3PIO43_LVDS3H_3N
IO44_LVDS3H_2PIO45_LVDS3H_2N
IO46_LVDS3H_1PIO47_LVDS3H_1N
INININININ
BI
INININ
BIBIBIBIBI
ININ
BIOUTOUTOUT
OUT
OUTOUT
GND
BI
BIBI
BI
BIOUT
BIBIBIBI
BIBI
BI
BI
IO BANK 3G10ax115f40
IO1_LVDS3G_24NIO2_LVDS3G_23PIO3_LVDS3G_23N
IO4_LVDS3G_22PIO5_LVDS3G_22N
IO6_LVDS3G_21PIO7_LVDS3G_21N
IO8_LVDS3G_20PIO9_LVDS3G_20N
IO10_LVDS3G_19PIO11_LVDS3G_19N
IO12_LVDS3G_18PIO13_LVDS3G_18N
IO14_LVDS3G_17PIO15_LVDS3G_17N
IO16_LVDS3G_16PIO17_LVDS3G_16N
IO20_LVDS3G_14PIO21_LVDS3G_14N
IO26_RZQ3G_LVDS3G_11PIO27_LVDS3G_11N
IO30_LVDS3G_9PIO31_LVDS3G_9N
IO32_LVDS3G_8PIO33_LVDS3G_8N
IO34_LVDS3G_7PIO35_LVDS3G_7N
IO36_LVDS3G_6PIO37_LVDS3G_6N
IO38_LVDS3G_5PIO39_LVDS3G_5N
IO40_LVDS3G_4PIO41_LVDS3G_4N
IO42_LVDS3G_3PIO43_LVDS3G_3N
IO44_LVDS3G_2PIO45_LVDS3G_2N
IO46_LVDS3G_1PIO47_LVDS3G_1N
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
FAT PIPES REGION : PORTS 4-11EXTENDED OPTION REGION : PORTS 12-15,17-20COMMON OPTION REGION : PORTS 0-3
AMC CONNECTOR
TCLKB,TCLKD : CLOCKS SHOULD OUTPUT THE AMC
PCIE PORT IN OPTION
LVDS<3:2> IN OPTION
MODIFIE: Mon Mar 23 09:50:48 2015
SHEET: 23 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 23 / 27
R202
R201R206
R205R200
R204R199
R203
C1251631621571561511501451441331321271261211201151141091081031029796919065665960505144453536293020211112
139138
136135
7778
7475
160159154153148147142141130129124123118117112111106105100
999493888768696263535447483839323323241415
8081
U1
C112
C113
C114
C115
C116
C117
C118
C119
C120
C97
C98
C99
C100
C101
C102
C103
C104
C105
C126
R7
C110
C111
R5
8 6
84725742
2718
92
4
1701641611581551521491461431401371341311281251221191161131101071041019895928986
8582797673706764615855524946434037343128252219161310
71
U1
R3R2R1
167166
168169
1657156
383
2617
5
41
U1
R6R4
0
RX_LVDS_CN<0>RX_LVDS_CP<2>RX_LVDS_CN<2>RX_LVDS_CP<3>RX_LVDS_CN<3>
RX_GBT_CP<2>RX_GBT_CN<2>RX_GBT_CP<1>RX_GBT_CN<1>
0
100N
100NRX_GBT_N<1>RX_GBT_P<1>RX_GBT_N<2>
0
100N
0
0
0
0
0
RX_GBT_P<0>
RX_LVDS_CP<0>RX_LVDS_CN<1>RX_LVDS_CP<1>
100N
20B8 20A8
21D1 21D1 21D1 20D4 20D4
20D1
19A8
20D1 20D1
21D1
19B8 19B8
19A8 19A8
20B8 20B8
21D1 21D1
24B6 2B8
21D1 21D1 21D1
20D1
21D1
21D1 21D1 21D1 21D1
19B5
19A5
20B4
20A4
20A4
20D1
19A5
19A5
20B4
20B4
20D1
20A4
20B4
20B4
19A5
19A8
24D6
24D6 24D6
2D2 2D2
24D6
2C7 2C7 2C7
2C2 2A3
2A5 2D2
21D1
20D4 20D4
20D4 20A8 20A8
20D4
11C7 11C7
19B5
21D1
20B8
20B8
RX_XAUI_N<0>RX_XAUI_P<0>RX_XAUI_N<1>
RX_XAUI_P<2>
RX_XAUI_P<3>
RX_GBT_CP<0>
AMC_TTC_CLK_CN
RX_XAUI_CP<3>RX_XAUI_CN<3>RX_XAUI_CP<2>RX_XAUI_CN<2>RX_XAUI_CP<1>
RX_XAUI_CP<0>RX_XAUI_CN<0>
RX_GBT_P<2>
RX_GBT_CN<0>
RX_XAUI_N<3>
AMC_TTC_CLK_NAMC_TTC_CLK_P AMC_TTC_CLK_CP
RX_1GBE_CP<0>
RX_XAUI_CN<1>
TX_GBT_N<0>
TX_LVDS_P<0>
TX_LVDS_P<2>
TX_LVDS_N<3>
TX_GBT_P<2>
TX_XAUI_P<1>
RX_1GBE_P<0>
TX_GBT_P<0>
TX_GBT_N<1>TX_XAUI_P<3>TX_XAUI_N<3>TX_XAUI_P<2>
TX_1GBE_N<0>
RX_PCIE_N<1>
TX_LVDS_N<0>
TX_LVDS_N<1>TX_LVDS_P<1>
TX_LVDS_N<2>TX_LVDS_P<3>
TX_PCIE_P<1>
TX_XAUI_P<0>
TX_GBT_P<1>
TX_PCIE_N<0>
TX_XAUI_N<1>
TX_XAUI_N<2>
TX_GBT_N<2>
TX_XAUI_N<0>
TX_PCIE_P<0>
RX_PCIE_P<1>TX_PCIE_N<1>
TX_1GBE_P<0>
AMC_SCL_LAMC_SDA_L
AMC_GA2
AMC_JTAG_TRST_N
AMC_JTAG_TCKAMC_JTAG_TMS
AMC_JTAG_MISOAMC_JTAG_MOSI
AMC_GA0AMC_GA1 AMC_PS1_N
AMC_ENABLE_N
AMC_PS0_N
RX_PCIE_CP<1>RX_PCIE_CN<1>RX_PCIE_CP<0>RX_PCIE_CN<0>
RX_PCIE_P<0>RX_PCIE_N<0>
RX_1GBE_CN<0>RX_1GBE_N<0>
RX_XAUI_P<1>RX_XAUI_N<2>
RX_LVDS_P<3>
RX_LVDS_P<2>
RX_LVDS_P<0>
RX_LVDS_N<2>
RX_LVDS_N<1>
RX_LVDS_N<0>
RX_LVDS_N<3>
RX_GBT_N<0>RX_LVDS_P<1>
100N
100N
100N
100N
10K
10K
10K
33K
10K
33K
10K
100N
100N
100N100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
IN
IN
ININ
ININ
ININ
clocksamc_con
portsamc_con
TCLKC_PTCLKD_NTCLKD_P
TCLKC_N
TCLKB_NTCLKB_P
TCLKA_NTCLKA_P
FCLKA_NFCLKA_P
RX20_N
RX19_N
RX18_N
RX17_N
RX15_N
RX14_N
RX13_N
RX12_N
RX11_N
RX10_N
RX9_N
RX8_N
RX7_N
RX6_N
RX5_N
RX4_N
RX3_N
RX2_N
RX1_N
RX0_N
RX20_P
RX19_P
RX18_P
RX17_P
RX15_P
RX14_P
RX13_P
RX12_P
RX11_P
RX10_P
RX9_P
RX8_P
RX7_P
RX6_P
RX5_P
RX4_P
RX3_P
RX2_P
RX1_P
RX0_P
TX20_N
TX19_N
TX18_N
TX17_N
TX15_N
TX14_N
TX13_N
TX12_N
TX11_N
TX10_N
TX9_N
TX8_N
TX7_N
TX6_N
TX5_N
TX4_N
TX3_N
TX2_N
TX1_N
TX0_N
TX20_P
TX19_P
TX18_P
TX17_P
TX15_P
TX14_P
TX13_P
TX12_P
TX11_P
TX10_P
TX9_P
TX8_P
TX7_P
TX6_P
TX5_P
TX4_P
TX3_P
TX2_P
TX1_P
TX0_P
GND
OUT
OUT
OUT
OUTOUT
BI
OUTOUT
OUTOUTOUTOUTOUTOUTOUTOUT
OUT
OUTOUTOUT
VP12VP12
OUT
p3v3_ipmi
*
IN
OUT
OUT
OUTOUT
OUTOUTOUT
OUTOUT
OUT
OUT
OUT
OUTOUT
OUTOUT
OUT
OUTOUT
p3v3_ipmi
*
OUT
GND
power amc_connector
GND55GND54GND53GND52GND51GND50GND49GND48GND47GND46GND45GND44GND43GND42GND41GND40GND39GND38GND37GND36GND35GND34GND33GND32GND31GND30GND29GND28
GND27GND26GND25GND24GND23GND22GND21GND20GND19GND18GND17GND16GND15GND14GND13GND12GND11GND10GND9GND8GND7GND6GND5GND4GND3GND2GND1GND0
RSRVD8 RSRVD6
MP
PWR7PWR6PWR5PWR4
PWR3PWR2PWR1PWR0
GND
***
managementamc_con
TDITDOTRST_NTMSTCK
PS0_N
SDA_LSCL_L
ENABLE_NGA2GA1GA0
PS1_N
*
*
*
*
*
*
*
*
OUT
ININ
ININININ
ININININ
*
INININ
INININ
IN
IN
ININ
*
p3v3_ipmi
FAT PIPES REGION : PORTS 4-11EXTENDED OPTION REGION : PORTS 12-15,17-20COMMON OPTION REGION : PORTS 0-3
AMC CONNECTOR
TCLKB,TCLKD : CLOCKS SHOULD OUTPUT THE AMC
PCIE PORT IN OPTION
LVDS<3:2> IN OPTION
MODIFIE: Mon Mar 23 09:50:48 2015
SHEET: 23 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 23 / 27
0
0
100N
100N
0
100N
0
0
0
0
0
100N
100N
100N
100N
100N
10K
10K
10K
33K
10K
33K
10K
100N
100N
100N100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
100N
R202
R201R206
R205R200
R204R199
R203
C125
U1
C112
C113
C114
C115
C116
C117
C118
C119
C120
C97
C98
C99
C100
C101
C102
C103
C104
C105
C126
R7
C110
C111
R5
U1
R3R2R1
U1
R6R4
20B8 20A8
21D1 21D1 21D1 20D4 20D4
20D1
19A8
20D1 20D1
21D1
19B8 19B8
19A8 19A8
20B8 20B8
21D1 21D1
24B6 2B8
21D1 21D1 21D1
20D1
21D1
21D1 21D1 21D1 21D1
19B5
19A5
20B4
20A4
20A4
20D1
19A5
19A5
20B4
20B4
20D1
20A4
20B4
20B4
19A5
19A8
24D6
24D6 24D6
2D2 2D2
24D6
2C7 2C7 2C7
2C2 2A3
2A5 2D2
21D1
20D4 20D4
20D4 20A8 20A8
20D4
11C7 11C7
19B5
21D1
20B8
20B8
RX_LVDS_CN<0>RX_LVDS_CP<2>RX_LVDS_CN<2>RX_LVDS_CP<3>RX_LVDS_CN<3>
RX_GBT_CP<2>RX_GBT_CN<2>RX_GBT_CP<1>RX_GBT_CN<1>RX_GBT_N<1>
RX_GBT_P<1>RX_GBT_N<2>
RX_GBT_P<0>
RX_LVDS_CP<0>RX_LVDS_CN<1>RX_LVDS_CP<1>
RX_XAUI_N<0>RX_XAUI_P<0>RX_XAUI_N<1>
RX_XAUI_P<2>
RX_XAUI_P<3>
RX_GBT_CP<0>
AMC_TTC_CLK_CN
RX_XAUI_CP<3>RX_XAUI_CN<3>RX_XAUI_CP<2>RX_XAUI_CN<2>RX_XAUI_CP<1>
RX_XAUI_CP<0>RX_XAUI_CN<0>
RX_GBT_P<2>
RX_GBT_CN<0>
RX_XAUI_N<3>
AMC_TTC_CLK_NAMC_TTC_CLK_P AMC_TTC_CLK_CP
RX_1GBE_CP<0>
RX_XAUI_CN<1>
TX_GBT_N<0>
TX_LVDS_P<0>
TX_LVDS_P<2>
TX_LVDS_N<3>
TX_GBT_P<2>
TX_XAUI_P<1>
RX_1GBE_P<0>
TX_GBT_P<0>
TX_GBT_N<1>TX_XAUI_P<3>TX_XAUI_N<3>TX_XAUI_P<2>
TX_1GBE_N<0>
RX_PCIE_N<1>
TX_LVDS_N<0>
TX_LVDS_N<1>TX_LVDS_P<1>
TX_LVDS_N<2>TX_LVDS_P<3>
TX_PCIE_P<1>
TX_XAUI_P<0>
TX_GBT_P<1>
TX_PCIE_N<0>
TX_XAUI_N<1>
TX_XAUI_N<2>
TX_GBT_N<2>
TX_XAUI_N<0>
TX_PCIE_P<0>
RX_PCIE_P<1>TX_PCIE_N<1>
TX_1GBE_P<0>
AMC_SCL_LAMC_SDA_L
AMC_GA2
AMC_JTAG_TRST_N
AMC_JTAG_TCKAMC_JTAG_TMS
AMC_JTAG_MISOAMC_JTAG_MOSI
AMC_GA0AMC_GA1 AMC_PS1_N
AMC_ENABLE_N
AMC_PS0_N
RX_PCIE_CP<1>RX_PCIE_CN<1>RX_PCIE_CP<0>RX_PCIE_CN<0>
RX_PCIE_P<0>RX_PCIE_N<0>
RX_1GBE_CN<0>RX_1GBE_N<0>
RX_XAUI_P<1>RX_XAUI_N<2>
RX_LVDS_P<3>
RX_LVDS_P<2>
RX_LVDS_P<0>
RX_LVDS_N<2>
RX_LVDS_N<1>
RX_LVDS_N<0>
RX_LVDS_N<3>
RX_GBT_N<0>RX_LVDS_P<1>
1631621571561511501451441331321271261211201151141091081031029796919065665960505144453536293020211112
139138
136135
7778
7475
160159154153148147142141130129124123118117112111106105100
999493888768696263535447483839323323241415
8081
8 6
84725742
2718
92
4
1701641611581551521491461431401371341311281251221191161131101071041019895928986
8582797673706764615855524946434037343128252219161310
71
167166
168169
1657156
383
2617
5
41
IN
IN
ININ
ININ
ININ
clocksamc_con
portsamc_con
TCLKC_PTCLKD_NTCLKD_P
TCLKC_N
TCLKB_NTCLKB_P
TCLKA_NTCLKA_P
FCLKA_NFCLKA_P
RX20_N
RX19_N
RX18_N
RX17_N
RX15_N
RX14_N
RX13_N
RX12_N
RX11_N
RX10_N
RX9_N
RX8_N
RX7_N
RX6_N
RX5_N
RX4_N
RX3_N
RX2_N
RX1_N
RX0_N
RX20_P
RX19_P
RX18_P
RX17_P
RX15_P
RX14_P
RX13_P
RX12_P
RX11_P
RX10_P
RX9_P
RX8_P
RX7_P
RX6_P
RX5_P
RX4_P
RX3_P
RX2_P
RX1_P
RX0_P
TX20_N
TX19_N
TX18_N
TX17_N
TX15_N
TX14_N
TX13_N
TX12_N
TX11_N
TX10_N
TX9_N
TX8_N
TX7_N
TX6_N
TX5_N
TX4_N
TX3_N
TX2_N
TX1_N
TX0_N
TX20_P
TX19_P
TX18_P
TX17_P
TX15_P
TX14_P
TX13_P
TX12_P
TX11_P
TX10_P
TX9_P
TX8_P
TX7_P
TX6_P
TX5_P
TX4_P
TX3_P
TX2_P
TX1_P
TX0_P
GND
OUT
OUT
OUT
OUTOUT
BI
OUTOUT
OUTOUTOUTOUTOUTOUTOUTOUT
OUT
OUTOUTOUT
VP12VP12
OUT
p3v3_ipmi
*
IN
OUT
OUT
OUTOUT
OUTOUTOUT
OUTOUT
OUT
OUT
OUT
OUTOUT
OUTOUT
OUT
OUTOUT
p3v3_ipmi
*
OUT
GND
power amc_connector
GND55GND54GND53GND52GND51GND50GND49GND48GND47GND46GND45GND44GND43GND42GND41GND40GND39GND38GND37GND36GND35GND34GND33GND32GND31GND30GND29GND28
GND27GND26GND25GND24GND23GND22GND21GND20GND19GND18GND17GND16GND15GND14GND13GND12GND11GND10GND9GND8GND7GND6GND5GND4GND3GND2GND1GND0
RSRVD8 RSRVD6
MP
PWR7PWR6PWR5PWR4
PWR3PWR2PWR1PWR0
GND
***
managementamc_con
TDITDOTRST_NTMSTCK
PS0_N
SDA_LSCL_L
ENABLE_NGA2GA1GA0
PS1_N
*
*
*
*
*
*
*
*
OUT
ININ
ININININ
ININININ
*
INININ
INININ
IN
IN
ININ
*
p3v3_ipmi
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
'0' = EXTERNAL CONNECTOR'1' = AMC EDGE CONNECTOR
MAPPING INSIDE USB BLASTER CABLE :NC PIN 8 CONNECTED TO GND
ARRIA10
3.3V<->1.8V TRANSLATION FOR ARRIA10 JTAG
DEFAULT CONFIG : ATMEGA128 DISCONNECTED AND SHORTENED FROM MAIN JTAG CHAIN
ATMEGA128MAIN JTAG
SEE IF DETECT COULD NOT BE DONE ON 2ND GND
CONNECTION TO BE CLARIFIED AND VERIFIED
REPLACE X RESISTANCE BY 0 AND 0 BY X TO PUT ATMEGA128 IN MAIN JTAG CHAIN
JTAG CHAINS
MODIFIE: Mon Mar 23 09:50:42 2015
SHEET: 24 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 24 / 27
10987654321
J3
C350 C351
14 18
7
10
11
12
13
5
4
3
2
U20
C349
R73
R72
R69
R70
R71
12 8M1
1
M1
182M1
146M1
164M1
R68
C348
R63R58 R60
19
M1
16
1
15
8
1314
12
1011
9
65
7
32
4
U19
R66
R65
R67
R62
R64R61R59
10987654321
J4
R57
P1V8
P1V8
33K
33K
10K
10K
10K
DNC
DNC
DNC
DNC
33
33
100N
100N 100N
33
33
100N
0
1K 33K
1K
FPGA_JTAG_TMS
FPGA_JTAG_MOSI
MAIN_JTAG_TMS
FPGA_JTAG_MOSI_3.3V
MAIN_JTAG_MISO
MAIN_JTAG_TCK FPGA_JTAG_TCK
FPGA_JTAG_MISO
CON_JTAG_MISO
CON_JTAG_TCK
CON_JTAG_TMS
CON_JTAG_TMSAMC_JTAG_TMS
AMC_JTAG_TCK
AMC_JTAG_MOSI
CON_JTAG_MISOAMC_JTAG_MISO
MAIN_JTAG_TMS
MAIN_JTAG_MOSI
MAIN_JTAG_TCK
CON_ATMEGA_JTAG_TMS
CON_ATMEGA_JTAG_TCK
CON_ATMEGA_JTAG_MOSI
CON_ATMEGA_JTAG_MISO FPGA_JTAG_MOSI_3.3V
CON_JTAG_DETECT
CON_JTAG_MOSI
CON_JTAG_TCK
MAIN_JTAG_TMS
MAIN_JTAG_MISO
MAIN_JTAG_MOSI
MAIN_JTAG_TCK
MAIN_JTAG_MOSI FPGA_JTAG_MOSI_3.3V
CON_JTAG_DETECTCON_JTAG_MOSI
CON_ATMEGA_JTAG_TCK
CON_ATMEGA_JTAG_MISO
CON_ATMEGA_JTAG_TMS
AMC_ENABLE_NCON_ATMEGA_JTAG_MOSI
18D1
18D5
THERMAL_PAD=GND
RGYR
23B4 2C3
2B8
2C3
2C3
2C3 24B4
24B4
24A3
23A7
23A7
23A7
23A7
18D1
18D5
GND=GNDGND=GND
VCC=P3V3VCC=P3V3VCC=P3V3GND=GND
GND=GND
VCC=P3V3
GND=GNDVCC=P3V3
VCC=P3V3GND=GND
24A4
24D6 24C4
24C3 24A1
24D3 24A6
24B6 24C3
24A6
24C3
24B6 24C3
24D7
24D7
24D7
24A1 24C3 2C3 24B6
24B6 2C3
2C3 24C6
2C3 24B6
24D3 24C3
24D3 24A6
24D3 24C3
24D7
24D7
24D6
24D6
24D6
24D3
24D3 24B6
24B6 24D3
24A1
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
*
p3v3_ipmi
*
con_sh_10p_coude
10987654321
P3V3
GND
*
IN
OUT
OUT
OUT
P3V3
txb0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
*
P3V3
GND
GND
GND
*
*
*
GND
*
*
GND
1Y4 1A4
sn74lvc244argyr1OE
1Y11A1GND
1Y31A3
1Y21A2
*
P3V3
INcon_sh_10p_coude
10987654321
IN
IN
OUT
P3V3
** *
sn74lvc244argyr2OE
GND
sn74cbtlv3257pw
1A
OE_N
2B2
3B1
2A
3A
4A4B24B1
3B2
2B1
1B21B1
S
VCC
GND
*
GND
*
*
*
OUT
OUT
IN
OUTOUT
GND
'0' = EXTERNAL CONNECTOR'1' = AMC EDGE CONNECTOR
MAPPING INSIDE USB BLASTER CABLE :NC PIN 8 CONNECTED TO GND
ARRIA10
3.3V<->1.8V TRANSLATION FOR ARRIA10 JTAG
DEFAULT CONFIG : ATMEGA128 DISCONNECTED AND SHORTENED FROM MAIN JTAG CHAIN
ATMEGA128MAIN JTAG
SEE IF DETECT COULD NOT BE DONE ON 2ND GND
CONNECTION TO BE CLARIFIED AND VERIFIED
REPLACE X RESISTANCE BY 0 AND 0 BY X TO PUT ATMEGA128 IN MAIN JTAG CHAIN
JTAG CHAINS
MODIFIE: Mon Mar 23 09:50:42 2015
SHEET: 24 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 24 / 27
P1V8
P1V8
33K
33K
10K
10K
10K
DNC
DNC
DNC
DNC
33
33
100N
100N 100N
33
33
100N
0
1K 33K
1K
THERMAL_PAD=GND
RGYRGND=GNDGND=GND
VCC=P3V3VCC=P3V3VCC=P3V3GND=GND
GND=GND
VCC=P3V3
GND=GNDVCC=P3V3
VCC=P3V3GND=GND
J3
C350 C351
U20
C349
R73
R72
R69
R70
R71
M1
M1
M1
M1
M1
R68
C348
R63R58 R60
M1
U19
R66
R65
R67
R62
R64R61R59
J4
R57
18D1
18D5
23B4 2C3
2B8
2C3
2C3
2C3 24B4
24B4
24A3
23A7
23A7
23A7
23A7
18D1
18D5
24A4
24D6 24C4
24C3 24A1
24D3 24A6
24B6 24C3
24A6
24C3
24B6 24C3
24D7
24D7
24D7
24A1 24C3 2C3 24B6
24B6 2C3
2C3 24C6
2C3 24B6
24D3 24C3
24D3 24A6
24D3 24C3
24D7
24D7
24D6
24D6
24D6
24D3
24D3 24B6
24B6 24D3
24A1 FPGA_JTAG_TMS
FPGA_JTAG_MOSI
MAIN_JTAG_TMS
FPGA_JTAG_MOSI_3.3V
MAIN_JTAG_MISO
MAIN_JTAG_TCK FPGA_JTAG_TCK
FPGA_JTAG_MISO
CON_JTAG_MISO
CON_JTAG_TCK
CON_JTAG_TMS
CON_JTAG_TMSAMC_JTAG_TMS
AMC_JTAG_TCK
AMC_JTAG_MOSI
CON_JTAG_MISOAMC_JTAG_MISO
MAIN_JTAG_TMS
MAIN_JTAG_MOSI
MAIN_JTAG_TCK
CON_ATMEGA_JTAG_TMS
CON_ATMEGA_JTAG_TCK
CON_ATMEGA_JTAG_MOSI
CON_ATMEGA_JTAG_MISO FPGA_JTAG_MOSI_3.3V
CON_JTAG_DETECT
CON_JTAG_MOSI
CON_JTAG_TCK
MAIN_JTAG_TMS
MAIN_JTAG_MISO
MAIN_JTAG_MOSI
MAIN_JTAG_TCK
MAIN_JTAG_MOSI FPGA_JTAG_MOSI_3.3V
CON_JTAG_DETECTCON_JTAG_MOSI
CON_ATMEGA_JTAG_TCK
CON_ATMEGA_JTAG_MISO
CON_ATMEGA_JTAG_TMS
AMC_ENABLE_NCON_ATMEGA_JTAG_MOSI
10987654321
14 18
7
10
11
12
13
5
4
3
2
12 8
1
182
146
164
19
16
1
15
8
1314
12
1011
9
65
7
32
4
10987654321
*
p3v3_ipmi
*
con_sh_10p_coude
10987654321
P3V3
GND
*
IN
OUT
OUT
OUT
P3V3
txb0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
*
P3V3
GND
GND
GND
*
*
*
GND
*
*
GND
1Y4 1A4
sn74lvc244argyr1OE
1Y11A1GND
1Y31A3
1Y21A2
*
P3V3
INcon_sh_10p_coude
10987654321
IN
IN
OUT
P3V3
** *
sn74lvc244argyr2OE
GND
sn74cbtlv3257pw
1A
OE_N
2B2
3B1
2A
3A
4A4B24B1
3B2
2B1
1B21B1
S
VCC
GND
*
GND
*
*
*
OUT
OUT
IN
OUTOUT
GND
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
LEVEL TRANSLATION
I2C LEVEL SHIFTER BETWEEN FPGA AND UPOD
REGROUP RES 'DNC' UPOD RESET AND RES 'DNC' TTC_CLK_SEL
TXS0104 FOR OPEN DRAIN
MODIFIE: Mon Mar 23 09:50:42 2015
SHEET: 25 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 25 / 27
R89
C364
C365
14 18
7
10
11
12
13
5
4
3
2
U25
C360
14 18
7
10
11
12
13
5
4
3
2
U26
C361
C363
14 18
7
10
11
12
13
5
4
3
2
U27
C362
C356
14 18
7
10
11
12
13
5
4
3
2
U21
C352
R75
R74
R76
C359
R88R85
R83
R81
C358
R87R86
R82
R84
C357
14 18
710
11
12
13
5
4
3
2
U22
C353
C355
R79
81
6372
4 5
U23
R78R77
C354
R80
81
6372
4 5
U24
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
100N
DNC
0
4.7K
0
DNC
100N
100N
100N
100N
100N4.7K
100N100N
100N
4.7K
100N
DNC
DNC
100N
100N
100N
4.7K
4.7K
0
10K
4.7K
100N
010K
MMC_FPGA_USER_IO0 MMC_FPGA_USER_IO0_1.8V
MMC_FPGA_USER_IO1_1.8V
TX_UPOD_SCLTX_UPOD_SDA
FPGA_NCONFIG
FPGA_INIT_DONE
RX_UPOD_R0_INTN_1.8V
RX_UPOD_R1_INTN_1.8V
RX_UPOD_L0_INTN_1.8V
RX_UPOD_L1_INTN_1.8V
MMC_FPGA_USER_IO1
MMC_FPGA_INIT_DONE
RX_UPOD_L1_INTN
RX_UPOD_L0_INTN
RX_UPOD_R1_INTN
RX_UPOD_R0_INTN
MMC_FPGA_RELOADN
TX_UPOD_R0_INTN_1.8V
TX_UPOD_R1_INTN_1.8V
TX_UPOD_L0_INTN_1.8V
TX_UPOD_L1_INTN_1.8VTX_UPOD_L1_INTN
TX_UPOD_L0_INTN
TX_UPOD_R1_INTN
TX_UPOD_R0_INTN
RX_UPOD_SCLRX_UPOD_SDA
TTC_CLK_SEL_1.8V
AMC_TTC_CLK_LOS_1.8V
LOCAL_TTC_CLK_LOS_1.8V
RX_UPOD_RESETN_1.8V
TX_UPOD_RESETN_1.8V
MMC_FPGA_RESETN_1.8V
FPGA_TEST_LED_N_1.8V
TX_UPOD_RESETN
MMC_FPGA_RESETN
FPGA_TEST_LED_N
LOCAL_TTC_CLK_LOS
AMC_TTC_CLK_LOS
RX_UPOD_RESETN
TTC_CLK_SEL
UPOD_SDA_1.8V
UPOD_SCL_1.8VUPOD_SDA_1.8V
UPOD_SCL_1.8V
2C3
THERMAL_PAD=GND
26D4
THERMAL_PAD=GND
13C3
13B5
13E5
12B7 12B7
21D4
21D4
18D5
21C7
21D4
21D4
21D4
21D4
RGYR
THERMAL_PAD=GND
RGYR
21C4
21D7
21D7
21D7
2C3
2C6 2A8
13E1
13B1
12B1
12E1
2C6
21D7
21D7
21D7
21D4
21C4
21D4
21C4
THERMAL_PAD=GND
RGYR13E7 13E7
13E3 13B3
13B7 13B7 12E7
12E7
12E5
12B5
12E3 12C3 12B3 13C3 12E3 12C3 13E3
THERMAL_PAD=GND
RGYR
RGYR
12C3 13E3
12C7 13E7
2C6
12E3
12E7
13C3
13C7
11C7
11C7
11C7
21D4 21D4 21D4 21D4
25A7 25A7 25A7 25A7
21D4 25B7 21D4 25B7 21D4 25B7 21D4 25B7
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
P3V3
GND
P3V3
GND
GND
txs0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
GND
P3V3
P3V3
BI
IN
BI
IN
IN
OUT
IN
GND
P3V3
txb0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
GND
GND
P2V5
GND
P3V3
*
*
OUT
OUT
*
IN
OUT
IN
IN
*
OUT
IN
IN
BIBI
IN
OUT
OUT
GND
GND
tca9509
SDABSCLBVCCBVCCA
SDAASCLA
GND EN
**
*
*
IN
IN
IN
IN
BIBI
GND
**
*
*
GND
txb0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
GND
GND
P3V3
GND
*
tca9509
SDABSCLBVCCBVCCA
SDAASCLA
GND EN
BI
GND
**
P2V5
OUTOUT
IN
BI
BI
*
P3V3
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
GND
GND
BI
GND
GND
txs0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
GND
P3V3
P3V3
txs0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
BI
BI
LEVEL TRANSLATION
I2C LEVEL SHIFTER BETWEEN FPGA AND UPOD
REGROUP RES 'DNC' UPOD RESET AND RES 'DNC' TTC_CLK_SEL
TXS0104 FOR OPEN DRAIN
MODIFIE: Mon Mar 23 09:50:42 2015
SHEET: 25 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 25 / 27
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
P1V8
100N
DNC
0
4.7K
0
DNC
100N
100N
100N
100N
100N4.7K
100N100N
100N
4.7K
100N
DNC
DNC
100N
100N
100N
4.7K
4.7K
0
10K
4.7K
100N
010K
THERMAL_PAD=GND
THERMAL_PAD=GND
RGYR
THERMAL_PAD=GND
RGYR
THERMAL_PAD=GND
RGYR
THERMAL_PAD=GND
RGYR
RGYR
R89
C364
C365
U25
C360
U26
C361
C363
U27
C362
C356
U21
C352
R75
R74
R76
C359
R88R85
R83
R81
C358
R87R86
R82
R84
C357
U22
C353
C355
R79
U23
R78R77
C354
R80
U24
2C3
26D4
13C3
13B5
13E5
12B7 12B7
21D4
21D4
18D5
21C7
21D4
21D4
21D4
21D4
21C4
21D7
21D7
21D7
2C3
2C6 2A8
13E1
13B1
12B1
12E1
2C6
21D7
21D7
21D7
21D4
21C4
21D4
21C4
13E7 13E7
13E3 13B3
13B7 13B7 12E7
12E7
12E5
12B5
12E3 12C3 12B3 13C3 12E3 12C3 13E3
12C3 13E3
12C7 13E7
2C6
12E3
12E7
13C3
13C7
11C7
11C7
11C7
21D4 21D4 21D4 21D4
25A7 25A7 25A7 25A7
21D4 25B7 21D4 25B7 21D4 25B7 21D4 25B7
MMC_FPGA_USER_IO0 MMC_FPGA_USER_IO0_1.8V
MMC_FPGA_USER_IO1_1.8V
TX_UPOD_SCLTX_UPOD_SDA
FPGA_NCONFIG
FPGA_INIT_DONE
RX_UPOD_R0_INTN_1.8V
RX_UPOD_R1_INTN_1.8V
RX_UPOD_L0_INTN_1.8V
RX_UPOD_L1_INTN_1.8V
MMC_FPGA_USER_IO1
MMC_FPGA_INIT_DONE
RX_UPOD_L1_INTN
RX_UPOD_L0_INTN
RX_UPOD_R1_INTN
RX_UPOD_R0_INTN
MMC_FPGA_RELOADN
TX_UPOD_R0_INTN_1.8V
TX_UPOD_R1_INTN_1.8V
TX_UPOD_L0_INTN_1.8V
TX_UPOD_L1_INTN_1.8VTX_UPOD_L1_INTN
TX_UPOD_L0_INTN
TX_UPOD_R1_INTN
TX_UPOD_R0_INTN
RX_UPOD_SCLRX_UPOD_SDA
TTC_CLK_SEL_1.8V
AMC_TTC_CLK_LOS_1.8V
LOCAL_TTC_CLK_LOS_1.8V
RX_UPOD_RESETN_1.8V
TX_UPOD_RESETN_1.8V
MMC_FPGA_RESETN_1.8V
FPGA_TEST_LED_N_1.8V
TX_UPOD_RESETN
MMC_FPGA_RESETN
FPGA_TEST_LED_N
LOCAL_TTC_CLK_LOS
AMC_TTC_CLK_LOS
RX_UPOD_RESETN
TTC_CLK_SEL
UPOD_SDA_1.8V
UPOD_SCL_1.8VUPOD_SDA_1.8V
UPOD_SCL_1.8V
14 18
7
10
11
12
13
5
4
3
2
14 18
7
10
11
12
13
5
4
3
2
14 18
7
10
11
12
13
5
4
3
2
14 18
7
10
11
12
13
5
4
3
2
14 18
710
11
12
13
5
4
3
2
81
6372
4 5
81
6372
4 5
P3V3
GND
P3V3
GND
GND
txs0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
GND
P3V3
P3V3
BI
IN
BI
IN
IN
OUT
IN
GND
P3V3
txb0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
GND
GND
P2V5
GND
P3V3
*
*
OUT
OUT
*
IN
OUT
IN
IN
*
OUT
IN
IN
BIBI
IN
OUT
OUT
GND
GND
tca9509
SDABSCLBVCCBVCCA
SDAASCLA
GND EN
**
*
*
IN
IN
IN
IN
BIBI
GND
**
*
*
GND
txb0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
GND
GND
P3V3
GND
*
tca9509
SDABSCLBVCCBVCCA
SDAASCLA
GND EN
BI
GND
**
P2V5
OUTOUT
IN
BI
BI
*
P3V3
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
GND
GND
BI
GND
GND
txs0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
GND
P3V3
P3V3
txs0104
OE
GND
B4
B3
B2
B1
A4
A3
A2
A1
VCCB VCCA
BI
BI
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
A10 TRANSMITTER/RECEIVER GXB CURRENT MONITORING
SEE IF POSSIBLE TO PUT ON FRONT PANELTEST PADS FROM FPGA
AMC IDENTIFIER
SEE IF POSSIBLE TO PUT ON FRONT PANEL
FPGA CONNECTIONS
FPGA HARD RESET
A10 VCC CURRENT MONITORING
GREEN
TEST LED FROM FPGA
SEE IF POSSIBLE TO PUT ON FRONT PANEL
MODIFIE: Mon Mar 23 09:50:43 2015
SHEET: 26 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 26 / 27
12
X1
R196
2 1
D7
12
X10
12
X9
12
X8
12
X7
12
X6
12
X5
12
X4
12
X3
10987654321
J2
12
X2
R50
2 1
S1
316
54 2
U8
C133
316
54 2
U9
C134
P1V8
240
100N
100N
10K
FPGA_TEST_LED_N
AMC_
ID<5
>
AMC_
ID<7
>
AMC_
ID<6
>
AMC_
ID<4
>
AMC_
ID<3
>
AMC_
ID<2
>
AMC_
ID<1
>
AMC_
ID<0
>
AMC_
ID<8
>
AMC_
ID<9
>
A10_VCCT_VCCR_GXB_CURRENT
A10_TEST_IO<1>A10_TEST_IO<2>A10_TEST_IO<3>A10_TEST_IO<4>A10_TEST_IO<5>A10_TEST_IO<6>A10_TEST_IO<7>A10_TEST_IO<8>A10_TEST_IO<9>
A10_VCCT_VCCR_GXBA10_VCCT_VCCR_GXB_M
A10_VCC_CURRENTA10_VCCA10_VCC_M
HARD_FPGA_RESET_N
A10_TEST_IO<0>
25D8
22D5
22D5
22D2 22D2
22D5
22D5
22D5
22D5
21D4
15B6
22D2
22D2
15B6
3D5 6B2
3D5 5C2 3D5
3D5
22D2 22D8 22D8 22D8 22D8 22D8
22D5
22D5
22D5
22D5
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
GND
P3V3
board_id
GND
ID
P3V3
P3V3
*
BIBIBIBIBIBIBI
IN
BIBIBI
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
IN
OU
T
OU
T
OU
T
board_id
GND
IDboard_id
GND
IDboard_id
GND
IDboard_id
GND
IDboard_id
GND
IDboard_id
GND
IDboard_id
GND
ID
P3V3
board_id
GND
ID
GND
con_sh_10p_coude
10987654321
board_id
GND
ID
INOUT
*
IN
GND
OUT
OUT
GND
ina213_dck
GND
OUT
IN+IN- REFV+
GND
P3V3
ina213_dck
GND
OUT
IN+IN- REFV+
GND
IN
A10 TRANSMITTER/RECEIVER GXB CURRENT MONITORING
SEE IF POSSIBLE TO PUT ON FRONT PANELTEST PADS FROM FPGA
AMC IDENTIFIER
SEE IF POSSIBLE TO PUT ON FRONT PANEL
FPGA CONNECTIONS
FPGA HARD RESET
A10 VCC CURRENT MONITORING
GREEN
TEST LED FROM FPGA
SEE IF POSSIBLE TO PUT ON FRONT PANEL
MODIFIE: Mon Mar 23 09:50:43 2015
SHEET: 26 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 26 / 27
P1V8
240
100N
100N
10K
X1
R196D7
X10X9X8X7X6X5X4X3
J2
X2
R50
S1
U8
C133
U9
C134
25D8
22D5
22D5
22D2 22D2
22D5
22D5
22D5
22D5
21D4
15B6
22D2
22D2
15B6
3D5 6B2
3D5 5C2 3D5
3D5
22D2 22D8 22D8 22D8 22D8 22D8
22D5
22D5
22D5
22D5
FPGA_TEST_LED_N
AMC_
ID<5
>
AMC_
ID<7
>
AMC_
ID<6
>
AMC_
ID<4
>
AMC_
ID<3
>
AMC_
ID<2
>
AMC_
ID<1
>
AMC_
ID<0
>
AMC_
ID<8
>
AMC_
ID<9
>
A10_VCCT_VCCR_GXB_CURRENT
A10_TEST_IO<1>A10_TEST_IO<2>A10_TEST_IO<3>A10_TEST_IO<4>A10_TEST_IO<5>A10_TEST_IO<6>A10_TEST_IO<7>A10_TEST_IO<8>A10_TEST_IO<9>
A10_VCCT_VCCR_GXBA10_VCCT_VCCR_GXB_M
A10_VCC_CURRENTA10_VCCA10_VCC_M
HARD_FPGA_RESET_N
A10_TEST_IO<0>
12
2 1
12
12
12
12
12
12
12
12
10987654321
12
2 1
316
54 2
316
54 2
GND
P3V3
board_id
GND
ID
P3V3
P3V3
*
BIBIBIBIBIBIBI
IN
BIBIBI
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
IN
OU
T
OU
T
OU
T
board_id
GND
IDboard_id
GND
IDboard_id
GND
IDboard_id
GND
IDboard_id
GND
IDboard_id
GND
IDboard_id
GND
ID
P3V3
board_id
GND
ID
GND
con_sh_10p_coude
10987654321
board_id
GND
ID
INOUT
*
IN
GND
OUT
OUT
GND
ina213_dck
GND
OUT
IN+IN- REFV+
GND
P3V3
ina213_dck
GND
OUT
IN+IN- REFV+
GND
IN
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
GND LOOPS
OTHERS
HEATSINK UPOD
SHELF GND = CONNECTED TO FRONT PLATE
MODIFIE: Mon Mar 23 09:50:43 2015
SHEET: 27 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 27 / 27
1P2
1P1
1P31P41P51P6
10987654321
M3
10987654321
M2
R197
R1983
2
1
X11
10M
10M
SHELF_GND
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN:
GND
heatsink made by SBU for 4 x upod
GND_10GND_9GND_8GND_7GND_6GND_5GND_4GND_3GND_2GND_1
GND
heatsink made by SBU for 4 x upod
GND_10GND_9GND_8GND_7GND_6GND_5GND_4GND_3GND_2GND_1
GND
*
*
GND
amc_esd_strip
ESD_3
ESD_2
ESD_1
GND LOOPS
OTHERS
HEATSINK UPOD
SHELF GND = CONNECTED TO FRONT PLATE
MODIFIE: Mon Mar 23 09:50:43 2015
SHEET: 27 / 27N.Dumont Dayotymca_card_v0N.Dumont Dayot PAGE: 27 / 27
10M
10M
P2P1
P3P4P5P6
M3M2
R197
R198
X11
SHELF_GND
11
1111
10987654321
10987654321
3
2
1
GND
heatsink made by SBU for 4 x upod
GND_10GND_9GND_8GND_7GND_6GND_5GND_4GND_3GND_2GND_1
GND
heatsink made by SBU for 4 x upod
GND_10GND_9GND_8GND_7GND_6GND_5GND_4GND_3GND_2GND_1
GND
*
*
GND
amc_esd_strip
ESD_3
ESD_2
ESD_1
2
5
13
E E
A A
B
C C
D
234
5
6
7
78
8
D
1
B
6 4
ETUDE:
DESSIN: