pattern sensitive placement for manufacturability
DESCRIPTION
Pattern Sensitive Placement For Manufacturability. Shiyan Hu, Jiang Hu Department of Electrical and Computer Engineering Texas A&M University College Station, TX, 77843. Outline. Lithography system Motivation Problem formulation Algorithms Experimental results Conclusion. - PowerPoint PPT PresentationTRANSCRIPT
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Pattern Sensitive Placement For Manufacturability
Pattern Sensitive Placement For Manufacturability
Shiyan Hu, Jiang HuShiyan Hu, Jiang Hu
Department of Electrical and Computer EngineeringDepartment of Electrical and Computer Engineering
Texas A&M UniversityTexas A&M University
College Station, TX, 77843College Station, TX, 77843
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OutlineOutline
Lithography systemLithography system MotivationMotivation Problem formulationProblem formulation AlgorithmsAlgorithms Experimental resultsExperimental results ConclusionConclusion
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Lithography ProcessLithography Process
oxidation
opticalmask
processstep
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single photolithographic cycle (from [Fullman]).
Part of layout
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Lithography SystemLithography System
Illumination
Source
Mask
Objective Lens
Wafer
193nm wavelength
45nm features
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MotivationMotivation
Printability problemPrintability problem– Lithography technology: 193nm wavelength Lithography technology: 193nm wavelength – VLSI technology: 45nm featuresVLSI technology: 45nm features– Lithography induced variationsLithography induced variations
Impact on timing and powerImpact on timing and power– Even for 180nm technology, variations up to 20x Even for 180nm technology, variations up to 20x
in leakage power and 30% in frequency were in leakage power and 30% in frequency were reported.reported.
Technology nodeTechnology node 130nm130nm 90nm90nm 65nm65nm 45n45nmm
Gate length (nm)Gate length (nm)Tolerable variation Tolerable variation
(nm)(nm)
90905.35.3
53533.753.75
35352.5
28282
Wavelength (nm)Wavelength (nm) 248248 193193 193193 193193
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Lithography Tech. v.s. VLSI Tech.Lithography Tech. v.s. VLSI Tech.
193nm
28nm, tolerable distortion: 2nm
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Improve Printability by RETImprove Printability by RET
Resolution Enhancement Technique (RET)Resolution Enhancement Technique (RET)–Post Physical Layout DesignPost Physical Layout Design–Weakness:Weakness:
Limited capacity and increasingly Limited capacity and increasingly difficultdifficultExpensive mask costExpensive mask cost
OPC
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Design For Manufacturability (DFM)Design For Manufacturability (DFM)
Efforts are needed in all design and Efforts are needed in all design and process stages.process stages.
Physical design considering Physical design considering printability: Design For printability: Design For Manufacturability (DFM). Manufacturability (DFM). – To make RET easier and cheaper To make RET easier and cheaper
to applyto apply
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Previous Works on DFMPrevious Works on DFM
Regular fabric: Regular fabric: – Introduce regular geometry, similar to FPGAIntroduce regular geometry, similar to FPGA– Compromised performanceCompromised performance
Restricted design rules:Restricted design rules:– Not able to accurately capture lithography effectsNot able to accurately capture lithography effects– Rule explosion: 2000 pages in 22nm technologyRule explosion: 2000 pages in 22nm technology
(From DAC’05)
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Previous Works on DFMPrevious Works on DFM
Regular fabric: Regular fabric: – Introduce regular geometry, similar to FPGAIntroduce regular geometry, similar to FPGA– Compromised performanceCompromised performance
Restricted design rules:Restricted design rules:– Not able to accurately capture lithography effectsNot able to accurately capture lithography effects– Rule explosion: 2000 pages in 22nm technologyRule explosion: 2000 pages in 22nm technology
RET-friendly detailed placement (ASPDAC’05):RET-friendly detailed placement (ASPDAC’05):– Small spacing perturbationSmall spacing perturbation– No cell flipping, no cell relocationNo cell flipping, no cell relocation
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Our ProblemOur Problem
Physical layout design considering Physical layout design considering manufacturabilitymanufacturability
Cell PlacementCell Placement– Given a circuit, decide the physical location of each Given a circuit, decide the physical location of each
gategate– A major step in the physical layout design flowA major step in the physical layout design flow– Objectives: small wirelength, small area, good Objectives: small wirelength, small area, good
timing, etc.timing, etc. Placement
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This WorkThis Work
Post-placement optimization for Post-placement optimization for printabilityprintability– Post-placement optimizationPost-placement optimization
Applicable to any existing placement to Applicable to any existing placement to make it easier to printmake it easier to print
Limit modification to retain benefitsLimit modification to retain benefits– Improve printabilityImprove printability
Measurement of printabilityMeasurement of printability How? How?
– Relocation and FlippingRelocation and Flipping
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Measurement of PrintabilityMeasurement of Printability
Manufacturability costManufacturability cost– Edge Placement Error (EPE), Image Log Edge Placement Error (EPE), Image Log
Slope (ILS), process window,…Slope (ILS), process window,…: EPE: EPE
From http://www.vlsitechnology.org/
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Our Optimization
Existing Placer
Relocation and FlippingRelocation and Flipping
Hard to print by
simulation
Easy to print by
simulation
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Cell Flipping to Improve PrintabilityCell Flipping to Improve Printability
50% reduction in gate length deviation
From http://www.vlsitechnology.org/
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Our ApproachOur Approach
Offline:Offline:– For each possible For each possible
pattern formed by pattern formed by two cells, assign a two cells, assign a manufacturability manufacturability costcost Accurate Accurate
lithography lithography simulationssimulations
Results saved Results saved in a lookup in a lookup tabletable
Online:Online:– Prefer easy-to-Prefer easy-to-
print patterns in print patterns in designdesign
Pattern: part between horizontally adjacent cell horizontally adjacent cell pairpair
From http://www.vlsitechnology.org/
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Problem FormulationProblem Formulation
Given a cell placementGiven a cell placement Perform post-processing optimizations, Perform post-processing optimizations,
which can be cell flipping and which can be cell flipping and relocationrelocation
Total manufacturability cost (sum of Total manufacturability cost (sum of manufacturability cost over all manufacturability cost over all patterns) is reduced subject to the patterns) is reduced subject to the modification (wire length) constraint.modification (wire length) constraint.
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Optimization Considering Cell FlippingOptimization Considering Cell Flipping
The algorithm is for row-based layout.The algorithm is for row-based layout. Perform optimization row by row.Perform optimization row by row. For each row of cells, perform the dynamic For each row of cells, perform the dynamic
programming style optimization.programming style optimization.
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Optimizing A Row by Cell FlippingOptimizing A Row by Cell Flipping
1
2
After processing the After processing the last cell, pick the last cell, pick the solution with best solution with best
manufacturability cost manufacturability cost while satisfying while satisfying
wirelength constraintwirelength constraint
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Solution Characterization and UpdateSolution Characterization and Update
Each candidate solution is associated withEach candidate solution is associated with– c: a cellc: a cell– CE: cumulative manufacturability costCE: cumulative manufacturability cost– CW: cumulative wire lengthCW: cumulative wire length
c is being processed, c is being processed, – CE CE CE + manufacturability cost of new CE + manufacturability cost of new
patternpattern– CW CW HPWL on all nets not spanning on any HPWL on all nets not spanning on any
unprocessed cell.unprocessed cell.c
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Solution PruningSolution Pruning
Two candidate solutionsTwo candidate solutions– Solution 1: (c, CE1, CW1)Solution 1: (c, CE1, CW1)– Solution 2: (c, CE2, CW2)Solution 2: (c, CE2, CW2)
Solution 1 is Solution 1 is inferiorinferior if if – CE1 > CE2 : larger cumulative CE1 > CE2 : larger cumulative
manufacturability costmanufacturability cost– and CW1 > CW2 : larger cumulative and CW1 > CW2 : larger cumulative
wirelengthwirelength Whenever a solution becomes inferior, it is Whenever a solution becomes inferior, it is
pruned.pruned.
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Single Row OptimizationSingle Row Optimization
Allow both cell flipping and cell relocation.Allow both cell flipping and cell relocation. Partition a row of cells into groups.Partition a row of cells into groups. Small modification Small modification a cell movable only within a a cell movable only within a
group. group.
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Flow for Single Row OptimizationFlow for Single Row Optimization
Partition a row of cells into groups
Pick groups for optimization
Perform group optimization tentatively
Accept the result if printability is improved and overhead satisfies
constraint
Difficult
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Group OptimizationGroup Optimization
Compute the placement with best manufacturability cost (no wirelength
constraint)
Compute the placement with best wirelength (initial placement)
Tradeoff: gradually tune best manufacturability placement towards the
best wirelength placement
Difficult
Difficult
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Placement with Best Manufacturability CostPlacement with Best Manufacturability Cost
: 0
: manufacturability cost
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Placement with Best Manufacturability CostPlacement with Best Manufacturability Cost
: 0
: manufacturability cost
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Placement with Best Manufacturability CostPlacement with Best Manufacturability Cost
: 0
: manufacturability cost
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Placement with Best Manufacturability CostPlacement with Best Manufacturability Cost
: 0
: manufacturability cost
Flipped
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Placement with Best Manufacturability CostPlacement with Best Manufacturability Cost
: 0
: manufacturability cost
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Placement with Best Manufacturability CostPlacement with Best Manufacturability Cost
: 0
: manufacturability cost
Every placement
corresponds to a Hamiltonian
path
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Minimum Cost Hamiltonian Path ProblemMinimum Cost Hamiltonian Path Problem
The placement with best manufacturability The placement with best manufacturability cost cost the minimum cost Hamiltonian Path the minimum cost Hamiltonian Path – No wirelength constraintNo wirelength constraint
Well-known NP-hard problemWell-known NP-hard problem Closest point heuristic is usedClosest point heuristic is used
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Handle Wirelength ConstraintHandle Wirelength Constraint
Start from best manufacturability solution Gradually adjust it to satisfy wirelength
constraint
A B C D E
B A E D C
Best Manufacturability
Best Wire
Reduce crossings: Reduce crossings: fewer crossings fewer crossings closer to closer to best wire solution best wire solution possible to satisfy the possible to satisfy the wirelength constraintwirelength constraint
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Handle Wirelength ConstraintHandle Wirelength Constraint
Start from best manufacturability solution Gradually adjust it to satisfy wirelength
constraint
A B C D E
B A E D C
Best Manufacturability
Best Wire
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Handle Wirelength ConstraintHandle Wirelength Constraint
Start from best manufacturability solution Gradually adjust it to satisfy wirelength
constraint
A B E D C
B A E D CBest Wire
Able to get the solution with good Able to get the solution with good manufacturability cost satisfying the wirelength manufacturability cost satisfying the wirelength constraintconstraint
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Multiple Row Based OptimizationMultiple Row Based Optimization
MotivationMotivation– A net often spans adjacent rowsA net often spans adjacent rows– Moving cells in different rows simultaneously Moving cells in different rows simultaneously
may reduce wirelengthmay reduce wirelength– Some previously “infeasible” Some previously “infeasible”
manufacturability-driven placement may manufacturability-driven placement may become “feasible”. More options.become “feasible”. More options.
Feasible: satisfy wirelength constraintFeasible: satisfy wirelength constraint– Improved manufacturability costImproved manufacturability cost
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ExperimentsExperiments
Experiment Setup– ISCAS’ 89 (>10K cells in a circuit) and
ISPD’ 04 benchmark (>200K cells in a circuit)
– 130nm technology– SPLAT for lithography simulation– 1% wire length increase bound– Lookup table size: <1M– Lookup table access time: <0.1ɥs per
entry– A Pentium 4 machine with a 3.0GHz CPU
2G memory
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ISCAS’89: EPE reduction %ISCAS’89: EPE reduction %
0
5
10
15
20
25
30
EPE R
educt
ion %
Cell Flipping Single Row Optimization Multiple Row Optimization
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ISCAS’89: Wirelength Increase %ISCAS’89: Wirelength Increase %
00.10.20.30.40.50.60.70.80.9
1
Wir
ele
ngth
Incr
ease
%Cell Flipping Single Row Optimization Multiple Row Optimization
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ISCAS’89: Runtime (seconds)ISCAS’89: Runtime (seconds)
0102030405060708090
100
CPU
(s)
Cell Flipping Single Row Optimization Multiple Row Optimization
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ObservationsObservations
Cell Flipping: Cell Flipping: – 9% EPE reduction9% EPE reduction– 0.17% additional wire0.17% additional wire– FastestFastest
Single Row Optimization: Single Row Optimization: – 14.6% EPE reduction14.6% EPE reduction– 0.35% additional wire0.35% additional wire– 2x slower compared to Cell Flipping2x slower compared to Cell Flipping
Multiple Row OptimizationMultiple Row Optimization– 22% EPE reduction22% EPE reduction– 0.57% additional wire0.57% additional wire– 4x slower compared to Cell Flipping4x slower compared to Cell Flipping
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ISPD’04: EPE Reduction %ISPD’04: EPE Reduction %
0
5
10
15
20
25
30
35
EP
E R
ed
uct
ion
%
Cell Flipping Single Row Optimization Multiple Row Optimization
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ISPD’04: Wirelength Increase %ISPD’04: Wirelength Increase %
Percentage
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Wir
ele
ng
th In
cre
ase
%
Cell Flipping Single Row Optimization Multiple Row Optimization
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ISPD’04: CPU (s)ISPD’04: CPU (s)
0
1000
2000
3000
4000
5000
6000
CP
U (
s)
Cell Flipping Single Row Optimization Multiple Row Optimization
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ObservationsObservations
Cell Flipping: Cell Flipping: – 11% EPE reduction11% EPE reduction– 0.16% additional wire0.16% additional wire– Very fastVery fast
Single Row Optimization: Single Row Optimization: – 18% EPE reduction18% EPE reduction– 0.29% additional wire0.29% additional wire– 50% slower50% slower
Multiple Row Optimization:Multiple Row Optimization:– 25% EPE reduction25% EPE reduction– 0.41% additional wire0.41% additional wire– 2x slower2x slower
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ConclusionConclusion
Propose three algorithms for pattern sensitive placement for manufacturability: – Cell Flipping only– Single Row Optimization– Multiple Row Optimization
>20% edge placement error reduction. <1% wire length overhead. Runtime acceptable for large placement
benchmark.
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