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May. 1978 B-7/84-100~2061-3

PRINTED IN USA

SERVICE MANUAL 6058

ADL-256

AUTO-ADD DATA LINK

UNION SWITCH a SIGNAL b~f TABLE OF CONTENTS

SECTION DESCRIPTION

I INTRODUCTION

1.1 GENERAL 1.2 TRANSMITTER UNIT 1.3 RECEIVER UNIT 1.4 APPLICATION INFORMATION

1.4.1 1.4.2 1.4.3

Typical System Configuration Transmission Line Alternatives Lightning/Surge Protection

II SYSTEM FIELD MAINTENANCE

2.1 GENERAL 2.2 TRANSMITTER UNIT

2.2.1 2.2.2 2.2.3

AC/DC Power Supply Transmitter Housekeeping Transmitter Opto Interface

2.3 RECEIVER'UNIT·

2.3.1 2.3.2 2.3.3 2.3.4

AC/DC Power Supply ~ceiver·Housekeeping Receiver Transistor Interface Receiver Relay Interface

2.4 P.C.B. NECESSARY FOR REPAIRING TRANSMITTER OR RECEIVER UNITS

2.4.1 Servicing Transmitter Unit 2.4.2 Servicing Receiver Unit

2.5 TROUBLESHOOTING TABLE

III SYSTEM DESCRIPTION AND THEORY OF OPERATION

J.l GENERAL 3.2· TRANSMITTER UNIT

3.2.1 Standby Mode 3 •. 2 • 2 Maintenance Mode

3.3 RECEIVER UNIT 3.4 BLOCK DIAGRAMS FOR RECEIVER AND

TRANSMITTER P.C.B.

IV L.E.D. INDICAT~ONS AND MAINTENANCE MODE

4.1 GENERAL

i

.· PAGE

1 - 1

1 1 1 - 1 1 - 7 1 -11

1 -11 1 -12 1 -12

2 - 1

2 - 1 2 - 5

2 - 5 2 - 5 2 - 8 " '.t;,j

~ ;,"f-

2 8 ~ - -~ ;':;, ·,~ :X·

2 8 2 8 2 -11 2 -11

2 -13

2 -13 2 -13

2 -15

3 l

3 - 1 3 - 1

3 - 2 3 - 2

3 - 2

3 - 5

4 - 1

4 - 1

~ UNION SWITCH & SIGNAL

TABLE OF CONTENTS {Continued)

SECTION DESCRIPTION

IV ( Continued)

v

4.2 TRANSMITTER UNIT L.E.D. INDICATIONS 4.3 -TRANSMITTER UNIT MAINTENANCE MODE OF

OPERATION 4.4 RECEIVER UNIT L.E.D. INDICATIONS 4.5 RECEIVER UNIT MAINTENANCE MODE OF

OPERATION

SHOP MAINTENANCE

5.1 GENERAL 5.2 CIRCUIT DESCRIPTION AC/DC POWER SUPPLY

PCB 5.3 CIRCUIT DESCRIPTION TRANSMITTER

HOUSEKEEPING PCB

5.3.1 5.3.2 5.3.3 5.3.4

5.3.5

5.3.6 5.3.7 5.3.8 5.3.9

Power Up Circuitry Clock Circuitry Bit Count and Load Circuitry Control Character Generation For Message Format Parallel- to Serial Conversion Circuitry Data Carrier Interface Circuits Test Circuitry LED Indications Option lOlX Flashing Relay Option

5.4 CIRCUIT DESCRIPTION OPTO INTERFACE PCB 5.5 CIRCUIT DESCRIPTION OF RECEIVER

HOUSEKEEPING PCB

5.5.1 5.5.2 5.5.3

5.5.4 5.5.5 5.5.6 5.5.7 5·. 5. a

Power Up Circuitry Clock Circuitry Message Format and Control Character Decoding Error Checking Circuitry Addressing and Strobe Circuitry Data Carrier Interface Circuits Test Circuitry L.E.D. Indications

5.6 CIRCUIT DESCRIPTION OF RECEIVER TRANSISTOR INTERFACE PCB

5.7 CIRCUIT DESCRIPTION OF RECEIVER RELAY INTERFACE PCB

5.8 MOTHER BOARD PCB

ii

PAGE

4 - 1

4 - 3 4 - 7

4 - 9

5 - 1

5 - 1

5 - 1

5 - 8

5 - 8 5 - 8 5 - 9

5 - 9

5 -10 5 -10 5 -21 5 -21 5 -21

5 -21

5 -29

5 -29 5 -29

5 -30 5 -30 5 -31 5 -31 5 -32 5 -32

5-43/5-44

5-51/5-52 5-59/5-60

TABLE OF CONTEN~S {Continued)

SECTION DESCRIPTION

VI APPENDIX

6.1 FLOW CHART UTILIZATION 6.2 -HANDLING CONSIDERATIONS FOR COS/MOS 6.3 LOGIC SYMBOLS 6.4 GLOSSARY OF TERMS 6.5 ORDERING INFORMATION

iii

UNION SWITCH & SIGNAL t::l:I

PAGE

6 - 1

6 - 2 6 - 3 6 - 4 6 - 7 6 -12

O'I 8 0 U1 00 .. c z "O 0 z .

i I-' I JJlll ~

I\.) lliria-,'IH& r,e;,i!!.f-I2~c.?f,?J:::'; ~, •, ,, ... ~ ~ ::c ~ en Q z )> r

Figure 1-1. ADL-256 Typical Transmitter Unit

\

UNION SWITCH & SIGNAL ClJ

\.0 l()

N I

i-'.l Q

~

N I

r-1

(IJ ~ ::s

°' ·r-1 ~

6058, p. 1-3

°' 0 Ul ClO ... 'O • ..... I ~

ADDRESS BUS

120 VA

TRANSMITTER HOUSEKEEPING P.C.B.

DATA AQUISITION FROM BUS STRUCTURE PARALLEL-TO-SERIAL FORMAT MESSAGE PROTOCOL SECURITY ENCODING

WORD O & 1

TRANSMITTER OPTO INTERFACE

16 CHANNELS INPUT SIGNAL CONDITIONING ..

• H DATA BUS

L ?N~ -. ' ' ' ....

16 ISOLATED DATA BIT INPUTS'

..... - - - - -· - - - - - -- ., I TRANSMITTER OPTO INTERFACE I I I .- - - - - - - - - - - - - -, I

WORD 30 & 31

l- - - - - - - - -f- - - - - -- .J

' d ...

POWER SUPPLY

C 60 Hz ...

+ +12 voe

.... •

,. -12 voe ... -_..,.., __ ._ •• 1'1""1.T r ~ mnl\UC"MTmmt:'D Tll\TTIT'

EIA OR TTL DATA INTERFACE (Optically Isolated)

f c z 0 z I ~ ... Cl)

i5 z > r-

UNION SWITCH & SIGNAL (:)1

TABLE 1-1

TRANSMITTER UNIT SPECIFICATIONS

GENERAL SPECIFICATIONS

Physical Dimensions:

Height

35.56 cm. 14 in. 19" rack mount

Width

43.82 cm. 17-1/4 in.

Weight - Package plus 11.26 Kg; 24 lbs. 12.5 oz. full complement of P.C. boards

Operating Temperature: -40 to +70°C; -40 to 158°F

Operating Humidity: 0 to 90% non condensing

Storage Temperature: -so to +100°C; -58 to 212°F

Data Capacity: 16 bits minimum 256 bits maximum

Depth

26.67 cm. 10-1/2 in.

Expandable in groups of 16 bits

Power Input (Nominal 120 VAC):

by the addition of 1 PCB per 16 bits

92 to 130 VAC 55 Hz to 65 Hz

AC Surge Capability 3000 volts peak for 1.5 milliseconds

at a 10 ohm source impedance

Power Consumption 16 watts with Data Carrier Unit (Maximum 256 Bit System at 120.VAC):

Power Available for +12 volts, 150 ma Data Carrier Equipment: -12 volts, 75 ma

INPUT SPECIFICATIONS

Number of Discrete Data Inputs:

Input Isolation Device:

Breakdown Voltage Transient Input High To Common Terminal:

Breakdown Voltage - All Inputs to Ground:

256 maximum - two individual isolated connections per input

Electro-Optical Coupler

+1000 V for 10 milliseconds

3000 volts

6058, p. 1-5

UJ UNION SWITCH & SIGNAL

TABLE 1-1 (Continued)

Input Voltage Threshold:

Binary O Binary 1

Maximum Steady State Voltage:

Input Current for Binary 1 Over Input Voltage Range:

Input Response Time Using Opto Interface P.C.B. UN085722-1001:

On Time Off Time

1 volt D.C. or A.C. RMS 5 volt D.C. or A.C. RMS

40 volts D.C. 32 volts A.C. RMS

2.2 ma. maximum

25 miliiseconds 150 milliseconds

{Typical)

Response Time Using Opto Interface P.C.B. UN085722-1011:

On Time Off Time

1 millisecond 1 millisecond

(Typical)

DATA COMMUNICATION SPECIFICATIONS

Data Rates, Switch Selectable:

Coding:

Data Interface:

Modes:

Data Output:

Mark Space

Request To Send Output:

·clear To Send Input:

Clock Output:

OPTIONS

UN085721-101X

6058, p. 1-6

75, 150, 300, 600, 1200, 2400 bits per second

Binary, non-return to zero

EIA Standard RS-232-C or TTL levels

Synchronous or asynchronous

EIA Levels

-5 voe +5 voe

on State +5 voe Off state -5 voe

on state 3.0 voe Off state -3.0 voe

swinging +5 voe

TTL Levels

o voe +5.o voe

+5.o voe o voe

N.A. N.A.

swinging o voe to +5 voe

Transmitter Housekeeping P.C.B. with relay flashing option (used for flashing indications from the transmitter location) Flashing Relay Contact Rating: Single form c, 1 amp, 32 voe

UNION SWITCH & SIGNAL w SECTION I

INTRODUCTION

1.1 GENERAL

The Auto-add Data Link 256 (ADL-256} is a system for moving information (or data) from one location to another via data carrier hardware·. The location at which the inf.ormation is inputted to the system is called the Transmitter Location. The location at which the information is outputted from the system is called the Receiver Location. The ADL-256 hardware located at a transmitter location is called the Transmitter Unit and the hardware located at the receiver location is called the Receiver Unit.

In Figure 1-1 can be found a photograph of a typical Transmitter Unit and in Figure 1-2 can be found a photograph of a typical Receiver Unit.

1.2 TRANSMITTER UNIT

In Figure 1-3 can be found a block diagram of the ADL-256 Transmitter Unit. At the transmitter location, information is inputted to the Transmitter Unit in the form of a voltage from such things as relay contacts or lamps. This voltage can be either AC or DC. These inputs are fed into the Opto Interface Printed Circuit Boards. Two isolated connections are provided for each input. Each Opto printed circuit board contains 16 inputs. A Transmitter Unit may contain between one and 16 Opto interface printed circuit boards resulting in a system capacity of between 16 and 256 bits in groups of 16 bits.

The Transmitter Housekeeping P.C.B. looks at all the inputs periodically, encodes the data from the Opto boards to ensure data transmission reliability, and outputs the data to an external data carrier transmitter. The power supply, internal to the Transmitter Unit, supplies power to all internal circuitry as well as the external data carrier transmitter. In Table 1-1 can be found a summary of the specifications for the Transmitter Unit.

6058,-p. 1-1

UNION SWITCH & SIGNAL

1.3 ADL-256 RECEIVER UNIT

In Figure 1-4 can be found a block diagram of the ADL-256 Receiver Unit. At the Receiver Unit, the Receiver Housekeeping P.C.B. inputs data from~ Data Carrier Receiver. This is the encoded data sent from the Transmitter Unit. The Receiver Housekeeping P.C.B. inputs this data, decodes it to assure that no errors have occurred during transmission, and routes the data to the appropriate output Interface PCB. The Receiver Unit is so structured.that the received data is routed to the same relative position on the same interface PCB as it was input to at the Transmitter Unit. The Receiver Unit contains between one and 16 interface PCB's, each of which support 16 outputs. Two types of output Interface PCB's are available. The first type is the Transistor Output PCB. This unit supplies open transistor collector outputs for each bit. The transistor is "on" when the correspondinq input at the Transmitter Unit has voltage applied. The second type of interface is the reed relay output PCB. This PCB supplies a form C {single transfer) relay contact for each output bit. This relay is picked up {front contact closed) when the corresponding input is energized at the Transmitter Unit. These relays are of the magnetic stick type. When power is removed from the unit, each relay will remain in the same position (open or closed) until power is reapplied and new data is received from the Transmitter Unit. Each Receiver Unit contains a power supply which runs all internal circuitry as well as the external data receiver. In Table 1-2 can be found a specification surnmarv for the Receiver Unit.

TABLE 1-2

RECEIVER UNIT SPECIFICATIONS

GENERAL SPECIFICATIONS:

Physical Dimensions (same as Transmitter Unit):

Weight - Package plus Full Complement of:

Relay Output Boards Transistor Output Boards

Operating Temperature:

Operating Humidity .

Width Depth Height

35.56 cm. 43.82 cm. 26.67 cm.

14 in. 17-1/4 in. 10-1/2 cm.

19 inch rack mount

15.36 Kg; 33 lbs, 12.5 oz~ 11.03 Kg; 24 lbs, 4 oz

-40 to +70°C; -40 to 158°F -30° to +70°C with reed relay outputs

Oto 90% non-condensing

6058, p. 1-7

TABLE 1-2 (Continued)

Storage Temperature:

Data Capacity:

-so to +100°C; -58 to 212°F

16 bits minimtmt 256 bits maximum Expandable in groups of 16 bits by addition of 1 PCB per 16 bits

Power Input (Nominal 120 VAC) 92 to 130 VAC

Power Available for Data Carrier Equipment:

Power Consumption (Maximum 256 bit System at 120 VAC):

OUTPUT SPECIFICATIONS:

Number of Indications or Controls:

Indication Delivery:

Transistor Output Rating:

Control Delivery:

Expected Mechanical Life:

Maximum Contact Rating:

6058, p. 1-8

55 Hz to 65 Hz

AC surge capability 3000 volts peak for 1.5 milliseconds at a 10 ohm source impedance

+12 volts, 150 ma -12 volts, 75 ma

24 watts with data set

256 maximum

Transistor output; open collector common ground

Maximum Voltage: 32 volts Maximum Current: 100 milliamps Surge Current: 1 amp for 10 msec.

Relay output, ·single form C contact per output (heels bussed in groups of 4)

100 million operations

1 amp, 32 voits DC or AC

UNION SWITCH a SIGNAL ffi TABLE 1-1 (Continued)

DATA COMMUNICATIONS SPECIFICATIONS:

Data Rate, Switch Selectable: 75, 150, 300, 600, 1200, 2400 bi ts per second·

Coding:

Data Interface:

Modes:

Data Input:

Mark Space

Carrier

Binary, non return to zero

EIA Standard RS-232-C or TTL

Synchronous or asynchronous

EIA Levels TTL Levels (minimum) (minimum)

-3 voe 0 voe 3 voe 2.4 voe

+3 voe 2.4 voe -3 voe 0 voe

6058, p. 1-9

°' 0 ll1 0) ... ttj • I-' I

I-' 0

EIA OR TTL DATA INTERFACE

(Optically Isolated

ADDRESS BUS

/

RECEIVER HOUSEKEEPING P.C.B.

MESSAGE PROTOCOL DECODING SECURITY CHECKS DATA DISTRIBUTION TO BUS

WORD 0,1

RECEIVER TRANSISTOR INTERFACE

16 OUTPUT BITS . RECEIVER RELAY INTERFACE

16 OUTPUT BITS (Heels Buse~ in Groups of 4) ·

,•

I _._.,_.L_ __

RECEIVER TRANSISTOR OR RELAY INTERFACE

L ___ .!o~ ~1-~

-,

I

_J

DATA BUS

+l: VDC =l POWER SUPPLY ~ 12 O VAC

-12 voe 60 Hz

Figure_l-4. BLOCK DIAGRAM ADL-256 RECEIVER UNIT

E c z 0 z I ~ :c ,.. en i5 z > r

UNION SWITCH a SIGNAL OJ

1.4 APPLICATION INFORMATION

GENERAL

The Transmitter and Receiver Unit Housekeeping PCB's must be mutually set to obtain proper system operation. They contain the following switch programmable features:

a. A 16 position (hexadecimal) switch for station address purpose.

All units are normally shipped from the factory with the switch set in position "C". The station address feature provides a high degree of security against cross.talk. This facility also permits expanding the system capacity from 256 bits to 512 bits by adding a second Transmitter and Receiver Unit to the system.

b. A six position switch for selecting one of the six bit per second rates of 75, 150, 300, 600, 1200 or 2400.

c. A three position mode switch for selecting one of the three mode positions; operation, standby or maintenance.

On the inside cover of the ADL-256 Transmitter and Receiver Units, a label lists the proper positions for PCB's, the proper address and bit rated adjustments for the housekeeping PCB's and the meanings of the light emitting diodes (LED's) mounted on the PCB's. Pictures of three typical ADL-256 labels are shown on Figures 2-1, 2-2 and 2-3.

1.4.1 Typical System Configuration

Figure 1-5 represents a typical application of the ADL-256 system. View "A" shows a configuration for transferring data from a central office to a field location. This case shows that a reed relay interface output PCB is used inside the field Receiver Unit to output the data.

View "B". shows a configuration for transferring data from a field location to a central-office. In this case a transistor output interface PCB is used inside the central office Receiver Unit to output the.data.

The ADL-256 system can use either transistor or reed relay output interface PCB's for the Receiver Unit's data output.

The system also permits the use of a combination of transistor and reed relay output interface PCB's within the same Receiver Unit. The later receiver card enclosure for transistor output (ventilated) P.C. No. UN085718-1002 must be used.

6058, p. 1-11

\JJ UNION SWITCH a SIGNAL

1. 4 •. 2 TRANSMISSION LINE ALTERNATIVES

Figure 1-6 displays the transmission line alternatives for the· system. View "A" displays a multi station set up based on all stations sharing one common transmission line reducing the minimum transmission line requirements. View "B" displays a multi station -set up based on each having a separate transmission line offering the following advantages:

a. Permits standardization of carrier.modem spare parts.

b. A transmission line fault only renders one field station inoperative.

1. 4. 3 LIGHTNING/SURGE PROTECTION

The ADL-256 equipment has been designed to provide a high level surge tolerance for the transmitter listed under the specifications Table 1-1, and for the Receiver Units listed under the specifications Table 1-2. Additional ADL-256 external surge protection devices are not necessary as long as the associated input/output interface boards to/from equ~pment tie-ins and wire runs originate and terminate within same instrument enclosure. For any tie-ins and wire runs external to the instrument enclosure, or any other specific applications, contact the nearest WABCO District Office.

6058, p. 1-12

OFFICE

CONTROLS

I/0 OFFICE

TRANSMIT CONTACTS

(2)

B+ N INPUT BIT 1

TRANSMIT LOGIC

ADL-256

(1) r----, 1 TRANSMIT I I OPTO-INT I I PCB I TRANS.

I I I I

L--, L - -~ 16 OPTO-COUPLERS I

HOUSEKEEPING

PCB

~ .,....-1----------l~(I ~ (3)

N (-) ~ NEG BUSS ~ <----~----' 'i. PER PCB I

t _______ -1

NOTES:

TRANSMIT CARRIER MODEM

(1) THE ADL-256 CODE SYSTEM IS EXPANDABLE TO 256 BITS, ONE INTERFACE/PCB MUST BE ADDED FOR EACH ADDITIONAL 16 BI·rs ABOVE THE lST 16 BITS TO EACH TRANSMIT AND RECEIVE LOGIC.

(2) ONE WIRE, FOR EVERY I/0 DATA BIT REQUIRED FOR APPLICATION, MUST BE RUN BETWEEN I/0 AND ADL-256 CABINET (t20AWG SUGGESTED).

(3) NEG. BUSS - ONE WIRE REQUIRED FOR EACH I/0 CONTACT, RELAY, OR MONITOR POWER SOURCE, UNLESS COMMON NEG BUSING OF POWER SOURCES ARE PERMITTED.

INDICATIONS

I/0 OFFICE RECEIVE

MONITOR DEVICE

B+

(2)

OUTPUT BIT N

NEG. BUSS

(3)

RECEIVE LOGIC

ADL-256 (INCLUDES STORAGE)

r---, I

I I I

(1)

RECEIVE HOUSEKEEPING

PCB

r---J L_ __ , I 16 TRANSISTOR I L - - ~E!_~B ___ .l

RECEIVE CARRIER

MODEM

Figure 1-5.

PHONE LINE

INTERFACE

PHONE LINE

INTERFACE

CARRIER COMMUNICATION

LINK

CARRIER COMMUNICATION

LINK

PHONE LINE

INTERFACE

PHONE LINE

INTERFACE E-

TYPICAL SYSTEM CONFIGURATION

RECEIVE CARRIER

MODEM

TRANSMIT CARRIER

MODEM

J

'

UNION SWITCH & SIGNAL m FIELD

RECEIVE (1) LOGIC ADL-256

(INCLUDES STORAGE)

RECEIVE HOUSEKEEPING

PCB

TRANSMIT LOGIC

ADL-256

TRANS.

r-----, I RECEIVE I I INTERFACE I PCB +v I

I I OUTPUT (2) I BIT N

CONTROLS

I/0 FIELD INTERPOSER RECEIVE RELAYS

I I I I

~-......:..'-}>-~~~-,1--l

: I +B

I 16 ...._ __ •-»-- OPTION

I PCB I \... _____ .J I (3)

NEG. BUSS '-~~~~)>-~~~~~--'

(1)

TRAIISMIT INTERFACE

PCB

-...

(2)

INPUT

INDICATIONS

I/0 FIELD INTERPOSER

TRANS.

B+ -BOUSE- E-~f > I

, BITN r (3)

KEEPING PCB

16 OPTO-COUPLERS PER PCB

. ... T I

~--1

) NEG. Buss·

\ , CONTACTS

6058, p. 1-13/1-14

2 WIRE DROP INTO FIELD STATION f3

T

FREQ 5

FREQ 6

FIELD STATION 13

TRANSMIT & REC.

Ll L2

c~ c:i FREQ. FREQ.

FIELD STATION 13

l 2

TRANSMIT & RECEIVE

(.( , ,I

c r ,,

4 WIRE DROP INTO FIELD STATION i2

T

FREQ 3

FREQ 4

FIELD STATION 12

TRANSMIT & REC.

VIEW "A"

MULTIPLE STATION APPLICATION BASED ON SHARING A COMMON TRANSMISSION LINE

WIRE DROP INTO FIELD STATION II

T (

(CONDUCTOR U) << ,,,

TRANSMISSION LINE----<::

,I,

( (< ,I

(CONDUCTOR 12) lu ,,

L3 i.4 L2

( ( ~ (~ <b FREQ I \ ...___ ) FREQ 2

FIELD STATION n

TRANSMIT & REC.

VIEW "B"

MULTIPLE STATION APPLICATION BASED ON DISCRETE TRANSMISSION LINES

(CONDUCTOR 11)

TRANSMISSION LINE-<

(CONDUCTOR 12)

c ( (CONDUCTOR U)

7/ TRANSMISSION LINE~

~) (CONDUCTOR i2

{CONDUCTOR U c {

TRANSMISSION LINE~

,/,/

(( Ll L2 Ll fL2 (CONDUCTOR #2) /,

c~ <~ FREQ. I I~ 0 FREQ. l FREQ. 2 FREQ. 2

FIELD STATION i2 FIELD STATION il

TRANSMIT & RECEIVE TRANSMIT & RECEIVE

FIGURE 1-6. TRANSMISSION LINE ALTERNATIVES


2 WIRE DROP INTO CENTRAL OFFICE

T

I I

STATION 13 STATION 12

TRANSMIT TRANSMIT

AND AND

RECEIVE RECEIVE

FREQ 5 = TRANS. FREQ 3 = TRANS.

FREQ 6 = REC. STATION U FREQ 4 = REC.

TRANSMIT

AND

RECEIVE

FREQ l = TRANSMIT

FREQ 2 = RECEIVE

CENTRAL OFFICE

CENTRAL Ll STATION 13 OFFICE

ALL CARRIER TRANSMIT MODEMS L2

AND HAVE SAME TRANSMIT

RECEIVE FREQ. (Fl)

SAME REC. FREQ. (F2)

Ll STATION 12

TRANSMIT L2 AND

RECEIVE

Ll STATION H

L2 TRANSMIT ) ANO

RECEIVE

6058, p. 1-15/1-16

UNION SWITCH & SIGNAL UJ

SECTION II .

SYSTEM FIELD MAINTENANCE

2.1 GENERAL

When improper operation of an ADL~256 Data Transmission System is detected, the first problem will be localizing the failure to either the transmitter or receiver location. When arriving at a location where a failure is suspected, the ·first thing noticed is that the ADL-256 Units are housed behind an aluminum cover. This cover serves the dual purpose of minimizing dirt entry through the front of the package while holding the printed circuit boards firmly in the package. For these reasons, it is important that the cover be replaced when servicing is completed.

The cover is held on by three, quarter turn fasteners along the top. Turn each of these 1/4 turn counter clockwise and pull the cover gently open from the top. The cover will stop at a position of 90°. The cover can be removed by sliding it upward and gently pulling towards you.

On 'the inside of the cover is a label listing the proper · positions for printed circuit boards, the proper address and bit rate adjustments for the housekeeping printed circuit board, and the meanings of the light emitting diodes (LED's) mounted on the Printed Circuit Boards. Pictures of three typical ADL-256 labels will be found in figures 2-1, 2-2, and 2-3.

With a little experience the patterns generated by the LED's during normal operation., will become familiar. This familiarity will allow a faster localization and correction of error conditions.

The ADL-256 Data Transmission System was designed so that field failures can be repaired by exchanging a known good printed circuit board for a suspected bad board. There is a-minimum number of different printed circuit board types in this system.

The following are functional descriptions of each PCB and their operation in the system.

6058, p. 2-1

O'I 0 u, 00 ...

"O

N I

N

SWITCH POSITIONS

MODE: I. OPERATE

2. STAND BY

3. MAINTENANCE

TEST: PUSH TO ENERGIZE

COUNT: UP • BIT

DOWN • WORD

INPUT: UP • MARK

DOWN • SPACE

BIT RATE SWITCH POSITION

O 2400 bps

0 1200 bp,

O 600 bps

O 300 bps

O ISO bp,

. 0 75 bps

STATION ADDRESS

0 0 01 02 0 3

0 4 os 06 07

0 8 0 9

O A

OB

3

4

6

oc OD OE OF

02 MODE 3

TEST • G) COUNT

~ INPUT

~ ~:F) POWER 8 OPERATE 8 CARRIER DETECT 8 ADDRESS DISABLE 8 COMP CHE"CK 8 DATA RECEIVER RELAY INTERFACE PCBS 8 LAST WORD 8 ERROR UN085725-1001

8 ALARM 8 BIT O 8 BIT l 8 BIT 2 8 BIT 3 8 BIT 4

8 -12 VOLTS 8 BITS 8 BIT 6

8 +12 VOLTS 8 BIT 7 WORD WORD WORD WORD WORD WORI WORD WO Rt WORD WORD WORD

AC POWER SUPPLY RECEIVER HOUSEKEEPING eo •2 84 86 88 810 812 814 816 818 820

PCB PCB UN085719-100l UN085723-l001 •1 83 es 87 89 811 813 815 817 819 •21

• Indicates the location of an LED on the PCB

Figure 2-1. ADL Typical Labels

WORD WORD WORI 822 824 826

823 825 827

WORD WORD 828 830

829 831

8 c: z 0 z I ~ :c Rt u, a ~ ,-

O'\ 0 Ul 0:, ... '"O

N I w

SWITCH POSITIONS

MODE: I. OPERA TE

2. STAND BY 3. MAINTENANCE


COUNT: UP • BIT

DOWN· WORD

BIT RATE

O 2400 bps

O 1200 bps

O 600 bps

O 300 bps

O 150 bps

O 75 bps

SWITCH POSITION

1

0 0 01 02 03

STATION ADDRESS

0 4 0 8 0 5 0 9 0 6 0 A

O 1 OB

4

5

6

oc OD OE OF

0~ MODE 3

TEST e G> COUNT -

Q g~F} POWER e OPERATE e REQUEST TO SEND e CLEAR TO SEND e ADDRESS DISABLE e TRANSMIT TRANSMITTER OPTO INTERFACE PCBS e LAST WORD e LOAD

UN085722-l001

e DATA e BIT O e BIT I e BIT 2 e BIT 3 e BIT 4

e -12 VOLTS e BIT 5 e BIT 6

e +12 VOLTS e BIT 7 XMTR HOUSEKEEPING

WORD WORD WORD WORD WORD WORD WORD WORD WORD WORD WORD

AC POWER SUPPLY PCB eo e2 e4 e6 es e10 e12 e14 el6 e1s e20

PCB UN085721-I001 0 UN085719-1001

•

UN085721-10ll O e1 e.3 es •1 .9 en eu ••s e11 •19 e21

• Indicates the location of· an LED on the PCB


WORD WORD WORD e22 e24 e2,

e23 e2s e21

WORD WORD e2a e.ao

e29 e31

c z 0 z I ~ • u, a : ,..

8

°' 0 u, (X) ...

"O

I\)

I .,:,.

SWITCH POSITIONS

MOOE: I. OPERATE

2. STANO BY

3. MAINTENANCE


COUNT: UP • BIT

DOWN · WORD INPUT: UP · MARK

DOWN · SPACE

BIT RATE

O 2400 bps

O 1200 bps

O 600 bps

0 300 bps

O 150 bps

O 75 bps

SWITCH POSITION

I

0 0 01 02 03

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06 07

0 8

0 9

O A

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eD e2 e4 e6 es e10 e12 •14 e16 •1a e20 e22 e24 e26 •2a e30 3 • TEST

® COUNT el e3 es •1 e9 en e13 e1s •11 e19 e21 •23 e2s •21 e29 e31 <ii) INPUT

~ ~:F) POWER

>-=-

e OPERATE e CARRIER DETECT e ADDRESS DISABLE e COMP CHECK e DATA RECEIVER TRANSISTOR INTERFACE PC8S e LAST WORD e ERROR UN085724-1001

e ALARM • BIT D e BIT I • BIT 2 • BIT 3 e BIT 4

e ,12 VOLTS e BIT 5 e BIT 6

e +12 VOLTS • BIT 7

AC POWER SUPPLY RECEIVER HOUSEKEEPING PCB PCB

UN085719-IOOI UND85723-IDOI

• Indicates the location of an LED on the PCB


' '

UNION SWITCH & SIGNAL ttJ


2.2.1 AC/DC Power Supply

Figure 2-4 is a photograph of the AC/DC Power Supply P.C.B with its cover removed. The AC/DC Power Supply accepts a nominal input of 120 VAC 60 Hz and provides regulated outputs of +12 volts D.C. @ .6A and -12 volts D.C. @ .2A respectively. Each output incorporates both over voltage clamp and foldback current limiting circuitry. The power supply is designed to provide power {+12VDC) for either a Transmitter or Receiver Unit as well as power for the external data carrier equipment and its interface circuitry. Two light emitting diodes (LEDs) are provided on the board to indicate the status of the power supply. The upper LED indicates the status of the -12 volt D.C. output,while the lower LED indicates the status of +12 volt D.C. output. These LEDs are normally illuminated during system operation.

2.2.2 Transmitter Housekeeping

Figure 2-5 is a photograph of the Transmitter Housekeeping P.C.B. The Transmitter Housekeeping board is essentually a parallel input to serial output converter. The transmitter sequentually addresses ·each Opto Interface P. c. B. in the Transmitter Unit. The input signals to the Opto boards are sampled by the Transmitter Housekeeping board when each opto board is addressed. These inputs are ac¢epted by the Transmitter Housekeeping P.C.B. in a parallel eight bit form via an 8 bit data bus. The Transmitter Housekeeping P.C.B. assembles the data into a message format and presents it as a serial output to a data carrier unit for transmission. Details of the message format and data encoding can be found in Section III of this manual. After completion of the message, the Transmitter Housekeeping P.C.B. begins a new message. The Transmitter Housekeeping P.C.B. is a constant scan, constant transmission system. The Transmitter Housekeeping board also contains data carrier interface circuitry. All interface circuitry is EIA standard RS-232-C compatible or TTL compatible by jumper application.

A clock output interface is also provided for system operation using synchronous data carrier equipment. A variable bit rate switch provides for switch selectable data rates between 75 bits per second to 2400 bits per second. Three modes of operation are provided via switch selection;· {Operate, Standby, Maintenance). A full description of these modes is given in Section III of this manual.

Sixteen LEDs are provided on the Transmitter Housekeeping P.C.B. to indicate the status of the Transmitter Unit during the Operate, Standby or Maintenance modes. For an explanation of these LED indications see Section III and IV of this manual.

6058, p. 2-5


!>t r-1 ~

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6058, p. 2-6

UNION SWITCH & SIGNAL ....._,

Figure 2-5. Transmitter Housekeeping Printed Circuit Board

6058, p. 2-7

W UNION SWITCH & SIGNAL

2.2.3 Transmitter Opto Interface

Figure 2-6 is a photograph of the Transmitter Opto Interface P.C.B. Each Opto Interface Board provides for the input of 16 external signal sources (indications or controls) to a Transmitter Unit. Two isolated connections are provided for each input. Transient protection circuitry, which will withstand potentials of one kilovolt without. destruction, is also provided for each input. Each input source is interfaced via its own optical coupler. Layout of the board is such that the optical couplers form a dividing line between the input circuitry and the internal logic signals. There is no electrical connection between the inputs and the internal power or signal lines. Input signals to the board can be voltages from 5 to 32V DC or AC RMS to be recognized as a logical "one".

The Transmitter Opto Interface P.C.B. also contains d~coding logic which automatically identifies which card slot in the Transmitter Unit card enclosure the board is plugged into. The outputs of the Transmitter Opto Interface P.C.B are Tristate. Normally the outputs are in the high impedance state. When correctly addressed, the first 8 (word 0) inputs are ready for parallel entry to the Transmitter Housekeeping P.C.B. via an 8 bit data bus. The second 8 (word 1) inputs are likewise output to the Transmitter Housekeeping P.C.B. when addressed. Two light emitting diodes (LED's) provide visual indication that either the first 8 or the second 8 inputs are being addressed. The address decoding logic also provides a signal to the Transmitter Housekeeping P.C.B. to confirm the presence of a board in a particular address slot.

2.3 RECEIVER UNIT

2.3.1 AC/DC Power Supply

The power.supply for the Receiver Unit is the same as the power supply used in the Transmitter Unit. See Figure 2-4.

2.3.2 Receiver Housekeeping_

Figure 2-7 is a photograph of the Receiver Housekeeping P.C.B. The Receiver Housekeeping P.C.B. provides the inverse functions of the Transmitter Housekeeping P.C.B. It is essentually an expandable serial to parallel converter. The Receiver Housekeeping P.C.B. accepts the transmitter data in a serial form via its data carrier interface circuitry. (EIA standard RS-232-C compatible or TTL compatible.) The Receiver Housekeeping logic does synchronization, address and error checking on the message format as well as on the data to assure no errors have occurred during transmission. The Receiver

6058, p. 2-:8

UNION SWITCH & SIGNAL ffi

-~ .•

Figure 2-6. Transmitter Opto Interface Printed Circuit Board

6058, p. 2-9

tij UNION SWITCH & SIGNAL

Figure 2-7. Receiver Housekeeping Printed Circuit Board

6058, p. 2-10

UNION SWITCH & SIGNAL OJ

sequentually addresses each interface PCB in the Receiver Unit. After the error checking is completed and no errors have been detected on each 8 bits of data, the data is delivered 8 bits (one word) at a time for output to the interface boards. If at anytime during the message an error is detected, the Receiver Housekeeping P.C.B. will not deliver the received data from the point of the detected error. The Receiver Housekeeping P.C.B. will begin looking for the beginning of a new message and deliver the received data ·if no errors are detected. For details of the error detection and types.of errors detected see Section III of this manual.

The Receiver Housekeeping P.C.B. is also provided with an alarm relay contact output. The Receiver Housekeeping P.C.B. will go into alarm if any 3 consecutive messages received are in error or if no messages are received for approximately 3 full (256 Bit) message times, or if there is a power failure. The receiver must receive a complete message with no errors to remove an alarm condition.

2.3.3 Receiver Transistor Interiace

Figure 2-8 is a photograph of the Receiver Transistor Interface P.C.B. Each transistor interface provides for the output of 16 bits of information (indications) from the the Receiver. Unit. Each output consists of a darlington transistor open collector capable of handling loads of 100 ma. at a maximum of 32VDC. The outputs are primarily designed for driving lamp type (filament) loads. The decoding logic on the Transistor Interface P.C.B. is similar to that on the Transmitter Opto Interface P.C.B. It automatically identifies which card slot in the Receiver Unit card enclosure the board is plugged into and also provides a signal to the Receiver Housekeeping P.C.B. to confirm the presence of the board when it is addressed. When correctly addressed,the data strobe signal causes information on the data bus to be strobed into a latch which drives the transistor outputs. Two LED's on the Transistor Interface P.C.B. provide visual indication that either the first 8 bits (Word 0) or the second 8 bits {Word 1) are being addressed.

2.3.4 Receiver Relay Interface

Figure 2-9 is a photograph-of. the Receiver Relay Interface P.C.B. Each Relay Interface board provides for the output of 16 bits of information (controls) from the Receiver Unit. Each output consists of a form "C" mercury wetted relay. The heels of the relays are bused in groups of 4. The relay output is capable of switching loads (Resistive or Snubbed Inductive) of up to lA at a maximum voltage of 32V DC or AC RMS.

6058, p. 2-11


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Figure 2-8. Receiver Transistor Interface P.C.B.

6058, p. 2-12

UNION SWITCH & SIGNAL Y.J

The decoding logic on the Receiver Relay Interface P.C.B. is similar to that of the other interface boards. (Transmitter Opto and Receiver Transistor.) It automatically identifies which card slot the Relay Interface P.C.B. is in and provides a signal to the Receiver Housekeeping P.C.B. when it is addressed. Like the other interface boards, the qards address depends on which slot.it is plugged into.

The Receiver Relay Interface P.C.B. also contains a latch which samples the data on the bus when the data strobe ·signal from the Receiver Housekeeping P.C.B. occurs. The data is strobed to the relay outputs when the deliver signal from the Receiver Housekeeping PCB occurs. The two LED's on the PCB provide visual indication that the PCB is being addressed.

2.4 P.C.B. NECESSARY FOR REPAIRING TRANSMITTER OR RECEIVER UNITS

2.4.1 Servicing Transmitter Unit

The following known good printed circuit boards will be required~

Quantity

1 1

1

2.4.2

AC/DC Power Supply P.C.B. Transmitter Housekeeping P.C.B.

Transmitter Opto Interface

Servicing Receiver Unit

UN085719-100~ UN085721-1001 UN085721-1011 UN085722-1001 UN085722-1011

As Applicable

As Applicable

The following known good printed circuit boards will be required • ..

Quantity

1 1 1

1

AC/DC Power Supply P.C.B. Receiver Housekeeping P.C.B. Receiver Transistor Interface

P.C.B. Receiver Relay Interface P.C.B.

UN085719-1001 UN085723-1001 UN085724-100lj

UN085725-1001 As Applicable

Whenever a failure of the ADL-256 System occurs, the following troubleshooting table presents a starting point for repairing the system. Note, references to maintenance flow charts for repairing both the Transmitter and·Receiver Units are made in the troubleshooting table •. For those unaccustomed to flow charts, a description of the flow chart utilization can be found in the Appendix of this manual.

6058, p. _2-13

w UNION SWITCH & SIGNAL

Figure 2-9.

6058, p. 2-14

Receiver Relay Interface P.C.B.

2.5 TROUBLESHOOTING TABLE

SYMPTOM

A singular bit output inoperative (No errors or alarm received).

System inoperative (All outputs · disabled or not being updated) (System may be in alarm).

PROBABLE CAUSE

l. Output Indication· (Lamp) has burned out.

2. Output connection at the receiver location has been broken.

3. Input connection at transmitt-er location has been broken.

4. Malfunctioning input circuitry on one of the Opto Interface boards at the transm~tter location.

5. Malfunctioning output circuitry on one of the output interface PCB's at the receiver location.

6. Failure of Transmitter Unit.

7. Failure of Receiver Unit

1. System Power Supply failure at transmitter or receiver location.

2. Data carrier unit failure at Transmitting or Receiving Unit.

UNION SWITCH & SIGNAL tij

REMEDY

l. Replace indication lamp.

2. Determine output.connection for corresponding non-operational bit and repair.

3. Determine in-put connection for corresponding non-operational bit and repair.

4. Replace input Interface PCB corresponding to malfunctioning bit.

5. Replace output Interface PCB (Relay or Transistor) corresponding to malfunctioning bit output.

6. Use transmitter maintenance flow chart to determine malfunction.

7. Use Receiver maintenance flow chart to determine malfunction.

1. Replace suspect power supply with new unit.

2. Replace suspect carrier equipment

6058, p. 2-15


TROUBLESHOOTING_ TABLE cont'd.

SYMPTOM PROBABLE CAUSE . REMEDY

System operates but errors and/ or alarm indications are received.

6058, p. 2-16

3. External output indication power supply has failed.

3. Check output supply and repair as ~equired.

4. MODE SELECTOR switches 4. Place MODE SELECTOR switch on both the Transmitter

and Receiver Housekeeping PCB are not in the OPERATE position

ori both Transmitter and Receiver Housekeeping PCB in the OPERATE position.

5. Failure of Transmitter 5. See note at the end of this table. or Receiver unit.

6. Failure of Transmitter 6. Use Transmitter maintenance flow chart to determine malfunction.

unit.

7. Failure of Receiver 7. Use Receiver maintenance flow chart to determine malfunction.

unit.

1. MODE SELECTOR switches on both the Receiver and Transmitter Housekeeping P.C.B. are not in the OPERATEposition.

2. Number of interface boards at the Transmitter location does not agree with number of interface boards at ~he Receiver location or v:ice-versa.

3. Bit Rate switches on Receiver or Transmitter Housekeeping·P.C.B. 's are not in agreement.

1. Place MODE SELECTOR switch on both the Transmitter and Receiver Housekeeping P.c.B.'s in the OPERATE position.

2. Install or remove interface boa_rds at Transmitter or Receiver location until board numbers are equal at both Transmitter and Receiver.

3. Bit Rate switches should be in position as indicated on the front cover of unit.

UNION SWITCH & SIGNAL t),'j

TROUBLESH<X>TING TABLE cont'd.

SYMPTOM PROBABLE CAUSE

4. Address switches on Receiver or Transmitter Housekeeping PCB's are not in agreement

5. Loose connections between the PCBis and their connector.

6. Intermittant Data Carrier Unit.

7. Failure of Transmitter or Receiver unit.

8. Failure of Transmitter Unit.

9. Failure of Receiver Unit.

NOTE

REMEDY

4. Address switches should be in position as indicated on tag on front cover of unit.

5. Assure all PCB's are fully inserted into their connectors.

6. Replace suspect data carrier unit.

7. See note at the end of this table.

8. Use Transmitter maintenance flow chart to determine malfunction.

9. Use Receiver maintenance flow chart to determine malfunction.

A transmitter or receiver failure can be determined as follows:

6058, p. 2-17

t:i:j UNION SWITCH & SIGNAL

Maintenance personnel must be located at both the transmitter and receiver location with phone communications to conduct these tests.

1) Extract all interface PCB's from their connectors at both the receiver and transmitter unit.

2) Since the ADL-256 is a continuous scan system it does not depend on the number of interface PCBs installed in the system. The system should cycle just the receiver and transmitter housekeeping PCBs if there are no failures on either of these boards. The system should operate properly (no errors or alarms at the receiver) if the boards are good. If errors or an alarm is present, replace the housekeeping PCBs and check for proper operation. If the unit will not cycle correctly with just a ~ransmitter and receiver housekeeping PCB installed check the external data carrier equipment.

3) If the system operates properly with just the housekeeping PCBs installed, sequentially insert an interface PCB at both the transmitter and the receiver unit and allow the system to cycle. Continue this process until the insertion of a pair of interface PCBs causes the system to malfunction. One of the interface PCBs is detective. Replace the defective interface PCB and all other boards at both the transmitter and receiver unit. Allow the system to cycle, checking for proper operation.

6058, p. 2-18

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UNION SWITCH & SIGNAL w .

SECTION III

SYSTEM DESCRIPTION AND THEORY OF OPERATION

3.1 GENERAL

Both the ADL-256 Transmitter and Receiver Units are designed on a bus structure. An identical mother board assembly is used in both the Transmitter and the Receiver Unit. Also provided on the mother board assembly are programmed addresses for each of the interface boards in tne unit. Each connector for the interface board in the motherboard assembly is programmed with a different address. Interface board connector number one is programmed as slot zero, connector number two is programmed as slot one, etc. The final interface board connector is programmed as slot 15. These 16 slots (0 to 15) provide for 16 interface boards, each of which is capable of handling 16 inputs or outputs. This accounts for 16 ·x 16 or 256 bits of data.


The Transmitter Housekeeping board initiates a message based on.its internal timing on a periodic basis. The message duration is a function of .the system bit rate and the amount of data to be transmitted. (The number of interface boards plugged into the unit). The message format is a standard ASCII computer protocol. Until the Transmitter Unit receives a "Clear To Send" signal from the data carrier equipment, message synchronization (SYU) characters are transmitted. After receiving the "Clear To Send" signal, two more SYN characters are transmitted. Each SYN character is 8 bits in length. The SYN characters are then followed by an 8 bit start of text (STX) character followed by a station address. The station address consists of 16 bits total. It is a 4 bit address followed by.its complement followed by the complement of these first 8 bits.

The station address capability is switch selectable and provides added security to the message format. Until transmission of the station address, all address inputs to the interface boards have been disabled via the address disable bus. At this point the Transmitter Housekeeping Board begins sequentually· addressing each interface board in the unit. When addressed, the inputs to the interface board are enabled to an 8 bit data bus. Each interface board handles two groups of 8 inputs. The least significant address bit (20) determines which of the 8 bits of data is enabled to the data bus. When addressed,the interface board also provides a signal to the Transmitter Unit.to indicate there is a board present in that particular address slot. As each 8 bits of data are enabled to the bus they are transmitted serially followed by

6058, p. 3-1

\lJ UNION SWITCH & SIGNAL

their complement: 8 bits of data followed by 8 bits of complemented data. ·

When the Transmitter Housekeeping board does not receive a board present signal when it addresses the next slot in the unit, it terminates the message with an 8 bit end of text (ETX) character. At this point the message cycle is reinitiated •. The message format is shown in Figure 3-1.

Two other modes of operation other than the operate mode described for the Transmitter Housekeeping P.C.B. are provided via a mode switch. They are: St~ndby and Maintenance Modes.

3.2.1 Standby Mode

When in the Standby Mode, the Transmitter Housekeeping board provices a ~Request To Send" signal to the external data carrier equipment and provides a dotting output at the setting of the bit rate switch. This output is useful for setting up the data carrier equipment bias.

3.~.2 Maintenance Mode

The Maintenance mode of operation permits an operator to hand step through a system by using the TEST switch on the Transmitter Housekeeping P.C.B. Depending on the position of the COUNT switch (BIT or WORD) on the Transmitter Housekeeping board, each time the TEST switch is depressed the transmitter steps through 1 bit at a time (COUNT switch in B!T position) or 8 bits at a time (COUNT switch in the WORD position).

For details of the circuit timing of the Transmitter Unit consult Section V of this manual.

3.3 RECEIVER UNIT

After the Receiver Housekeeping P.C.B. receives a carrier detect signal from the data carrier equipment, it waits for the beginning of a message. The Receiver decodes the serial data input until at least two consecutive SYN characters are received. When at least two SYN characters followed by an STX (start of text) character are decoded, the next 16 bits of data must be the station address followed by its complement. The Receiver Housekeeping P.C.B., like the Transmitter Housekeeping P.C.B., incorporates a switch selectable station address switch. The Statipn Address switch setting must agree with the station address data being received for the message to· be accepted by the Receiver Unit. When a correct address is received followed

6058, p. 3-2

°' 0 U1 (X)

" 'O . w I

w

8 Bits 8 Bits 8 Bits 8 Bits 8 Bits 8 Bits 8 Bits 8 Bits 8 Bits

SYN SYN STX ADDRESS ADDRESS WORD O WORD O LAST WORD LAST WORD ETX SYN SYN STX ADDRESS

----" --r ' Any number of words Oto 30 followed by their complement

(An overall message cannot exceed 32 words)

Figure 3-1. Message Format

c z 0 z I ~ ::c .. 0 a z ):,,, ,...

E


by its complement, the Receiver Housekeeping P.C.B. begins to address the interface PCBs in the Receiver Unit. Each 8 bits of data received must be followed by 8 bits of complemented data. If no errors in the complement check are detected, the ~ bits of data received are strobed.to the addressed interface board. When the interface board is addressed,it provides a signal to the Receiver Housekeeping P.C.B. indicating there is an interface board in that address slot. When this signal is not received, the next 8 bits of data decoded must be an ETX (end of text) character. To complete the mess~ge, the ETX character must be followed by a SYN character. If at any time an error in the complemented data is encountered, the data strobe for the interface board does not occur and Receiver Housekeeping P.C.B. begins looking for the start of another message. (Two SYN characters followed by an STX character followed by the correct station address and its complement.) If any 3 consecutive messages are received in error, the Receiver Housekeeping P.C.B. goes into aiarm. A normally energized alarm relay is deenergized and provides a means of energizing an external system alarm indication. The Receiver Unit is also designed such that if no messages are received for a time equivalent to 2.7 full (256· Bits) message times, the unit goes into alarm. For the system to be removed from alarm, a complete message without any errors must be received. The Receiver Unit is capable of detecting the following error types:

1. Complement errors 2. Overcount errors - more data is transmitted

than the receiver expects. 3. Undercount errors - less data is transmitted

than the receiver expects. 4. Station address error 5. ETX character not followed by a SYN character

Two other modes of operation, other than the Operate mode described, are provided via the MODE SELECTOR switch on the Receiver Housekeeping P.C.B. They are the Standby and the Maintenance modes.

The Standby mode resets the Receiver Unit and disables the alarm output. The Maintenance mode allows the operator to hand step data into the receiver on a bit or word basis, using the TEST switch.

For details of the circuit timing of the Receiver Unit, consult Section V of this manual.

It should be noted that for proper system operation to occur, the following conditions must be met.

6058, p. 3-4

1. The Bit Rate switch on the Transmitter Housekeeping P.C.B. must agree with the Bit Rate switch on the Receiver Housekeeping P.C.B.


2. The Station Address switch on the.Transmitter Housekeeping P.C.B. must agree with the Station Address switch on the Receiver Housekeeping P.C.B.

3. The number of Interface boards plugged into the Transmitter Unit must agree with the number of ·interface boards plugged into the Receiver Unit •.

4. Frequency of the data carrier equipment at the Receiver Unit and its corresponding Transmitter Unit must be the same.

3.4 BLOCK DIAGRAMS FOR RECEIVER AND TRANSMITTER P.C.B.

The following block diagrams provide an indication of the circuitry on both the Transmitter Unit boards and the Receiver Unit boards. {See the following Block Diagrams Figures 3-2 thru 3-7.)

6058, p. 3-5

°' 0 u, co ...

tO

w I

m

REQUEST TO SEND+----

CLEAR TO SEND~

MODE SELECTOR 1. OPERATE 2. STANDBY 3. MAINTENANCE

MAINTENANCE SWITCHES

TTL7EIA INTERFACE (Request to Send & Clear to Send)

..

___. ....

POWER-UP

CIRCUITRY

• • (SYN,STX,ETX,

AND ADDRESS GENERATORS) CONTROL LOGIC

AND LED 'INDICATIONS

DRIVERS

~

H

CRYSTAL CONTROLLED

CLOCK AND BIT RATE SELECTOR

l

16 LED INDICA

TIONS

~

g~~ESS --~~~~~~~~~· us

WORD ADDRESSING

LOGIC

.

(5)

TTL/EIA CLOCKW OUTPUT CLOCK

INTERFACE OUTPUT

BOARD ·1 PRESENT

8 BITf DATA __... BUS INPUT

J,

MESSAGE PROTOCOL

AND ADDRESS GENERATION

..

--------~r------ -..,.. -, 1

• , : RELAY ,.,ri-'+ FLASHING i FLASHING ~ RELAY : OPTION t : OUTPUT

PARALLEL TO

SERIAL CONVERTER COMPLEMENT

.GENERATOR

I I > L I ------ ___ ....

1----111 TTL/EIA DATA OUTPUT INTERFACE

SERIAL DATA

H OUTPUT

Figure 3-2. BLOCK DIAGRAM TRANSMITTER HOUSEKEEPING P.C.B.

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.. 16 ISOLATED INPUTS ~

ADORES INPUTS

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•

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& 16 SURGE OPTICAL INPUT TRISTATE

PROTECTION OUTPUTS ISOLATORS FILTERING

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i

4

TRISTATE OUTPUTS

~

. .,. ON=PCB is

ADDRESS correctly DECODING addressed. LOGIC ..... ADDRESS OFF=PCB is not

.._ I ,,. INDICATION correctly .,.. LEDS addressed.

, . i

Figure 3-3. BLOCK DIAGRAM TRANSMITTER OPTO INTERFACE P.C.B.

. ~

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.

-

8 BIT DATA BUS OUTPUT

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CARRIER DETECT INPUT ___,.;i

SERIAL DATA ~ INPUT

MODE SELECTOR 1. OPERATE 2. STANDBY 3. MAINTENANCE

MAINTENANCE SWITCHES·

TTL/EIA INTERFACE

(Carrier Detect and Data)

BOARD PRESENT

POWER-UP

r---------'"'"".'--, I

CRYSTAL CONTROLLED

---.... CIRCUITRY ---I I I

CLOCK SYNCHRONIZATION

CIRCUITRY I .. CLOCK • AND BIT RATE

I I I I I

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CONTROL LOGIC AND

.LED INDICATION DRIVERS

SELECTOR

WORD J ADDRESSING 1-------.. LOGIC

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WORD ~DD RESS

BUS (5)

1----------------~-------. DATA STROBE

1--------------...,. DELIVER

l MESSAGE PROTOCOL DECODING

AND· ADDRESS AND

ERROR CHECKING LOGIC

16 LED ~INDICA

TIONS

--,-~ ALARM ALARM~ : ~~~iiT RLEAY ....

Jt. ..... ... _______ .,

... ...

SERIAL TO . ~a arr

PARALLEL · DATA CONVERTER OUTPUT

BUS

Figure 3-4. BLOCK DIAGRAM RECEIVER HOUSEKEEPING P.C.B.

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ID

DATA BUS INPUTS

(8)

ADDRESS INPUTS

(5)

ADDRESS DISABLE

BOARD PRESENT

OUTPUT

r

l

r l

~

ON=P C• a

OFF=P a

DATA STROBE

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. .

I

..

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ADDRESS DECODING LOGIC

' . 1 ..

ADDRESS INDICATION

LEDS

... .. .. . LATCH ,>

> . )

~ 4~

16 TRANSISTOR

OUTPUTS

--JI

LATCH • ..

Figure 3-5. BLOCK DIAGRAM RECEIVER TRANSISTOR INTERFACE P.C.B.

~

•

.... -. J TRANSISTOR OUTPUTS

•

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a

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(8)

.

..

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DATA STROBE T

ON=PCB cor add

OFF=PCB add

is ectly essed. is not essed.

~ ADDRESS t INPUTS . •

(5)

ADDRESS DISABLE --;

ADDRESS INDICATION LEDS

4" "'

ADDRESS DECODING LOGIC

BOARD PRE :ENT OUTPUT I ... ....

DELIVER

-

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")

.._:_____. .. .... , RELAY

DRrVERS • +

.... -- ......

16 LATCHING FORM C RELAY OUTPUTS

(Heels aused in Groups of 4)

WORD .. '!lo DRIVE ..... - BITS -

0-7

'1'

...... . WORD .... , , DRIVE

BITS 8-15

II\

Figure 3-6. BLOCK DIAGRAM RECEIVER RELAY INTERFACE P.C.B.

...... ,

...... ~ ., ....... ::::: ,

.... .::: .,

' ., ....... -

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120 VA, 60. Hz INPUT

c

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+12 voe .. LED " INDICATION

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- .. DIODE

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~ ,

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~ 12 voe ,

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c z 0 z I ~ Ill (It

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8

UNION SWITCH & SIGNAL \JJ

SECTION IV

L.E.D. INDICATIONS AND MAINTENANCE MODE

4.1 GENERAL

As a further aide in localizing problems at either a Transmitter or Receiver Unit, the ADL-256 has a maintenance mode of operation as well as light emitting diode (LED). indications for determining the status of the system. This section of the manual is intended to provide an explanation of the maintenance mode of operation and the meaning and usage of the LED indications at both the transmitter and receiver locations to isolate system faults.

4.2 TRANSMITTER UNIT L.E.D. INDICATIONS

The majority of LED indications at the Transmitter Unit are located on the transmitter housekeepinq printed circuit board. Figure 4-1 locates the LED's and switches on the Transmitter Housekeeping P.C.B. The following is an explanation of each of the LED indications on the Transmitter Housekeeping PCB.

1) Operate--This LED is illuminated only when the MODE switch on the Transmitter Housekeeping P.C.B. is in the OPERATE, #1 position. During normal operation this LED should be illuminated.

2) Request to Sen~--is illuminated to indicate a signal is being sent to the data carrier unit indicating the transmitter is ready to transmit data to the data carrier unit. During normal operation this LED should be illuminated.

3) Clear to Send--This LED is illuminated indicating that the data carrier unit has responded to the"request to send"signal,indicating it is ready to accept data for transmission. During normal operation this LED should be illuminated •.

4) Address Disable--This LED indicates the status of the address bus for the interface PCBs in the Transmitter Unit. When illuminated, no addressing of the interface PCBs can occur. This LED is normally illuminated when the control characters (SYN, STX & ETX} and the station address and its complement are on the data bus ready for transmission. This LED

6058, p. 4-1


MODE SELECTOR 1 OPERATE

Osio BY

3 MAINT

@ TEST

BIT

Q COUNT

WORD

Figure 4-1

LED INDICATIONS

OPERATE

REQUEST TO SEND

CLEAR TO SEND

ADDRESS DISABLE

TRANSMIT

LAST WORD

LOAD

DATA

BIT O

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

Transmitter Housekeeping P.C.B. LED and Switch Locations

6058, p. 4-2

UNION SWITCH a SIGNAL tt:J

4) Address Disable (continued)

5)

6)

7)

8)

9)

is not illuminated when the interface PCBs are being addressed and presenting their data to the data bus.

Transmit--This LED is illuminated when the first load pulse occurs. It indicates the information is being ·presente<t to the data carrier unit for transmission. · · This LED is illuminated during normal operation.

Lastword--This LED is illuminated when the lastword in the message has been transmitted apd the ETX character is being transmitted. In normal operation this LED is illuminated when the ETX character is on the data bus.

Load--This LED is illuminated when the load pulses occur. In norma! operation the.LOAD LED is illuminated every 8 clock pulses when the control characters are on the data bus and every 16 clock times when the station address and data are on the data bus.

Data--This LED is illuminated indicating the status of the serial data being transmitted (on = A "Logical l", off = A "Logical O")

Bit O through Bit 7--These LEDs indicate the status of the information on each line of the data bus at all times.

4.3 TRANSMITTER UNIT MAINTENANCE MODE OF OPERATION

The Transmitter Unit is in the maintenance mode when the mode switc-h on the Transmitter.Housekeeping P.C.B. is in position #3, HAINT. When in the maintenance mode, the Transmitter Unit can be hand stepped on a bit or word (8-16 Bits) basis. When the· TEST switch on the Transmitter Housekeeping.P.C.B. is depressed, the transmitter advances either 1 Bit or 1 Word (8-16 Bits) at a time depending on the position of the COUNT switch (Bit or Word). The following is a procedure for handstepping the Tra~smitter Unit through a message.

1) Place the MODE SELECTOR switch on the Transmitter Housekeeping P.C.B. in the MAINT position, Position 3.

2) Place the COUNT switch on the Transmitter Housekeeping P.C.B. in the WORD position.

3) The LEDs on the Transmitter Housekeeping P.C.B. should be illuminated as per truth Table 4-11. (SYN character is on the data bus.)

6058, p.· 4-3


4) Push the TEST switch and refer to truth Table 4-1 for the LEDs illuminated on the Transmitter Housekeeping P.C.B. (SYN character is on the data bus.)

5) Repeat Step 4.

6) Push the TEST switch on the Transmitter Housekeeping P.C.B. (STX character is on the data bus) refer to Table 4-1 for the LEDs illuminated on the Transmitter Housekeeping P.C.B.

7) Push the TEST switch on the Transmitter Housekeeping P.C.B. LEDs illuminated as per Table 4-1 and Table 4-2. (Station address in on the data bus.)

8) Push the TEST switch on the Transmitter Housekeeping PCB. The LEDs illuminated as per Table 4-1. Note the data bit LEDs, Bit Oto Bit 7, indicate the status of the inputs of Word O on the first interface PCB.

Continuing to push the TEST switch will advance the unit by 1 Word. The LEDs on the interface boards will be sequentually illuminated as they are addressed and the data of the addressed word is displayed on the data bus by the Bit LEDs. This permits the operator to handstep through each interface-board and observe the status of its inputs to the data bus.

9) When the last LED on the last interface PCB is illuminated, the last word of data will be on the data bus. Depress the TEST switch. LED on the

· Transmitter Housekeeping P.C.B. are illuminated as per Table 4-1. ·

10) Switch the COUNT switch to the BIT position.

11) Depress the TEST switch. LEDs on the Trarismitter Housekeeping P.C.B. are illuminated as per Table 4-1. (ETX character is on the data bus.)

12) Switch the COUNT switch to the WORD position. From this point the message repeats itself. Return to Step 4 to repeat the message.

6058, p. 4-4

Note at any time the status of the serial data can be observed on the DATA LED by placing the COUNT switch in the BIT position and pressing the TEST switch for each Bit of Information. Note during the address and data information each 8 bits will be followed by their· complement. Note the data displayed by the DATA LED is part of the previously addressed word, not the word being presently addressed (the information displayed by the DATA LED is 8 Bits behind the present data).

LED Indications

Operate

Req. to Send

Clr. to Send

Addr. Disable

Transmit

Last Word

Load

Data

Bit O

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

1 = ON

0 = OFF

X = DON'T CARE

Step Step 3 4&5

0 0

0 0

0 a l 1 0 1 0 0

0 0

x 0

0 0

1 l 1 1 0 0

l 1 0 0

0 0

1 1

Step Step· 6 7

0 0

0 0

0 a 1 1

1 1 Q. 0

0 0

0 x 0 See

Table 1 4-2

For 0 Bit

LEDs 0

0

0

0

1

.*Bit 7 is a "O" if Jumper Jl is installed.

TABLE 4-1

UNION SWITCH & SIGNAL 83 Step Step Step

8 9 11

0 0 0

0 0 0

0 0 0

0 0 1

1 1 .1

0 0 1 0 0 0

x 1 x LEDS 1 1 in die-ate 1 1 status of inputs

-i 0 to the

1 0 inter- I 0 face board being

1 o· ad- 1 dressed

0

1 l*

. 6058, p. 4-5


· STATION ADDRESS SWITCH (SWS) POSITION

LEDs 0 1 2 3 4 5 6 7 8 9 A B c D E F

Bit O 0 I 0 I 0 1 0 1 0 1 0 1 0 1 ·O 1 Bit 1 o- 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 - 1 I Bit 3 0 0 0 0 0 0 0 0 1 ·1 1 1 1 l· 1 1 Bit 4 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Bit 5 1· 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Bit 6 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Bit 7 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

1 = ON

0 = OFF

TABLE 4-2

6058, p. 4-6


In the WORD position of the COUNT switch the LOAD LED will be pulsed on each time the TEST switch is pushed. In the BIT position of the COUNT switch the LOAD LED will be illuminated every 8 pushes of the TEST switch when the control characters (SYN,STX and ETX) are being transmitted. The LOAD LED will be illuminated every 16 pushes of the TEST switch during the address and data information portion of the message.

4.4 RECEIVER UNIT LED INDICATIONS

The majority of the LED indications at the Receiver Unit are located on the Receiver Housekeeping P.C.B. Figure 4-2 provides the location of these LEDs on the Receiver Housekeeping P.C.B. The following is an explanation of each of the LED indications on the Receiver Housekeeping P.C.B.

1) Operate--This LED is only illuminated when the MODE SELECTOR switch on the Receiver Housekeeping P.C.B. is in the #lOPERATE position. During normal operation this LED should .be illuminated ..

2) Carrier Detect--This LED is illuminated indicating the carrier signal from the data carrier equipment is being received. This LED should be illuminated during normal operation.

3) Address Disable--This LED indicates the status of the address Bus for the interface PCBs in the Receiver Unit. When illuminated,no addressing of the interface PCBs can occur. This LED is normally illuminated when the control characters {SYN, STX AND ETX) and the station address and its complement are being received. This LED is not illuminated when the interface PCBs are being addressed and the received data is being delivered to its appropriate interface board for output.

4) Complement Check--This LED is illuminated when the complement check is being made on the station address and data information.

5) Data--This LED indicates the status of the incoming serial data (On= "Logical l", Off= "Logical O").

6) Last Word--This LED is illuminated after the last word of data has been received and the ETX character has been received.

6058, p. 4-7

\.lJ UNION SWITCH & SIGNAL

MODE SELECTOR

1 (\ OPE~TE

u STDBY.

3 MAINT.

TEST

BIT

Je)RD COUNT

tG)RK INPUT

SPACE

Figure 4-2

LED INDICATIONS

OPERATE

CARRIER DETECT

ADDRESS DISABLE

CO.t"'..PLE~!ENT CHECK

DATA

LAST I10RD

ERROR

ALARM BIT O

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

Receiver Housekeeping P.C.B. LED and Switch Locations

6058, p. 4-8

UNION SWITCH & SIGNAL ffi 7) Error--This LED is illuminated when an error has

been detected. The errors the Receiver Unit will detect are as follows:

a) Complement Error b) Station Address Error c) ETX Error d) ETX not followed by SYN Error e) Overcount Error f) Undercount Error

8) Alarm--This LED is illuminated when the Receiver Unit is in alarm. Alarm conditions are as follows:

a) Three consecutive messages received in error. b) No message received for 2.7 full (256 Bit)

message times.

9) Bit Oto Bit 7 LEDs--These LEDs are illuminated indicating the status of the information on the data output bus.

4.5 RECEIVER UNIT MAINTENANCE MODE OF OPERATION

The Receiver Unit is in the Maintenance mode when the MODE SELECTOR switch on the Receiver Housekeeping P.C.B. is in position #3, MAINT. When in the Maintenance mode the Receiver Unit can be hand stepped on a Bit or Word (8 Bits) basis depending on the position of the COUNT switch, BIT or WORD. The Receiver Unit will only accept data that is presented in the correct message format. Therefore it is necessary to input the control characters as well as the station address information on Bit by Bit basis. The following is a procedure for hand stepping a Receiver Unit through a message.

Note: IF AT ANY T!ME AN ERROR rs MADE IN ENTER!NG DATA TO THE RECEIVER UNIT, IT WILL BE NECESSARY TO RETURN TO STEP 3 AND BEGIN ENTERING DATA AGAIN AFTER SWITCHING THE MODE SELECTOR SWITCH TO THE STD-BY POSITION AND THEN RETURNING TO THE MAINT POSITION.

No activity will be observed on the Receiver Housekeeping P.C.B. until at least two Synch Characters {SYN) followed by a start of text (STX) character have been correctly entered. During the entering of the station address information, activity on the data bus Bit LEDs Oto 7 should be noted. If this does not occur, reset the Receiver Unit as above and begin re-entering data.

1) Place the MODE SELECTOR switch in the #3 MAINT position.

6058, p. 4-9


2) Place the COUNT switch on.the Receiver Housekeeping P.C.B. to the BIT position.

3) Using the INPUT arid TEST switches input the following 8 Bits of data (SYN character). Input is accomplished· by placing the INPUT switch in either the MARK or SPACE position and depressing the TEST switch to enter each Bit.

INPUT SWITCH POSITION

Bit 0 Space Bit 1 Mark Bit 2 Mark Bit 3 Space Depress TEST Switch Bit 4 Mark Once To Enter Each Bit. Bit 5 Space Bit 6 ·space Bit 7 Mark

LEDs on Receiver Housekeeping P.C.B. are illuminated according to Table 4-3.

4) Repeat. Step 3 •

. 5) Using the INPUT and TEST switches input the following 8 Bits of.data (STX character).


Bit 0 Space Bit 1 Mark Bit 2 Space Bit 3 Space Depress TEST Switch Bit 4 Space Once To Enter Each Bit. Bit 5 Space Bit 6 Space Bit 7 Mark·

LEDs on the Receiver Housekeeping P.C.B. are illuminated as per Table 4-3.

6) Using the INPUT and TEST switches input the following 8 Bits of Data (Station Address) as applicable per Table 4-4. The LEDs on the Receiver Housekeeping P.C.B.· are illuminated as per Table 4-3.

7) Using the INPUT and TEST switches input the following 8 Bits of data as per Table 4-5 (Complement Station Address)

6058, p. 4-10

The LEDs on the Receiver Housekeeping P.C.B. are illuminated as per Table 4-3.

*Bit

UNION SWITCH Ii SIGNAL tij

8) Note at this point the first word on the interface PCBs should be addressed. The LED on the first interface PCB corresponding to the first word should be illuminated. The receiver is ready to accept data at this point. The data can be hand stepped in on a Bit or Word basis. Each 8 Bits of data entered must be followed by its complement. (Note: At no time during the hand step procedure will the data entered be delivered to the outputs.) After entering the ~ighth Bit of Data Information, the COMPLEMENT CHECK LED will be illuminated and the Bit LEDs will display the last 8 Bits of Data entered. The 8 Data Bits are then followed by their complement. The COMPLEMENT CHECK LED will be extinguished when the last Complement Bit is entered. The Bit LEDs will display the data information entered. The next LED on the interface PCBs will be illuminated.

This procedure can be continued to address each interface PCB in the Receiver Unit.

After the last word of data followed by its complement has been entered, the last LED on the last interface PCB will extinguish. At this point the receiver is looking for an End of Text (ETX} Character.

9) Place the COUNT switch in the BIT position.

10) Using the INPUT and TEST switches, input the following 8 Bits (ETX Character).


Bit 0 Mark Bit 1 Mark Bit 2 Space Bit 3 Space Depress TEST Switch Bit 4 Space Once To Enter Each Bit. Bit 5 Space Bit 6 Space Bit 7 Mark*

7 is to be entered as a space if Jumper Jl is installed.

LEDs on Receiver Housekeeping P.C.B. are illuminated as per Table 4-3. The ETX Character must be followed by a SYN Charact"er to extinguish- the LAS-T WORD ·-LED.

11) Using the INPUT and TEST switch, input the following 8 Bits -(SYN Character}.

6058, p. 4-11


Bit O Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7


Space Mark Mark Space Mark Space Space Mark

Depress TEST switch Once To Enter Each Bit.

From this point the message is complete and a new message can be hand stepped into the receiver from Step 4.

NOTE: AT NO TIME DURING THE HAND STEP PROCEDGRE WILL THE DATA ENTERED BE DELIVERED TO THE OUTPUTS.

At any time after the beqinning of message format (SYN, SYN, STX) has been entered, an error can be entered and the ERROR LED on the Receiver Housekeeping P.C.B. should be illuminated. The ERROR LED will be illuminated immediately when a complement error occurs, but during the address or control character portion of the message only after the entire character has been entered in error. When an error occurs, the receiver begins looking for the beginning of a new message (two SYN followed by an STX character). The ERROR LED will be extinguished when the first Bit of the STATION ADDRESS is entered. Any 3 consecutive messages entered with errors will illuminate the ALARM LED. The Alarm Relay will not drop in the maintenance mode even througn the ALARM LED is illuminated. The ALARM LED will be extinguished only when an entire good message is received.

SYN-SYN-STX-ADDRESS-ADDRESS-WORD 0-WORD 0--------LAST WORD-

LAST WORD-ETX-SYN-----------

The ALARM LED will be extinguished when the last bit of the SYN Character following the ETX Character is entered.

6058, p. 4-12

UNION SWITCH & SIGNAL m

LEO Steps 3,4,S Step 6 Step 7 Step 8 Step 10

Operate 0 0 0 0 0 Carrier 0 0 0 0 0 Detect

Addr. Disable 1 l· 0 0 1 Comp. Check 0 1 0 l* 0

Data x x x x x Last Word 0 0 0 0 1 Error 0 0 0 0 0

Alarm 0 0 0 0 0 Bit LEOS Bit LEDs

Bit 0 0 0 are illu- are illu- x minated minated

Bit: 1 0 1 according according x to the to comple-

Bit 2 0 0 station ment of x address the statio:q.

Bit 3 0 0 entered address x ente.ied,.

Bit 4 0 0 x See Table See Table

Bit 5 0 0 4-4 4-5 x Mark=On Mark=On

0 0 --· ·X Bit 6 Space=Off Space=Off or the

Bit 7 0 1 last 8 Bits of

x Data Entered

*See Text Step 8, pg. 4-11

I= ON

0 = OFF

x = DON'T CARE

TABLE 4-3

6058, p. 4-13


*Station INPUT SWITCH POSITION(DEPRESS TEST SWITCH TO ENTER EACH BIT, Address Switch(SW6} Position Bit O Bit 1 Bit 2 Bit 3· Bit 4 Bit 5 Bit 6 Bit 7

0 Space Space Space Space Mark Mark Mark Mark

1 Mark Space· Space Space Space Mark Mark Mark

2 Space Mark Space Space· Mark Space Mark Mark

3 Mark Mark Space Space Space Space Mark Mark

4 Space Space Mark Space Mark Mark Space Mark

5 Mark Space Mark Space _Space Mark Space Mark

6 Space Mark Mark Space Mark Space Space Mark

7 Mark Mark Mark Space Space Space Space Mark

8 Space Space .Space M~rk Mark Mark Mark Space

9 Mark Space Space Mark Space Mark Mark Mark

A Space . Mark Space Mark Mark Space Mark Space

B Mark Mark Space Mark Space Space Mark Space

c Space Space Mark Mark Mark Mark Space Space

D Mark Space Mark Mark Space Mark Space Space

E Space Mark Mark Mark Mark Space Space Space

F Mark Mark Mark Mark Space Space Space Space

REFER TO TBE TAG ON THE !NS!DE COVER OF THE UNIT AND. DETERMINE THE STATION ADDRESS SWITCH POSITION AND ENTER DATA FROM THE ABOVE TABLE AS APPLICABLE.

Station Address Bits TABLE 4-4

I

*NOTE: THE STATION ADDRESS IS IN HEXADECIMAL FORM. NUMBERING IS FROM OTO F. FOR THOSE UNFAMILIAR WITH THE HEXADECIHAL NUMBERING SYSTEM, REFER TO THE APPENDIX.

6058, p. 4-14

UNION SWITCH & SIGNAL w *Station INPUT SWITCH POSITION(DEPRESS TEST SWITCH TO ENTER EACH BIT) Address Switch (SW6) Position Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

0 Mark Mark Mark Mark Space Space Space Space

1 Space Mark Mark Mark Mark Space sp·ace Space

2 Mark Space Mark Mark Space Mark Space Space

3 Space Space Mark Mark Mark Mark Space Space

4 Mark Mark Space Mark Space Space Mark Space

5 Space Mark Space Mark Mark Space Mark Space

6 Mark Space Space Mark Space Mark Mark Space

7 Space Space Space Mark Mark Mark Mark Space

8 Mark Mark Mark Space Space Space Space Mark

9 Space Mark Mark Space Mark Space Space Mark

A Mark Space Mark Space Space Mark Space Mark

B Space Space Mark Space_ Mark Mark Space Mark

c Mark Mark Space Space Space Space Mark Mark

D Space Mark Space Space Mark Space Mark Mark

E Mark Space Space Space Space Mark Mark Mark

F Space Space Space Space Mark Mark Mark Mark

USE THE ABOVE TABLE TO ENTER THE COMPLEMENT OF THE STATION ADDRESS AS APPLICABLE.

*See note on Table 4-4

·complement

Station Address Bits Table 4-5

6058, p. 4-15

UNION SWITCH & SIGNAL QJ

SECTION V

SHOP MAINTENANCE

5.1 GENERAL

This section is provided as a guide to the Shop Maintenance--· Technician in test and repair of· the printed circuit boards of the ADL-256 System. A circuit diagram as well .as a printed circuit board layout for locating components and test points is provided for each printed circuit board. A circuit_ description, flow charts and timing diagrams where applicable are provided as an aid in determining correct operation of the ADL-256 Printed Circuit Boards. ·

_A description of various circuit logic symbols is provided in the Appendix for aid in interpreting the circuit diaqrams.

NOTE: ALL LOGIC ON -THE ADL-256 PRINTED CIRCUIT BOARDS IS CMOS TYPE, THEREFORE CARE MUST BE TAKEN IN HANDLING AND REPAIRING THESE BOARDS. IT IS SUGGESTED THAT IF THE TECHNICIAN IS UNFAMILIAR WITH CMOS CIRCUITRY, THE DEFECTIVE PCB's SHOULD BE RETURNED TO THE MANUFACTURER FOR REPAIR. REFER TO THE APPENDIX FOR HANDLING CONSIDERATIONS FOR CMOS CIRCUITRY.

5.2 CIRCUIT DESCRIPTION AC/DC POWER SUPPLY P.C.B

Figure 5-1 and 5-2 are the component and parts location and circuit diagram of the AC/DC Power Supply P.C.B. The AC input to the power supply P.C.B. is on pins 3&C an<;l 6&F of the "A" connector. ON-OFF switch SW-1 controls the AC input to Tl. Fl provides overcurrent protection, while MOV 1 (Metal Oxide Varistor) provides protection for Tl from line transients. Tl provides voltage step.down to 36 VAC. Capacitors C2 and C3 provide protection for the diode bridge D3, 4, 5, and 6 from· power line spikes and also reduces R.F.I. of the bridge rectifier commutating transients. The output of the bridge rectifier is filtered by capacitors C4 and CS to reduce the ripple content. The unregulated positive and nega~ive voltages are then fed to their respective voltage regulators. The positive voltage regulator will be described. The positive voltage is supplied to the collector of Q3 via fuse F2, and an external jumper between pins 6 and 7 of the "B" connector. Q3 the series pass output transistor is controlled by QS.. The voltage reference is· established by zener diode D?·in the emitter of QS. The required voltage at the pase of QS will be equal to VD7 + VBE and is provided by voltage divider R7, Rl6 and Rl7. Rl6 is adjusted to provide a regulated output of 12 voe. Any tendency for a drop in regulated voltage output results in a reduction

6058, p. 5-1


in base drive current to Q5. The subsequent reduction in collector current of Q5 provides increased base drive to Q3 via R9. This action decreases the effective series resistance of Q3 and maintains the output voltage at its pre-set level. Any tendency for a rise in regulated voltage output, produces the same reaction except the current changes described are in the opposite direction. Capacitors ClO and Cl2 improve the regulators transient response and reduce high frequency noise output.

Fold back current limiting is utilized in the plus 12 voe regulator. Current limiting action occurs at approximately 700 milliamps. As the load current increases above this point the output current will decrease, reaching a final value of approximately 27o·milliamps. At the current limit point, Q4 turns on and controls the series pass transistor Q3 by limiting its base drive. The current limit thresbold is controlled by R8, Rl2, RlO, Rll and the VBE of Q4. Foldback action is provided by RIO, Rll. The negative 12 voe regulator is identical to the positive 12 voe regulator except that it does not incorporate foldback current limiting since the maximum current output is 200 milliamps.

Two identical voltage clamp circuits are present on the power supply P.C.B., one for the positive 12 voe output and one for the negative 12 voe output. The positive voltage clamp will be described, the circuit consists of a unijunction level detector which supplies a firing pulse to the gate of a thyristor. The thyristor essentially shorts the output of the regulator. The firing point is adjusted by voltage divider R2, R3 and R4. Adjustment is made at final board checkout to a level of approximately 13.75 voe. Under normal conditions, capacitor Cl3 will charge to a voltage dependent on the intrinsic stand off ratio of Ql and the adjusted clamping voltage level. Zener diode 01, clamps the base of Ql to a level of 12 voe. When overvoltage conditions occur, the voltage level at the emitter of Ql will increase to the firing level of Ql. At this point Cl3 will be discharged into the gate of Q2. Q2 will effectively short the output of the voltage regulator. Power must be removed to reset the circuit. Note: Firing of the overvoltage circuitry may or may not clear the associated regulator fuses depending on the type of circuit failure which has occurred.

6058, p. 5-2

I

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I a, C111+ :: ,i:.., ...._-----.;..:o.a-•,• ~a:.}:.1 410 ·: :'.1. - ~ L ___ J RH ( y~~~-

UI ~ 470

._ __ ._ ____ ... -----~~~v·~:f\-~cN~:o,.i----'1---J Ul'lllo •6.t\lOC 110 :t> ,,..

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AI.L CCIIPONOtTS ..,.. All« ON PIC81 UNLESS NOTED!

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T~ .~!. 4 Rl5 Cl4

4T T ·-···~~~....o"""'-------------... -,---... -------< .... --... --.. ----'

Figure 5-1. AC/D~ Power Supply Circuit Diagram

AC/OC P()ll{R 9.JPPL Y P.C.B. CIRQJIT DIAGRAM

WABCD ~ ---o

11771

fiSIWWW ·-CIIIIPMY 1111111 SIIITCII l SIIUl lllfflllll -- ...


6058, p. 5-3/5-4

°' 0 u, CX) .. 'tl • u, I

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lDOL·&lLS80Nfl OH ~ A lddflS 113MOd :JO/ :JV ON

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Figure 5-2. AC/DC Power Supply Components & Parts Location

c z 0 z I ~ :c ... 0 c5 z > r

E

W . UNION SWITCH & SIGNAL

Component Symbol

Cl - C3 C4 - CS C6 C7 ca C9 - ClO Cll Cl2 Cl3 -·Cl4

Dl - 02 03 - 06 D7· - 08

Fl F2 F3

LD1-LD2

MOV-1

Ql Q2 Q3 Q4 - Q5 Q6 Q7 Q8 Q9 - QlO

6058, p. 5-6

AC/DC POWER SUPPLY COMPONENTS & PARTS LOCATION

REFER TO FIGURE 5-2

Description

Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor

0.1 mfd. ±20%· MYLAR 2300 mfd. EXTRALYTIC 0. 01 rnfd. ±10% CERAMIC 0.1 mfd. ±20% MYLAR 0. 01 rnfd. ±10% CERAMIC 100 rnfd. ±10% TANTALUM 0.1 rnfd ±20% MYLAR 0.47 mfd. 200V MYLAR . .

Diode 1N4742A Diode 1N4003 Diode 1N5234B

Fuse 0.5 Amp. SLO-BLO, Fuse 2 Amp. 3AG Fuse 1 Amp. 3AG

LED HP5082-4415

Varistor Vl30LA20B

Transistor 2N4852 Thyristor Cl06Bl Transistor MJlOOO Transistor 2N3904-5 Transistor MJ900 Transistor 2N4852 Thyristor Cl06Bl Transistor 2N3906-5

3AG

,.-··

UNION SWITCH & SIGNAL m AC/DC Power Supply Components & Parts Location (Figure 5-1) cont'd)

Component Symbol Description

Rl Resistor 270fl 5% R2 Resistor 2.7KO 5% R3 Resistor Var. 2KQ l/2W R4 Resistor 6.8KQ 5% RS Resistor 2700 5% R6 Resistor 470 5% R7 Resistor 2.7KO 5% R8 Resistor 5.60 5% R9 Resistor 2.2KO 5% RlO Resistor 2.2K05% Rll Resistor 2700 5% Rl2 Resistor 5.60 5% Rl3 Resistor Var. 2KO l/2W Rl4 Resistor 4700 5% RlS Resistor 2.7Kfl 5% Rl6 Resistor Var. 2KO l/2W Rl7 Resistor 4.7KO 5%

. Rl8 Resistor 2.2KO 5% Rl9 Resistor 5.60 5% R20 Resistor 2700 5% R21 Resistor 2.7KO 5% R22 Resistor Var. 2KO l/2W R23 Resistor 6.8Kfl 5% R24 Resistor 21on 5% R25 Resistor 470 5% R26 Resistor 4.7Kn 5% R27-R28 Resistor 2.2KO 5% R29 Resistor 21on 5% R30 Resistor 5.6n 5% R31 Resistor 470n 5% R32-R35 Resistor 1500 5%

SWl Switch Micro SW #8Gl014A

Tl Transformer Signal #247-7-36

*All Resistors Carbon Type Unless Otherwise Noted.

*All Resistors 1/4 Watt Unless Otherwise Noted.

6058, p. 5-7


5.3 CIRCUIT DESCRIPTION TRANSMITTER HOUSEKEEPING P.C.B.

The following text is intended to be read while referring to the following Figures: .

a) Figure 5-3, Circuit Diagram of the Transmitter Housekeeping P.C.B.

b) Figure 5-4, Transmitter Housekeeping Logic Timing Diagram

c) Figure 5-5, Transmitter Housekeeping Logic Flow Diagram

d) Figure 5-6, Transmitter Housekeeping Components and Parts Location

5.3.1 Power-Up Circuitry

Transistor Q7 and its associated circuitry (Dl, 038, R75, R76, R64 and ClO) form the power up circuit for the Transmitter Housekeeping P.C.B. As the input voltage rises to the level established by voltage divider R75 and R76 and zener diode Dl (approximately 7 to 8 volts DC) transistor Q7 charges capacitor ClO through R~4. This output is fed to a schmitt trigger circuit (IC22 and resistors R69 and R70) which gives a fast rise time output when its switching threshold is reached. Note when switching between any mode position of switch SW!, the power up circuitry prov.ides a reset through IC20, 037 and R72 for the circuitry of the Transmitter Housekeeping P.C.B.

5.3.2 Clock Circuitry

The clock circuitry is located in the upper right hand section of the circuit diagram. One stage of IC14 and its associated components R42, R43, C7, CS, C9 and Yl comprise the oscillator circuit. The frequency of oscillation is determined by crystal Yl. The frequency is 2.457600 MHz. Trim capacitor CS provides adjustment of the frequency. The oscillator stage of IC14 is decoupled by Cl2 and R90. The remaining stages of IC14 are used to buffer and square up the output of the oscillator stage. The 2.457600 MHz signal at TPl is fed into !Cl~ a seven stage ripple counter. The output at pin 3 of IC13 is 19.2 KHz. This output is fed to IC21, another 7 stage ripple counter. Bit rate selector switch SW4 selects the various output stages of IC21, providing for Bit rates of 75, 150, 300, 600, 1200 or 2400 bits per second. Note the output at TP6 is twice the setting of bit rate switch SW4. 1/2 of IClO (Bit Flip-Flop) provides the additional division to achieve the actual bit rate.

6058, p. 5-8

UNION SWITCH a SIGNAL {lJ

5.3.3. Bit Count and Load Circuitry

The clock output of IClO (Bit Flip-Flop) feeds IC~ a 7 stage ripple counter (Bit Count). Outputs Ql, Q2 anq Q3 of IC4 are decoded by IC3 and provide a toggle signal for load FlipFlop, IC9, every 8 or 16 clock pulses. The toggle signal for the load flip-flop occurs every 8 clock pulses until the ~eset to ICll (8/16 flip-flop) is removed. Load.pulses then occur every 16 clock pulses until ICll ·is reset again. During normal operation the load pulses occur -every 8 clock pulses when the message format characters (SYN, STX, and ETX) are -on the data bus, and the load pulses occur every 16 clock pulses when the address information or data is on the data bus. When the data information is to be transmitted, the reset on IC16 (Word Count) a 7 stage ripple counter,is removed. The outputs of IC16 are buffered by IC22 and provide the address inputs for the interface boards in the Transmitter Unit. IC16 is clocked by each

load pulse to advance it to the next address.

5.3.4 Control Character Generation for Message Format

Th.e input data bus is_ comprised of pins A through J on the "B" connector. All lines on the data bus are normally at a high (Logical 1) level, being pulled up by resistors Rl3 through R20. The various control characters and the address for the message format are generated by pulling appropriate lines to a low (Logical 0) level. The first control characters in the message format are the SYNCH (SYN) characters and the start of text (STX) character. The SYN character is generated by 1/2 of IC19 (SYN I), 1/2 of ICll (SYN II), 1/2 of IC3, 1/6 of IC5 and diodes 021 through 024. The output of IC5 (Pin 4) is held at a low level while !C's 19 and 11 are held reset. When the reset is removed from IC5, IC19 is toggled by the next load pulse. After two load pulses,.the output of IC5 will switch to a high level and the SYN character will be removed from the data bus. The addition of 1/4 of IC2, 1/6 of IC15 and diodes 015 througn 020 generate the STX character at this point_. The STX character will be removed from the data· bus when the next load pulse occurs (8 clock pulses later). The address portion of the message format is generated by 1/2 of IC18 (address flip-flop), 1/4 of IC12, 1/6 of IC15, and Address switch SW5. SW5 is a Hexadecimal switch that provides for 16 different address states (0 through F)*. (Note at this point load pulses begin occurring every 16 clock pulses until. the end of the message occurs). The end of message character, ETX (End of Text) is generated by last word Flip-Flop IC9, 1/6 of IC15, and diodes 09 through 014 (014 is a jumper option, Jl~ All control° characters, SYN, STX, and ETX are transmitted with even parity when this jumper is in, otherwise the control characters are transmitted with their last bit always a "l").

*For those unfamiliar with Hexidecimal refer to the Appendix of this manual.

6058, p. 5-9


After the last load pulse qccurs the last word flip-flop, !C9 is reset and a new message begins. The las~ word flip-flop can be set under two conditions. They are: (1) When the board present signal is not received (at a low level) indicating there is not interface board in the slot presently addressed by the transmitter. (2) When the Q6 output of IC16 goes to a high level indicating a full system, 32 words of data, has been addressed.

5.3.5 Parallel to Serial Conversion Circuitry

inputs to the Transmitter Housekeeping P.C.B. are in an .8 bit parallel form. Parallel to serial converter IC23 accepts the data in parallel from the data bus when a load pulse occurs. The data is shifted out serially, on a bit by bit basis during each clock pulse. One-sixth of I24 complements the data output and feeds it into the parallel to serial converter IC23, to generate the complement of the data and address information. Every 8 bits of data and address information is followed by its complement.

5.3.6 Data Carrier Interface Circuits

Four interface circuits are provided on the Transmitter Housekeeping P.C.B. They are the Request To Send Output, Clear To Send Input, Clock Output, and Data Output interfaces. Each output interface circuit.is optically isolated and provides voltage output swings of ±5 VDC for EIA interfaces or swings from 0.0 VDC to +5 VDC for TTL interfaces. The Request To Send Output is on at +5V and off at -5V for an EIA !nterface. (+5 on and O.OV off for TTL.) The Data Output is in the mark state at -5VDC and in the space state at +5 VDC for an EIA interface. (OV for ~rk, +5V for Space for TTL). The Clock Output is at +5 VDC for a logical 1 and at -5 VDC for a logical O for an EIA interface (+5V for Logical 1 and OV for Logical O for TTL). Reference voltages for all the interface circuits are established by diodes D2, D3 and D4 and their associated components. (R2, R4 and D42.) The TTL references are established by jumpering pin 18 and V to pin 16 and Ton the "A" connector.

The Clear To Send Input is also optically isolated and will accept only EIA voltage levels. Plus 5 VDC corresponds to the Clear To Send "on", while -5VDC corresponds to Clear To Send "off". Hysterisis is provided by resistor R83 and capacitor Cll in the Clear To Send input circuit. The Clear To Send function remains in the state it was last in (on or off) even when its input is removed.

6058, p. 5-10

FUl.085721-2000 TRANSMITTER HOUSEKEEPING CIRCUIT DIAGRAM

I• Of'PAff 1. ST,UIIOfff >• »A1hTOIMI«

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Figure 5-,3.

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9'9P ¥IP

"-• "~alt

... .... .. .. r-:.--f-----~--~---,~-'l ......... ~-?YOO

¥~~··· ··-.. uaer-~ v .. ~

I I I I I I I I

Circuit Diagram of Transmitter Housekeeping PCB


6058, p. 5-11/5-12

'----- RANOOM 81TS ------

Figure 5-4.

LASf WORO -+--~ ·I·

CAPA1'A81LITY o TO ,o IIOROS

0

"

'''I'' 'T' ---- ... ,- ..... -·- .. --- .... ·---___ ._ .......... .... -· ... -·-·-.. --... -----__ .. _____ _ ·-·---·-·-·--

r--~•'f'l-•rtf.n.AT( POINT@)

NOTES: J • WOADS O THROUGH LAST WORD

CAN ti[ ANY t;ONDINATtON Of' I 81TS F'Ol.LOJl'E(' llilY THEIR RESP£CTIV£ COWLEUE:Nr

APPLICAT ICJ.I & CHARACTERISTIC owG•s FOR AOL-256 DATA

TRANSMJSSICJ.1 SYSTEM

~~~~l,!J,!S!!!!~L-J:..:.'.LJL::l::..J"'-"'=--,-;-~--I

Transmitter Housekeeping Logic Timing Diagram

6058, p. 5-13/5-14

'-----I DOT - DOT

ADDRESS DISABLE -· WORD COUNT -o lal~.i&Ti ::~ COT -o T"""3MIT -o R!:SE"T -1 TEST REQ -o

R£QU£ST

TO SEND -1

CLOCK-CLOCK

+1

RESET - O

I I I I I I I I I I I I

,----_J I I I I I I I I I I

_J

'60RD COUNT -WORD COUNT + I

DATA eusWORD ADDRESSED

....

DATA BUS -ETX

DATA BUS

-•m

TRANSMIT -1

REQ TO SEffD -·

ATA nus--- STX

DAT,. BUS -T,.T ION ,.DDRES

14-----1

DATA aus- SYN

N

BIT COUNT --

BIT COUNT +I

SIT 7-

iTfo

LOAD .-I

CLEAR TO SEND

CLEAR TO SEND

INPUT

DATA BUS

SYN

BIT COUNT

BIT COUNT +1

LOAD -o BfT COUHT-O TEST REQ -o BITS 0-7 -

D1'TA BUS

Figure 5-5. Transmitter Housekeeping Logic Flow Diagram

N

y

..

BIT COUNT

BIT COUNT +1

LOAD -o BIT COUNT-0 TEST REQ.-0 BITS 0-7 -

o ... r,. BUS

RETURN

BIT CQJNT

SIT COUNT +1

LOAD -o BIT COUNT -o TEST REQ -o BITS 0-7 -

OAT.A BUS

TEST MQ -1

y

BIT COUNT

BIT COUfCT +1

TEST MQ -o

TRANSMITTER. HOUSEKEEPING UIJOe5721-1001 LOGIC FLO'W Dll'.GfV'J"\

10-7-75

. ,_,.

APPLICATION 8:. CHARACTERISTIC DWGS. FOR ADL-25G DATA TRANSMISSION SYSTEM

COOtl 1011"1' ... 1()/'•L?t •m•


6058, p. 5-15/5-16

O"I 0 U1 00 ...

"O

U1 I

...... ...J

.. .. .. :::. e:::. e::. . ; .. .::;

Figure 5-6.

.. e:. .. ..

•: ·=-c, ~ ·~ ·= ~ ~ •; ·= ...

eg ..,

e:; "' .. es •~ ••

•• •• "?l •

• fl . LJ ......

• :I::! • 025

•• ::r:::: em •::r::::•021 11111111 . . . . J SW! e C:::: • R38 ~- __._. e ::::J eR39

Transmitter Housekeeping Components and Parts Location

(

• s • ( ::l Q G c ;;; ) r

I


Component Symbol

Cl C2 - C4 CS - C6 C7 ca C9 ClO Cll Cl2

Dl - 03 04 - 042 043-45 LED

!Cl - IC2 IC3 IC4 ICS IC6 IC7 IC8 IC9 - ICll· IC12 IC13 IC14 IC15 IC16 IC17 IC18 - IC19 IC20 IC21 IC22 IC23 IC24 IC25 - IC26 IC27 IC28 IC29 - IC32

6058 I P• 5-18

TRANSMITTER HOUSEKEEPING P.C.B. COMPONENTS & PARTS LOCATION

REFER TO FIGURE 5-6

Description

Capacitor 0.001 mfd. SOOV CERAMIC Capacitor 4.7 mfd. 35VTANTALUM Capacitor 0.001 mfd. 3000V CERAMIC Capacitor 43 Pfd. SOOVMICA Capacitor 8-35 Pfd.VARIABLE Capacitor 56 Pfd. 300V MICA Capacitor 4.7 mfd. 35V TANTALUM Capacitor 0.001 mfd. SOOV CERAMIC Capacitor 1.0 mfd. 35V TANTALUM

Diode, Zener 1N5231B Diode, 1N914B Diode 1N4007 Diode, LiQht Emitting HP5082-4415

IC MC14049Cl or Equiv. IC MC14012CL or Equiv. IC MC14024CL or Equiv. IC MC14049CL or Equiv. IC MC14011CL or Equiv. IC MC14027CL or Equiv. IC MC14011CL or Equiv. IC MC14027CL or Equiv. IC MC14011CL or Equiv. IC MC14024CL or Equiv. IC MC14007CL or Equiv. IC MC14050CL or Equiv. IC MC14024CL or Equiv. IC MC14011CL or Equiv. IC MC14027CL or Equiv. IC MC14049CL or Equiv. IC MC14024CL or Equiv. IC MC14050CL or Equiv. IC MCi4014CL or Equiv. IC MC14049CL or Equiv. IC MC14011CL or Equiv. IC MC14024CL or Equiv. IC MC14027CL or Equiv-. Optical Coupler 4N27

TRANSMITTER HOUSEKEEPING P.C.B.

Component Symbol

Ql-Q4 Q5-Q6 Q7-Ql0 Qll

Rl R2 R3 R4 R5-Rl2 Rl3-R28 R29 R30-R37 R38-R39 R40 R41 R42 R43 R44-R45 R46 R47 R48 R49 R50-R53 R54-R57 R58-R59 R60-R61 R62-R68 R69 R70-R71 R72-R73 R74 R75 R76-R77 R78 R79 R80 R81 R82 R83-R84 R85 R86 R87 *All Resistors

COMPONENTS & PARTS LOCATION REFER TO FIGURE 5-6 (Continued)

Description

Transistor 2N3906 - 5 Transistor 2N3904 - 5 Transistor 2N3906 - 5 Transistor 2N3904 - 5

Resistor 1oon l/2W Resistor lK n l/4W Resistor 1oon l/2W Resistor lKn l/4W Resistor 2.2Kf2 l/4W Resistor Network lOOK Resistor 100Kf21/4W Resistor 2.2KQ l/4W Resistor lOOKn l/4W Resistor 12K f21/4W Resistor lOOKn l/4W Resistor lSMeg.n l/4W Resistor 12Kn 1/4W Resistor 2.2Kn 1/4W Resistor 12K(2 l/4W Resistor 2.2Kn 1/4W Resistor 12Kn 1/4W Resistor 2.2Kn 1/4W Resistor 270n l/2W Resistor 4.7Kn 1/4W Resistor 47n l/2W Resistor lKn l/4W Resistor lOOKn l/4W Resistor 15 Meg.U 1/4W Resistor 1 Meg.U l/4W Resistor 2.2KU l/4W Resistor 4.7KU l/4W Resistor 2.2KU l/4W Resistor 12KU l/4W Resistor 2700 1/2W Resistor 2.2KU 1/4W Resistor 41n 172w·· Resistor 4.7KU l/4W Resistor lKU l/4W Resistor lOKn l/4W Resistor lOOKU 1/4W Resistor 47KU l/4W Resistor 47Kn 1/4W

Carbon Type Unless Otherwise Noted.

Ul'flUl"l l:lffl ''-" ta l)IUl'fAI. ,,,,..,.

6058, p. 5-19

\,LI UNION SWITCH & SIGNAL

Component Symbol

R88 R89 R90

RLY-1

SWl SW2 SW3 SW4 SW5

Yl

TRANSMITTER HOUSEKEEPING P.C.B. COMPONENTS & PARTS LOCATION

REFER TO FIGURE 5-6 (Continued)

Descriptiqn

Resistor, 270 Q l/2W Resistor, lOOK Q l/4W Resistor 100 Q l/4W

Relay #AWCM-16151-1 ADAMS-WESTLAKE

Switch, 3 Position GRAY HILL# 9P60-0l-1-3N Switch, Pushbutton (Black cap) C&K #8125-RS3 Switch, Toggle C&K #7101 M D9 AB Switch, Dip DAVEN #llllAA Switch, Hex Code AMP #531137-1

Crystal, ERIE 2.457600 MHZ

* All Resistors Carbon Type Unless Otherwise Noted.

6058, p. 5-20

UNION SWITCH a SIGNAL '1JJ

5.3.7 Test Circuitry

IC's 6, 7 and 8 along with switches SW2 and S3 and MODE SELECTOR switch SWl provide for testing of the Transmitter Unit. When SWl is in the Maintenance mode, depressing the TEST switch SW2 handsteps the Transmitter Housekeeping P.C.B. through, on a bit by bit or word by word.basis, depending on the position of the COUNT switch SW3. (BIT or WORD). When SW2 is depressed the reset is removed from pin 12 of Bit Flip-Flop IClO until the load pulse occurs, either 1 Bit or 8-16 Bits later. See Section 4.3 for the Handstepping Procedures.

5.3.8 LED Indications

Sixteen LED indications are provided on the Transmitter Housekeeping P.C.B. to indicate the status of the Transmitter Unit in any mode of operation. Each LED is driven by a buffer or inverter gate at 5 milliamps. See Section 4.2 for the meanings of each LED indication.

5.3.9 Option lOlX Flashing Rel~y Option

IC27, IC28, RLYl, 030, 1/6 of IC20 and capacitors CS and CG make up the relay flashing circuitry. RLY-1 toggles, depending on the bit rate setting and message length, either every .85 seconds.or every other message time. The relay output is used to flash indications from the Transmitter Unit. All indications wired through this relay contact will be alternately transmitted ."on" and "off" when these indications are energized.

5.4 CIRCUIT DESCRIPTION OPTO INTERFACE P.C.B.

The following text is intended to be read while referring to the following Figures:

a) Figure 5-7, Circuit Diagram of Transmitter Opto Interface Board

b) Figure 5-8, Transmitter Opto Interface Logic Flow Diagram

c} Figure 5-9, Transmitter Opto Interface Components and Parts Location.

Sixteen identical data input circuits are provided on this board. (Input indication Oto i~put indication 15). The· input indication O input will be described. Two isolated input pins are provided on the "A" board connector for each input. Pins 1 and A are for ·input indication 0. Resistors Rl and R2, diodes Dl and 018 and capacitor Cl provide the

6058, p. 5-21


transcient input protection for this input. Diode Dl provides half wave rectification of AC input signals as well as blocking negative inputs to 1 kilovolt. Diode 018 is a zener diode which clips all input signals at its zener voltage of 48 volts •. · Constant current diode 034 assures a current of no greater than 2.2 milliamps is supplied to· optical coupler OCl over the entire input voltage range (5 to 32 VAC RMS) (5 to 40 VDC). Optical coupler OCl provides complete electrical isolation of all input signals from the internal logic signals.

Resistors R33 and R49 and capacitor Cl7·provide an input time constant for high noise immunity. Response time is typically 22 milliseconds rise time and 150 milliseconds fall time for Transmitter Opto Interface P.C.B. UN085722-1001. Input response time can be shortened by use of Transmitter Opto Interface P.C.B. UN085722-1011. (Typical response time 1 millisecond both rise and fall) (Capacitors C17 to C32 are eliminated in this version).· The output of the time constant circuit is fed to IC!, a tri-state strobed hex buffer inverter. IC's 5, 6 and 7 provide the address decoding logic which controls the output of the tri-state gates. The address program inputs to IC7, a Quad-Exclusive-or Gate, (Pins 20, X, 21 and Yon connector "B") are received when the Opto Interface board is plugged into the Transmitter Unit. The address inputs (Pins 11 and M, 12 and N, 13 and P, 14 and R, and 15 and S) to IC7 are received from the Transmitter Housekeeping P.C.B. When the address inputs are the same as the complement of the programmed inputs, either the first 8 tri-state outputs or the second 8 tri-state outputs are enabled. (Outputs are normally in the high impedance state) Address bit 20 the least significant address bit (Pins 15 and S), determines which group of outputs is enabled. (Bit 20 at a low level bits 0-7 enabled. Bit 20 at a high level bits 8-15 enabled.) LEDl and LED2 provide indication of which 8 bits are enabled. LEDl illuminated--bits 0-7 (Word 0) enabled. LED2 illuminated--Bits 8-15 (Word 1) enabled. The board present signal on pins 9 and K of connector "B" is at a low voltage state, (Logical 0) when the Opto Interface board is correctly addressed, and provides a signal to the Transmitter Housekeeping P.C.B.,indicating that a board is present in the slot presently being addressed by the Transmitter Housekeeping P.C.B. The output inhibit signal places all outputs to a low state when positive voltage is applied to~ pin 10 or Lon connector "B".

A low state applied to pin 16 or T disables all addressing of the PCB.

Pull up and series resistors are provided for each input to a logic gate for input protection.

6058 I P• 5-22

C~STOR

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TRANSMITTER OPTO

INTERFACE SCHEMATIC !- , WABCO IIUTlll1NME • - c.>MY ~ = ... ~CN & SICIIAl 11:ii: .

l<==i~c:::!L'.f;.:~.---~ 0085722 c-:·r1·1 11775 _. --..,.... • ..;..!...

Figure 5-7. Circuit Diagram Opto Interface Board


6058, p. 5-23/5-24

OUTPUTS 1-15

-· y

OUTPUTS 1•1 S

D.AT.-. BUS

OUTPUTS l•I S

INDIC,'f ION INPUTS 1-15

N

OUT,UTS 1•15

LOW u1no.ANCE

Figure 5-8.

LEDi .__ I

LEDi ..,___ 0

OUT"1TS TO

evsHt&H IMPEON«:£

Ll<ST WORD -· LEDi .,..__ 0 LED2 ...,__ 0

y

BOARD i't1tsiift -· LEDi +-- I OUTPUTS 0•7

LOW IMPEDANCE

OUTPUTS 0•7

o.-r.-. BUS

OUTPUTS 0-7 -INOICATIOH INPUTS 0•1

N

Transmitter Opto Interface Logic Flow Chart Diagram

OUTPUTS O•T

-·

AE.FE.R.ENC£5

TP.ANSHITTIE." OPro INTEllllP'AC& P.C ••

~~;~:i.~2;;!~6 f.~:i~1i·r~::~rvPlQ PAR"T HO.)

TRMSMITTER OPTO INTERF.-C:£ LOGIC FLOW DIAGRHI

APPLICATION & CHARAClERISTIC OV.'G'S F<J! AOL-256 DATA

TRANSMISSION SYSTEM


6058, p. 5-25/5-26

O'\ 0 U1 00 ... tu

U1 I

N -..J

-4

~ z c: en z ii!= -4 co -4 UI ,., _. :u...., c:, ':J .,, --1= =S

c J ( ) A83

C33 R84n ~82 -A75n

Rionn -

n RBBU

R&6 R78

R79 R67

R68 ::J

i19 !'.!n

Cl 7 All c =::J + C:J QTP17 R49 C::J

C =:> +R34C:::J

QIP1B CIB RSO C:J

C =:> +me. ::J Q IP19 Cl 9 RSI C ::J

C =:> +R36C::J

Q IP20 C2

0 RS2 C :J

c =:> +RllC.:::J

Q IP21 C!l RSJ C ::J

c =:> +RJBC:::J

Q IP22 C22

AS4 C :J

c =:> +"39C: :J

Q TP23 C!l RSS C: :J

C =:> +" 40c::J

Q IP24 C24

RS& C ::J

C =:> +R41C::J QTP25 C25 RSI C ::J

C ==> +""c:::i Q IP26 C26 R58 C:::J

C =:> +143C::J

Q TP27 C27R59 C J C =::i .t"c:::i

QTP2aC21A&O C::J

C ==> +"'c:::i QTP29 C29R&1 C::J

C ==> +'°c:::i Q TPJO CJO A62 C:::J

C ==> +"'c:::i QTP31 CJIA63 C::J

·c =:i +"'c:::i "'u

11~'111"·" BA r

,--, lP3 oft -t TP2 * t * TPI ,t. t .t ~ :=:::!Cl O n~nr-t~n O nlii1n[Tn n O nliil n n n n ........ !C2 l!lul!J ~ l!!!uu 1l:u l!jULJL 11!!1 I (' ,--, 036 ~ DJ LJ DJS _J 02 034 ------

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= = !C& 09

r C& Rr' ~· D& R~ ,t CS RrlO. ~J R~ 021 C4 RI. 04

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DCB -..J 041 _j DB 040 ,, __ .._ _. * C9 ' o9

All 1' CB .RI& Rl5 024 Cl .Rl4 ,--. TP12 t ....

OC9 Q Rt Q O ::=:::::* *ni:4ri -ln*i1~n~nr1 ~*il~n~l n ~n ........ 1c10 l!IULI .l:u,l!!!uu ·"=LJtl!IULJL ,, I t9 ,- -, 045 --' 044 _j 011 043 ·L--8

OC1l Cl2 ' 612

R23 * Cll .R22 R21 027 CID eR20 .___.* IP15 t R3o'-·---..:..;;.;;~========

,--, 0 r~ 0 r~f O . · ........ :m.Ln~n ~ r1'i"l~n~n - nfl~n"ln n, ,__, i<l!ILJL_I l!!I ,t.l!!ULJ l!!I l!!!ULJ fe

!ell ou -..J 01 LJ 047 _J 014 LJ *-o•s · LJ 0,3 L ::= :::::oc,4 032 Cl5 • S R29 ,;$;' Cl4 .• R28 R27 030 C13 R26

TP16 033 .on ::= :::: .L n !iii n ,., n OCIS 1'1!9 LJ LJ l!!I All

::= :::: * 049 LJ .L LJ :.'J I OC16 t Cl& t

· ... ·111n II -r-J

Figure 5-9. Transmit OPTO Interface PCB Components and Parts Location

c z 0 z I ~ :r;

• (II

t5 z ), ,-

E

\,,,1,,,1 UNION SWITCH & SIGNAL

COMPONENT SYMBOL

Cl - Cl6 Cl7 - C32 C33 C34

Dl - 017 018 - 033 034 - 049

ICl - IC4 ICS - IC6 IC7

LEDl - LED2

OCL - OC16

Rl-R-32 R33-R-48 R49-R64 R65 R66-76 R77 R78-R88

TRANSMIT OPTO INTERFACE P.C.B. COMPONENTS & PARTS LOCATION

REFER TO FIGURE 5-9

DESCRIPTION

Capacitor 0.1 mfd. 200 VDC Capacitor 1 mfd. 35 VDC Capacitor 0.001 mfd. 500 V Capacitor 4.7 mfd. 35 V

Diode 1N4007 Diode 1N5368B Diode 1N5305

IC MC14502CL or Equivalent IC CD4068BF or Equivalent IC MC14507CL or Equivalent

MYLAR TANTALUM CERAMIC TANTALUM

Diode, Light Emitting HP5082-4415

Optical Coupler CLI-10 or Equivalent

Resistor 22on Resistor lSOKSl Resistor 22KSl Resistor 2.2KSl Resistor lOOKSl Resistor 2.2KSl Resistor lOOKSl

lw l/4W l/4W l/4W l/4W l/4W l/4W

* All Resistors Carbon Type

605"8, p. 5-28

UNION SWITCH a SIGNAL OJ

5.5 CIRCUIT DESCRIPTJON OF RECEIVER HOUSEKEEPING PCB

The following text is intended to be read while referring to the following figures:

a) Figure 5-10, ADL-256 Receiver Housekeeping Circuit Diagram

b) Figure 5-11, Receiver Housekeeping Logic Timing Diagram

c) Figure 5-12, Receiver Housekeeping Logic Flow Diagram d) Figure 5-13, Receiver Housekeeping PCB Components

and Parts Location

5.5.1 Power Up Circuitry

Transistor Q5, Diodes DlO and 012, Resistors R63, R64 and R65 and capacitor Cl7 form the Power Up Circuitry for the Receiver Housekeeping PCB. As the input voltage to the PCB rises to the level established by voltage divider R64 and R65 and zener diode 012 (Approximately 7 to 8 volts DC), transistor Q5 charges capacitor Cl7 through R63. This output feeds a schmitt trigger circuit formed by IClO and resistors R49 and R50. This circuit provides a fast risetime output when its switching threshold is reached. A reset is provided to the circuitry of the Receiver Housekeeping PCB.by IC2 through Dll and R51 when the MODE switch (SWl) is operated.

5.5.2 Clock Circuitry

The Clock circuitry is located in the upper right hand section of the circuit diagram. One stage of IC16 and its associated components Rl 7, Rl8, Cl, C2, C3 and Yl comprise the o.scillator circuit. The frequency of oscillation is determined by crystal Yl at 2.457600 MHz. Trim capacitor C2 provides adjustment of the frequency. The oscillator stage of IC16 is decoupled by Cl5 and R59. The remaining two stages of IC16 are used to buffer and square up the output of the oscillator stage. The 2.457600 MHz signal at TPl is fed to IC15, a seven stage ripple counter. Output at pin 3 of IC15 is 19.2 KHz. IC24, another seven stage ripple counter, provides additional division of the 19.2 KHz signal. Bit rate selector switch SW5 selects the various outputs of IC24, providing for Bit Rates of 75, 150, 300, 600, 1200 or 2400 bits per second. The output at TP2 is twice the setting o~ the Bit Rate Switch SW5, with the additional division being provided by clock flip-flop IC23 to obtain the actual bit rate. This circuitry is similar to that on the Transmitter Housekeeping PCB.· An addition to the · circuit is sync monostable IC20 and its associated components R56 and Cl4. The sync monostable provides a reset to the clock during the message Format until the address portion of the message is received. This provides for synchronization of the clock at the beginning of each message.

6058, p. 5-29

'


5.5.3 Message Format and Control Character Decoding

The message is inputted serially to shift register 1 and 2, IC18. Character decoders 1 and 2, ICs 19 and 25, are BCD to decimal decoders. IC26 provides appropriate gating of the outputs of the BCD to Decimal Decoders for decoding of the message control characters~ One-half of IC37 counts the number of SYN characters which are received. At least two consecutive SYN characters must be received before receiving a STX (Start of Text) character. Upon receiving the STX character; start flip-flop IC28 is set and the reset is removed from shift registers 3 and 4, IC17. The next 16 bits of information received must be the station address information followed by its complement. The Station Address received must correspond to the setting of the Station Address switch SW6. When the address information is correctly received, the reset on IC35, the Word Count, 7 stage ripple counter, i.s removed and the Address Disable signal is removed from the interface PCB's in the Receiver Unit~ The next information in the message is the data, followed by its complement. The data is serially shifted into shift registers 1, 2, 3 and 4, IC's 18 and 17. When the Board Present signal, pin 9 and K connector "B", is not received, Last Word Flip-Flop IC21 is set and the addresses to the interface PCBs are disabled via the Address Disable signal on Pin 16, T of connector "B". The next ch~racter received must be an ETX (End of Text) character. Character decoders 1 and 2, IC's 19 and 25, decode the ETX character and IC26 provides appropriate gating of· the decoded outputs of the decoders.

Jumpers Jl and J2 provide for even parity or the last bit always a "l" for the control characters. With Jumper Jl installed all received control characters must be even parity. With J2 installed the last bit of.all received control characters must be a "l". Note: For proper system· operation when Jl is installed on a Transmitter Housekeeping P.C.B., Jl must be installed on the corresponding Receiver Housekeeping P.C.B. When Jl is not installed on the Transmitter Housekeeping P.C.B., J2 must be installed on the corresponding Receiver Housekeeping P.C.B. ·

5.5.4 Error Checking Circuitry

As the address and data information is received, a complement· check is made by 1/4 of IC.33, -an exclusive-or gate. If either input to IC33 is ever different, the output of IC33 will be at a high level and error flip-flop IC23 will be set (complement error received). Error count flip-flop IC12 counts the consecutive messages iri error. If three consecutive messages are received in error,the ·Q3 output of IC12 will be at a high level and alarm relay RLYl will drop. The alarm relay is normally energized until the Receiver Unit goes into alarm.

6058, p. 5-30

UNION SWITCH & SIGNAL t:l1

IC13 forms an alarm timer. If no messages are received for approximately 2.7 full 256 Bit message times, the Q4 output of IC13 will be.at a high level and the alarm relay will drop. An entire message free of errors must be received before the alarm relay is reset. Diode 014 prevents back EMF from the alarm relay and capacitors C4 and cs·provide contact protection for the alarm relay contacts.

5.5.5 Addressing and Strobe Circuitry

The outputs of IC35 (Word Count) are buffered by IC34 and provide the addres~ing outputs to the interface boards· (Pins 11 through 15 on connector "B"). Seven stage ripple counter, IC35, is advanced each time the complement check of the data is completed. After the complement check is complete and no errors have been detected, IC37 gated by IC30 and IC34 provides a ~.l millisecond strobe pulse for the Receiver Transistor Interface PCB's in the Receiver Unit. This pulse is too short to energize the relays on a Receiver Relay Interface P.C.B. A Deliver pulse is provided for this purpose. IC12, gated from IC22, ICll, and IC3, qenerates . the delivery pulse. It is 14 Bit times in length as determined by res. Note these pulses occur only when no message errors have been detected. When errors are detected, address received flip-flop, IC28, is reset and strobe timers, IC37 and IC12, are held reset until the start of a new message.

5.5.6 Data Carrier Interface Circuits

Two !nterface Circuits are provided on the Receiver Housekeepinq PCB. They are the Carrier Detect and the Data Input interface. Each interface circuit is optically isolated and accepts voltage input swings of ±5 voe for EIA interfaces and voltage swings from o.o voe to +5 voe for TTL interfaces. Two Jumpers must be installed for operation·with EIA voltage levels (Jumper Al7, u to Al6, T and All, M to Al2, · N) • These Jumpers are removed for TTL operation and pins 19, Wand 8, J must be Jumped to +5 voe. The carrier detect signal is "on" at +5 voe and "off" at -5 voe for an EIA interface. (+5 "on" and O.OV "off" for TTL). The data is received as a "Mark" for -5 voe and as a "Space" for +5 voe for an EIA interface. (0.0 "Mark" and s voe "Space" for TTL.)

6058, ·p. 5-31


5.5.7 Test Circuitry

IC's 7 and 8 along with switches SW2, SW3, $W4, and MODE SELECTOR switch SWl provide for testing of the Receiver Unit. When the MODE SELECTOR switch, sw1·, is set to ·the 3 MAINT position (Maintenance Mode), depressing the TEST switch, SW2, inputs data according to the positions of SW3 and SW4. SW3 ,. the COUNT switch, indicates how many Bits of.Oat~ will be entered when the TEST switch is depressed (COUNT switch in the BIT position-:..one Bit entered,· COUNT switch in the WORD position--eight (8) Bits entered) •. The lNPUT switch SW4 indicates the status of the Bits being entered (either MARK or SPACE--Logical "l" or Logical "0").

Refer .to Section 4.5 for Details of the Maintenance MODE of, Operation.·

5.5.8 LED Indications

Sixteen (16) LED indications are provided on the Receiver Housekeeping P.C.B. to indicate the status of the Receiver Unit in any mode of operation. Each LED is driven by a buffer or inverter gate at 5 milliamps. See Section 4.4 for the meaning of each LED indication. ·

6058, p. 5-32

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6058, p. 5-33/5-34

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6058, p. 5-35/5-36

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Receiver Housekeeping Logic Flow Chart

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6058, p. 5-37/5-38

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6058, p. 5-39


COMPONENT SYMBOL

Cl C2 C3 C4-C5 C6 C7 ca C9 ClO Cll. Cl2 C13-Cl4 Cl5 Cl6 C17 Cl8 Cl9

01-011 012 013 014-016

IC1-IC4 IC5 IC6 IC7 IC8 IC9-IC10 ICll IC12-IC13 IC14 IC15 IC16 IC17-lC18 IC19 IC20 IC21 IC22 IC23 IC24 IC25 IC26 IC27 IC28 IC29 IC30

6058, p. 5-40

RECEIVER HOUSEKEEPING P.C.B. COMPONENTS & PARTS LOCATION

REFER TO FIGURE 5-13

DESCRIPTION

Capacitor 43 pfd.MICA Capacitor 9-35 pfd.VARIABLE Capacitor 56 pfd.MICA Capacitor 0.001 mfd. 300V CERAMIC Capacitor 100 pfd.MICA Capacitor 0.001 mfd.CERAMIC Capacitor 4. 7 mfd. 35 voe TANTALUM Capacitor 0.001 mfd~CERAMIC Capacitor 4. 7 mfd. 35 voe TANTALUM Capacitor 100 pfd. MICA Capacitor O. 001 mfd. CE.RAMIC Capacitor 100 pfd.MICA Capacitor 1.0 mfd. 35 voe TANTALUM Capacitor 100 pfd.MICA Capacitor 4. 7 mfd. 35 voe TANTALUM Capacitor 100 pfd.MICA Capacitor 4. 7 mfd. 35 voe TANTALUM

Diode 1N914B Diode, Zener 1N5231B Diode 1N914B Diode 1N4007 Diode, Light Emitting HP50824415

IC MC14049CL or Equivalent IC MC14024CL or Equivalent IC MC14023CL or Equivalent IC MC14013CL or Equivalent IC MC14011CL or Equivalent IC MC14050CL or Equivalent IC MC14001CL or Equivalent IC MC14015CL or Equivalent IC MC14011Cl or Equivalent IC MC14024CL or Equivalent IC MC14007CL or Equivalent IC MC14015CL or Equivalent IC MC14028CL or Equivalent IC MC14528CL or Equivalent IC MC14013CL or Equivalent IC MC14011CL or Equivalent IC MC14027CL or Equivalent IC MC14024CL or Equivalent IC MC14028CL or Equivalent IC MC14~23CL or Equivalent IC MC14001Cl or Equivalent IC MC14027CL or Equivalent IC MC14011CL or Equivalent IC MC14023CL or Equivalent

UNION SWITCH & SIGNAL W

COMPONENT SYMBOL DESCRIPTION

IC31-IC32 IC MC14012CL or Equivalent IC33 IC MC14507CL or Equivalent IC34 IC MC14050CL or Equivalent IC35 IC MC14024CL or Equivalent IC36 IC MC14001CL or Equivalent IC37 IC MC14015CL or Equivalent IC38-IC39 Optical Isolator 4N27

Ql-Q4 Transistor 2H3904-5 QS Transistor 2N3906~5

Rl-Rl6 Resistor 2.2K'2 l/4W Rl7 Resistor 15 Meg. n l/4W Rl8 Resistor 12K'2 l/4W Rl9-R20 Resistor 100K'2 l/4W · R21 Resistor 12K'2 l/4W R22-R24 Resistor 100K'2 l/4W R25 Resistor 1 Meg. Q l/4W R26 Resistor lOKO l/4W R27-R28 Resistor lOOKO l/4W R29 Resistor 4. 7K '2 l/4W R30 Resistor 47KO l/4W R31 Resistor 3.9K '2 l/4W R32 Resistor 100K'2 l/4W R33 Resistor 47K'2 l/4W R34 Resistor lOKO l/4W R35 Resistor 100 n l/4W R36 Resistor 470 n l/4W R37 Resistor lOK n l/4W R38 Resistor 4. 7K O l/4W R39 Resistor 47K O l/4W R40 Resistor 3.9K n l/4W R41 Resistor lOOK O l/4W R42 Resistor 47K '2 l/4W R43 Resistor lOK n l/4W R44 Resistor lK"O l/4W R45 Resistor lOK O l/4W R46 Resistor 100 0 l/4W R47 . Resistor lOK O l/4W R48 Resistor 20K O l/4W R49 Resistor 15 Meg.O:l/4W RSO Resistor 1 Meg.O l/4W RSl Resistor .2.2K O l/4W R52 Resistor 1 M~g. 0 l/4W R53 Resistor lOK O l/4W

·R54-RSS Resistor 470 n l/4W R56 Resistor lOK O l/4W R57 Resistor 1, Meg.O l/4W R58 Resistc;>r 2. 2R: 0 l/4W R59 Resistor 100 0 l/4W R60 Resistor 1 Meg. O l/4W

All Resistors Carbon Type Unless Otherwise Noted

6058, p. 5-41


COMPONENT SYMBOL

R61 R62 R63 R64 R65 R66 R67

RLY-1

SW-1 SW-2 SW3-SW4 sw~s SW-6

Yl

DESCRIPTION

. Resistor Resistor Resistor Resistor Resistor Resistor Resistor

lOKQ 1 Meg.Q lOOKQ 2.2KQ 12KQ lOKQ 1 Meg.o

l/4W l/4W l/4W l/4W l/4W l/4W l/4W

Relay iAWCM-16151-lADAMS and WESTLAKE

Switch, 3 Position GRAY MILL #9P60-01-l-3N Switch, Pushbutton C&K #8125-RS3 Switch, Toggle C&K #7101 M D9 AB Switch, Dip DAVEN #llllAA Switch, Hex .Code AMP #. 531137-1

Crystal ERIE, 2.457600 MHZ

All Resistors Carbon Type Unless Otherwise Noted

6058, p. 5-42


5.6 CIRCUIT DESCRIPTION OF RECEIVER_TRANSISTOR INTERFACE

The following text is intended to be read while referring to the following figures:

a) Figure 5-14, Recei"ver Transistor Interface Circuit Diagram

b) Figure 5-15, Receiver Transistor Interface Logic Flow Diagram

c) Figure 5-16, Receiver Transistor Interface PCB Components and Parts Location

The Receiver Transistor Interface PCB provides for. the output of 16 Bits of indications (Indication O through 15). Each output (Ql-Ql6) is a NPN Darlington Transistor with an unconunitted collector output. The output transistors for indications O through 7 (Word 0) are driven by IC6.and IC7 (Quad Latch), while the output transistors for indications 8 through 15 (Word 1) are driven by Quad Latch IC8 and IC9. Resistors R36 through R51 limit the base current to Ql through Ql6 to 1.5 milliamps. The information on the Data Bus (Pins 1-8 on Connector "B") is gated to the appropriate latch (IC6 and IC7 or IC8 and IC9) when the board is correctly addressed and the DATA STROBE signal occurs •. IC's 1, 2 and 3 provide the address decoding logic that controls which group of latches the data is delivered to when the DATA STROBE signal occurs. The address program inputs to ICl, a Quad Exclusive-Or Gate, (Pins 20, X, 21 and Yon Connector "B") are received when the Transistor interface PCB is plugged into the Receiver Unit. The address inputs to ICl (Pins 11 and M, 12 and N, 13 and P, 14 and R, and 15 and. S) are received from the Receiver Housekeeping PCB. When the address inputs are the same as the complement of the progranuned inputs the board is addressed. When the DATA STROBE signal occurs, the data on the Data Bus will be stored in the first group of latches (IC6 and IC7) or the second group (IC8 and IC9). Address Bit 2° (Pins 15 and S), the least significant address bit, determines which group receives the information on the Data Bus. (Bit 2° a low level the data is strobed to IC6 and IC7, Bit 20 a high level, the data is strobed to IC8 and IC9). Two light emitting diodes, LEDl and LED2, provide visual indication of when the transistor interface board is being addressed. LEDl illuminated--indication Bits 0-7 (Word 0). LED2 illuminated--indication Bits 8-15 {Word 1). The BOARD PRESENT signal on pins 9 and K of connector "B" is at a low (Logical 0) level when the transistor interface board is correctly addressed. This provides a signal to the Receiver Housekeeping PCB indicating that a board is present in the slot presently being addressed by the Receiver House_-~~ keeping Logic. When a low (Logical 0) level is applied to RESET (Pins 17 and U of Connector "B"), the information presently on the Data Bus.is strobed to all latches (IC6,7,8 and 9). A low (Logical 0) level applied to Pin 16 or T disables all addressing of the PCB. ·A pull up and series resistor is provided for each input to.a logic gate for input protection.

6058, p. 5-43/5-44

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Figure 5-14. Receiver Transistor Interface Circuit Diagram

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6058, p. 5-45/5-46

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.l.!ll.A::I. TRANSISTOR

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Receiver Transistor Interface Logic Flow Diagram

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oimuf IHDICATIONS

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6058, p. 5-47/5-48

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I c :J R53 Rt c :J --

= R&I :: R59 N O

c :J RI c :J R7 c :J R& c :J R5

C2 :

IP23 0 c

R50 n R51 TP22

0

TPl70

TPIBO TPl9 0

t:.r,...

ICB *

IC& *

n n n n uuuu

: R57 : 155 . -c :J R4 c :J 13 c :J R2 c J RI c J R46 c J 145 c :J a44

u

TP21 R49

0 c

TP24 c 0

R41

TP20 0

TPII O RO

TPIO 0

TPJI 0 !PS 0

TPl2 0

111111111111-111111 BF

I i c :I R37

c .J R3& c :J RJB

C :J R39

R35 .016

• R20 c J c 'JI

R34 .015 R21 c J CJ

:J .014 R33 R22 c J c J

R32 .013

R23

::J [ J

RJI .012

R24

:::J c J • . 011

:J° ..... R25 [ J .... ..-..

129 ]

4111 II

LED2 0 OLEDI ~ fJ} fo

IP29n TP30n Ou Ou

Rl9 R52

c: z c:, co CJI ...., .QI N

! c:,

9

"' ,., n ,., < ,., "' .... = > z en ;::;; .... c:, :a z .... ,., "' .... > n ,.,

~ rA

Figure 5-16. Receiver Transistor Interface PCB Components and Parts Location

c z 0 z I ~ :c .. (II

ci z )I, ,-

E


Component Symbol

Cl C2

Dl 02

I Cl IC2-IC3 IC4 IC5 IC6-IC9

LED1-LED2

Ql-Ql6

Rl-Rl8 Rl9 R20-R35 R36-R51 R52 RS3-R74

RECEIVER TRANSISTOR INTERFACE P.C.B.

COMPONENTS & PARTS LOCATION REFER TO FIGURE 5-16

Description

Capacitor, 0.001 mfd. 500V CERAMIC Capacitor 4. 7 mfd. 35V TANTALUM

Diode 1N4007 Diode 1N914B

IC IC IC

· IC IC

MC14507CL or Equiv. CD4068BF or Equiv. MC14049CL or Equiv. M~l4011CL.or Equiv. MC14042CL or Equiv.

Diode, Light Emitting HP5082-4915

Transistor, 2N6387

Resistor, lOOKQ l/4W Resistor, 2.2KQ l/4W Resistor, 220Q l/2W Resistor, 8.KQ l/4W Resistor, 2.2K~ l/4W Resistor, lOOKQ l/4W

All Resistors Carbon Type Unless Otherwise Noted.

6058, p. 5-50

UNION SWITCH 8i SIGNAL \JJ

5.7 CIRCUIT DESCRIPTION OF RECEIVER RELAY INTERFACE P.C.B.

The following_text is.intended to be read while referring to the following figures:

a) Figure 5-17, Receiver Relay Interface P.C.B. Circuit Diagram

b) Figure 5-18, Receiver Relay Interface Logic Flow Diagram ..

c) Figure 5-19, Receiver R~lay Interface P.C.B. Components and Parts Location

The Receiver Relay Interface PCB provides for the output of 16 Control Bits (Control Bit 0-15). Each output consists of a single Form C latching relay. The heels of the relay outputs are bused in groups of (4) four. Both the N.O. (normally open) and the N.C. (normally closed) relay contacts are brought out to the "An connector of the PCB. Snubbing capacitors Cl throu_gh C32 provide contact protection for each relay output. When the DATA STROBE signal (Pin 10 and Lon Connector "B") occurs, the data on the Data Bus lines (Pins 1-8 on Connector "B") is enabled to Quad latch IC's 5 and 6 for temporary storage. IC's 7, 8 and 9 provide the address decoding logic that controls which group o"f relays (control 0-7 or control 8-15) receive the data stored in the Quad latches (IC5 and IC6). The address program inputs to IC7, a Quad Execlusive-Or Gate, (Pins 20, X, 21, and Yon the "B" Connector) are received when the Relay Interface PCB is plugged into the Receiver Unit. The address inputs to IC7 (Pins 11 and M, 12 and N, 13 and P, 14 and R, 15 and S) are received from the Receiver Housekeeping PCB. When the address inputs are the same as the complement of the programmed inputs, the board is addressed, When the DELIVER signal (Pins 18 and v Connector "B") occurs (at a low [Logical OJ level) the information stored in the Quad latches (IC5 and IC6) will be delivered to control Bits 0-7 or control Bits 8-15. Address Bit 2° (Pins 15 and S), ·the least significant address bit, determines which group of contrQl relays receives the Data

. stored in the latches. (Bit 2° a low level--control Bits 0-7. Bit 2° a high level--control Bits 8-15) the BOARD PRESENT

signal (Pins 9 and K of Connector "B") is at a low (Logical 0) level when the.Receiver Relay Interface P.C.B. is correctly addressed. This provides a signal to the Receiver Housekeeping P.C.B. indicating that a board is present in the slot presently addressed by the Receiver Housekeeping Logic. Output drive for the relays is provided by ICl, IC2 and IC3. The voltage return for relays RLYl through RLY8 is through Darlington Transistor Ql. The voltage return for relays RLY9 through RLY16 is provided by Q2. Diodes 033 through 064 prevents back EMF of the relay coils.· All inputs to logic gates are protected by a pull-up and a series resistor.

6058, p. 5-51/5-52

,,_.,TOii ---...-4

DI QUAD QI 2

LATCH

o, IC5

QI J

DJ QZ 10

04 QZ

CL QJ II IOOK

.,, POt. Q3 12

VDO Q4

vss Q4 .. S,£~--....,_..._,'---..---:-:---!-~RV2~1~----------t------"-!DI QUAD Qlf2:.....------.... -------~

LATCH

1,v~--..,,._:....:..._ __ ,._....:~;,---jf,--"11y,J~----------+--------tD2 ICI iiiF''---------e--""l

10,L AA

... , A SS OISA&Li

IS,s ADOAESS an 2°

y p a T •'

14 ,R AOD~S$ atT •'

.. rllt08RW atf 2•

JJ,P AOORt'S BIT •• f'ROGIIAM i If •• x

12,N A [SS 9tT • •

•• PIICMMltAM 81 T 2 •

,,, .. A A SS SIT .24

••• HT

TP2

•••• OU cu

Zt,z DCC-

NOTE: .IQ! Cl 50< I PTI .t.

1. l,2 •' ,,

••• 1

•.• ..... .. AELAYS

HEX INV£11TER 9UFFER(MOTOROI.A '9clt041CL OR EQUIV.) QUAD & 91T LIITCH(UDTOROI.A ffucl,e,2cL OR £Qu1v.l

~~:L:x~~=f:;::~=T~!:~ ::Ci:!:;~, OR t:QulV QUAD 2 INPUT MffD GATE:{MOTOftOLA ftuct•OIICL OR EQIUV

AYI-IIYl5 ARE MERCURY Wl.TR:O IMGIICTIC :iTICK TYPE .--c.

u DJ q, 10

1• 04 -· q,

QJ II

qi .. q,

TPIJ

...... , DI

010

D•O IN400J

Ntoe, IN•••:s ..... , 04J DII •

N4001 Dll

o,. IN4001 IN400J ...

DU ...... ,

...... , 041

NO 1) 4

"-""-1,-.~~~~~~--="'-'~o __ .....,, ,___ CONTIIOI.. J

'-'=====---------"'-=~t,I0,11

CONTIIOL S

NO f) I

L----11.!:::::f"---------'~C~ON:T~R~ 1

C 5 - K,L,111

ND 10) U

!.--1~:::::,-:ii"iji![P.'iioe;--"'~p

•• NO II) IS

1---l~~';j'--------"'~C~OlffllOt.~5 II

1...====::::::~.-..;,w-;irnir---':....1=1~•~1:1"'•

.. "° If)"

L----11~~::f"--------"'~C~ONT::!.!i_ I I •I X,Y,Z • (II) -~DUt. __ •_•_n_,_•_-_•_•_••--+-11E-ct_1_w_a_11E_u_•_1_NT_E __ IH'=AC£=-L-oa_1c_o_1 .. _"""' __ t::i r;lt

REC! IVER RELAY 1Nr£RFACE SC!lE'.l'T IC

sN'

Figure 5-17. Receiver Relay Interface PCB Circuit Diagram


6058, p. 5-53/5-54

I.ED t =- ON

LEO 2 :.. OFF

OATA INP'UT BITS O TO 1 ENTRY

TO TEMPORARY

STORA<HC (Ics I ·>

Y£S

DATA TRANSFERED FROM TEMPORARY STORAGE TO FINAL STICK REt.AYS RYf

TO RYI

DATA PRESENTED TO EXTERNAL EQU I l'MENT VIA RELAY CONTACTS CONTRot. 0 THRU T

Figure 5-18.

NO

NO

YES

COMPARATOR ( I Nl'UT ADORESS

TO PROGRAMMED ADORESS)

Y£S

BOARO Nt!sENT

SIGNAL -.

NO

Y£S

Receiver Relay Interface Logic Flow Diagram

LEO t = OFF

LE02=0N

Y£S

DATA IN,UT 8 ITS O TO 7 ENTRY TO

TtMPORARY STORAGE

hes • •>

Y£S

DATA TRANSFERED FROM TEMPORARY STORAGE TO F' I HAL STICK RELAYS RYt TO RYf 6

DATA P'R£9ENTED TO EXTERNAL EQUIPMENT VIA RELAY CONTACTS

CONTROL I THIIW I S

REFEREICES

~~:~:~~.:~"'fa!~:=:~E ,_:,;~·:;,:) UJ776SH-250 (sw,sSvA(E PART NO.) 00,sn,-SH.2 SCHEMATJC

llt£C[IV!R RELAY INTERP'ACE LOGIC F'LOW OIAIRAM

APPL !CATION & CHARACTERISTIC

OWG•S FOR AOl-251; OATA

TRANSMISSION SYSTEM


6058, p. 5-55/5-56

°' 0 U1 CX) ..

l't,

Ul I

Ul ~

("

L:

Figure 5-19.

UN085725-1001 ff f fTYP. ~ . • • .. I I/ II I

I Cl C2

•' 1 I

••• II • 1 I I Pr ,c& •

• • • 1/ 1 t I

C7 C8

'.'-' _____ ,;

·1111

Receiver Relay Interface PCB Components and Parts Location

c z 6 z

~· 2 ... !! . C) z > ,..

8


Component Symbol

Cl-C32 C33 C34

Dl-065 066

IC1-IC4 IC5-IC6 IC7 IC8-IC9 IClO-ICll

LED1-LED2

Ql-Q2

Rl-R4 R5-R44

RY1-RY16

6058, p •. 5-58

RECEIVER RELAY INTERFACE P.C.B. COMPONENTS & PARTS LOCATION

REFER TO FIGURE 5-19

Description

Capacitor, 0.001 mfd. 3000V CERAMIC Capacitor, 10 mfd. TANTALUM Capacitor, 0.01 mfd. lOOV CERAMIC

Diode 1N4003 Diode 1N914B

IC MC14049CL IC MC14042CL IC MC14507CL IC MC14501CL IC MC14011CL

or Equiv. or Equiv. or Equiv. or Equiv. or Equiv.

Diode, Light Emitting

Transistor, 2N6386

Resistor, 2.2KQ 5%, l/4W CARBON Resistor Network, lOOK Q, 5%

Relay ADAMS & WESTLAKE I AWCM - 16582-1

UNION SWITCH a SIGNAL \JJ

5.8 MOTHER BOARD P.C.B. (Refer to Figure 5-20)

The ADL-256 is designed on a Bus structure. All back plane wiring is accomplished by a Mother Board P.C.B. The Mother Board P.C.B. is housed behind a protective shield at the rear of the ADL-256 Card File. The same Mother Board is used for both the Transmitting and Receiving Units. Figure 5-20 is a circuit layout of the Mother Board PCB. Eighteen (18) connector slots are provided on the P.C.B. The first two slots are for the power supply and the Housekeeping PCB respectively._ The remaining 16 slots are for the interface PCB-' s·. Pins 20, X, 21 and Y are used to program the address of the interface board plugged into these slots. Each slot is programmed as the complement of the actual slot number (0 - 15). No~e: No maintenance of this PCB should be .required, therefore this PCB is riveted into the ADL-256 Card Enclosure.

6058; p. 5-59/5-60

, .. :~-,.,_

0 0 ·O

----- -------------------·······- - ---·····---- - ~~·------------·······- ~--~----------- - --------------------• • • • .. • • • .. • • • • • • • -SLOT

15

0

SLOT 11

SLOT SLOT 9 8

0

INTERFACE PCB

SLOT 5

SLOT SLOT SLOT SLOT 4 3 2 1

0

Figure 5-20. Mother Board Printed Circuit Board

• • • • • 10

• • • • • • • • •

0 0


0

00 00 n 00

n 00 n 00 n 00

-12 VOLTS

• 0

POWER SUPPLY

0

6058, p. 5-61/5-62

SECTION VI

APPENDIX

UNION SWITCH & SIGNAL ......,

6058, p. 6-1


6.1 FLOW CHART UTILIZATICN

The symbols in a flow chart are t6 be followed in a sequence as indicated by arrors as shown below:

Step 1 ------>- Step 2

A given sequence begins and ends with blocks called terminals. These blocks always have this form:

~eginning of Tes~ or(,-E_n_d_o_f_T_e_s_t_)

During a test sequence, it will be necessary for the tester to perform certain actions such as changing printed circuit boards. These operations have the following form •

.Change Suspect Printed Circuit

Board

The third type of symbol is used where the tester must make an observation or a decision. The symbol is:

y

Notice that there are two outputs from the symbol. The one output, marked N, should be followed if and only.if the answer to the question asked is No. The other output, marked Y, should be followed if and only if the answer to the question asked is Yes.

6058, p. 6-2

Predefined process one or more named operations or program steps specified in a subroutine or another set of flowcharts.

UNION SWITCH a SIGNAL UJ

6.2 HANDLING CONSIDERATIONS FOR COS/MOS (Complementary-Symmetry MOS) INTEGRATED CIRCUITS

Although protection against electrostatic effects is provided by built-in circuitry, the following precautions should be taken in handling these circuits:

1. Soldering-iron tips.and test equipment should be grounded.

2. Devices should not be inserted in non-conductive containers such as conventional plastic snow or trays. A conductive material such as "ECCOSORB LD26" or equivalent should be used.

Low-source-impedance pulse generators connected to the inputs of these devices must be disconnected before the de power supply is turned off. All unused input leads must be connected to either VSS or VDD, whichever is appropriate, for the logic circuit operation desired.

6058, p. 6-3

- UNIUN :,WI rc;H & SIGNAL

6.3 LOGIC SYMBOLS

EXCLUSIVE OR

INPUT A

0 0 1 1

(XOR)

INPUT B

0 1 0 1

CIRCUIT SYMBOL

NANO GATE :_, )-OR

INPUT A

0 0 1 1

INPUT B

0 1 0 1

A

B

CIRCUIT SYMBOL

OUTPUT

0 1 1 0

J ),____· OUTPUT

1 1 1 0

CIRCUIT SYMBOL

INVERTER

INPUT A

6058, p. 6-4

0 1

OUTPUT

1 0

CIRCUIT SYMBOL

d A A ) NOR GATE OR B B

INPUT A INPUT B OUTPUT

0 0 1 0 1 0 1 0 0 1 1 0

CIRCUIT SYMBOL

BUFFER A C> INPUT A OUTPUT

0 0 1 1

LOGIC CIRCUITS J K FLIP FLOP

PREVIOUS STATE

I ~p

s Q Cp* J K s R Q Q Q

R Q

....r 1 x 0 0 0 1 0 _r x 0 0 0 1 1 0

* = Level Change _;- 0 x 0 o _ 0 0 1 x = Don't Care _r- x 1 0 0 1 0 1

** = Invalid Condition \__ x x 0 0 x NO CHANGE 1 = High Level x x x 1 0 x 1 0 0 = Low Level x x x 0 1 x 0 1

x x x 1 1 x ** **

6058, p. 6-5


D FLIP FLOP

CIRCUIT SYMBOL

1:p Cp* D R s Q Q

s Q __r- 0 -0 o- 0 1 __r 1 0 0 1 _O_

R Q \._ x 0 0 Q Q NO CHANGE x x 1 0 0 1 x x 0 1 1 0 x x 1 1 ** **

* = Level Change x = Don't Care

** = Invalid Condition 1 = High Level 0 = Low Level

6058, p. 6-6

6.4 GLOSSARY OF TERMS

ASYNCHRONOUS

Not synchronous. Each event, or performance of each operation starts as a result of a signal generated by the completion of the previous ev~nt or operation.

BCD

Binary Coded Decimal. Four bits of _binary information can be used to encode one decimal digit. When a decimal digit is encoded in this way it is called a Binary Coded Decimal (BCD}. Binary coded numbers O through 9 are as follows:

Number D c B A

0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1

"A" respresents the l~ast significant binary digit

BIT

An abreviation of Binary Digit. A single occurrence of a character in a binary language employing exactly two distinct characters "l" or "O" ("on" or "off")

BUS

A conductor, or group of conductors used for transmitting signals or power from one or more sources to one or more destinations.

COMPARATOR

A comparator is a device used to determine whether two numbers of bits of information are equal.

COMPLEMENT

The complement of a variable or function is the binary opposite of that_ variable or function. If a variable or function is 1, its complement will be 0. If a variable or function is O, its

6058, p. 6-7


complement will be 1. The complement of 011010 is 100101. The"_" (BAR) symbol over a signal name or group of bits indicates the complement of that signal or group. Address would indicate the complement of Address.

C-MOS

Complementary - symmetry metal-oxide-semiconductor. A logic form involving both P-channel and N-channel MOS-FETS featuring low power requirments, high noise immunity, and large Fan-in/ Fan-out capability.

COUNTER

A counter is a device which will maintain a continuous record of the number of pulses which it has received at its input. The output of the counter indicates the sum of the number of input pulses.

D-TYPE FLIP-FLOP

AD-type flip-flop will propogate whatever information is at its D (Data) input prior to the clock pulse, to the Q output, on receipt of a clock pulse.

DECODER

A decoder is a device used to convert information from a coded form into a more usable form (e.g. Binary-to-decimal decoder).

DIGIT

A digit is one character in a number. There are 10 digits in the decimal number system (0-9) there are two digits in the binary number system (1 & 0).

EIA

Electronic Industries Association - responsible for establishing electrical industries standards. EIA voltage levels for data communication are summarized in the data communication specifications section of the manual (Section I, Table 1-1).

BTX - End of Text character. Used to terminate a message. 8 bits in length with·the following form.

BIT O BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

1 1 0 . 0 0 0 0

* BIT 7 may also be a "O" depending on the jumper options employed. Refer to Maintenance Section 4 of this manual for further explanation.

6058, p. 6-8

1

Ul'tlVl't .)ffl I"" • .,,unAL ~

EXCLUSIVE - OR

The exclusive or function is valid, or its value is 1, if one and only one of the input variables is present. The exclusive or applied to two variables is present, or 1, if the two binary input variables are different.

FLIP-FLOP

A flip-flop is a storage device which can be used to retain one bit of information. A fl.ip-flop can be in the. "1" (set) state or the "0 11 (reset) state. In the 11 1" state, its Q output presents a high level and its Q output a low level. In the 11 0" state, its Q output presents a low level and its Q output a high level. (See D-type and J-K Flip-Flop).

FSK

Frequency shift keying. The form of frequency modulation in which the modulating wave shifts the output frequency between predetermined values, and the output wave has no discontinuity. Commonly, the instantaneous frequency is shifted between two discrete values termed the mark and space frequencies.

GATE

A logic circuit having two or more inputs and a single output designed to give an output signal only when a certain combination of input signals exists.

HEXADECIMAL

(16 digits O thru F) is a numbering system with a base of 16

HEX DECIMAL BINARY -----0 0 131313~ 1 1 J.J fiJ Jll 2 2 ~Jll/3 3 3 J.J fiJll 4 4 J,Jlj J.J 5 5 J,Jlf,Jl 6 6 J,Jllf,J 7 7 /3111 8 8 lf,J 13 J.J 9 9 ljf,Jl A 10 lfiJl/3 B 11 1/311 c 12 11/3/3 D 13 11/31 E 14 111/3 F 15 1111

6058, p. 6-9

OJ UNION SWITCH & SIGNAL

INVERTER

An inverter (Not Gate) is a device which performs the operation of inversion. It will present at its output the inverse or complement of the information at its input.

J-K FLIP-FLOP

A J-K Flip-Flop has two conditioning groups of inputs (J&K) and a clock input. If both J&K inputs are low prior to the clock pulse it will remain in its initial condition when the clock pulse occurs. If the J input is high and the K input LOW, the flip-flop will go to the "1" (Set) state on receipt of the clock pulse; when the J input is LOW, and the K input HIGH, the flip-flop will switch to the "O" (Reset) state at

· the clock pulse. When both J&K are high the flip-·flop will complement its initial state.

NANO GATE

A NANO gate is enabled when both of its inputs are present or HIGH. When a NANO gate is enabled, its output is LOW. The term NANO is a contraction of the words NOT AND.

NOR GATE

A combination of a NOT (inverter) and an OR circuit. A Binary circuit having two or more inputs and a single output, in which the output is OFF ("O") if any one of the inputs is on ("1") and on ("1") only if all inputs are off ("O") together.

RESET

A signal which restores a storage device or system to a prescribed state.

SHIFT REGISTER

A shift register can contain several bits of information. When a shift pulse occurs all the information in the register is shifted one place.

STX

Start of Text character - use to begin a message •. 8 Bits in length with the following form.

BIT O BIT l BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

0 1 0 0 0 0 0 1

6058, p. 6-10

,-

UNION SWITCH & SIGNAL \,,,IJ

SYN

Synchronization character. Transmitted at the beginning of each message. 8 Bits in length with the following form.

BIT O BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

0 1 1 0 1 .0 0 1

SYNCHRONOUS

A system in which the sending and receiving instruments are operating continuously at substan:tially the same rate and are maintained by means of correction if necessary. In a synchronous system each event, or the performance of each operation, starts as a result of a signal generated by a clock.

THRESHOLD

The value of a physical stimulas (voltage) that permits a signal to be seen a specific percentage of the time o.r at a specific accuracy level. The voltage level required to change the state of a Binary Logic Circuit.

TTL

Transistor-Transistor Logic. TTL voltage levels for data communications are summarized in the data communications specifications section of the manual (Section I, Table 1-1).

TRISTATE

Refers to an output condition of three states. Either On (1), Off (0) or a high impedance state.

WORD

An ordered set of characters that is the normal unit in which information is stored, transmitted or operated on. 8 Bits in length for the AD~-256 System.

6058, p. 6-11


6.5 ORDERING INFORMATION

Equipment - Order by WABCO type or model number specifying option numbers where required.

Replacement Parts - Order by WABCO part number and a brief description whenever possible. If this information is not available, specify model number of equipment on which it is used, symbol number if applicable and a complete description.

ADDRESS OF ORDERS

Address all orders, correspondence relating thereto and requests for quotations to:

RETURNED MATERIALS

Customer Service Department WABCO Union Switch & Signal ·Division 1789 South Braddock Ave. Swissvale, Pa. 15218

Should it become necessary to return material to us for any reason, your cooperation in observing the following procedure is requested.

Before any materials are returned to us contact a WABCO representative and request return authorization for the material to be returned. It will be necessary for us to know the following:

1. The purchase order or WABCO general order number on which shipment was made.

2. Date of order.

3. Complete description of material to be returned including part or type number and serial number of complete units. ·

4. Why material is being returned.

5. Disposition desired, to be replaced, repaired or for credit.

With the above information, return authorization forms will be forwarded to you. Retain one copy for your file and use the second as a packing slip with the returned material. Mark the outside of the shipping carton with the Return Authorization Number. Address all shipments to:

6058, p. 6-12

Customer Service Department WABCO Union Switch & Signal Division 1789 South Braddock Ave. Swissvale, Pa. 15218

UNION SWITCH & SIGNAL \JJ

When material is received by us, repairs or replacement will be made as. quickly as possible or credit will be issued.

6058, p. 6-13

w UNION SWITCH & SIGNAL

ADL 256 MANUAL EXCEPTIONS

FOR NYCTA

PAGE

1-6 Input response time for UN085722-1011 is not applicable for NYCTA.

1-6 Data rate for NYCTA is 300 bits per second

1-6 Data Interface for NYCTA is EIA standard RS-232-C

1-6 Mode of operation is asynchronous for NYCTA

1-6 Option UN085721-101X not applicable for NYCTA

1-7 Reed Relay Interface is not applicable for NYCTA

1-8 Control delivery is not appiicable for NYCTA

1-9 Data rate for NYCTA is 300 bits per second

1-9 Data Interface for NYCTA is EIA standard RS-232C

1-105 1-11 Receiver Relay Interface is not applicable for NYCTA 1-12

2-1

2-2

2-11

2-13

2-13

2-13

Receiver Relay

Figure 2-1 not

Section "2.3.4

UN085721-1011

UN085722-1011

UN085725-1001

Interface is not applicable

applicable for NYCTA

not applicable for NYCTA




2-14 Figure 2-9 not applicable for NYCTA

for NYCTA

3-6 Figure 3-2 Relay Flashing Option not applicable for NYCTA


4-5 Table 4-1 Jumper Jl is not installed for NYCTA

4-6 Station address switch is in position "C" for NYCTA

4-11 Jumper Jl is not'installed for NYCTA

4-14 Station address switch is in position "Cd for NYCTA

6058 I P • 6-14

UNION SWITCH & SIGNAL \..I.I

ADL-256 MANUAL EXCEPTIONS FOR NYCTA (Continued)

PAGE

4-15 Station address switch is in.position "C" for NYCTA

·s-9 Jumper Jl is not installed for NYCTA

5-10 Section 5.3.6 Data Interface for NYCTA is EIA standard RS-232C

5-17 Figure 5-6 Jumper J2 installed for NYCTA

5-18 Components C5,C6,D30, IC27 and IC28 not applicable for NYCTA

5-20 Component RLY-1 not applicable fo~ NYCTA

5-21 Section 5.3.9 not applicable for NYCTA

5-22 OPTO Interface PCB is UN085722-1001 for NYCTA

5-29 Bit Rate for NYCTA is 300 Bits Per Second

5-30 Jumper J2 is installed for NYCTA

5-30 Section 5.5.3 Jumper Jl is not installed for NYCTA

5-31 Section 5.5.6 NYCTA is EIA therefore jumpers between pins A17 & U and Al6 & T and between pins All & Mand A12 & N are installed.

5-39 Figure 5-13 Jumpers J2, J3, J4 and JS installed for NYCTA

s-s1J Section 5.7 not applicable for NYCTA 5-52

5-53} 5-54

Figure 5-17 not applicable for NYCTA

s-ssJ 5-56

Figure 5-18 not applicable for NYCTA


5-58 Not applicable for NYCTA

6058, p. 6-15

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