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Peripheral Parallel Interface (PPI)
ADI CAST 2005
Who have PPI in Blackfin Family? Advanced TechnologyIn Development
2xPPI, 4xSerial Ports, USB2.0
BF56x
PRESENT FUTURE
Perf
orm
ance
BF535
BF561
msp500SoftFone
PCI, USB4xTimers, Watchdog Timer16xGPIO, RTC
400-600 MHzPPI, 16-bit EBIU4xSerial Ports
GSM/GPRS/EDGE;Full 4-slot receive; Low standy power
500–600 MHz2xPPI, 32-bit EBIU4xSerial Ports
BF56x4xPPI, 4xSerial Ports, 10/100 Ethernet MAC, PCI, HPI
BF539
PPI, 10xSerial Ports, I2C, CAN
BF536/537
PPI, 5xSerial Ports, I2C, CAN, 10/100 Ethernet MAC
Mobile Handsets, Smart Phones and PDAs
Consumer Media
msp5xxSoftFone
Multimode, multimediawireless handsets;Low standy power
BF533-750
BF561-750
BF534
PPI, 5xSerial Ports, I2C , CAN, 48xGPIO
PPI, 3xSerial Ports, USB2.0
BF53x
BF533
BF532
BF531
Automotive, Industrial and Instrumentation
756 MHzPPI, 16-bit EBIU4xSerial Ports
756 MHz2xPPI, 32-bit EBIU4xSerial Ports
Blackfin PPI feature
Bidirectional, half-duplex interface
Supports bit-parallel CCIR-656 recommendation
Can optionally ignore Field 2 (don’t DMA)
Works hand-in-hand with 2D DMA Engine
Can skip even or odd data elements
Supports 16-bit data packing mode
4 control signal polarity choices (H,V,CLK)
Up to 66MHz rate (SCLK/2)
Blackfin PPI feature cont..
BF561’s extra important feature of PPI Two independent PPI(PPI0 and PPI1)Supports 32-bit data packing modeEach PPI are Bidirectional, half-duplex interface
In future, new member of blackfin family will have a PPI with more large size of PPI buffer (it will make PPI work more efficiently and avoid more problem caused by DMA bandwidth)
PPI architecture
Up to 16 data lines, 1 clock, 3 Frame Syncs4 dedicated pins (PPI4 – PPI0)12 multiplexed PF pins (PF4 – PF15)PPI_CLK pin operating up to SCLK/2Frame Syncs 1&2 muxed with Timer pinsFrame Sync 3 muxed with UART RX (TBD)
DAB PPIPPI CLK max. SCLK/2
FS1/HSYNC/TIMER1
FS2/VSYNC/TIMER2
FS3/FIELD/PF3
Data Bus
PAB
8-16 bits
PPI Memory-Mapped Registers
PPIx_CONTROL – Controls setup and operation of PPI
PPIx_STATUS – Reports FIFO and bit errors, as well as Field #
PPIx_DELAY – Holds # of cycles to delay before latching in data (GP I/O modes only)
PPIx_COUNT – Contains # of samples (per row) to latch in or drive out
PPIx_FRAME – Used for frame synchronization
Blackfin PPI ITU656 mode
ITU-656 Input (3 Modes)
Entire Field (H and V Blanking, Active Video and control codes) Vertical Blanking Interval only (with associated H blanking)Active video only
Supports non-NTSC/PAL if properly formatted for ‘656 Can drop every other field for bandwidth savings
ITU-656 Output
User sets up blanking and encoding info in memory
Blanking
Line 1Line 2Line 3
Line 261Line 262Line 263
Video
Line 1 Line 2 Line 3 Line 261 Line 263
t
Video8-16 bit
BUS Blank
(H)SYNC
(V)SYNC(F)IELD
CVBS
Video Video VideoBlank Blank Blank
Line 262
Video Blank
Video Framing
DAB
PAB
FIFO16-bit wide
16 deep
DMA Controller
PPI_CONTROL
PPI_STATUS
PPI_COUNT
PPI_DELAY
PPI_FRAME
Data Bus
FF 00 00 C7 10 80 …EF 38 EE
PCHK
PACK GATE
FF
00
00
XY
80
10
80
10
80
10
FF
00
00
XY
CB
Y CR
Y CB
Y CB
Y FF
00
EAV SAV EAV
4 268 4 1440
Blanking Active Video
- PCHK: Preamble Check Unit- PACK: 8->16-Bit Packing Unit- GATE: Data Control Unit
8bit
Dat
a B
us
DMA Request
PPI_CLK
PPI ITU-656 Input Mode
PPI ITU-656 Output Mode
DAB
PAB
DMA Controller
FIFO16-bit wide
16 deep
PPI_CONTROL
PPI_STATUS
PPI_COUNT
PPI_DELAY
PPI_FRAME
Data Bus
UPACK GATE
37 ED 38 EF…80 10 C7 00 00 FF
- UPACK: 16->8-Bit Unpacking Unit- GATE: Data Control Unit
DMA Halt
PPI_CLK
Blackfin interface with video Codec
Blackfin can interface with video codec with PPI .Most video codec support ITU656 mode.
Advantage1: Can save sync signals ,Just data bus and PPICLK is needed for interface decrease the complexity HW design. Advantage2: Avoid the timing error bring up in the sync signal transfer.
PPI use external CLK (mostly 27Mhz in video application)
PPI in ITU656 mode
8- or 10-bit data w/embedded control
CLK
‘656-Compatible Video Source
PPI
PPIx
PPI_CLK
8- or 10-bit data w/embedded control
CLK‘656-Compatible Video Display
PPIx
PPI_CLK
PPI Configuration in ITU 656 mode In/Out
Just two PPI registers need initialize//The PPI is set to receive 525 lines for each NTSC frame 625 for Pal frame*pPPI_FRAME = 525;
//PPI enabled, input mode, active video only, receive field 1&2, packing enabled, //DMA16 enabled, skipping disabled, 8bit //data bus, nothing inverted*pPPI_CONTROL = PORT_EN | FLD_SEL | PACK_EN | DLEN_8 ;
PPI DMA setting://Target address of the DMA*pDMA0_START_ADDR = 0x0;
*pDMA0_X_COUNT = ?;
*pDMA0_X_MODIFY = ?;
*pDMA0_Y_COUNT = ?;
*pDMA0_Y_MODIFY = ?;
//DMA Config: Enable DMA | Memory write DMA | Discard DMA FIFO before start |// enable assertation of interrupt | NDSIZE for stop mode | Enable STOP DMA*pDMA0_CONFIG = DMAEN | DI_EN | WNR | WDSIZE_32 | RESTART | DI_EN;
Frames and Frame Synchronization
Synchronization in 656 mode always occurs at the start of Field 1 (F = 0).
PPI_COUNT register is not necessary.
PPI_FRAME register is used to check for synchronization errors
if an SAV transition is missed, resynchronization will reoccur at the next V or F signal
How to control Video codec in blackfin ?
ADV7183
ADV7171
BF533
PFx
PFy
SCL
SCL
SDA
SDA
•Can use 2 PF pins to emulate 2-wire protocols such as SCCB and I2C in software
Blackfin General Purpose mode
Single Sync (FS1 only)Useful for Data Converter applications“Infinite Capture” input sub-mode requires either
initial H/W sync to be sent, or“Self Trigger” through S/W write (no need for H/W FS)
3 Syncs (FS1, FS2, FS3)useful for video I/O with H/W signaling“Frame Capture” mode outputs syncs from processor while data is input into processor2 Syncs can be used by ignoring 3rd sync where appropriate (pullFS3 to ground)
Modes are set in PPI_CONTROL register
Single Sync Input Mode
PPI_CLK, PPI_FS1, PPI_DATA are inputsProgrammable delay register (PPI_DELAY) inserts a time delay (inunits of PPI_CLK cycles) to start transfer after FS1 has been assertedCount register (PPI_COUNT) holds the number of samples the PPI will receivePPI_COUNT ignored during Infinite Capture
PPI_CLK
PPI_FS1
PPI_DATA
PPI_DELAY
1 2 3 N-1 N
PPI_COUNT
Three Sync Input Mode
PPI_CLK, PPI_FS1/2/3, PPI_DATA are inputsCoincident assertion of FS1 and FS2 with FS3 low indicates the start of a frame
FS3 used to indicate odd/even fields. In a 2-FSx configuration, this line is pulled low.
PPI_FRAME register is set to the number of lines per frame (lines are delineated by FS1 assertions)
PPI_CLK
PPI_FS1
PPI_DATA
PPI_DELAY
1 2 3 N-1 N
PPI_COUNT
PPI_FS2
PPI_FS3
DAB
PAB
DMA Controller
FIFO16-bit wide
16 deep
PPI_CONTROL
PPI_STATUS
PPI_COUNT
PPI_DELAY
PPI_FRAME
FS1
FS2
FS3
Data Bus
10 80 10 80…….EF 38 EE
SYNCPACK GATE
- PACK: 8->16-Bit Packing Unit- GATE: Data Control Unit- SYNC: Data Sync Unit
DMA Request
PPI_CLK
PPI General Purpose Input Mode
Frame Capture Input Mode
PPI_CLK, PPI_DATA are inputsPPI_FS1, PPI_FS2 are outputs
TIMER1_WIDTH/TIMER1_PERIOD used to set up PPI_FS1 timingTIMER 2 set up to generate PPI_FS2 timing
PPI_FRAME register is set to the number of lines per frame (lines are delineated by FS1 assertions)
PPI_CLK
PPI_FS1
PPI_DATA
PPI_DELAY
1 2 3 N-1 N
PPI_COUNT
PPI_FS2
TIMER1
TIMER2
DAB
PAB
DMA Controller
FIFO16-bit wide
16 deep
PPI_CONTROL
PPI_STATUS
PPI_COUNT
PPI_DELAY
PPI_FRAME
PPI_CLK
Data Bus
UPACK GATE
37 ED 38 EF…80 10 C7 00 00 FF
- UPACK: 16->8-Bit Unpacking Unit- GATE: Data Control Unit- TIMER1/2: Make use of Timers
DMA Halt
FS1
FS2
PPI_CLK
PPI General Purpose Input Mode Frame Capture
Single Sync Output Mode
PPI_CLK is inputPPI_FS1 and PPI_DATA are outputs
Timer 1 used to set up timing for FS1There is a 1-cycle delay between FS1 assertion and start of PPI_DELAYCount register (PPI_COUNT) holds the number of samples the PPI will output, less one (i.e., set for N-1)
PPI_CLK
PPI_FS1
PPI_DATA
PPI_DELAY
1 2 3 N-1 N
PPI_COUNT
Three Sync Output Mode
PPI_CLK is inputPPI_FS1, PPI_FS2, PPI_FS3 and PPI_DATA are outputs
Timer 1 used to set up timing for FS1Timer 2 used to set up timing for FS2FS3 toggles coincident with an FS1 assertion, after an FS2 assertion
PPI_CLK
PPI_FS1
PPI_DATA
PPI_DELAY
1 2 3 N-1 N
PPI_COUNT
PPI_FS2
PPI_FS3
TIMER1
TIMER2
DAB
PAB
DMA Controller
FIFO16-bit wide
16 deep
PPI_CONTROL
PPI_STATUS
PPI_COUNT
PPI_DELAY
PPI_FRAME
PPI_CLK
Data Bus
UPACK GATE
37 ED 38 EF…80 10 C7 00 00 FF
- UPACK: 16->8-Bit Unpacking Unit- GATE: Data Control Unit- TIMER1/2: Make use of Timers
DMA Halt
FS1
FS2
FS3/PF3
PPI_CLK
PPI General Purpose Output Mode
Interface with high-speed ADC
8-16 bits data
CLK
HSYNC
A/D Converter
PPI_FS1
PPIx
PPI_CLK
Mostly use GP single sync input mode
Interface with high-speed DAC
8-16 bits data
CLK
HSYNCPPI_FS1
PPIx
PPI_CLK
Mostly use GP single sync output mode
Interface with CMOS sensor
Mostly use GP Frame capture mode
8-16 bits dataCLK
HSYNCVSYNC
PPIPPI_FS1PPI_FS2
PPIx
PPI_CLKImage Source
Interface with TFT LCD display
Mostly use GP Frame Syncs Output mode
5-6-5 RGB dataCLK
HSYNCVSYNC
PPIPPI_FS1PPI_FS2
PPIx
PPI_CLK
TFT LCD
HSYNCVSYNC
Hands on
This hands on will show :1. How to interface Blackfin with LCD 2. How to configure the LCD driver
backgroundBF533 is used as controller to driving LCD based on PPI GP modeLCD (Sharp LQ035Q7DB02 ) is 640x480 pixels .
Operation:Every student could configure the LCD driver code as following slideGive their own configuration and try it in Eflag’s blackfin demo platform
PPI configuring
A 16-bit RGB (5-6-5)word is sent out through the PPI. The PPI sends this data in general purpose mode with one frame sync to indicate the start of each transmitting line. The registers necessary in configuring the PPI to correctly send data to the LCD panel are:
Delay register: This register contains the number of PPI1 clock cycles to delay after the assertion of the PPI1_FS1 frame sync pin before transmitting the output data. Count register: This register holds the number of words to writeout through the PPI per line, minus one. Control register: Through this register, the PPI is configured to send data in general purpose transmit mode with 1 frame sync anda data length of 16 bits.
PPI configuring cont.
Delay register: This register contains the number of PPI1 clock cycles to delay after the assertion of the PPI1_FS1 frame sync pin before transmitting the output data.
Count register: This register holds the number of words to write out through the PPI per line, minus one.
Control register: Through this register, the PPI is configured to send data in general purpose transmit mode with 1 frame sync and a data length of 16 bits.
Timer configuring
This hands on use Timer1 and Timer 2 of BF533 to generate timing ASIC normally required to generate specific timing signals required for the row and column drivers of the LCD panel.
Normally Timer1/2 will generate the Hsync and Vsync for LCD panel. In configuring the timers to generate the appropriate signals, three registers must be carefully configured:
Period register.Width register.Configuration register.
Timer configuring cont.
Period register: This register holds the period of the waveform. This register must be configured according to the datasheet of the LCD panel for the exact timing required to be generated.
Width register: This register holds the pulse width of the waveform. care must be taken to ensure that the pulse width is programmedaccording to the timing requirements specified in the LCD panel’s data sheet.
Configuration register: This register specifies the operating mode of the timers.It is through this register that the timers are configured for PWM mode, SCLK is selected as the clock counter, and the polarity of the pulse is configured as either positive or negative.
PPI DMA configuring
The PPI DMA should be configured for the transmission of data.
For the DMA transmit configuration, MMRs are written directly, The following registers are written directly:
X and Y Count registers .X and Y Modify registers.Configuration register.
PPI DMA configuring cont.
X and Y Count registers: In this particular application, the output frame size is 480 bytes * 329 lines. Since the word size used is 32 bits, the X Count register is configured to be 120 (480/4), and the Y Count register is configured to be 329.
X and Y Modify registers: Since the word size used is 32 bits, the number of bytes to modify after each read is 4 (32-bits = 4 bytes).
Configuration register: In this register, we define the DMA mode to be autobuffer model
Setting code
void Init_PPI(void){
*pPPI_CONTROL = ?; //Generic 3-sync mode*pPPI_DELAY = ?; // cycle delay before writing out data*pPPI_COUNT = ?; //640 samples per line
}
void Init_PPIDMA(void){
*pDMA0_START_ADDR = ?;*pDMA0_CONFIG = ?; //Autobuffer mode, 2D, 16-bit transfers, Tx
*pDMA0_X_COUNT = ?;*pDMA0_X_MODIFY = ?;*pDMA0_Y_COUNT = ?;*pDMA0_Y_MODIFY = ?;
}
void Init_Timer(void){
*pTIMER_DISABLE = ?;
*pTIMER1_CONFIG = ?;*pTIMER1_PERIOD = ?;*pTIMER1_WIDTH = ?;
*pTIMER2_CONFIG = ?;*pTIMER2_PERIOD = ?;*pTIMER2_WIDTH = ?;
}