Peripherals

Alexander Nelson

September 30, 2019

University of Arkansas - Department of Computer Science and Computer Engineering

Peripherals

Peripherals – on MSP432P401R

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Peripherals

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Common Peripherals

Common peripherals available:

• GPIOs

• Timers/Counters (General)

• Watchdog Timer

• Analog to Digital Converter

• Digital to Analog Converter

• Serial (UART, SPI, I2C)

• Memory (EEPROM/Flash)

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What are Timers/Counters

Hardware element that counts

• Timers count clock cycles

• Counters count arbitrary signal changes

Counts up to threshold and sets interrupt flag

• CPU can poll interrupt flag

• CPU can be interrupted and driven by interrupt flag

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Components of a Timer/Counter

Components:

• Clock Prescaler (Divider)

• Clock source selection (If there are multiple clocks)

• N-Bit timer/counter (Actual count value)

• Compare Registers

• Capture Registers

• Control Logic

• Status/Control Registers (Define behavior)

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Timer Hardware

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Clock Selection

Clock selection – Choose clock source that is close to, but faster

than needed value

MSP432P401R – Up to 48MHz system clock

Internal 32.768kHz LFXT Oscillator (can be bypassed for external

clocking) Internal High-frequency crystal support up to 48MHz

(HFXT)

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Clock Selection

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Clock Prescaling

Clock Prescaler modifies rate at which timer changes

Allow timer/counter to cover larger range

# of Necessary bits can be determined by:

log2(∆t × Freqclock)

Example: (0.5s range ×1, 000, 000 = 19bits

Divide clock to reduce # of bits

Example (Clock divided by 64): (0.5s range ×1,000,00064 = 14bits)

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Clock Prescaling

Precision/Range of timer are direct tradeoffs

Higher range = lower precision

Usually # of bits is fixed by the hardware

Example:

MSP432 has 4 16-bit counters/timers & 2 32-bit counter/timer

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Compare Register

Compare Register – Hardware for control-defined comparison

Detect if counter <,>, or == compare register

Can:

• Trigger interrupt

• Set flag for polling

• Drive changes on external pins

• Reset counter register

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Capture Register

Capture Register – Dedicated hardware for capture time of event

When external event occurs, counter register value latched to

capture register

Why is this necessary? What is the software equivalent & issues?

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Capture Register

Capture Register – Dedicated hardware for capture time of event

When external event occurs, counter register value latched to

capture register

Why is this necessary?

Software driven capture may miss one or more timer counts before

reading register

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Timer/Counter Polling

Can poll from register & read value

e.g.

while(COUNTER_REG < VALUE);

Can be used to perform timer-polling based delay

Reasonable & predictable accuracy compared to software delay

Especially useful when other actions are being performed (e.g. tick

functions)

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Getting Desired Timing

Takes some thought to get close to desired frequency

Resulting Frequency = input-clock/prescaler/(maxcount+1)

• Max Count may be defined by compare reg or max value of

counter

• Clock division = prescaler * (maxcount+1)

• You must choose the prescaler & max count to get clock

scaling you want

• Prescaler typically limited to a few select values

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Example

Assume 1MHz input clock, need 3kHz period from 8-bit timer.

Design a timer using clock division and a compare register to meet

this timing:

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Exercise

Exercise:

Design a timer-based loop for calling synchronous tick functions

Two tick functions – One @ 10Hz, One @ 50Hz

Assume System clock of 1MHz, External oscillator of 32.768kHz

Choose a clock & prescaling (must be power of 2) to fit in 8-bit

timer

Write the control loop to call these two functions

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Timer Actions

Timer can be set up to regularly do one or more:

• Trigger an interrupt

• Cause hardware to make pin value change

• Reset timer

Actions can occur on one of the following:

• Overflow

• Compare/Match events

Automatic pin changes allow for precise & flexible digital waveform

generation

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Simultaneous Timers

Sometimes multiple irregular (perhaps simultaneous) timing events

are needed

Leapfrogging – Moves compare value in software instead of

resetting the counter in hardware

Useful if multiple timers are to be implemented with limited set of

hardware timers

Ex: timing event and preserve total time

• Set compare register for first trigger event and set up ISR

• Reset and start counter

• Upon call of ISR, determine next event value and set compare

register

• Repeat

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Extending Timer (software + overflow)

Effective timer/counter range can be extended using software and

the overflow bit

Example: count 10.5 *max counter

• Start counter, value = 0

• Counter overflows (overflow bit set)

• Software detects overflow, increments value resetsoverflow flag

• Value reaches 10, ISR set on compare register

• Counter hits 12 max, interrupt occurs

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Multi-byte timer Access

Reading/Writing to multi-byte timers needs consideration

Example:

• Counter contains 0x00FF

• Read lower byte

• Counter ticks

• Read upper byte

• Yields 0x01FF, rather than 0x100

Usually some hardware that loads opposite byte into temporary

hardware

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Output Modes

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UART

UART – Universal Asynchronous Receiver-Transmitter

Asynchronous – No shared clock

Each device responsible for own timing of known transmission

frequency

Common BAUD rates – 110, 150, 300, 1200, 2400, 4800, 9600,

19200, 38400, 57600, 115200, 230400, 460800, 921600

Generating these frequencies is similar to generating frequency for

timer

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UART Timing

Timing requires

• Clock selection

• Clock

prescaling

• Clock

Modulation

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