pex 8648-aa rdk - broadcom...adapter board that plugs into the host system, four mini-sas cables and...

PEX 8648-AA RDK Hardware Reference Manual

Version 1.2

December 2010

Website: www.plxtech.com Technical Support: www.plxtech.com/support

Copyright © 2010 by PLX Technology, Inc. All Rights Reserved – Version 1.2 December 6, 2010

© 2010 PLX Technology, Inc. All Rights Reserved.

PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.

PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc.

Other brands and names are the property of their respective owners.

Document Number: 8648-AA RDK-HRM-1.2

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2 Copyright © 2010 by PLX Technology, Inc. All rights reserved ii

Contents Preface ...................................................................................................................................................................... iv

Notice ..................................................................................................................................................................... iv About This Manual ................................................................................................................................................. iv Revision History...................................................................................................................................................... iv

1 General Information ............................................................................................................................................. 1 1.1 PEX 8648 Switch Features ............................................................................................................................ 2 1.2 PEX 8648 RDK Base Board Features ........................................................................................................... 2

2 System Architecture ............................................................................................................................................. 3 3 Hardware Architecture ......................................................................................................................................... 5

3.1 PCI Express Port Configuration ..................................................................................................................... 5 3.2 Non-Transparent Operation ......................................................................................................................... 12 3.3 PCI Express Hot-Plug Circuitry ................................................................................................................... 12 3.4 Reference Clock Circuitry ............................................................................................................................ 14 3.5 Port Configuration and Status LED Indicators ............................................................................................. 16

3.5.1 PORT STATUS LED Indicators ............................................................................................................ 17 3.5.2 UP PORT LED Indicators...................................................................................................................... 17 3.5.3 NT PORT LED Indicators ...................................................................................................................... 17

3.6 Hardware Strapping Balls ............................................................................................................................ 18 3.7 Power Circuitry ............................................................................................................................................ 20 3.8 Reset Circuitry ............................................................................................................................................. 21 3.9 Serial EEPROM Interface (U2) .................................................................................................................... 21 3.10 JTAG Interface (JP7) ................................................................................................................................... 22 3.11 I2C Interface (JP8 and JP9) ......................................................................................................................... 22 3.12 Device-Specific Sideband Signals ............................................................................................................... 23

3.12.1 FATAL_ERR# (TPV22, DS1) ................................................................................................................ 23 3.12.2 PEX_INTA# (TPV21, DS2) ................................................................................................................... 23 3.12.3 PEX_NT_RESET# (TPV49) .................................................................................................................. 23

4 Base Board Mechanicals/Component Placement ............................................................................................. 24 4.1 Monitoring Point, LED Indicator, and Control Summary ............................................................................. 25

4.1.1 Monitoring Points .................................................................................................................................. 25 4.1.2 LED Indicators ....................................................................................................................................... 26 4.1.3 Controls ................................................................................................................................................. 27

4.2 Board Layout Information ............................................................................................................................ 28 4.2.1 Trace Routing Design Rules ................................................................................................................. 28 4.2.2 Power De-Coupling ............................................................................................................................... 28 4.2.3 PCB Layer Stackup ............................................................................................................................... 30

5 References ......................................................................................................................................................... 31 6 Bill of Materials & Schematics ............................................................................................................................ 32

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2 Copyright © 2010 by PLX Technology, Inc. All rights reserved iii

Figures Figure 1. PEX 8648 RDK Base Board Component Layout ....................................................................................... 1 Figure 2. PEX 8648 RDK Being Used in a PC .......................................................................................................... 3 Figure 3. PEX 8648 RDK Base Board Component Layout ....................................................................................... 4 Figure 4. Station 0, x4 UP and x4x4x4 DOWN ......................................................................................................... 7 Figure 5. Station 0, x16 UP ....................................................................................................................................... 7 Figure 6. Station 0, x8 UP and x8 DOWN (Factory Default) ..................................................................................... 8 Figure 7. Station 0, x8 UP and x4x4 DOWN ............................................................................................................. 8 Figure 8. Station 0, x8 UP and x8 NT ........................................................................................................................ 9 Figure 9. Station 0, x4 UP, x4 NT, and x4x4 DOWN ................................................................................................. 9 Figure 10. Station 1, x4x4x4x4 DOWN .................................................................................................................... 10 Figure 11. Station 1, x16 DOWN ............................................................................................................................. 10 Figure 12. Station 1, x8x8 DOWN (Factory Default) ............................................................................................... 11 Figure 13. Station 1, x8x4x4 DOWN ....................................................................................................................... 11 Figure 14. PEX 8648 RDK Base Board PCI Express Hot-Plug Circuitry ................................................................ 13 Figure 15. PEX 8648 RDK Base Board Reference Clock Circuitry ......................................................................... 15 Figure 16. PEX 8648 RDK Base Board Port Configuration and Status LED Indicators ......................................... 16 Figure 17. PEX 8648 RDK Base Board Hardware Strapping DIP Switches – SW1, SW11,

SW4, SW5, SW9, SW6, SW2, and SW10, Default Settings ..................................................................... 18 Figure 18. PEX 8648 RDK Base Board Power Circuitry ......................................................................................... 20 Figure 19. JTAG Header (Top View) ....................................................................................................................... 22 Figure 20. I2C Headers (Top View) ......................................................................................................................... 22 Figure 21. TPV21, TPV22, DS1, and DS2 Placement on PEX 8648 RDK Base Board ......................................... 23 Figure 22. PEX 8648 RDK Base Board Mechanical Outline ................................................................................... 24 Figure 23. PEX 8648 RDK Base Board Dimensions ............................................................................................... 24 Figure 24. De-Coupling Capacitor Footprints .......................................................................................................... 28 Figure 25. PEX 8648 RDK Base Board Power Ball and Perimeter De-Coupling Capacitor Footprints

(Reverse Screen) ...................................................................................................................................... 29 Figure 26. PEX 8648 RDK Base Board External PCB Layer Stackup Report ........................................................ 30

Tables Table 1. PEX 8648 RDK Base Board Port Configurations ........................................................................................ 6 Table 2. PEX 8648 Switch Port Status LED On/Off Patterns, by State .................................................................. 17 Table 3. PEX 8648 RDK Base Board Hardware Strapping DIP Switches – SW1, SW11,

SW4, SW5, SW9, SW6, SW2, and SW10 ................................................................................................ 19 Table 4. PEX 8648 RDK Base Board Monitoring Points ......................................................................................... 25 Table 5. PEX 8648 RDK Base Board LED Indicators ............................................................................................. 26 Table 6. PEX 8648 RDK Base Board Controls ....................................................................................................... 27

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2 Copyright © 2010 by PLX Technology, Inc. All rights reserved iv

Preface

Notice This manual contains PLX Confidential and Proprietary information. The contents of this manual may not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.

PLX provides the information and data included in this manual for your benefit, but it is not possible to entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this information. The information in this manual is subject to change without notice. Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for any errors, or incidental or consequential damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8648 RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.

About This Manual This Hardware Reference Manual describes the PLX PEX 8648 Rapid Development Kit (PEX 8648 RDK), from a hardware perspective. It contains a description of all major functional circuit blocks on the PEX 8648 RDK base board, and serves as a reference for creating software for this product. This manual also includes a complete Bill of Materials and Schematics.

Revision History

Date Version Comments

March 2008 1.0 Initial release. Supports Board Revision 100, which includes the PEX 8648 switch, Silicon Revision AA.

November 2008 1.1 Minor update.

December 2010 1.2 Updated the schematic and BOM to reflect the new 360K ohm R170 resistor.

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2 Copyright © 2010 by PLX Technology, Inc. All rights reserved 1

1 General Information

The PLX PEX 8648 RDK is a Rapid Development Kit based upon PLX Technology’s ExpressLane™ PEX 8648, a 48-Lane, 12-Port, 3-Station PCI Express Gen 2 switch. The PEX 8648 RDK provides a complete hardware and software development platform to facilitate getting designs up and running quickly, lowering risk and reducing time-to-market. The PEX 8648 RDK consists of a base board containing three PEX 8648 hardware modules, an adapter board that plugs into the Host system, four mini-SAS cables and a SATA cable (used to connect the adapter board to the base board), and a Software Development Kit (SDK). The SDK is downloadable from the PLX web site, at www.plxtech.com/products/sdk.

This manual primarily focuses on the PEX 8648 RDK base board, and its use with other parts provided as part of the RDK. Figure 1 provides a component-side view of the PEX 8648 RDK base board.

RefClk 1:12

Fanout

Configuration Module

SATA

37.34 cm (14.7 inches)

U11

P2 Configuration ModuleP3

PEX864827 x 2716

31

0 15

32

47

OPEN

OPEN

OPEN

OPEN OPEN

OPENOPEN OPEN

Configuration ModuleP1

Figure 1. PEX 8648 RDK Base Board Component Layout

Note: In Figure 1 and other figures in this manual that represent the base board, the Port-related LEDs indicate a sample Port configuration. The figures do not show which LEDs are turned ON/OFF to match the indicated Port width and Port Numbers.


1.1 PEX 8648 Switch Features 48-Lane, 12-Port, 3-Station PCI Express Gen 2 switch

Standard 676-ball Flip Chip Plastic BGA (FCBGA) package (27 x 27 mm2) with Heat Spreader

480 GT/s aggregate bandwidth (5.0 GT/s/Lane x 48 SerDes Lanes x 2 (full duplex))

Non-blocking Crossbar Switch interface supports TLP bandwidth capacity of each x16 Link

Out-of-band communication/initialization interfaces (serial EEPROM and I2C)

2,048-byte Maximum Payload Size

Performance tuning

Choice of width (number of Lanes) per unique Link/Port – x4, x8, or x16

Allows any Port to be designated as the upstream Port (Port 0 is recommended)

Configuration with Strapping balls, serial EEPROM, or I2C

Lane reversal

Polarity reversal

Quality of Service (QoS) with one Virtual Channel (VC0) and eight Traffic Classes (TC[7:0])

Non-Transparent Bridging (NTB)

Read Pacing (intelligent bandwidth allocation)

Dual Cast

INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) ball support

Compliant to the following specifications:

PCI Local Bus Specification, Revision 3.0

PCI Bus Power Management Interface Specification, Revision 1.2

PCI to PCI Bridge Architecture Specification, Revision 1.2

PCI Express Base Specification, Revision 2.0

PCI Express Card Electromechanical Specification, Revision 2.0

The I2C-Bus Specification, Version 2.1

1.2 PEX 8648 RDK Base Board Features PLX PEX 8648 PCI Express Gen 2 switch in a 676-ball FCBGA package.

11 downstream PCI Express slot connectors. Hardware configuration is determined by plug-in Configuration modules.

DIP switches, for hardware configuration of the PEX 8648 switch.

Transparent or Non-Transparent (NT) switch support.

Two Hot-Plug-controllable slots – one through a Parallel Hot-Plug Controller interface, and one through the Serial Hot-Plug Controller interface.

Socketable serial EEPROM.

I2C interface, to read and write registers.

Manual pushbutton PERST#.

LED indicators for visual inspection of Port configuration and status.


2 System Architecture

The PEX 8648 RDK is a PLX Rapid Development Kit primarily intended for use by PLX customers for silicon evaluation and design reference for PEX 8648 switches in the 27 x 27 mm2 package. The PEX 8648 RDK consists of three main hardware components:

Base board, which is meant to lay on a benchtop and houses the PEX 8648 switch

PCI Express slot-to-cable adapter board, which is meant to plug into a PC platform for the upstream Port connection

Cable assembly, which connects the base board to the adapter board

Figure 2 provides a diagram of the PEX 8648 RDK, being used in a PC. Figure 3 represents the placement of major component blocks on the PEX 8648 RDK base board.

The PEX 8648 RDK base board is similar to a motherboard in form factor. The base board is meant to lay on a benchtop, and provides 11 PCI Express slots for add-in boards. Board power is supplied by an external ATX supply (P5). The PEX 8648 RDK base board supports up to 12 Ports (one upstream and 11 downstream). By default, the upstream Port is Port 0 and the NT Port is Port 1. All available Port width combinations are possible with the PEX 8648 RDK, by means of Configuration modules that enable versatile routing of the Lanes from the PEX 8648 switch to the PCI Express connectors. Controls are provided, to support Hot-Plug capability for Port 5 (Parallel Hot-Plug) and Port 8 (Serial Hot-Plug). On-board LED indicators display various configuration and status information. The power distribution system for the PEX 8648 RDK is such that accurate current draw measurements can be made, as well as supplying various PEX 8648 RDK base board supply voltages from an external source, for the purposes of voltage margining.

SAS

SAS

SAS

SAS

SATA

PERST#REFCLK

Lanes 0-3

Lanes 4-7

Lanes 8-11

Lanes 12-15

Host Motherboard

Adapter

RDK Base Board

Ref

Clk

1:

12

Fano

ut

Con

figur

atio

n M

odul

e

SATA

MICTOR

MICTOR

37.34 cm (14.7 inches)

37.34 cm (14.7 inches)

U11

CABLE SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 SLOT 9 SLOT 10 SLOT 11

PORT WIDTH

PORT NUMBER

UP PORTNT PORT

PORT STATUS

J1

J2

J3

J9

J10

J11

J6

J7

J8

J4

J5

IP1

IP2

IP3

IP4

P4

P5

P6

P7

P8

P9

P10

P11

J12 J13J14

JP11

JP13

JP12

P2C

onfig

urat

ion

Mod

ule

P3

SLOT8-HP SLOT5-HP

RESETPERST

1.0VDC

2.5VDC

PEX

8648

27 X

27

16

31

015

32

47

SASLanes 4-7

SASLanes 8-11

SASLanes 12-15

SASLanes 0-3

OP

EN

OPE

N

OPE

N

OPE

NO

PEN

OP

ENO

PEN

OP

EN

Con

figur

atio

n M

odul

eP1

Figure 2. PEX 8648 RDK Being Used in a PC


Figure 3. PEX 8648 RDK Base Board Component Layout


3 Hardware Architecture

3.1 PCI Express Port Configuration The PEX 8648 is a 48-Lane, 12-Port, 3-Station non-blocking PCI Express Gen 2 switch that supports Transparent and NT modes of operation. The footprint for the PEX 8648 switch is laid out so that a heat sink can be attached to the switch, or a high-speed BGA test socket can be loaded onto the PEX 8648 RDK base board.

The PEX 8648 RDK base board fixes the upstream Port at Port 0 and the NT Port at Port 1, by default. The upstream Port connects to the Host through four mini-SAS cables that carry four Lanes each, and a serial ATA cable that provides RefClk and PERST#. This is a significantly less-expensive and less-bulky solution than using a PCI Express cable. On the Host side, the mini-SAS cables pass through the PC’s bulkhead and attach to the PEX 8648 RDK adapter board, which plugs into one of the PC’s PCI Express slots, allowing the computer lid to be closed.

The PEX 8648 RDK adapter board has a x16 male edge connector, to support Port 0 as a x16 Port. If the adapter board is to be plugged into a smaller slot, a small Catalyst-style adapter must be used, which raises the adapter board by 18 mm (0.7 inches). This makes the upper-most mini-SAS connector inaccessible, which is acceptable, because this connector carries Lanes 12 through 15, which would not be used. Also, there is sufficient clearance for the computer lid to close. Each Station has four possible Port configurations – x4x4x4x4, x16, x8x8, and x8x4x4. The lowest four Lanes of Station 0 (Lanes 0 through 3) route directly to the lowest four Lanes of the SAS connectors, the lowest four Lanes of Station 1 (Lanes 16 through 19) route directly to the lowest four Lanes of Slot 4, and the lowest four Lanes of Station 2 (Lanes 32 through 35) route directly to the lowest four Lanes of Slot 8. The remaining 12 Lanes of each Station route to a Configuration module. These modules map the Lanes to the remaining mini-SAS and/or PCI Express connectors, as needed, to obtain the desired Port configuration. Table 1 describes how to set up the various Port configuration options for each Station.

Note: The possibilities for Station 0 are more complex, because it houses the upstream Port and NT Port.

The Configuration modules consist of a 10 x 40 ball board-to-board, high-speed connector, with one-half of the connectors mounted on the PEX 8648 RDK base board, and its mate mounted on a small 2-layer PCB that performs the re-mapping. There are no other components. There are four different Configuration modules, one for each possible Station configuration. Each module’s functionality is clearly labeled, and a 3-pin interface on each module communicates its function to the CPLD glue logic.

The PCI Express Lanes for Station 1 and Station 2, from the PEX 8648 switch to the Configuration modules, have soft touch midbus probe headers, for monitoring PCI Express traffic. Refer to the Agilent Soft Touch Midbus Probe User’s Guide, for further details regarding the headers.


Table 1. PEX 8648 RDK Base Board Port Configurations

Station 0 Port Configuration

Configuration Module Installed

(P1) SW2[2 – 1]

Setting Connectors

Used SW1[6] Setting Refer to

x4 UP x4x4x4 DOWN

x4x4x4x4 LL (IP1), J1, J2, J3 H Figure 4

x16 UP x16 LH (IP1, IP2, IP3, IP4) H Figure 5

x8 UP x8 DOWN

(Factory Default) x8x8 HL (IP1, IP2), J2 H Figure 6

x8 UP x4x4 DOWN

x8x4x4 HH (IP1, IP2), J2, J3 H Figure 7

x8 UP x8 NT

x16 HL (IP1, IP2), IP3, IP4 L Figure 8

x4 UP x4 NT

x4x4 DOWN x8x4x4 LL (IP1), IP2, J2, J3 L Figure 9



(P2) SW2[4 – 3]

Setting Connectors Used – Refer to

x4x4x4x4 DOWN x4x4x4x4 LL J4, J5, J6, J7 Figure 10

x16 DOWN x16 LH J4 Figure 11

x8x8 DOWN (Factory Default)

x8x8 HL J4, J6 Figure 12

x8x4x4 DOWN x8x4x4 HH J4, J6, J7 Figure 13



(P3) SW2[6 – 5]

Setting Connectors Used – –

x4x4x4x4 DOWN x4x4x4x4 LL J8, J9, J10, J11

x16 DOWN x16 LH J8

x8x8 DOWN x8x8 HL J8, J10

x8x4x4 DOWN (Factory Default)

x8x4x4 HH J8, J10, J11

Note: In Table 1, parenthesis around the IP components are used to indicate the connectors that comprise the upstream Port.


Figure 4 through Figure 13 illustrate the hardwire routing arrangement for each configuration. The routing for Station 2 is the same as for Station 1, except that it uses J8 through J11 and Lanes 32 through 47 of the PEX 8648 switch.

PEX

8648

27 x

27

16

31

015

32

47

Con

figur

atio

n M

odul

ex4

x4x4

x4

Figure 4. Station 0, x4 UP and x4x4x4 DOWN

PEX

8648

27 x

27

16

31

015

32

47

Con

figur

atio

n M

odul

ex1

6

Figure 5. Station 0, x16 UP


PEX

8648

27 x

27

16

31

015

32

47

Con

figur

atio

n M

odul

ex8

x8

Figure 6. Station 0, x8 UP and x8 DOWN (Factory Default)

PEX

8648

27 x

27

16

31

015

32

47

Con

figur

atio

n M

odul

ex8

x4x4

Figure 7. Station 0, x8 UP and x4x4 DOWN


SAS

SAS

SAS

SASLanes 0-3

Lanes 4-7

Lanes 8-11

Lanes 12-15

Host Motherboard

Adapter

PE

X86

4827

x 2

716

31

015

32

47

IP1

IP2

IP3

IP4P1

Lanes 0-3

Lanes 4-7

Lanes 8-11

Lanes 12-15C

onfig

urat

ion

Mod

ule

x16

J1

J3

J2SAS

SAS

SAS

SASLanes 0-3

Lanes 4-7

Lanes 8-11

Lanes 12-15

NT Motherboard

Adapter

Note: Station 0 must be configured as x8x8, but the ConfigurationModule used must be x16.

SASLanes 4-7

SASLanes 8-11

SASLanes 12-15

SASLanes 0-3

Figure 8. Station 0, x8 UP and x8 NT

SAS

SAS

SAS

SASLanes 0-3

Lanes 4-7

Lanes 8-11

Lanes 12-15

Host Motherboard

AdapterIP1

IP2

IP3

IP4P1

Lanes 0-3

Lanes 4-7

Lanes 8-11

Lanes 12-15

J1

J3

J2SAS

SAS

SAS

SASLanes 0-3

Lanes 4-7

Lanes 8-11

Lanes 12-15

NT Motherboard

Adapter

Note: Station 0 must be configured as x4x4x4x4, but the ConfigurationModule used must be x8x4x4.

SASLanes 4-7

SASLanes 8-11

SASLanes 12-15

SASLanes 0-3

Figure 9. Station 0, x4 UP, x4 NT, and x4x4 DOWN


PEX8

648

27 x

27

16

31

015

32

47

P2

J7

J6

J5

J4

Con

figur

atio

n M

odul

ex4

x4x4

x4

Figure 10. Station 1, x4x4x4x4 DOWN

PEX8

648

27 x

27

16

31

015

32

47

P2

J7

J6

J5

J4

Con

figur

atio

n M

odul

ex1

6

Figure 11. Station 1, x16 DOWN


PEX8

648

27 x

27

16

31

015

32

47

P2

J7

J6

J5

J4

Con

figur

atio

n M

odul

ex8

x8

Figure 12. Station 1, x8x8 DOWN (Factory Default)

PEX8

648

27 x

27

16

31

015

32

47

P2

J7

J6

J5

J4

Con

figur

atio

n M

odul

ex8

x4x4

Figure 13. Station 1, x8x4x4 DOWN


3.2 Non-Transparent Operation Only the Station 0 Ports – Ports 0, 1, 2, and 3 – support NT mode. By default, the NT Port is assigned to Port 1, by way of DIP switch SW1. To use the NT function, however, DIP switch SW1 must be used to Set the PEX 8648 switch’s Strapping balls so that the switch is in NT mode. Mini-SAS connectors are used to connect to the Host on the NT Port, by way of cables.

For further details regarding the various hardware configurations for NT mode, refer to Section 3.1, “PCI Express Port Configuration.”

For further details regarding DIP switch SW1, refer to Table 3, “PEX 8648 RDK Base Board Hardware Strapping DIP Switches – SW1, SW11, SW4, SW5, SW9, SW6, SW2, and SW10.”

For details regarding the PEX_NT_RESET# sideband signal, refer to Section 3.12.3, “PEX_NT_RESET# (TPV49).”

3.3 PCI Express Hot-Plug Circuitry The PEX 8648 switch supports Hot-Plug on three downstream Ports, by way of dedicated 10-signal Parallel Hot-Plug interfaces. In addition, a serial I2C interface, in conjunction with an external I/O Expander IC, can be used to support Hot-Plug on any Port. The PEX 8648 RDK base board has external Hot-Plug circuitry that supports Parallel Hot-Plug to Slot 5, and Serial Hot-Plug to Slot 8.

The PEX 8648 RDK base board supports Parallel Hot-Plug, only on Port 5 of Station 1, routed to Slot 5, and only when Station 1 is configured as x4x4x4x4. To support Parallel Hot-Plug, Slot 5 has a dual-voltage Hot-Plug Controller chip associated with it (U15), which controls power to this slot. If Port 5 is the upstream Port, the Strapping signals that Set the upstream Port are used to bypass the Hot-Plug circuitry for Slot 5.

Note: Other Port configurations that include Port 5 – x8x8 or x8x4x4 – do not support Hot-Plug. In this case, Port 5 routes to Slot 6, which does not include Hot-Plug circuitry.

The PEX 8648 RDK base board supports Serial Hot-Plug on Port 8 of Station 2 (U18). A serial I2C interface, with an external I/O Expander IC (U17), supports Serial Hot-Plug functionality on this slot. Because Port 8 is the primary slot on Station 2, Port configuration of Station 2 does not matter. Port 8 is always Hot-Plug-capable.

Figure 14 illustrates the PEX 8648 RDK base board PCI Express Hot-Plug circuitry.


SLO

T8-HP

SLO

T5-HP

RefClk 1:12

Fanout

Configuration Module

Bracket

SATA

MIC

TOR

MIC

TOR

U11

CA

BLE

SLO

T 1S

LOT 2

SLO

T 3S

LOT 4

SLO

T 5S

LOT 6

SLO

T 7S

LOT 8

SLO

T 9S

LOT 10

SLO

T 11

PO

RT

WID

TH

PO

RT

NU

MB

ER

UP

PO

RT

NT P

OR

T

PO

RT S

TATU

S

J9

J10

J11

J6 J7 J8J4 J5

IP1

IP2

IP3

IP4

P4

P5

P6

P7

P8

P9

P10

P11

J12J13

J14

JP11

JP13

JP12

P2 Configuration ModuleP3

SLO

T8-HP

SLO

T5-HP R

ES

ET

PE

RS

T

ATN

LED

PW

R LE

D

ATN

BU

TTON

PORT 5 –PARALLEL HOT PLUG

PORT 8 –SERIAL HOT PLUG

SA

SLanes 4-7

SA

SLanes 8-11

SA

SLanes 12-15

SA

SLanes 0-3

PEX864827 x 2716

31

0 15

32

47

J1 J2 J3

OPEN

OPEN

OPEN

OPEN OPEN

OPENOPEN OPEN

Configuration ModuleP1

Figure 14. PEX 8648 RDK Base Board PCI Express Hot-Plug Circuitry


3.4 Reference Clock Circuitry The differential PCI Express RefClk is brought onto the PEX 8648 RDK base board from the Host PC, by way of the PEX 8648 RDK adapter board and a Serial ATA cable connection. It is used to drive a dual-level set of 1:4 Fan-Out buffers (U3, U4, U5, and U7) to provide a 1:12 Clock Fan-Out buffer. One of these clocks connects to the PEX 8648 switch and is always enabled. The other 11 clocks connect to the 11 PCI Express slot connectors. Except for Slot 5 and Slot 8, these RefClks are always enabled. Slot 5 is the downstream connection selected to demonstrate Hot-Plug capability using the Parallel Hot-Plug interface. Therefore, by default, Slot 5 is enabled by the PEX 8648 switch’s Parallel Hot-Plug Controller for Port 5. Slot 8 is the downstream connection selected to demonstrate Hot-Plug capability using the Serial Hot-Plug Controller and an external I/O Expander IC. Figure 15 illustrates the PEX 8648 RDK base board’s Reference Clock circuitry.


PEX864827 x 27

16

31

015

32

47

Figure 15. PEX 8648 RDK Base Board Reference Clock Circuitry


3.5 Port Configuration and Status LED Indicators The PEX 8648 RDK base board includes several LED indicators, to indicate the board’s Port configuration and status. (Refer to Figure 16.)

The Strapping switches instruct the PEX 8648 switch how to configure its Ports, which Port is to be the upstream Port, and which Port (if any) is to be the NT Port. An on-board CPLD provides glue logic, which decodes the Strapping switch settings. The on-board Configuration modules determine the PEX 8648 RDK base board’s hardwired width and Port Number associated with the cable and each PCI Express slot. These are indicated by the 7-segment PORT WIDTH and PORT NUMBER LED indicators.

PORT WIDTH

PORT NUMBER

UP PORTNT PORT

PORT STATUS

DS5 DS8 DS11 DS14 DS15DS12DS9DS6 DS7 DS10 DS13 DS16

DS29 DS30 DS31 DS32DS17 DS18 DS20DS19 DS21 DS22 DS24DS23 DS25 DS26 DS28DS27DS45 DS46 DS48DS47 DS49 DS50 DS52DS51 DS53 DS54 DS56DS55

DS33 DS36 DS39 DS42 DS34 DS37 DS40 DS43 DS35 DS38 DS41 DS44

SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 SLOT 9SLOT 3SLOT 2SLOT 1CABLE SLOT 10 SLOT 11

Figure 16. PEX 8648 RDK Base Board Port Configuration and Status LED Indicators


3.5.1 PORT STATUS LED Indicators The PORT STATUS indicators (refer to Figure 16) are green LEDs that are driven by the PEX 8648 switch’s PEX_PORT_GOOD[11:0]# balls. Table 2 describes the relationship of the LED On/Off patterns as they relate to Port status.

Table 2. PEX 8648 Switch Port Status LED On/Off Patterns, by State

State LED Pattern

Link is down Off

Link is up, 5 GT/s, all Lanes are up On

Link is up, 5 GT/s, reduced Lanes are up Blinking, 0.5 seconds On, 0.5 seconds Off

Link is up, 2.5 GT/s, all Lanes are up Blinking, 1.5 seconds On, 0.5 seconds Off

Link is up, 2.5 GT/s, reduced Lanes are up Blinking, 0.5 seconds On, 1.5 seconds Off

3.5.2 UP PORT LED Indicators The upstream Port (UP PORT) indicators (refer to Figure 16) are green LEDs that indicate which Port is assigned as the upstream Port. By default, Port 0 is the assigned upstream Port on the PEX 8648 RDK base board.

3.5.3 NT PORT LED Indicators The NT PORT indicators (refer to Figure 16) are green LEDs that indicate which Port is assigned as the NT Port. Only Station 0 Ports – Ports 0, 1, 2, or 3 – can be assigned as the NT Port. By default, Port 1 is the assigned NT Port on the PEX 8648 RDK base board.


3.6 Hardware Strapping Balls The PEX 8648 switch has several Strapping balls that provide the capability to perform various types of hardware initialization, without the use of software. These Strapping balls are brought out to a bank of eight DIP switches on the PEX 8648 RDK base board – SW1, SW11, SW4, SW5, SW9, SW6, SW2, and SW10. (Refer to Figure 17.) Table 3 defines each DIP switch and its default settings.

Figure 17. PEX 8648 RDK Base Board Hardware Strapping DIP Switches – SW1, SW11, SW4, SW5, SW9, SW6, SW2, and SW10, Default Settings


Table 3. PEX 8648 RDK Base Board Hardware Strapping DIP Switches – SW1, SW11, SW4, SW5, SW9, SW6, SW2, and SW10

DIP Switch Switch Switch Strap Signal Description

Base Board Default Setting

SW1

4 – 1 UP-PORTSEL[3:0] Determines which Port is the upstream Port. 0000b (Port 0)

5 Not used Don’t Care

6 NT-ENABLE# Enables (Low) or disables (High) NT mode. 1

8 – 7 NT-PORTSEL[1:0] Determines which Port is the upstream NT Port. 01b (Port 1)

SW11 4 – 1 SHP-SLOT[3:0] Determines which Port has Serial Hot-Plug control. 0000b (Port 8)

SW4 3 – 1 I2C-ADDR[2:0]

In combination with the I2C Configuration register Slave Address field (offset 294h[6:3]), determines the PEX 8648 switch’s I2C Slave address.

111b

SW5 1 HP-ENABLE Enables Hot-Plug capability to Port 5, using Parallel Hot-Plug interface B. 1

2 HP-MRL-B# Simulates the MRL# signal for Parallel Hot-Plug capability to Port 5. 0

SW9 1 SHP-ENABLE Enables Hot-Plug capability to Port 8, using the Serial Hot-Plug interface. 1

2 SHP-MRL# Simulates the MRL# signal for Serial Hot-Plug capability to Port 8. 0

SW6 1 ONBOARD-10V-ON Enables the on-board 1.0 VDC voltage generator to the PEX 8648 switch. 1

2 ONBOARD-25V-ON Enables the on-board 2.5 VDC voltage generator to the PEX 8648 switch. 1

SW2

2 – 1 STN0-PORTCFG[1:0] Determines the PEX 8648 switch Station 0 Port configuration. Default is x8x8. 10b

4 – 3 STN1-PORTCFG[1:0] Determines the PEX 8648 switch Station 1 Port configuration. Default is x8x8. 10b

6 – 5 STN2-PORTCFG[1:0] Determines the PEX 8648 switch Station 2 Port configuration. Default is x8x4x4. 11b

SW10

1 PLL-BYPASS# Selects PLL_BYPASS function, to aid with in-factory testing. 1

2 Not used Don’t Care

3 FAST-BRINGUP# Selects FAST_BRINGUP function, to aid with in-factory testing. 1

4 12-PORT-MODE Factory Test Only. 1

5 SERDES-MODE-EN# Selects SERDES_MODE function, to aid with in-factory testing. 1

6 PROBE-MODE# Selects PROBE_MODE function, to aid with in-factory testing. 1


3.7 Power Circuitry The PEX 8648 RDK base board is a benchtop board, meant to receive 3.3 VDC and 12 VDC from one or more external ATX benchtop supplies. Figure 18 illustrates the PEX 8648 RDK base board power circuitry.

Note: The user must power-up the PEX 8648 RDK base board before powering up the Host computer, so that enumeration will see the PEX 8648 switch and any downstream devices. A circuit detects the power-up sequence between the PEX 8648 RDK base board and Host computer, and turns On a red LED (DS4) if an incorrect sequence occurs. An incorrect sequence is detected by monitoring PERST# from the Host computer, and a “voltage good” signal from a voltage supervisor IC (U8), which monitors board power.

Figure 18. PEX 8648 RDK Base Board Power Circuitry


Dedicated power rails supply the two voltages (2.5V and 1.0V) to the PEX 8648 switch, and only the PEX 8648 switch. This allows accurate current draw measurements when operating in various Port configurations and traffic levels. In the default configuration, each of these power rails is driven by on-board voltage regulators – U13 generates 1.0V from 12 VDC, and U14 generates 2.5V from 3.3 VDC. For the purposes of current draw measurements or voltage margining, an external supply can be used to supply 1.0V and 2.5V, using two banana jacks (J13 and J12, respectively). In this case, the on-board regulators are turned Off by DIP switch SW6. Bicolor red/green LED indicators are used with each of these power rails, to indicate that each voltage is within 10% of nominal.

Power to the PCI Express slot connectors is also supplied by one or more external ATX benchtop supplies. +3.3 VDC to these connectors is on one power rail, and +12 VDC to these connectors is on another. Full board loading of 75W add-in boards is supported. This requires 33A for +3.3 VDC, and 60.5A for +12 VDC. +3.3 VDC is provided by the 20-pin main connector (P5). +12 VDC is obtained from six 4-pin peripheral connectors (P6 through P11).

Note: Load resistors are attached to the 3.3 , 5, and 12 VDC ATX power rails, to ensure that if the PEX 8648 RDK base board is lightly loaded, the ATX supply used will still be able to regulate its voltages.

Power to Slot 5 is controlled by a dual-voltage, Hot-Plug Controller chip (U15), which is controlled by the PEX 8648 switch’s Port 5 Hot-Plug interface. If Port 5 is the upstream Port, the Strapping signals that Set the upstream Port are used to always keep this dual-voltage controller chip turned On.

Power to Slot 8 is also controlled by a dual-voltage, Hot-Plug Controller chip (U18), which is controlled by the PEX 8648 switch’s Serial Hot-Plug interface. If Port 8 is the upstream Port, the Strapping signals that Set the upstream Port are used to always keep this dual-voltage controller chip turned On.

3.8 Reset Circuitry The PEX 8648 RDK base board accepts a PERST# from the Host computer, using a SATA cable connection. The signal is ORed with a manual Reset circuit. This ORed signal connects to the PEX 8648 switch’s PEX_PERST# Input ball, and the downstream slots’ PERST# connector pins. However, in the case where Slot 5 or Slot 8 is not an upstream slot, PERST# to these slots is controlled by their respective Hot-Plug interfaces.

The manual Reset circuit consists of a voltage supervisor chip (U8), and pushbutton switch (SW3) to Reset input of that chip. The voltage supervisor monitors 3.3 VDC and Reset input. If the Reset input is Low, or the supply rail is out of range, the Reset output is held asserted. When both conditions no longer exist, the Reset output de-asserts after a programmable Reset Timeout period (128.6 ms, by default).

3.9 Serial EEPROM Interface (U2) The PEX 8648 RDK base board includes a socketable serial EEPROM (Mill-Max AT25128A) (U2). The serial EEPROM contents can be used to initialize the PEX 8648 switch, after power-on reset.


3.10 JTAG Interface (JP7) The PEX 8648 RDK base board includes a dedicated 2x5 JTAG header (JP7) to the PEX 8648 switch. (Refer to Figure 19.) The 10-pin connector is designed to allow a direct interface to third-party JTAG TAP Controllers, such as the Corelis USB-1149.1/E Controller. The header provides connections for TCK, TDI, TDO, TMS, TRST#, and GND.

There is no “standard” JTAG header pin arrangement; therefore, JTAG header type and pin assignments are arbitrary. The header and pin assignment chosen for the PEX 8648 RDK base board is compatible with the Corelis JTAG single TAP cable (AS00790050-A0).

Figure 19. JTAG Header (Top View)

3.11 I2C Interface (JP8 and JP9)

The PEX 8648 RDK base board includes a two-wire, I2C-compatible Slave mode interface, with 3-bit addressing. Through this out-of-band Channel, users can read, write, and configure the PEX 8648 switch’s internal registers, run internal output Probe mode, monitor Error Counters, and monitor other PEX 8648 switch statuses. The PEX 8648 RDK base board provides two 2x2 pin headers (JP8 and JP9), which interface to the PEX 8648 switch’s I2C Port, to allow chaining of multiple boards.

There is no “standard” I2C header pin arrangement; therefore, I2C header type and pin assignments are arbitrary. (Refer to Figure 20.) The lower three bits of the I2C Slave address selection is determined by a DIP switch setting (SW4[3:1]).

Figure 20. I2C Headers (Top View)


3.12 Device-Specific Sideband Signals The PEX 8648 switch has three device-specific sideband signals – FATAL_ERR#, PEX_INTA#, and PEX_NT_RESET#.

3.12.1 FATAL_ERR# (TPV22, DS1)

FATAL_ERR# (Conventional PCI SERR# equivalent) output is used to indicate when the PEX 8648 switch detects a Fatal, Unrecoverable error. This signal is brought out to labeled test point pad TPV22 on the PEX 8648 RDK base board, so that the FATAL_ERR# signal ball can be accessed. The FATAL_ERR# signal also drives a red LED indicator, DS1. (Refer to Figure 21 for TPV22 and DS1 locations.)

MIC

TOR

MIC

TOR

CA

BLE

SLO

T 1S

LOT 2

SLO

T 3S

LOT 4

SLO

T 5S

LOT 6

SLO

T 7S

LOT 8

SLO

T 9S

LOT 10

SLO

T 11

PO

RT

WID

TH

PO

RT

NU

MB

ER

UP P

OR

TN

T PO

RT

PO

RT STATU

S

J9

J10

J11

J6 J7 J8J4 J5

IP1

IP2

IP3

IP4

P4

P5

P6

P7

P8

P9

P10

P11

J12J13

J14

JP11

JP13

JP12

SLOT8-H

PS

LOT5-H

P RE

SET

PER

ST

SAS

Lanes 4-7

SAS

Lanes 8-11

SAS

Lanes 12-15

SAS

Lanes 0-3

J1 J2 J3

Figure 21. TPV21, TPV22, DS1, and DS2 Placement on PEX 8648 RDK Base Board

3.12.2 PEX_INTA# (TPV21, DS2) PEX_INTA# output is used for Conventional PCI INTA# signal compatibility. This signal is brought out to labeled test point pad TPV21 on the PEX 8648 RDK base board, so that the PEX_INTA# signal ball can be accessed. The PEX_INTA# signal also drives a yellow LED indicator, DS2. (Refer to Figure 21 for TPV21 and DS2 locations.)

3.12.3 PEX_NT_RESET# (TPV49) PEX_NT_RESET# output is used to signal the reception of a Hot Reset from the NT Port Link Interface to the NT Port Virtual Interface. This signal is brought out to labeled test point pad TPV49 on the PEX 8648 RDK base board, so that the PEX_NT_RESET# signal ball can be accessed.


4 Base Board Mechanicals/Component Placement

Figure 22 illustrates the PEX 8648 RDK base board and component placement. Figure 23 illustrates the PEX 8648 RDK base board dimensions.

Figure 22. PEX 8648 RDK Base Board Mechanical Outline

Figure 23. PEX 8648 RDK Base Board Dimensions


4.1 Monitoring Point, LED Indicator, and Control Summary This section summarizes the PEX 8648 RDK base board interfaces that are used for monitoring, indicating, and controlling PEX 8648 switch performance.

4.1.1 Monitoring Points Table 4 lists the functions of all monitoring points available for use on the PEX 8648 RDK base board.

Table 4. PEX 8648 RDK Base Board Monitoring Points

Reference Designator Description

J12 2.5 VDC to the PEX 8648 switch.

J13 1.0 VDC to the PEX 8648 switch.

J14 Ground.

J15 and J16 Reference Clock.

TPV19 and TPV18 Ccathode and Anode of thermal diode within the PEX 8648 switch.

TPV21 PEX_INTA# from the PEX 8648 switch.

TPV22 FATAL_ERR# from the PEX 8648 switch.

TPV49 PEX_NT_RESET# to the PEX 8648 switch.


4.1.2 LED Indicators Table 5 lists the functions of all LED indicators available for use on the PEX 8648 RDK base board. Additional information for the Port-related LED indicators is provided in Section 3.5, “Port Configuration and Status LED Indicators.”

Table 5. PEX 8648 RDK Base Board LED Indicators

Reference Designator Signal Color Description

DS1 FATAL_ERR# Red Indicates that FATAL_ERR# is being driven by the PEX 8648 switch.

DS2 PEX_INTA# Yellow Indicates that INTA# is being driven by the PEX 8648 switch.

DS3 PERST#_PCIe_SWITCH Red Indicates that PERST#, to the PEX 8648 switch and downstream slots, is asserted.

DS4 POWER_UP_SEQUENCE_INCORRECT Red Indicates that the PEX 8648 RDK base board was not powered up before the Host CPU.

DS28 – DS17 UP_PORT[11:0] Green

Indicates which Port is the upstream Port, for Ports 11 through 0, respectively.

DS32 – DS29 NT_PORT[3:0] Green

Indicates which Port is the upstream NT Port, for Ports 3 through 0, respectively.

DS56 – DS45 PRT_STATUS[11:0] Green

Indicates whether the Port is active/configured for use, for Ports 11 through 0, respectively.

DS58 HP_ATNLED_B# Yellow Attention LED for Parallel Hot-Plug slot, J5.

DS59 HP_PWRLED_B# Green Power LED for Parallel Hot-Plug slot, J5.

DS60 SHP_PWRLED# Green Power LED for Serial Hot-Plug slot, J8.

DS61 SHP_ATNLED# Yellow Attention LED for Serial Hot-Plug slot, J8.

DS62 INTERLOCK Yellow INTERLOCK LED for Serial Hot-Plug slot, J8.

DS63 2.5VDC_POWR_GOOD Red/Green Green when 2.5 VDC to the PEX 8648 switch is present and within 10% of nominal; otherwise, red.

DS64 1.0VDC_POWR_GOOD Red/Green Green when 1.0 VDC to the PEX 8648 switch is present and within 5% of nominal; otherwise, red.


4.1.3 Controls For a detailed description of the Strapping ball DIP switches, refer to Section 3.6, “Hardware Strapping Balls.” The remaining controls are three pushbutton switches, defined in Table 6.

Table 6. PEX 8648 RDK Base Board Controls

Reference Designator

Pushbutton Name Description

SW3 RESET Initiates a manual PERST# to the PEX 8648 switch and all downstream slots.

SW7 SLOT5-HP Initiates a Hot-Plug event for Slot 5, the Parallel Hot-Plug slot.

SW8 SLOT8-HP Initiates a Hot-Plug event for Slot 8, the Serial Hot-Plug slot.


4.2 Board Layout Information

4.2.1 Trace Routing Design Rules Impedance of the PCI Express differential pairs is 91 ohms ±5%. The differential pairs are routed as edge-coupled stripline pairs.

4.2.2 Power De-Coupling Power de-coupling is provided by two means – plane capacitance provided by the PCB layer stackup and discrete de-coupling capacitors. Plane capacitance filters noise above approximately 100 MHz. The footprints for the discrete de-coupling capacitors are designed such that the inductance between the pad and plane is reduced by careful via placement. (Refer to Figure 24.)

The PEX 8648 switch power balls are individually de-coupled by 0201-size, 1,000-pF capacitors, with larger-value capacitors providing additional de-coupling around the perimeter of the package. (Refer to Figure 25.)

Figure 24. De-Coupling Capacitor Footprints


Figure 25. PEX 8648 RDK Base Board Power Ball and Perimeter De-Coupling Capacitor Footprints (Reverse Screen)


4.2.3 PCB Layer Stackup The PEX 8648 RDK base board is a 12-layer, 62-mil thick PCB. (Refer to Figure 26.) This stackup includes six routing layers, three ground planes, and three power planes. The target signal impedance for all routing layers is 50 ohms ±5% single-ended impedance, and 91 ohms ±5% differential.

This PCB layer stackup was chosen for the following reasons:

Power/ground plane arrangement provides capacitance to filter noise above 100 MHz from the supply voltages

Differential pair routing layers and plane layers arrangement provides shielding for the PCI Express signals

Figure 26. PEX 8648 RDK Base Board External PCB Layer Stackup Report


5 References

The following is a list of documentation to provide further details.

PLX Technology, Inc. 870 W Maude Avenue, Sunnyvale, CA 94085 USA Tel: 800 759-3735 (domestic only) or 408 774-9060, Fax: 408 774-2169, www.plxtech.com

PEX 8648-AA Data Book, Version 0.92 or higher

PCI Special Interest Group (PCI-SIG) 3855 SW 153rd Drive, Beaverton, OR 97006 USA Tel: 503 619-0569, Fax: 503 644-6708, www.pcisig.com

PCI Local Bus Specification, Revision 3.0

PCI Bus Power Management Interface Specification, Revision 1.2

PCI to PCI Bridge Architecture Specification, Revision 1.2

PCI Express Base Specification, Revision 2.0

PCI Express Card Electromechanical Specification, Revision 2.0

Agilent Technologies, Inc. 5301 Stevens Creek Boulevard, Santa Clara , CA 95051 USA Tel: 877 424-4536 (domestic only) or 408 345-8886, Fax: 408 345-8474, www.agilent.com

Soft Touch Midbus Probe User’s Guide, April, 2007

NXP Semiconductors www.standardics.nxp.com

The I2C-Bus Specification, Version 2.1


6 Bill of Materials & Schematics

This section replicates the PEX 8648 RDK base board Bill of Materials and provides a copy of the base board Schematics.

Item Qty Manufacturer Manufacturer Part # Description Package

Type Component

Designator(s) Distrib

utor Distributor

Part # Part

SURFACE MOUNT COMPONENTS

1 108 Kemet C0402C104K8PACTU CAP .10UF 10V CERAMIC

X5R 0402 SMT, 0402

C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, C61, C62, C63, C64, C65, C66, C67, C68, C69, C70, C71, C72, C73, C74, C75, C76, C77, C78, C79, C80, C81, C82, C83, C84, C85, C86, C87, C88, C89, C90, C91, C92, C93, C94, C95, C96, C124, C125, C126,

C132, C138, C144, C227, C232, C233, C234, C236, C237

Digi-Key 399-3027-1-ND 0.1uF

2 22 AVX TAJC226K020R CAP TANTALUM 22UF

20V 10% SMD EIA size

C

C97, C98, C99, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109, C110, C111, C112, C113, C114,

C115, C116, C117, C118

Digi-Key 478-1711-1-ND 22uF

3 32 Panasonic ECJ-0EB1C103K CAP .01UF 16V CERAMIC

0402 SMD SMT, 0402

C119, C120, C121, C122, C127, C128, C129, C130, C133, C134, C135, C136, C139, C140, C141, C142, C192, C193, C194, C195, C196, C197, C198, C199, C214, C215, C216, C217, C218, C219,

C220, C221

Digi-Key PCC103BQCT-ND 0.01uF

4 5 Panasonic ECJ-3YB1C106M

CAP 10UF 16V CERAMIC X5R 1206 LOVOLT

FOOTPRINT

SMT, 1206, LoVolt

C123, C131, C137, C143, C148 Digi-Key PCC2227CT-ND 10uF

5 2 Panasonic ECJ-1VB1H473K CAP .047UF 50V

CERAMIC X7R 0603 SMT, 0603 C145, C222

Digi-Key PCC2286CT-ND 0.047uF

6 9 Kemet C0603C105K8PACTU CAP CERAMIC 1.0UF 10V

X5R 0603, 2 VIA

SMT, 0603, 2via

C149, C188, C189, C190, C191, C210, C211, C212, C213

Digi-Key 399-3118-1-ND 1uF

7 2 Kemet C1206C226K9PACTU

CAP 22UF 6.3V CER X5R SMD 1206 LOVOLT

FOOTPRINT

SMT, 1206, LoVolt

C150, C151 Digi-Key 399-3229-1-ND 22uF

8 16 Kemet C0603C104K4RACTU CAP .10UF 16V CERAMIC

X7R 0603 SMT, 0603

C152, C153, C154, C155, C158, C159, C162, C164, C223, C224, C225, C226,

C228, C229, C230, C231

Digi-Key 399-1096-1-ND 0.1uF



Type Component


utor Distributor

Part # Part

9 101 Panasonic ECJ-ZEB1E102K CAP 1000PF 25V

CERAMIC X7R 0201 SMT, 0201

C156, C157, C160, C161, C163, C166, C168, C169, C170, C172, C173, C174, C175, C176, C177, C178, C179, C180, C181, C182, C183, C185, C186, C187, C200, C201, C202, C203, C205, C206, C207, C208, C310, C311, C312, C313, C314, C315, C316, C317, C318, C319, C320, C321, C322, C323, C324, C325, C326, C327, C328, C330, C331, C332, C333, C334, C335, C336, C337, C338, C339, C340, C350, C352, C354, C356, C358, C360, C362, C364, C366, C369, C370, C371, C372, C373, C374, C375, C376, C377, C378, C379, C380, C381, C382, C383, C384, C385, C386, C387, C388, C389, C390, C391, C392, C393,

C394, C395, C396, C397, C398

Digi-Key PCC2130CT-ND 1000pF

10 3 Lumex SML-

LXT0805SRW-TR

LED THIN660NM SUPRED DIFF0805SMD

SMT, 0805 DS1, DS3, DS4

Digi-Key 67-1555-1-ND Red

11 4 Lumex SML-

LXT0805YW-TR

LED THIN 585NM YEL DIFF 0805 SMD

SMT, 0805 DS2, DS58, DS61, DS62

Digi-Key 67-1554-1-ND Yellow

12 30 Lumex SML-

LXT0805GW-TR

LED THIN 565NM GRN DIFF 0805 SMD

SMT, 0805

DS17, DS18, DS19, DS20, DS21, DS22, DS23, DS24, DS25, DS26, DS27, DS28, DS29, DS30, DS31, DS32, DS45, DS46, DS47, DS48, DS49, DS50, DS51, DS52, DS53, DS54, DS55, DS56, DS59, DS60

Digi-Key 67-1553-1-ND Green

13 2 Panasonic LNJ107W5PRW LED, RED/GREEN HI BRT

S TYPE SMD, If=10mA DS63, DS64 Digi-Key P526CT-ND LED_BI

14 4 Molex 757830036

Connector, right angle with shell 0.8mm pitch for mini-SAS,4x 26 CKT internal

cable,

shell TH, SMT 26-

pin connector

IP1, IP2, IP3, IP4 I_PASS_26CKT_75783_0036

15 2 Amp 767054-1 CONN, 38-pin MICTOR, RECPT, STRAIGHT JP11, JP13 MICTOR 38

RECEPT

16 2 Johnson/Emerson 142-0711-201 CONNECTOR, SMA, SMT,

STRAIGHT, 50 OHM SMT_SM

A J15, J16 Mouser 530-142-0711-201 SMT_SMA

17 3 FCI 74221 Header, BGA, 10x40, receptacle P1, P2, P3 CM_10x40

18 1 Molex 47080-4001 CONNECTOR, SATA, right-angle P4 SATA header

19 29 ON Semiconductor MMBT3904LT

1 NPN, GPSS, MMBT3904,

SOT23

Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23,

Q24, Q25, Q26, Q27, Q28, Q29

MMBT3904LT1

20 4 International Rectifier IRF7470 MOSFET, N-CHAN, 10A,

Rds=13 mohm SO8 Q31, Q32, Q33, Q34 IRF7470

21 6 CTS 742C083512J RESNET, MF, 5.1 KOHM NIL 5%, ISOLATED 742-CTS-

RN-8 RN1, RN2, RN3, RN4, RN5, RN7 Digi-Key 742C083512JCT-ND 5.1K

22 6 Panasonic ERJ-3EKF1431V RES 1.43K OHM 1/10W

1% 0603 SMD SMT, 0603 R1, R2, R3, R4, R175, R176

Digi-Key P1.43KHCT-ND 1.43K



Type Component


utor Distributor

Part # Part

23 22 Yageo 9C06031A0R00JLHFT RES 0.0 OHM 1/10W 5%

0603 SMD SMT, 0603

R7, R8, R9, R10, R12, R13, R14, R16, R17, R18, R19, R25, R26, R27, R28, R46, R250, R272, R280, R282, R283,

R284

Digi-Key 311-0.0GCT-ND 0

24 55 Panasonic ERJ-3GEYJ512V RES 5.1K OHM 1/10W 5%

0603 SMD SMT, 0603

R11, R57, R64, R67, R69, R73, R75, R86, R91, R94, R97, R100, R102, R117, R120, R122, R127, R129, R145, R148, R150, R154, R156, R162, R163, R165, R166, R167, R168, R174, R177, R178, R179, R239, R240, R241, R249, R254, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R269, R277,

R278, R281, R285, R302, R303

Digi-Key P5.1KGCT-ND 5.1K


0603 SMD SMT, 0603 R20, R21, R22, R62, R63, R304



0603 SMD SMT, 0603 R23


27 5 Panasonic ERJ-3GEYJ103V RES 10K OHM 1/10W 5%

0603 SMD SMT, 0603 R24, R33, R35, R55, R56

Digi-Key P10KGCT-ND 10K

28 8 Panasonic ERJ-3GEYJ512V RES, Shunt Select

Footprint, 0603 SMT,

0603-2 R29, R31, R34, R39, R40, R41, R44,

R45 Digi-Key P5.1KGCT-ND 5.1K Shunt


1% 0603 SMD SMT, 0603 R42, R43


30 4 Panasonic ERJ-3GEYJ391V RES 390 OHM 1/10W 5%

0603 SMD SMT, 0603 R48, R49, R164, R169

Digi-Key P390GCT-ND 390


0805 SMD SMT, 0805 R50, R81, R108, R135

Digi-Key 311-0.0ACT-ND 0

32 32 Panasonic ERJ-1GEF33R2C RES 33.2 OHM 1/20W 1%

0201 SMD SMT, 0201

R51, R52, R59, R66, R68, R77, R78, R82, R83, R87, R88, R93, R95, R104, R105, R109, R110, R113, R114, R119, R121, R131, R132, R136, R137, R140, R143, R144, R147, R149, R158, R159

Digi-Key P33.2ABCT-ND 33.2

33 32 Panasonic ERJ-1GEF49R9C RES 49.9 OHM 1/20W 1%

0201 SMD SMT, 0201

R53, R54, R60, R61, R72, R74, R79, R80, R84, R85, R89, R90, R99, R101, R106, R107, R111, R112, R115, R116, R125, R128, R133, R134, R138, R139, R141, R142, R153, R155, R160, R161

Digi-Key P49.9ABCT-ND 49.9

34 14 Yageo 9C06031A0R00JLHFT RES, Shunt Select

Footprint, 0603 SMT,

0603-2

R30, R32, R65, R70, R71, R92, R96, R98, R118, R123, R126, R146, R151,

R152

Digi-Key 311-0.0GCT-ND 0 Shunt

35 4 Panasonic ERJ-3EKF4750V RES 475 OHM 1/16W 1%

0603 SMD SMT, 0603 R76, R103, R130, R157

Digi-Key P475HCT-ND 475

36 2 CTS 742C163221J RES ARRAY 220 OHM 16TRM 8RES SMD R171, R172 Digi-Key 742C163221JCT-ND 220

37 1 Panasonic ERJ-3GEYJ330V RES, CF, 33 OHM, 1/16W,

5%, 0603 SMD SMT, 0603 R173


38 31 Panasonic ERJ-2GEJ512X RES 5.1K OHM 1/16W 5%

0402 SMD SMT, 0402

R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R253,

R276

Digi-Key P5.1KJCT-ND 5.1K



Type Component


utor Distributor

Part # Part

39 37 Panasonic ERJ-3GEYJ151V RES 150 OHM 1/10W 5%

0603 SMD SMT, 0603

R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R251, R252, R256, R274, R275, R279, R299, R300,

R301



0603 SMD SMT, 0603 R238



0603 SMD SMT, 0603 R242



1% 0603 SMD SMT, 0603 R243



1% 0603 SMD SMT, 0603 R244, R312


44 4 TTelectronics LR2512-01-R020-F Res. 2W, 0.02 ohm 1% SMT, 2512 R245, R248, R270, R271 Mouser 66-LR2512-01-R040-F 0.02


1% 0603 SMD SMT, 0603 R246, R247, R268, R273


46 2 CTS 741X083472J RES ARRAY 4.7KOHM 8TERM 4RES SMD

741X-CTS-RN-

8 R255, R286 Digi-Key 741X083472JCT-ND 4.7K

47 1 CTS 741X163472J RES ARRAY 4.7KOHM 8TERM 8RES SMD

741X-CTS-RN-

16 R257 Digi-Key 741X163472JCT-ND 4.7K


1% 0603 SMD SMT, 0603 R291, R293, R296, R298



1% 0603 SMD SMT, 0603 R292, R297



1% 0603 SMD SMT, 0603 R294, R295



1% 0603 SMD SMT, 0603 R308



1% 0603 SMD SMT, 0603 R309



1% 0603 SMD SMT, 0603 R310



1% 0603 SMD SMT, 0603 R311



1% 0603 SMD SMT, 0603 R313


56 3 Omron B3S-1002 SWITCH TACT 6MM SMD MOM 230GF SW3, SW7, SW8 Digi-Key SW416-ND B3S-1002

57 1 PLX PEX8648-AA50BC F IC, PCI Express Switch,

Gen 2, 48 Lane FCBGA67

6 U1 PEX8648-PBGA676

58 4 SpectraLinear CY28400-2 IC, 1:4 100MHz Differential Clock Fanout U3, U4, U5, U7 CY28400-2

59 2 Fairchild NC7SZ04M5X IC, NOT GATE SOT23-5 U6, U16 NC7SZ04M5X

60 1 Maxim MAX6412UK29-T

IC, Reset controller, 2.9V threshold, Adj. reset

timeout SOT23-5 U8 MAX6412

61 1 Fairchild NC7SZ08M5 IC, AND Gate, SOT23-5 U9 NC7SZ08



Type Component


utor Distributor

Part # Part

X Tpd=15nsec, 24mA

62 1 Fairchild NC7SZ74K8X IC, D-FLOP, PSET and CLR

8-Lead US8,

JEDEC MO-187, Variation CA 3.1

mm Wide

U10 NC7SZ74

63 1 Lattice ispXPLD 5256MX IC, CPLD U11 ispXPLD 5256MX

256fpBGA

64 1 Ecliptek EMK23G2H-1.000M Osc, 1.000MHz, 3.3V,

100ppm EMK23 U12 1.000MHz

65 1 Belfuse S7AH-08E1A00 IC, Non-iso DC/DC

converter, 12V-to-1V @ 8A

SMT, 7-pin

Belfuse U13 S7AH-08E1A00

66 1 Maxim MAX8556ETE IC, V-REG, 4 A, ADJ, Enable, POK Thin

QFN16 U14 MAX8556

67 2 TI TPS2311IPW IC, DUAL HOT SWAP CONTROLLER TSSOP20 U15, U18 TPS2311

68 1 Maxim MAX7311AUG IC, 2-WIRE, 16-BIT IO

EXPANDER TSSOP24 U17 MAX7311AUG

69 1 Intersil ISL6132IR IC, MULTI-VOLTAGE SUPERVISOR L24.4x4 U19 ISL6132

70 2 TI SN74CB3Q16244 IC, Bus Switch, 16-Bit SSOP48 U20, U21 SN74CB3Q16244

71 1 Fairchild NC7SZ00M5X IC, NAND Gate,

Tpd=15nsec, 24mA SOT23-5 U22 NC7SZ00

72 2 Panasonic ERJ-1TYJ101U RES 100 OHM 1W 5%

2512 SMD SMT, 2512 R314, R316

Digi-Key PT100XCT-ND 100

73 2 Panasonic ERJ-1TYJ201U RES 200 OHM 1W 5%

2512 SMD SMT, 2512 R315, R317

Digi-Key PT200XCT-ND 200

74 1 Panasonic ERJ-3EKF3603V RES 360K OHM 1/10W 1% SMT, 0603 R170

Digi-Key P360KHCT-ND

THROUGH HOLE COMPONENTS

100 2 Vishay 94SP187X0016EBP CAP, Oscon, 180uF, 16V E case C146, C147 180uF

101 5 Lumex LDD-A516RI LED 7-SEG .56 DUAL S-RED CA DIR DS5, DS6, DS7, DS41, DS44 Digi-Key 67-1461-ND Red

102 19 Lumex LDS-A516RI LED 7-SEG .56 SNGL S-RED CA DIR

DS8, DS9, DS10, DS11, DS12, DS13, DS14, DS15, DS16, DS33, DS34, DS35, DS36, DS37, DS38, DS39, DS40, DS42,

DS43

Digi-Key 67-1475-ND Red

103 1 Amp 103308-1 CONN HEADER LOPRO STR 10POS 15AU 0.1" 2x5 JP7 Digi-Key A26267-ND JTAG Header

104 2 3M 929710-10-02 CONN HEADER .100 DUAL STR 4POS 0.1" 2x2 JP8, JP9 Digi-Key 929710-10-02-ND HEADER 2X2

105 1 3M 929400-01-36

HEADER, Lattice Programming, 1x8

VERTICAL, .1in THRU-HOLE

JP10 Digi-Key 929400-01-36-ND Lattice JTAG



Type Component


utor Distributor

Part # Part

106 1 3M 929710-10-10 CONN HEADER LOPRO STR 20POS 15AU 0.1" 2x10 JP12 Digi-Key 929710-10-10-ND

PRB MODE INPUT HEADER

107 1 3M 929400-01-36

HEADER, NVM Programming, 1x4

VERTICAL, .1in THRU-HOLE

SIP4 JP14 Digi-Key 929400-01-36-ND 1x4 HEADER

108 11 Molex 87715-3302 PCI Express x16 Through-hole connector TH, 164-

pin J1, J2, J3, J4, J5, J6, J7, J8, J9, J10, J11 PCI_EXP_X16_FEMALE_CONN

109 2 Concord Electronics 09-9127-1-

0212 Banana Jack, Insulated,

Red BANANA J12, J13 banana_jack

110 1 Concord Electronics 09-9127-1-

0210 Banana Jack, Insulated,

Black BANANA J14 banana_jack

111 1 Molex 39-29-9202 Header, ATX, 20 position, ST dual-row ATX20_S

T P5 Newar

k ATX_20 ST

112 6 Molex 15-24-4449 Header, HD 4-pin, straight P6, P7, P8, P9, P10, P11 Arrow IDE4_HEADER

113 1 ITT SDA08H1BD SWITCH DIP TOP SLIDE EXT 8POS DIP16 SW1 Digi-Key CKN6091-ND SW DIP-8

114 2 ITT SDA06H1BD SWITCH DIP TOP SLIDE EXT 6POS DIP12 SW2, SW10 Digi-Key CKN6079-ND SW DIP-6


116 3 ITT SDA02H1BD SWITCH DIP TOP SLIDE EXT 2POS DIP4 SW5, SW6, SW9 Digi-Key CKN6055-ND SW DIP-2


118 1 Mill-Max 210-93-308-41-001000 Socket, EEPROM, DIP8,

Thru-hole DIP8 U2 Digi-Key ED60000-ND AT25128A

MANUALLY INSERTED COMPONENTS

200 1 Atmel AT25128A-10PI-2.7 IC SRL EE 128K 2.7V 8DIP DIP8 U2 Digi-Key AT25128A-10PI-2.7-ND AT25128A

201 2 PLX Technology 91-0091-00-A CONFIGURATION MODULE, x8x8 P1, P2

202 1 PLX Technology 91-0092-00-A CONFIGURATION MODULE, x8x8x4 P3

MISCELLANEOUS COMPONENTS

300 1 PLX Technology 90-0082-100-A

PCIe 48 LANE SWITCH RDK PCB, BASEBOARD,

GEN2, Rev 100

301 1 Advanced Thermal Solutions

ATS-54270D-C2-R0

HEAT SINK 27MM x 27MM x 9.5MM U1

Digi-Key ATS1201-ND

302 1 PLX Technology 91-0083-001-A RDK x16 Cable Adapter

303 9 3M Bumpon SJ5009BK 3M Bumpon, Black, .40" x .88", PCB feet The

Olander

SJ5009BK



Type Component


utor Distributor

Part # Part

Company

PARTS THAT SHOULD NOT BE ASSEMBLED


0603 SMD SMT, 0603 R124, R180

Digi-Key 311-0.0GCT-ND NL

401 4 JP3, JP4, JP5, JP6 Midbus LAI

402 4 Panasonic ERJ-3GEYJ330V RES, CF, 33 OHM, 1/16W,

5%, 0603 SMD SMT, 0603 R287, R288, R289, R290


PLX Part # 93-0082-100-A

Product Name: PEX 8648-AA RDK

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

91-0082-100-A 102

PEX8648 RDK - Functional Block Diagram

PLX Technology, Inc.870 W. Maude AvenueSunnyvale, CA 94085www.plxtech.com

C

1 21Tuesday, November 16, 2010

Title


Date: Sheet of

91-0082-100-A 102



C


Title


Date: Sheet of

91-0082-100-A 102



C


mSAS mSAS mSAS mSAS

PEX 8648CPLDGLUE LOGIC

PORT CONFIGURATION AND STATUS INDICATORSNOTE: THESE INDICATORS REFLECT THE BOARD CONFIGURATION AS DEFINED BY THE SWITCH SETTINGS AND THECONFIGURATION MODULES INSTALLED. THEY DO NOT NECESSARILY REFLECT THE PEX8648 CONFIGURATION.

x8 x4x4x12 x8 x4x4x12x4 x4

x4x4x12x4 x8

EEPROM

JTAG

I2C

STRAPPINGSWITCHES

SLOT1 SLOT2 SLOT3

SLOT4 SLOT5 SLOT6 SLOT7 SLOT8 SLOT9 SLOT10 SLOT11

1 Functional Block Diagram2 Board Layout Information3 Station 0 Interface4 Station 1 Interface5 Station 2 Interface6 Config Module 07 Config Modules 1 and 28 Station 0 Connectors9 Station 1 Connectors10 Station 2 Connectors11 PCIe SWITCH INTERFACE12 PCIe SWITCH POWER13 REFCLK Fanout 114 REFCLK Fanout 215 Switches16 CPLD Glue Logic17 MICTOR Connectors18 Port Width Indicators19 Port Status Indicators20 Hot Plug21 Power

Sheet # Title

Schematic Table of Contents

PORT WIDTH

PORT NUMBER

PORT STATUS

NT PORT

CABLE

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

SLOT8

SLOT9

SLOT10

SLOT11

CONFIG MODULE - P2 CONFIG MODULE - P3

CONFIG MODULE - P1

UPSTREAM PORT

100

January 10, 2008 First board build000

Revision History

Rev. # Date Reason for Revision

February 8, 2008 Station 0 routing changed. Some footprints corrected.

101 6/4/2010 Modified the name of 8648 symbol

102 11/16/2010 Changed R170 to 360 K ohm resistor

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of

91-0082-100-A 102

PEX8648 RDK - Board Layout Information


C


Title


Date: Sheet of

91-0082-100-A 102



C


Title


Date: Sheet of

91-0082-100-A 102



C


PREPREG, Er=4.1, 4.2 mil

L7, GND2, 1.2 mil

L8, SIGNAL 4, 0.6 mil


L2, GND1, 0.6 mil


L4, POWER1, 0.6 mil


L6, POWER2, 1.2 mil




CORE, Er=4.2, 6.0 mil





L9, POWER3, 0.6 mil

BoardThickness = 62 mils

LAYER STACKUP

SOLDERMASK, 0.8 mil




L11, GND3, 0.6 mil


SOLDERMASK, 0.8 mil

INNERTRACES

Cu = 0.50 oz

DIFF Trace Zo = 91 ohmWIDTH = 4.0 milSPACING = 7.0 mil

SINGLE Trace Zo = 50 ohmWIDTH = 7.0 mil

NL = No Load

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PEX_Tx2_C_pPEX_Tx2_C_n






PEX_Tx1_C_nPEX_Tx1_C_p


PEX_Tx9_C_n

PEX_Tx12_C_p

PEX_Tx9_C_p

PEX_Tx12_C_n

PEX_Tx13_C_p


PEX_Tx13_C_n

PEX_Tx14_C_p


PEX_Tx14_C_n

PEX_Tx11_C_p

PEX_Tx15_C_p

PEX_Tx11_C_n

PEX_Tx15_C_n

Deneb_REFCLKp{13}Deneb_REFCLKn{13}

PEX_Tx0_p {8}PEX_Tx0_n {8}PEX_Rx0_p {8}PEX_Rx0_n {8}
















Title


Date: Sheet of

91-0082-100-A 102

PEX8648 RDK - Station 0 Interface


C


Title


Date: Sheet of

91-0082-100-A 102



C


Title


Date: Sheet of

91-0082-100-A 102



C


C20.1uF C20.1uF

C90.1uF C90.1uF

C310.1uF C310.1uF

C70.1uF C70.1uF

C190.1uF C190.1uF

C170.1uF C170.1uF

C210.1uF C210.1uF

C230.1uF C230.1uF

C160.1uF C160.1uF

C140.1uF C140.1uF

C50.1uF C50.1uF

C250.1uF C250.1uF

C120.1uF C120.1uF

C30.1uF C30.1uF

C270.1uF C270.1uF

C290.1uF C290.1uF

PEX 8648

Station 0

U1A

PEX8648

PEX 8648

Station 0

U1A

PEX8648

PEX_PETp[0] AE5PEX_PETn[0] AF5PEX_PERp[0] AB5PEX_PERn[0] AC5
















PEX_REFCLKpAE9PEX_REFCLKnAF9

REXT_A0AC9

REXT_B0AB9

NCAA9

NCAE18NCAF18

REXT_A1AC18

REXT_B1AB18

NCAA18

C100.1uF C100.1uF

C10.1uF C10.1uF

R11.43K1%

R11.43K1%

C320.1uF C320.1uF

C80.1uF C80.1uF

C200.1uF C200.1uF

C180.1uF C180.1uF

C220.1uF C220.1uFR21.43K1%

R21.43K1%

C240.1uF C240.1uF

C60.1uF C60.1uF

C260.1uF C260.1uF

C150.1uF C150.1uF

C130.1uF C130.1uF

C40.1uF C40.1uF

C280.1uF C280.1uF

C110.1uF C110.1uF

C300.1uF C300.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Deneb_Txn_25Deneb_Rxp_25

Deneb_Txp_25

Deneb_Rxn_25

Deneb_Txn_C_25

Deneb_Txp_C_28


Deneb_Txp_26

Deneb_Rxn_26

Deneb_Txp_C_25

Deneb_Txn_C_28


Deneb_Txp_27

Deneb_Rxn_27

Deneb_Txp_C_29

Deneb_Txn_C_24


Deneb_Txp_28

Deneb_Rxn_28

Deneb_Txp_C_24

Deneb_Txn_C_29 Deneb_Txn_29Deneb_Rxp_29

Deneb_Txp_29

Deneb_Rxn_29

Deneb_Txp_C_30

Deneb_Txp_C_26


Deneb_Txp_30

Deneb_Rxn_30

Deneb_Txn_24

Deneb_Txn_C_26

Deneb_Txn_C_30


Deneb_Txp_31

Deneb_Rxn_31

Deneb_Txp_C_27

Deneb_Txp_C_31

Deneb_Rxp_24

Deneb_Txp_24

Deneb_Txn_C_27

Deneb_Txn_C_31

Deneb_Rxn_24


Deneb_Txp_17

Deneb_Rxn_17

Deneb_Txn_C_17

Deneb_Txp_C_20


Deneb_Txp_18

Deneb_Rxn_18

Deneb_Txp_C_17

Deneb_Rxn_21

Deneb_Txn_26

Deneb_Txp_21

Deneb_Txn_31

Deneb_Rxp_22

Deneb_Txp_27

Deneb_Rxp_16

Deneb_Txn_21

Deneb_Rxn_26

Deneb_Rxn_31

Deneb_Rxp_27Deneb_Rxn_27



Deneb_Rxp_30

Deneb_Rxp_24

Deneb_Rxn_30

Deneb_Rxn_24


Deneb_Rxp_26

Deneb_Rxp_31

Deneb_Rxn_22

Deneb_Txn_27

Deneb_Txp_22

Deneb_Rxp_23

Deneb_Rxn_16

Deneb_Txp_28

Deneb_Txn_22

Deneb_Txp_16

Deneb_Rxn_23

Deneb_Txn_C_20

Deneb_Rxp_17

Deneb_Txn_28

Deneb_Txp_23

Deneb_Txn_16

Deneb_Rxn_17

Deneb_Txp_29

Deneb_Txn_23

Deneb_Txp_17

Deneb_Rxp_18

Deneb_Txn_29

Deneb_Txn_17

Deneb_Rxn_18

Deneb_Txp_30

Deneb_Txp_18

Deneb_Txp_24

Deneb_Rxp_19

Deneb_Txn_30

Deneb_Txn_18

Deneb_Txn_24

Deneb_Rxn_19

Deneb_Txp_19

Deneb_Txp_25

Deneb_Rxp_20

Deneb_Txn_19

Deneb_Txn_25

Deneb_Rxn_20

Deneb_Txp_20

Deneb_Rxp_21

Deneb_Txp_26

Deneb_Txp_31

Deneb_Txn_20


Deneb_Txp_19

Deneb_Rxn_19

Deneb_Txn__C_16

Deneb_Txp_C_21


Deneb_Txp_20

Deneb_Rxn_20

Deneb_Txp__C_16

Deneb_Txn_C_21 Deneb_Txn_21Deneb_Rxp_21

Deneb_Txp_21

Deneb_Rxn_21

Deneb_Txp_C_22

Deneb_Txp_C_18


Deneb_Txp_22

Deneb_Rxn_22

Deneb_Txn_16

Deneb_Txn_C_18

Deneb_Txn_C_22


Deneb_Txp_23

Deneb_Rxn_23

Deneb_Txp_C_19

Deneb_Txp_C_23

Deneb_Rxp_16

Deneb_Txp_16

Deneb_Txn_C_19

Deneb_Txn_C_23

Deneb_Rxn_16

Deneb_Txp_25{7}

Deneb_Txn_19{9}

Deneb_Txn_25{7}

Deneb_Txp_20{7}

Deneb_Rxp_24 {7}

Deneb_Txp_26{7}

Deneb_Txn_20{7}

Deneb_Rxn_24 {7}

Deneb_Txn_26{7}

Deneb_Txp_21{7}

Deneb_Rxp_25 {7}

Deneb_Txp_27{7}

Deneb_Txn_21{7}

Deneb_Rxn_25 {7}

Deneb_Txn_27{7}

Deneb_Txp_22{7}

Deneb_Rxp_16 {9}Deneb_Rxn_16 {9}








Deneb_Rxp_26 {7}

Deneb_Txp_28{7}

Deneb_Txn_22{7}

Deneb_Rxn_26 {7}

Deneb_Txn_28{7}

Deneb_Txp_23{7}

Deneb_Rxp_27 {7}

Deneb_Txp_29{7}

Deneb_Txn_23{7}

Deneb_Rxn_27 {7}

Deneb_Txn_29{7}

Deneb_Rxp_28 {7}

Deneb_Txp_30{7}

Deneb_Rxn_28 {7}

Deneb_Txn_30{7}

Deneb_Rxp_29 {7}

Deneb_Txp_31{7}

Deneb_Rxn_29 {7}

Deneb_Txn_31{7}



Deneb_Txp_16{9}Deneb_Txn_16{9}

Deneb_Txp_17{9}Deneb_Txn_17{9}

Deneb_Txp_18{9}

Deneb_Txp_24{7}

Deneb_Txn_18{9}

Deneb_Txn_24{7}

Deneb_Txp_19{9}

Title


Date: Sheet of

91-0082-100-A

pex 8648-aa rdk - broadcom...adapter board that plugs into the host system, four mini-sas cables and...

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