Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/071

FONT IP intra-train feedback prototype status

Philip BurrowsJohn Adams Institute

Oxford University

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/072

Outline

• Introduction + overview

• FONT4 system at ATF

Design of feedback hardware elements

Results of beam tests

• FONT5 ILC prototype at ATF2

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/073

IP intra-train feedback system - concept

Last line of defence against relative beam misalignment

Measure vertical position of outgoing beam and hence beam-beam kick angle

Use fast amplifier and kicker to correct vertical position of beam incoming to IR

FONT – Feedback On Nanosecond Timescales

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/074

FONT: Feedback On Nanosecond Timescales

Oxford + Daresbury:

Philip BurrowsGlenn ChristianHamid Dabiri Khah Tony HartinAlexander KalininJavier Resta LopezColin Perry

Graduate students:Christine Clarke Christina Swinson Ben ConstanceRobert Apsimon

SLAC, KEK, DESY, CERN

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/075

Overview

Task: prototype beam-based (intra-train) feedback system

Completed: ultra-fast all-analogue feedback prototypes

FONT2 / NLCTA: 54ns latency

FONT3 / ATF: 23ns latency

Ongoing: ILC digital feedback prototype

FONT4 / ATF: digital FB processor tests w. 3 bunches

Design of feed-forward system

FONT@ESA: EM background impact on FB BPMs (Hartin)

Future: Multibunch (20 – 60 bunches?) operations, algorithm tests

FONT5 / ATF2

Feed-forward

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/076

FONT4 prototype at KEK/ATF

Kicker BPM 1

Digital feedback

Analogue BPM processor

Driveamplifier

BPM 2

BPM 3

e-

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/077

Kicker BPM 1

Digital feedback

Analogue BPM processor

Driveamplifier

BPM 2

BPM 3

e-

FONT4 prototype at KEK/ATF

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/078

BPM processor

Replaced connectorised version

with custom PCB – new version tested

November 2006

Single

stage

down-mix

to basebandLatency c. 7ns

Resolution c. 5um

old

new

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/079

Digital Feedback Board

2 x Analog Input channels (single-ended)

2 x Analog Output channels (differential) 4 x General-purpose digital outputs

3 x external clock/trigger inputs

Xilinx Virtex4 FPGA

Analog Devices ADC/DACs

40 MHz oscillator

RS232 comms

JTAG port PROM

GP I/O Header

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0710

Specifications:• +- 15A (kicker terminated with 50 Ohm)• +- 30A (kicker shorted at far end)• 35ns risetime (to 90%)• pulse length 10 us (specified for 20-60 bunches)• repetition rate 10 Hz

Order placed with TMD Technologies Sept 06:

1st prototype unit December 1

2nd prototype unit December 8 (5ns faster)

Tested with beam at ATF Dec 06, Feb + May 07

Kicker driver amplifier

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0711

FONT4: latency estimate

• Time of flight kicker – BPM: 4ns• Signal return time BPM – kicker: 10ns

Irreducible latency: 14ns

• BPM processor: 7ns• ADC/DAC (3.5 89 MHz cycles) 40ns• Signal processing (8 357 MHz cycles) 25ns• FPGA i/o 3ns• Amplifier 40ns• Kicker fill time 3ns

Electronics latency: 118ns

• Total latency estimate: 132ns

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0712

FONT4: beamline at KEK ATF (May 07)

BPM processor boardAmplifier FEATHERKicker

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0713

First closed-loop operation (Dec 06) B

ea

m P

osi

tio

n

1 2 3

FB off154ns

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0714

Be

am

Po

siti

on

1 2 3

FB off

FB on

154ns

First closed-loop operation (Dec 06)

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0715

Feedback with delay-loop (Feb 07)

154ns

Incoming bunches

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0716

Feedback with delay-loop (Feb 07)

FB on, no delay loop

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0717

Feedback with delay-loop (Feb 07)

FB on, with delay loop

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0718

Feedback with delay-loop (Feb 07)

FB on, with delay loop

Latency ~ 135ns

May 07: optimise gain, delay-loop setting, 1/Q …

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0719

With 1/Q + optimised gain (May 07)

154ns

FB off

FB on

‘banana’ effectcorrected!

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0720

Until ATF shutdown for connection to ATF2 (June 08):

Continue closed-loop FB tests• Close FB loop• Delay loop• 1/Q normalisation• Study + characterise train-train and bunch-bunch jitter• Deal with static position offsets in train• Adaptive gain• ‘Turn-key’ operation• Improve BPM resolution to 1um level

FONT4 test plan

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0721

Until ATF shutdown for connection to ATF2 (June 08):

Continue closed-loop FB tests• Close FB loop• Delay loop• 1/Q normalisation• Study + characterise train-train and bunch-bunch jitter• Deal with static position offsets in train• Adaptive gain• ‘Turn-key’ operation• Improve BPM resolution to 1um level

Deploy + commission system at ATF2 ( > October 08)

FONT4 test plan

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0722

The next major development would be FB tests using a long ILC-like train of 20-60 bunches

(FONT4 amplifier was specified to allow this)

• Depends on success of ATF fast-extraction kicker tests, 2008/9??

• Would allow us to make FB algorithms robust:take into account bunch-bunch correlations along trainadaptive gain as beam conditions change (drift)incorporate feed-forward information from upstreamadd beam-related ‘luminosity’ signal for fast scanning?

• Could in principle be done at FLASH

FONT5 test plan

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0723

FONT bench test system

Manufacture synchronised ILC bunch-train, clocks, and trigger

Develop algorithms and program FPGA

Close loop

(Include amplifier and dummy kicker also!)

Trigger

Bunch

2.16 MHz Diagnostic

Philip Burrows BDS/MDI session, LCWS07, DESY, 31/05/0724

FONT goals 2007-10

1) Develop ILC intra-train beam feedback system + contribute engineered design to EDR

2) Deploy prototype system at ATF2

3) Design + simulate integrated global alignment, FB + luminosity tuning strategy for EDR