pi_ito_2015_embedded_ arm.pdf

Embedded System Development Track

Embedded.....Everywhere

PiTechnologies Embedded Team

PiTechnologies 2

Where are we ?

Dr. Muppala is currently an associate professor

Department of Computer Science and Engineering

The Hong Kong University of Science and Technology

Embedded For FCI !

Dr. Jogesh K.Muppala http://www.cs.ust.hk/~muppala/

PiTechnologies 3

CS students have often shied away from the field of Embedded Systems due to Hardware area

Recent trend for Embedded System with the growing importance of software component has brought about new opportunities for CS students

If we lessening the emphasis on the hardware aspects we can still allow them to master sufficient knowledge and skills to venture in this filed

Embedded For FCI !

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Track Agenda

Session 1: Introduction to Embedded System Development

LAB 1 : C programming (1)

Session 2: Microcontroller Architecture

LAB2 : C Programming (2)

Session 3: C programming for Embedded applications and Mikro-C

LAB3 : C programming for Embedded applications and Mikro-C

Session 4: Microcontroller applications based on ESD smart kit

LAB4 : Microcontroller applications based on ESD smart kit

Session 5: Microcontroller applications based on ESD smart kit

LAB5 : Microcontroller applications based on ESD smart kit

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Track Agenda

Session 6: ARM processor architecture and ARM based applications

LAB6 : ARM processor architecture and ARM based applications

Session 7 : Software Engineering

LAB7 : Software Engineering

Session 8 : Real time operating systems

LAB8 : Embedded Operating System

Session 9: : Embedded Operating System

LAB9 : Practical applications in embedded systems

Session 10: Final Project

LAB10 : Final Project

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PiTechnologies 7

PiTechnologies Embedded Team

ARM Processor Architecture Introductory Level

Course outline

General introduction about ARM

ARM Processor fundamentals

Exception and Interrupt handling

19999999

9 PiTechnologies 9

Agenda


Basic Concepts

What is ARM ?

Why ARM?

ARM Design Philosophy

ARM Application

ARM License and families

ARM ISA

Embedded System Hardware

Embedded System Software

ARM Processor Technology

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Agenda


Basic Concepts

What is ARM ?

Why ARM?


ARM Application


ARM ISA




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BASIC Concepts

ISA- Instruction Set Architecture- is part of computer architecture related to programming including :

data types,

instructions,

registers,

addressing mode,

memory architecture,

and interrupts

Basic Concepts

RISC Design philosophy

Simple but powerful instructions (do less )

Executed within a single cycle at high speed

Reduce the complexity of hardware

Provide greater flexibility in software

Place greater demands on the compiler intelligence

ALPHA ,ARC,ARM,AVR,MIPS and SPARC

reduced mean the work required for single instruction is reduced (reducing memory access) compared to CISC

Basic Concepts Design Rules for RISC Philosophy

Instruction

reduced ,one cycle instruction

programmer synthesize complex operation (/)(*)

fixed length instructions To allow pipeline Pipeline

processing of instruction divided in to many stages executed in parallel in pipelines which advances one step each

clock cycle to maximize throughput

Basic Concepts

Register

general purpose, can hold address or data

acts as fast local memory for data processing operation

Basic Concepts

Load-Store Architecture

Processor operate on data stored on registers

Load and store instructions transfer data between register bank and external memory

Saving the cost of memory access by separating memory access from data processing (use data multiple time)

Basic Concepts

Typically CISC chips have a large amount of different and complex instructions and that because the philosophy behind it is that hardware is always faster than software, therefore one should make a powerful instruction set

Basic Concepts

You must keep in your mind the main difference between RISC and CISC

Hardware Hardware

Compiler Compiler

More complex

Less complex

CISC RISC

Basic Concepts

Again you should think what you want not what is the better

Agenda


Basic Concepts

What is ARM ?

Why ARM?


ARM Application


ARM ISA




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What is ARM ?

Advanced RISC Machine

ARM: 32-bit RISC processor

Developed by ARM Ltd founded 1990

In 2000 billion arm core in the market

In 2009, ARM processors account for approximately

90% of all embedded 32-bit RISC processors.

Example products: iPod, iPhone, Nokia

N93,N95,NEXUS, ..etc PiTechnologies 21

Agenda


Basic Concepts

What is ARM ?

Why ARM?


ARM Application


ARM ISA




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Why ARM ?

Reduce power consumption

Code density.

Arm have great hardware debugging technology

so you can view what happen on hardware during

the execution with great visibility

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Agenda


Basic Concepts

What is ARM ?

Why ARM?


ARM Application


ARM ISA




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ARM is not a pure RISC arch. (some enhancement )

ARM instruction set differ from pure RISC to make arm suitable for embedded application

Differences between arm and RISC

Variable cycle execution for certain instructions

Inline barrel shifter leading to more complex instructions

Thumb 16-bit instruction set

Conditional execution

Enhanced instructions (DSP like, 16 x 16-bit multiplication)

Agenda


Basic Concepts

What is ARM ?

Why ARM?


ARM Application


ARM ISA




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ARM Application

ARM Applications

ARM Processor: Cortex-

A8

Silicon Partner:

Qualcomm

ARM Processor Family: Cortex-A Series ARM Processor: Cortex-A8 Silicon Supplier: Samsung

ARM Processor Family: Cortex-A Series ARM Processor: Cortex-A8 Silicon Supplier: Qualcomm QSD 8650 @ 1 GHz

ARM Processor Family: Cortex-A Series ARM Processor: Cortex-A8 Silicon Supplier: Samsung Hummingbird S5PC110 ARM Processor

Family: ARM11 Silicon Supplier Freescale i.MX353 applications processor

ARM Processor Family: ARM9

ARM Application

ARM Application TEGRA CHIP

ARM Application

Dual-Core ARM Cortex A9 CPU:

NVIDIA Tegra features the worlds first dual core CPU for mobile applications in addition to support for Symmetric Multi-Processing (SMP) which enable :

Tasks to be parallelized between the two ARM Cortex A9 processors,

Delivers faster load times of Web pages, quicker UI responsiveness, and faster rendering of complex Web pages.

ARM Application TEGRA Powered Devices

Tablets

ARM Applications

The Snapdragon application processor core, is Qualcomm's

own design.

Based on ARM Cortex-A8 core and ARM v7 instruction set, but

theoretically has much higher

performance for multimedia-

related SIMD operations.

All Snapdragon processors contain the circuitry to

decode high-definition

video (HD) resolution

ARM Applications

The Samsung Hummingbird is a system-on-a-chip (SoC) designed

for mobile devices, which is based

on the 45nm ARM Cortex

A8 architecture with

a PowerVR SGX540 GPU.

One advantage of the Hummingbird SoC is the high performance with

low power consumption.

The chip was first used in the Samsung Galaxy S, followed

by the Samsung Wave,

the Samsung Galaxy Tab,

the Samsung GT-I9020T (Google

Nexus S),

ARM Applications

ARM and Open Source Technologies

ARM and Open Source Smartphones

Open hardware mobile phone

ARM9 processor based on SC32442 from Samsung

Support multiple Linux distribution and hold capabilities to support multi boot

Schematic ,Hardware and reference manuals are available to community for use

ARM and Open Source

txtr reader is product of Txtr, Berlin based company engaged in building tools & services for digital reader.

It is based on Freescale i.Mx31 SoC which contains ARM11 processor core.

It can also encourages existing device vendor to integrate txtr service on there platform.

Reader hardware consist of

Bluetooth, Wifi,

Near Field Communication (NFC)

EDGE modem to communicate with device.

Interface such as, 3D Accelerator meter,

Touch screen based Electronic ink display,

vibrator motor makes it more attractive platform for developing entertainment applications.

ARM and Open Source

Odroid is for developers focused on entertainment and gaming

device.

It comes with schematics & includes it's support in Linux &

Android.

Odroid contains Samsung S5PC100 SoC, which contains

ARM Cortex-A8 833MHz

processor, 512 MB RAM, Touch

screen & HDMI output, Wi-Fi,

Bluetooth

ARM Applications

From all the previous we conclude that why ARM is one of the most commonly used 32-bit embedded processor core

Top semiconductor companies depend build product based on ARM because

Low power consumption

High code density

Low cost memory

Internal debugging capabilities

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Agenda


Basic Concepts

What is ARM ?

Why ARM?


ARM Application


ARM ISA




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ARM Naming Convention

y z labels ARM x Number of the core Memory management model Cache information Extra features

ARM Naming Convention

Agenda


Basic Concepts

What is ARM ?

Why ARM?


ARM Application


ARM ISA




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ARM ISA

ARM processor provides support for two sets:

ARM Instruction Set

32-bit instruction length

Thumb Instruction Set

16-bit instruction length

It improves code density

Compressed version of ARM Instruction Set

Jazelle

Java byte codes

Allows faster operation for JME mobile applications PiTechnologies 46

Conclusion

ARM feature

power consumption

High Code Density

Low Cost Memory

Internal Debugging Capabilities

ARM Instruction Set

Variable Cycle Execution

Inline barrel Shifter

Thumb 16 bit inst.

Conditional execution

Enhanced instruction

PiTechnologies 47

Agenda


Basic Concepts

What is ARM ?

Why ARM?


ARM Application


ARM ISA




PiTechnologies 48


ARM processor controls the embedded device. Different versions are

available to suit the desired operating characteristics ARM processor core is the engine that execute instructions and

manipulates data Controller coordinate important functional block interrupt and

memory controllers are commonly used Peripherals provide all input-output capability external to chip Bus used to communicate between the core and surrounding parts


Selection of memory depends on:

Performance

Power consumption

Price

Memory characteristics:

Memory hierarchy

Memory types

Memory width


Memory width: 8, 16, 32 and 64-bit Consider as design issue when you deal with ARM Also have effect on over all cost and performance ratio

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Agenda


Basic Concepts

What is ARM ?

Why ARM?


ARM Application


ARM ISA




PiTechnologies 53


PiTechnologies 54

Agenda


Basic Concepts

What is ARM ?

Why ARM?


ARM Application


ARM ISA




PiTechnologies 55

ARM Technology

There are a common set of industry-leading technologies found across the entire range of ARM processors, including

The powerful ARM, Thumb and Thumb-2 instruction sets

DSP and SIMD extensions

NEON advanced SIMD instructions for efficient multimedia processing

IEEE 754-compliant hardware floating point support (VFP)

Hardware-accelerated Java support (Jazelle)

TrustZone security extensions

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ARM Processor Fundamentals

ARM Core Data Flow Model

Registers

Program Status Registers

Processor Modes

Pipeline

Core Extension

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This figure shows the ARM Von-Neumann

Architecture

For Von-Neumann the same bus hold data

and address

HARVARD implementation of the core use

two different busses

Instruction decoder translate instruction

before they are executed

Sign Extend unit converts sign 8/16-bit

numbers into 32-bit values before storing

in the register file

Register file is storage bank made up of 32-

bit register and data placed on it


ARM use Load-Store architecture like all RISC

processor, load copy data from memory to register in

the core and store copy data from register to memory

Register Can hold sign or unsigned 32-bit values

ALU: Arithmetic Logic Unit

MAC: Multiply Accumulate unit

Operation flow will be by taking Rn and RM from

busses then the results Rd Stored in register file


Load/store instructions use ALU to generate memory

address to be stored in address register

The Incrementer is responsible for incrementing the

address on the address register for reading multiple

registers from sequential addresses

Its Clear that barrel shifter and ALU can calculate wide

range of expressions and addresses

Registers

All registers are 32-bits wide and can hold either data or an address

There are up to 18 active register 16 for data-

r0 to r15 - visible to all programmer and 2 for processor status

r13 - sp: stack pointer register, which holds

stack head in the current processor mode r14 - lr: link register, which hold the

return address whenever subroutine is called r15 - pc: program counter register, which hold

the current instruction address

Registers

Depending on the context r13 and r14 may be used as general purpose and banked during processor mode change

But its dangerous to use r13 as general register as its hold as valid stack point

Register r0 to r13 are orthogonal so any instruction applied to r0 can be applied to r13

In addition there is 2 program status register CPSR and SPSR

Registers ..contd

CPSR : Current Program Status Register

32-bit register holds current processor's status

To monitor and control internal operations

Some processor have J-bit in flags for Jazelle


Conditional flags

Q indicate overflow and saturation for core contain DSP extension

J set for jazella enabled in some cores (need software license

from SUN and ARM)to take advantage of this mode

Processor Modes

Processor mode determine which register are active and read

/write access to CPSR

Privileged mode allow full read-write access to CPSR, non-

privileged allow read for control field but allow read and write

to conditional flags

Processor Mode

Processor Modes

Processor

mode

Abb. Description

User usr Normal program execution mode

FIQ fiq Used for fast interrupt handling

IRQ irq Used for general purpose interrupt handling

Supervisor sve A protected mode for the operating system

Abort abt Implements virtual memory and/or memory

protection

Undefined und Supports software emulation of hardware

coprocessors

System sys Runs privileged operating system tasks

ARM Processor Runs in one of 7 Modes:

Processor Mode

Abort mode when attempt to access not exist memory location

Fast int. & int. mode represents two level of interrupts

Supervisor Mode the mode processor in it in starting up and

after reset and when operating system want to make its

initialization and kernel operate on it

System Mode is special version of user mode but have full read

and write access to CPSR

User Mode for program and applications

Undefined Mode for unknown instructions and Coprocessor

Processor Modes

Modes other than user mode are called Privileged mode

FIQ, RIQ, Supervisor, Abort and Undefined are called Exception mode

The following triggers change the mode of the processor:

Software control (by operating system)

External interrupt (IRQ or FIQ)

Processor exceptions (data abort , prefetch abort ,undefined inst.,)

Registers

Based on Processor modes, different types of registers exist.

The user and system mode come with r0-r15 plus the CPSR.

Registers

The previous figure illustrate 37 register in register file

There is 20 register hidden from program at different times

This shading register is available when processor in particular mode

Any processor mode can change its mode by write to CPSR except user mode

CPSR is saved is SPSR when mode changed (interrupt)

Pipeline

The average rate of instruction execution per processor cycle is called Instruction Throughput

To speed up the execution, RISC processors fetch the next instruction while executing the current instruction, which is known

as Pipeline Mechanism

Basic RISC pipeline stages are:

Fetch: load the instruction to be executed from memory

Decode: identify the instruction to be executed

Execute: perform instruction processing and write the results back to corresponding registers

Pipeline

An examples of three instruction sequence execution:

Pipeline

ARM Vs. THUMB

ARM architecture with core v4 and above define 16 bit instruction set called THUMB

THUMB instruction set is subset of ARM instruction set also function and aliases

Program in THUMB state cannot execute ARM state and vice versa

You must switch the assembler to produce appropriate opcode

Functionality of THUMB instruction set is subset of ARM instruction set

In THUMB only branch can be conditionally executed

ARM Vs. THUMB

In THUMB mode most instructions can access only low register ro to r7- but high register has limited access

Barrel shifter used in separate instructions not in the same instruction

No instruction will access CPSR or SPSR directly

No instruction for semaphore and co-processor

operating in general purpose register for data processing instruction with two operand and the result putted in one of the two input operand

Core Extensions

Core extensions are a set of components reside close to the ARM core to do extra functionality

Its standard components placed next to ARM core

Its improve performance ,mange resources, designed to provide flexibility in handling particular application

Each ARM family has its own set of extensions available

There is three hardware extensions exist around arm core depending on ARM family

Core Extensions

The extensions is

Cache and Tightly Coupled Memory

Memory Management

Co-processor Interface

Core Extensions Cache &TCM

Cache is block of fast memory placed between main memory

and core

With cache processor can run the majority of the time without

having to wait for data from slow external memory

Most ARM use single -level internal to processor

Not all embedded system need the performance gained by

using cache

Core Extensions Cache &TCM

We have two cache forms for von-Neuman style cores and Harvard style core

In von- Neumann called unified cache why ?

The logic that connect memory system with the AMBA bus called control and logic block

Cache increase the performance but decrease system predictability

Core Extensions -Cache & TCM

Predictability problem will appear in real time system

In this system I have defined time to execute each task so its hard to violate this time

In cache I don't know what is the content exist on it when I executing any task

So I cannot determine the accurate time required for executing

In hard real time system big problem will occurs if the execution not in time

Core Extensions-Cache & TCM

The conclusion I cannot predict the full status of the cache and time required for execution after period of time or the cache able to serve me in deterministic time or not

Also I don't know if the required data exist in cache so the execution will be fast or I need extra time to access main memory

So in real-time system its hard to use cache

Solution in TCM

Core Extensions - TCM

Tightly Coupled Memory is a fast SRAM located close to the core processor

TCM is treated as a memory in the address map, and can be accessed as a fast memory

Performance is highly improved without affecting predictability when TCM is used As i can put or remove data from TCM

An ARM processor may have both TCM and cache (performance and real time response )

Core Extensions - MMU

MMU used to mange multiple memory devices to organize this device and help in protecting devices from application that trying to make inappropriate access

ARM core have three different type of MM hardware

No extension provide no protection for system

Memory Management extensions in ARM are: Memory Protection Unit (MPU)

Memory management unit (MMU)

Core Extensions -MM

Memory protection unit

Provides partial protection, divides memory into memory regions each with special co-processor registers for specific access permissions for each

Memory Management Unit:

Has tables and provides virtual to physical memory maps and access permissions, used for sophisticated embedded systems with OSs supported multitasking

Non protected memory

Fixed and provide no flexibility used for simple system It is normally used for small, simple embedded systems that require no protection from rogue applications

Core Extensions - Coprocessor

Co-processor is a unit that can be attached to the core

Each coprocessor can come with its own registers, instructions, processing capabilities

There can be multiple co-processors attached to the core.

When decoding an instruction, and it is found that it is a coprocessor instruction it is passed to the relevant coprocessor for execution

If the coprocessor does not exist, then the core performs a UNDEF exception

This allows the programmer to handle the coprocessor instructions in SW (by handling the UNDEF exception)

Exceptions, Interrupts and Vector Table

When an exception or interrupt occurs, the PC is filled by the appropriate address from the vector table.

Each vector must contain a branch instruction to the appropriate routine

Linux and windows CE can use the advantage of high and low memory address

When exception or interrupt occurs the processor suspend normal execution and start loading instructions from exception vector table

Each vector table entry contains a form of branch instruction pointing to the start of specific routine (just address)

Exceptions ,Interrupts and Vector

Exceptions, Interrupts and Vector Table

RESET: Occurs at power up or at reset of CPU in this case the branch instruction will jump to the initialization code so its the first instruction executed by processor after power up

UNDEF: Occurs when an instruction can not be decoded or processor cannot decode instruction

SWI: Occurs when SWI instruction is executed (used used as the mechanism to invoke OS routine)

PABT: occurs when the processor attempts to fetch an instruction from an address without the correct access permissions. The actual abort occurs in the decode stage.

Exception ,interrupts and vector

table

DABT: similar to pre fetch abort but raised when an instructions

attempt to access data memory without correct access

permission .

IRQ/FIQ: H/W Interrupts (if not masked in CPSR) used by external hardware to interrupt the normal execution of the

processor FIQ reserved for hardware requiring faster

response

Lets Start .

Can You Build Your Own Core ?

Lets Start .

Available tools to start

Skyeye

GNU ARM

Open Cores

101

ARM Families

ARM Instruction Set

ARM Families

ARM Families

ARM has designed a number of processors that are grouped into different families according to the core they use.

The families are based on the ARM7, ARM9, ARM10, and ARM11cores

ARM 7 FAMILY Von-neuman style

Three stage pipeline

Execute ARM v4T instruction set

Example : ARM7TDMI Very popular core

used in most embedded 32 bit applications

provide very good performance to power ratio

First core include THUMB, Fast multiply instructions and embedded ICE technology

ARM Families ARM 9 Family

announced in 1997

Because of its five-stage pipeline, the ARM9processor can run at higher clock frequencies than the ARM7 family. The extra stages

improve the overall performance of the processor.

The memory system has been redesigned to follow the Harvard architecture

The first processor in the ARM9 family was the ARM920T, which includes a separate D + I cache and an MMU. This processor can be used by operating systems requiring virtual memory support.

The ARM940T includes a smaller D +I cache and an MPU. The ARM940T is designed for applications that do not require a platform operating system.

Both ARM920T and ARM940T execute the architecture v4T instructions.

There are two variations: the ARM946E-S and the ARM966E-S. Both execute architecture v5TE instructions. They also support the optional embedded trace macrocell (ETM), which allows a developer to trace instruction and data execution in real time on the processor. This is important when debugging applications with time-critical segments.

ARM Families

The ARM946E-S includes TCM, cache, and an MPU.

The sizes of the TCM and caches are configurable. T

his processor is designed for use in embedded control applications that require deterministic real-time response. I

n contrast, the ARM966E does not have theMPU and cache extensions but does have configurable TCMs.

The latest core in the ARM9 product line is the ARM926EJ-S synthesizable processor core, announced in 2000. It is designed for use in small portable Java-enabled devices such as 3G phones and personal digital assistants (PDAs).

The ARM926EJ-S is the first ARM processor core to include the Jazelle technology, which accelerates Java bytecode execution.

ARM Families

ARM10 Family announced in 1999, was designed for performance. It extends the ARM9

pipeline to six stages. It also supports an optional vector floating-point (VFP) unit, which adds a seventh stage to the ARM10 pipeline. The VFP significantly increases floating-point performance and is compliant with the IEEE 754.1985 floating-point standard.

The ARM1020E is the first processor to use an ARM10E core. Like the ARM9E, it includes the enhanced E instructions. It has separate 32K D + I caches, optional vector floating-point unit, and an MMU. The ARM1020E also has a dual 64-bit bus interface for increased performance.

ARM1026EJ-S is very similar to the ARM926EJ-S but with both MPU and MMU. This processor has the performance of the ARM10 with the flexibility of an ARM926EJ-S

ARM Families

Specialized Processors StrongARM was originally co-developed by Digital Semiconductor and is now exclusively

licensed by Intel Corporation.

It is has been popular for PDAs and applications that require performance with low power consumption.

It is a Harvard architecture with separate D+I caches.

StrongARM was the first high-performance ARM processor to include a five-stage pipeline, but it does not support the Thumb instruction set.

It is a Harvard architecture and is similar to the StrongARM, as it also includes an MMU.

SC100 is at the other end of the performance spectrum. It is designed specifically for low-power security applications. The SC100 is the first SecurCore and is based on an ARM7TDMI core with an MPU.

This core is small and has low voltage and current requirements, which makes it attractive for smart card applications

Questions?

Mahmoud S.Khalifa [email protected]

Web: www.PiTechnologies.net Facebook Page : PiTechnologies. Page

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pi_ito_2015_embedded_ arm.pdf

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