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Rajkumar Pitchai Phaneendra vatsavaiPHY Interface for the PCI Express (PIPE) Architecture Mindtree Limited 2013. Confidential - for limited circulation onlyConfidential - for limited circulation only1Confidential - for limited circulation onlyLayering diagram- Physical layer

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Confidential - for limited circulation onlyPHY layer - Partitioning3

Confidential - for limited circulation only.4TLDLLPLElectrical BlockMACLogical BlockPCSPMAPCIe Protocol StackTXRXRXTXPIPE Interface8b/10bElastic BufferRx DetectionConfidential - for limited circulation onlyPHY/MAC interface

5Confidential - for limited circulation onlyPHY Functional diagram6

Confidential - for limited circulation onlyTransmitter - 8b/10b encoder PurposeTo embed a clock into the serial bit stream transmitted on all lanesNo clock is therefore transmitted along with serial data bit streamThis eliminates the need for a high frequency clock signal on the link which would generates the EMI noise.

Why Encoding?PCIe is a serial bus with the clock embedded in the data, it needs to ensure that enough level transitions (1 to 0 and 0 to 1) occur for a receiver to recover the clockTo increase level transitions, PCIe uses 8b/10b encoding, where every eight bits are encoded into a 10-bit symbol that is then decoded at the receiver. Thus, the bus needs to transfer 10 bits to send 8 bits of encoded data.7Confidential - for limited circulation only8b to 10b encodingSignal indicator D(data character) or K(control character)CRD (current running disparity)-> represents the sum of 1s & 0s for the transmission link since link initialization

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Confidential - for limited circulation only8b to 10b encoding9

Confidential - for limited circulation onlyControl character encoding10Control characters are encode into controls symbols(special symbols) like STP,SDP,END,EDB,COM,PAD,SKP,FTS & IDLThese characters are not scrambled by the transmitter logic, but are encoded into 10bit symbols.Since these are not scrambled, receiver logic can easily detects the symbols in an incoming symbol stream

Confidential - for limited circulation only

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Confidential - for limited circulation onlyAdvantages of 8b/10b EncoderEmbedded clockEncoding of special control charactersError detection12Confidential - for limited circulation onlyTransmitter Block (2.5GT/s , 5GT/s) 13

Confidential - for limited circulation onlyTransmitter Block (8.0GT/s)

14Confidential - for limited circulation onlyReceiver BlockSpecial symbol detectorElastic buffer8b/10b decoder

Elastic buffer (Synchronization buffer):

Used to ensure data integrity when bridging two different clock domainsThis is the simple FIFO where data is deposited at certain rate and removed at a rate derived from different clock

15Confidential - for limited circulation onlyElastic bufferWhile a transaction , at one device recovered clock from receiver data and the clock transmitted at another device may slightly differSo recovered clock & the receiver clock will differ. In this case data corruption will occur.To avoid this situation elastic buffers are used & the data recovered through special symbols.Whenever recovered clock is faster/slower than system clock, there is a overflow/underflow in the elastic buffer will occur.16Confidential - for limited circulation onlyElastic buffer- NeedLocal clock domain that it uses to clock all of its internal gates and to transmit dataRecovered(received) clock domain uses to latch inbound data. Data being received will have to cross the clock boundary from the recovered clock domain to the local clock domain device to process that informationExact purpose to allow received data to transition from recovered clk domain to local clk domain

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Confidential - for limited circulation onlyElastic buffer- how it works?Function of elastic buffer is to bridge these two clk domains by compensating their phase & frequency differences- thereby allowing the received data to maintain its integrity Bridging these 2 clk domains by depositing the received data into the buffer(recovered clk domain) & pulling the dataout of the buffer (local clk domain)Since 2 clk domains are running at diff freq, buffer has potential to overflow underflow.so to prevent this error condition, buffer enables to insert or remove the special symbols as SKP symbols(transmitter are required to send SKP ordered set)18Confidential - for limited circulation onlyImplementation of elastic buffer:

19Confidential - for limited circulation only8b/10b decoder:20

D/K indicatorDisparity calculatorDisparity Error detectionConfidential - for limited circulation onlyReceiver Block (2.5 and 5.0 GT/s)21

Confidential - for limited circulation onlyReceiver Block (8.0 GT/s)

22Confidential - for limited circulation onlyKey features of PCI Express PHY23Standard PHY interface enables multiple IP sources for PCI express logical layer & provides a target interface for PCI express PHY vendorsSupports 2.5GT/s only or 2.5GT/s and 5.0GT/s, or 2.5 GT/s, 5.0 GT/s and 8.0 GT/s serial data transmission rateUtilizes 8-bit,16-bit or 32-bit parallel interface to transmit and receive PCI express dataAllows integration of high speed components into a single functional block as seen by the endpoint device designerData and clock recovery from serial stream on the PCI Express bus

Confidential - for limited circulation onlyKey features of PCI Express PHYHolding registers to stage transmit and receive dataSupports direct disparity control for use in transmitting compliance pattern(s)8b/10b encode/decode and error indication128/130b encode/decode and error indicationReceiver detectionBeacon transmission and receptionSelectable Tx Margining, Tx De-emphasis and signal swing values24Confidential - for limited circulation onlyName : Rajkumar PitchaiEmail : Rajkumar_pitchai@mindtree.comwww.mindtree.comIndia | USA | UK | Germany | Sweden | Belgium | France | Switzerland | UAE | Singapore | Australia | Japan | ChinaConfidential - for limited circulation only