pipeline synchronization

Avshalom Elyada, Ran Ginosar Pipeline Synchronization 1

Pipeline Pipeline SynchronizationSynchronization

A Unique and Successfully A Unique and Successfully Implemented Approach to Implemented Approach to

the Synchronization Problemthe Synchronization Problem

Based on the articleBased on the article“Pipeline Synchronization” “Pipeline Synchronization” by Jakov N. Seizovic, 1994by Jakov N. Seizovic, 1994


Search for New Search for New SolutionsSolutions

• More and more sync operations per unit time:– complex chipsmore inter-domain transitions– Higher freq less settling time smaller MTBF

• Existing solutions no longer deliver required PoF– And if they can it is a matter of the next

generation or two…

• inter-domain interfaces are often long interconnects; need to solve both with one mechanism


Current SolutionsCurrent Solutions

• Reviewed in previous lectures– Two-flop – Clock shifting/streching, predicitve– …

• All treat sync as “one-shot” process, at end of which signal is either synced or not



• Pipeline approach: control signals synced in stages, along with data flow

• Each step of the pipeline “partially synchronizes” the signal, reducing it’s degree of asynchronicity.

• More stages less PoF: safety vs. latency tradeoff

• Data is latched at each stage– Divide long interconnect into short segments– Deal with inter-bit skew


Degree of Degree of AsynchronicityAsynchronicity

• Until now, signal was either synchronous or asynchronous

• For sync in stages, let’s look at more information:– A signal’s arrival time in interval [0-T]

as random variable with distribution function

and degree of asynchronicity :


• For a time-window 0<Tw<T, Asynchronicity of a signal is defined as:

• Intuitive meaning: when sampling within a window of Thold+Tsetup=Tw , As is the lowest prob. of MS behavior that can be achieved.

Asynchronicity of Asynchronicity of SignalsSignals


Insightful ExamplesInsightful Examples• Synchronous: can make As = 0 if satisfy

Thold+Tsetup< certain Tmax

• Asynchronous: As = Tw/T

• As = 1 corresponds to a “Malicious” signal: no matter where we sample, the signal always arrives within our time window



• Building blocks– Stage-synchronizer based on one or

two Mutual-Exclusion elements– FIFO element

• Start with async elements (latch & latch-like)– Explore possible use of DFFs for both

data & sync (ctrl) path• More appealing to sync. designers


An ME as a Synchronizer An ME as a Synchronizer (I)(I)

• Outputs mutually exclusive : only one asserts at a given time

• Connect ‘clk’ and signal ‘R’ to inputs• ‘A’ synced output, other output unused

clk

S

clk

XR1

R0

A1

A0

ME

R A

A +

R -

A -

R

Clk +Clk -

Clk=0

Clk=1


An ME as a An ME as a SynchronizSynchroniz

er (II)er (II)

A is synced to clk


An ME as a Synchronizer An ME as a Synchronizer (III)(III)

Inverse the clk:A syncs to clk sync to posedge

R1

R0

A1

A0

ME

R A

clk


ME ImplementationME Implementation• A latch with a MS

filter• As inherent to any

sync. decision h/w, ME has a MS-state.– If in MS-state, Ao

does not assert until MS resolved

– Next clk edge forces ME out of MS-state.


Dual-edge SynchronizerDual-edge Synchronizer• Want to use 2-

phase protocol, better for long interconnects

• Need to sync rise and fall of Ri->Ro

• Use 2 MEs and another latch


FIFO FIFO ElementElement

• Holds data in stage while ctrl is synced

• 2-phase single-rail handshake– 2-phase more suited for

long interconnects

• Latch as mem. element– can also use DFF, appeal

to sync. designers

• Simple async ctrl (petrify)– More on implementation

next time…


Pipeline w/ Embedded Pipeline w/ Embedded SynchronizingSynchronizing

S Ri

Ai

Di

Ro

Ao

Do

S Ri

Ai

Di

Ro

Ao

Do

S Ri

Ai

Di

Ro

Ao

Do

Synchronous Asynchronous

Taken from “Synchronization Ideas”, Charles E. Dike, Intel Corporation


Likewise for Multi-Likewise for Multi-Synchronous DomainsSynchronous Domains

S Ri

Ai

Di

Ro

Ao

Do

S Ri

Ai

Di

Ro

Ao

Do

Ri

Ai

Di

Ro

Ao

Do

S

Mult.-sync. domain B Mult.-sync. domain A

S

S

S

Taken from “Synchronization Ideas”, Charles E. Dike, Intel Corporation


Step-by-Step-by-StepStep


Long Interconnect:Long Interconnect:Pipeline SynchronizerPipeline Synchronizer

Seizovic, “Pipeline Synchronization,” Async 1994Kessels, Peeters, Kim, "Bridging Clock Domains by synchronizing the mice in the mousetrap", PATMOS, 2003

B clk

half cycledistance

• Last 3 stages in each direction contain synchronizers

A clk

ME

ME

A clk

REQ

ME

B clk

ME

ME

ACK

ME


Probability of Failure Probability of Failure • Pipeline PoF as formally proven in article:

-k(T/2-Toh)/τ Pk=P0*e– P0– PoF without any sync– k– # stages

• t = T/2-Toh is the time each sync hasToh = synchronizer+FIFO delay

• Recall prob. of exit MS is P(t) = exp(-t/τ)• Intuitively, each stage works alone

during its allocated time (while clk is high, minus overhead). The contributions are combined.


FutureFuture

• At each stage, time for sync isT/2 –Toh. Insert logic in the pipeline– On data, no problem– On ctrl possible, Toh effectively grows

need more stages for same PoF– But pipeline would have added

functionality• Can also contemplate insertion of

ME-elements along existing pipelines in synchronous designs…


Glancing BackGlancing Back

Need for better solution that also addresses long-interconnect issueAsynchronicity (degree of)Syncing in stages: pipelineME as a synchronizerFIFO elementPipeline Synchronizers


Next PresentationNext Presentation

More on Pipeline Sync, …“Bridging Clock Domains by Synchronizing the Mice in the Mousetrap” Kessels, Peeters, KimPhilips Research Laboratory, 2003

pipeline synchronization

Documents