power efficient ram mapping algorithm for fpga embedded
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POWER-EFFICIENT RAM MAPPINGALGORITHM FOR FPGA EMBEDDED
MEMORY BLOCKS
PRESENTING BY:
SHERIN SCARIASEMESTER 1.M.Tech
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INTRODUCTION
Embedded memory blocks have been found toconsume between 10% and 20% of core dynamic
power in typical FPGA designs
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INTRODUCTION
The application domain of FPGAs is expanding
to include mobile and power-sensitiveenvironments
In FPGA, embedded memory blocks areimplemented using synchronous SRAM.
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INTERNAL BEHAVIOUR OF
SYNCHRONOUS RAM
SRAM contains R/W enable signals, clock enable
signals
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INTERNAL BEHAVIOUR OF
SYNCHRONOUS RAM
READ OPERATION :
The following events occur in sequence, in response to a
rising clock edge.o The memory port clock (MClk) is strobed, causing the
BIT lines to be precharged to Vcc.o The read address is decoded, and one word line is
activated.
o The BIT line difference is identified by senseamplifiers, causing the read data to be strobed into acolumn multiplexer.
o The Read Data passes through the column multiplexerand a latch conditioned by Read Enable to the RAMexternal Read Data lines.
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INTERNAL BEHAVIOUR OFSYNCHRONOUS RAM
WRITE OPERATION :
o MClk is strobed, causing the BIT lines to beprecharged to Vcc.
oThe Write Enable signal, which conditioned byMClk,creates a write pulse that transfers write
data to the write buffers, and a word line isactivated following write address decode.
o The write buffer data is stored in the RAM cell.
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INTERNAL BEHAVIOUR OFSYNCHRONOUS RAM
In R/W operations mainly dynamic power is
consumed by BIT line precharging. To eliminate the precharging we are using a clockenable signal, there by reducing powerconsumption.
The goal of power aware RAM mapping is toreduce memory precharges.
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TYPICAL RAM MAPPING FLOW
1)Logical memory creation. User-defined RAMdescriptions are processed by the FPGA compilation softwareto create logical memories with the desired characteristics.
2)Logical-to-physical RAM processing. Logical RAMsare converted into one or more RAM blocks, which match theexternal interface and size constraints of available embeddedmemory blocks.
3) Embedded memory block placement. RAM blocksandassociated control logic are assigned to available on-chipembedded memory block and logic resources.
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REASONS FOR DYNAMICPOWER CONSUMPTION
In the case of asynchronous memories, read and
write enable signals were used, instead of clockenable signals.
Size of logical memory may not match with thatof the embedded blocks.
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SOLUTION : EFFECTIVE RAMMAPPING
Two algorithms
1)Conversion of read and write enables toread and write clock enable signals.
2) Implement a multi banked RAMmapping for mapping to more than one
embedded memory blocks.
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CONVERSION OF ENABLESIGNALS
Read clock enable
Both read enable and read clock enable signalsmust be active to successfully perform anembedded memory block read transaction.
Read enable input is attached to a control signal
and read clock enable input is always tied toactive logic 1.
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MULTI-BANKED RAM MAPPING
Done by variation in depth and widthconfiguration.
There are 2 types of banking.
1) Vertical slicing.2) Horizontal slicing.
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VERTICAL SLICING
The memory is sliced along the depth.
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VERTICAL SLICING
Advantage:
No much address decoders and multiplexers, Sopower consumption by these blocks is nil.
Disadvantage:
Each memory block is active in each memoryaccess, so substantial power consumption.
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HORIZONTAL SLICING
Memory is divided along its width.
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HORIZONTAL SLICING
Advantage:
Only one memory block is active in each memoryaccess, so no substantial power consumption.
Disadvantage:
Dynamic power is consumed by added addressdecoder and multiplexer.
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SO WHICH SLICING TECHNIQUE..?
In Vertical slicing implementation, memory
block power is increased and multiplexer,decoder power is decreased.
In Horizontal slicing implementation,multiplexer, decoder power is increased and
memory block power is decreased.
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LOGICAL RAM PARTITIONINGALGORITHM
To evaluate the relative power consumption of a
series of logical to physical ram mapping.
Mapping is based on no. of embedded memoryblocks, decoder, multiplexer etc.
Mapping evaluation is performed for each blocksizes.
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LOGICAL RAM PARTITIONINGALGORITHM
The relative cost for each mapping is determined byequation
x Cost=W*Pmux+N*Pram+Paddr_decoder
Cost - relative power cost for the mappingW -width of the logical RAM
Pmux per bit dynamic power of a read port multiplexerN number of requiredembedded memory blocksPram per block dynamic powerPaddr_decodedynamic power consumption of the address
decoder.
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POWER-AWARE MEMORY
PARTITIONING ALGORITHM
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1.Initially resource-feasible mapping for each logicalmemory block is determined.
2.All possible logical-to-physical mapping are countedand evaluated based on their power consumption.
3. For each logical memory, the minimum power depthand width configuration of each memory block is
stored.4.Then initial physical mapping is replaced by low
power mapping.
5.It is again re-ordered so that mapping having lowest
dynamic power is considered first.
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CONCLUSION
These techniques take advantage of the internal
structure of FPGA embedded memory to reducememory dynamic power dissipation.
Embedded memory block clock enables areused to deactivate RAM block pre-charging.
Several optimizations for power-savingapproaches could be implemented in the future.
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THANK YOU
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THANK YOU