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Power Electronic Devices Semester 1 Lecturer: Javier Sebastián Electrical Energy Conversion and Power Systems Universidad de Oviedo Power Supply Systems

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Power Supply Systems. Electrical Energy Conversion and Power Systems . Universidad de Oviedo. Power Electronic Devices. Semester 1 . Lecturer: Javier Sebastián. Research Group Power supply Systems (Sistemas Electrónicos de Alimentación). - PowerPoint PPT Presentation

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Page 1: Power Electronic Devices

Power Electronic Devices

Semester 1

Lecturer: Javier Sebastián

Electrical Energy Conversion and Power Systems

Universidadde Oviedo

Power Supply Systems

Page 2: Power Electronic Devices

2

Research GroupPower supply Systems

(Sistemas Electrónicos de Alimentación)

Javier Sebastián

Dr. Electrical Engineer (Ingeniero Industrial)Full professorRoom 3.1.21Edificio nº 3, Campus Universitario de Viesques 33204 Gijón (Asturias). Spain

Phone (direct): 985 18 20 85 Phone (secretary): 985 18 20 87Fax: 985 18 21 38E-mail: [email protected]: http://www.unioviedo.es/sebas/

Page 3: Power Electronic Devices

Review of the physical principles of operation of semiconductor devices.

Thermal management in power semiconductor devices. Power diodes. Power MOSFETs. The IGBT. High-power, low-frequency semiconductor devices (thyristors).

3

Outline

Page 4: Power Electronic Devices

4

Outline

Review of physical principles of semiconductors

Power electronics devices

G

D

S

Page 5: Power Electronic Devices

Basic electromagnetic theory.

Basic circuit theory.

The operation of basic electronics devices in circuits. The student must understand the behaviour of the following electronics devices in simple circuits:

Diodes.

Bipolar Junction Transistors, both PNP and NPN types.

Field Effect Transistor, especially enhancement-mode Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), both in N-channel- and P-channel types.

5

Previous requirements

Page 6: Power Electronic Devices

Lesson 1 - Review of the physical principles of operation of semiconductor devices

Semester 1 - Power Electronics Devices

Electrical Energy Conversion and Power Systems

Universidadde Oviedo

6

Page 7: Power Electronic Devices

7

OutlineReview of the physical principles of operation of semiconductor devices: Basic concepts about semiconductor materials: band diagrams, intrinsic

and extrinsic semiconductors, mechanisms for electric current conduction and continuity equation and its use in simple steady-state and transient situations.

Basic concepts about PN junctions: Equilibrium conditions, forward- and reverse-biased operation and calculation of the current flow when biased.

Reverse-biased voltage limits of PN junctions.

PIN junctions.

Conductivity modulation.

Transient effects in PN junctions in switching-mode operation.

Metal-semiconductor junctions.

Page 8: Power Electronic Devices

8

Energy level in a semiconductor as a function of inter-atomic spacing

Inter-atomic spacing

Ener

gy o

f ele

ctro

ns

--

- -

------

Actual spacing

At 0 K, empty

At 0 K, filled

Page 9: Power Electronic Devices

9

Concept of band diagram

Band gap

Valence band

Conduction band

Eg

4 electrons/atom--

--

4 states/atom

Ener

gy o

f ele

ctro

ns

Empty at 0 K

Filled at 0 KMaterial Eg [eV]

Ge 0.66 Si 1.1

4H - SiC 3.26GaN 3.39

Page 10: Power Electronic Devices

10

Band structure for insulators, semiconductors and metals at 0 K

Band gap Eg

Conduction band

Valence band

SemiconductorEg=0.5-2 eV

Band gap Eg

Conduction band

Valence band

InsulatorEg= 5-10 eV

MetalsNo Eg

Valence band

Conduction band

Overlap

Page 11: Power Electronic Devices

11

Band structure for semiconductors at room temperature. Concept of “hole”

SemiconductorEg=0.5-2 eV

Eg

Conduction band

Valence band

-- -+-

• Some electrons jump from the valence band to the conduction band. They are charge carriers because they can move from one atom to another.

• The empty state in the valence band is referred to as a “hole”.• The holes have positive charge. They are also charge carriers.

Visualization using the bonding model

Si Si

Si Si

- -

- -

- -

- -

- --

- -

- -

--

+

Page 12: Power Electronic Devices

12

Si

-

- -

- -

- -

- --

- -Si

Si Si

- -

-

12

-

+

Recombination

Si

-

- -

- -

- -

- --

- -Si

Si Si

- -

-

-

+

-

Concepts of generation and recombination

Eg

-- -+-

Generation

Eg

-- -+

-

Page 13: Power Electronic Devices

13+-

+ + + + + + + -------

-

Si Si Si Si

Si Si Si Si

- - - - -

- - - - -

- - -

- - -

--

- --

--

- - - -

- - - -

-

+

--

+

Why both holes and electrons are electric charge carriers?

• In general, there will be electric current due to both electrons and holes• Example: when there is an electric field in the semiconductor lattice

Page 14: Power Electronic Devices

14

How many electrons and holes are there in 1 cm3?

• The number of these electrons and holes strongly depend on both Eg and the room temperature. It is called intrinsic concentration and it is represented as “ni”.

• The concentration of electrons in the conduction band (negative charge carriers) is represented as “n”. The concentration of holes in the valence band (positive charge carriers) is represented as “p”.

• Obviously n = p = ni in this type of semiconductors (intrinsic semiconductors)

• Some examples of the value of ni at room temperature:

Material Eg [eV] ni [elect./cm3]

Ge 0.66 2.4·1013

Si 1.1 1.5·1010

GaAs 1.4 1.8·106

4H - SiC 3.26 8.2·10-9

GaN 3.39 1.9·10-10

Taking into account the number of bonds of valence band electrons in 1cm3 of silicon, only one bond is broken for each amount of 1013 unbroken bonds (at room temperature)

Page 15: Power Electronic Devices

15

Concept of extrinsic semiconductors: doping semiconductor materials

• Can we have different concentration of electrons and holes? • The answer is yes. We need to introduce “special” impurities into the crystal:

Donors: atoms from column V of the Periodic Table. We obtain an extra electron for each atom of donor.

Acceptors: atoms from column III of the Periodic Table. We obtain an extra hole for each atom of acceptor.

- - -

- -

--

-

- -

Si

- -

12

34

Sb

Si

Si

--

- -

Donor

- - -

- -

-

-

- -Si

- -

12

3

Al

Si

Si

--

-

Acceptor

5-

+ -

-+

Page 16: Power Electronic Devices

16

N-type and P-type semiconductors

- - -

- -

--

-

- -

Si

- -1

2

34

Sb+

5-

Si

Si

--

- -Donor

- - -

- -

-

-

- -

Si

- -1

2

3

Al-

Si

Si

+

--

--Acceptor

N-type semiconductor: • Majority carriers are electrons.• Minority carriers are holes.• Positively-charged atoms of donor

(positive ions).

P-type semiconductor:• Majority carriers are holes.• Minority carriers are electrons.• Negatively-charged atoms of

acceptor (negative ions).

Page 17: Power Electronic Devices

17

hole

electron

+

-

P-type silicon Acceptor ions (negative ions)

Al- Al- Al- Al- Al-

Al- Al- Al- Al- Al-

-

+

Thermal generation

Donor ions (positive ions)

Sb+ Sb+ Sb+Sb+

Sb+

Sb+ Sb+ Sb+ Sb+ Sb+

-

+

--

-

- -

--

---

Thermal generation

N-type silicon

Charges in N-type and P-type semiconductors

++

+

+

+

+

+

++

+

Page 18: Power Electronic Devices

18

Sb+ Sb+ Sb+

Sb+ Sb+ Sb+

-

+

--

- ---

N-type

Charge carries in N-type and P-type semiconductors

P-type

Al- Al- Al-

Al- Al- Al-

-

+

+ +

+

+

+

+

• Concentration of majority carriers: pP

• Concentration of minority carriers: nP

• Mass action law: pP·nP = ni2

(only valid at equilibrium)

• Concentration of majority carriers: nN

• Concentration of minority carriers: pN

• Mass action law: nN·pN = ni2

(only valid at equilibrium)

Very important equations!!!

Page 19: Power Electronic Devices

19

Sb+ Sb+ Sb+

Sb+ Sb+ Sb+

-

+

--

- ---

N-type

Static charges in N-type and P-type semiconductors

P-type

Al- Al- Al-

Al- Al- Al-

-

+

+ +

+

+

+

+• Concentration of acceptors: NA

(only negative static charges in a P-type semiconductor)

• Concentration of donors: ND

(only positive static charges in a N-type semiconductor)

Page 20: Power Electronic Devices

20

Sb+ Sb+ Sb+

Sb+ Sb+ Sb+

-

+

--

- ---

N-type

Neutrality in N-type and P-type semiconductors

P-type

Al- Al- Al-

Al- Al- Al--

+

+ +

+

+

+

+

• Positive charges in volume V: pP·V

• Negative charges in volume V: nP·V + NA·V

• Neutrality: pP = nP + NA

• Silicon, aluminium and antimony were neutral before being used Þ The extrinsic semiconductor must be neutral, too.

• Negative charges in volume V: nN·V

• Positive charges in volume V: pN·V + ND·V

• Neutrality: nN = pN + ND

Very important equations!!!

Page 21: Power Electronic Devices

21

Sb+ Sb+ Sb+

Sb+ Sb+ Sb+

-

+

--

- ---

N-type

Calculating the concentration of electrons and holes (I)

P-type

Al- Al- Al-

Al- Al- Al-

-

+

+ +

+

+

+

+

• Neutrality: pP = nP + NA

• Mass action law: pP·nP = ni2

2 known (NA and ni) and 2 unkown (pP and nP) variables Þ can be solved

• Neutrality: nN = pN + ND

• Mass action law: nN·pN = ni2

2 known (ND and ni) and 2 unkown (nN and pN) variables Þ can be solved

Page 22: Power Electronic Devices

22

Sb+ Sb+ Sb+

Sb+ Sb+ Sb+

-

+

--

- ---

N-type

Calculating the concentration of electrons and holes (II)

P-type

Al- Al- Al-

Al- Al- Al-

-

+

+ +

+

+

+

+

• NA >> ni

• Neutrality: pP » NA

• Mass action law: nP » ni2/NA

• ND >> ni

• Neutrality: nN » ND

• Mass action law: pN » ni2/ND

• Frequent case: quite heavy doped semiconductors

Very useful equations!!!

Page 23: Power Electronic Devices

23

Mechanisms to conduct electric current: Drift (I)

• Semiconductors can conduct electric current due to the presence of an electric field E

jp

jn

E

+ + + + +

- - - - -

-

-

-+

+

- +

+

+

+

+

+-

-

--

jp_Drift = q·p·p·E is the current density of holes due to drift.

jn_Drift = q·n·n·E is the current density of electrons due to drift.

Page 24: Power Electronic Devices

Mechanisms to conduct electric current: Drift (II)

Ge (cm2/V·s)

Si (cm2/V·s)

GaAs (cm2/V·s)

n 3900 1350 8500 p 1900 480 400

q = magnitude of the electronic charge (1.6·10-19 coulombs).

p = hole mobility.

n = electron mobility.

p = hole concentration.

n = electron concentration.

E = electric field.

24

jp_Drift = q·p·p·E

jn_Drift = q·n·n·E

Page 25: Power Electronic Devices

25

Electrons have migrated due to “diffusion” (you can see the same phenomenon in gases)

jn_Diff

1 2

n1 n2 < n1

--

--

--

--

--

--

--

--

--

Mechanisms to conduct electric current: Diffusion (I)

Page 26: Power Electronic Devices

26jn_Diff

1 2

n1 n2 < n1

• If we maintain a different concentration of electrons, we also maintain the motion of electrons in the lattice

n

-

--

--

---

-

-

-

-

--

-

-

--

-

-

-

-

--

---

-

-

-

--

Mechanisms to conduct electric current: Diffusion (II)

Page 27: Power Electronic Devices

27

jn_Diff

1 2

n1 n2 < n1- - ---

--

--

-- -

--

-

-

- - --

-

-

n

The current density is proportional to the electron concentration gradient:

jn_Diff = q·Dn· n

Mechanisms to conduct electric current: Diffusion (III)

Dn = electron diffusion coefficient.

Page 28: Power Electronic Devices

28

1 2

p1 p2 < p1

++

+

+

+

+

+

+

+

+

++

+

++

+

+ + +

+

+

+

p

The current density is proportional to the hole concentration gradient:

jp_Diff = -q·Dp· p

Dp = hole diffusion coefficient.

jp_Diff

Mechanisms to conduct electric current: Diffusion (IV)

Page 29: Power Electronic Devices

29

Ge (cm2/s)

Si (cm2/s)

GaAs (cm2/s)

Dn 100 35 220 Dp 50 12.5 10

jp_Diff = -q·Dp· p

jn_Diff = q·Dn· n

Mechanisms to conduct electric current: Diffusion (V)

q = magnitude of the electronic charge (1.6·10-19 coulombs).

Dp = hole diffusion coefficient.

Dn = electron diffusion coefficient.

Ñp = hole concentration gradient.

Ñn = electron concentration gradient.

Page 30: Power Electronic Devices

30

Summary of conduction mechanisms

jp_Diff = -q·Dp· p

jn_Diff = q·Dn· n

jp_Drift = q·p·p·E

jn_Drift = q·n·n·E

• Drift currents depend on the carrier

concentration and on the electric field.

• Diffusion currents do not depend on the carrier concentration, but on the carrier concentration gradient.

Page 31: Power Electronic Devices

31

A B

There are some relationships between spatial and time variations of carrier concentrations because electrons and holes cannot mysteriously appear and disappear at a given point, but must be transported to or created at the given point via some type of ongoing action.

Continuity equations (I)

The concentration of holes can be time-changing due to:• Different current density of holes across “A” and “B”.• Excess of carriers over the equilibrium (mass action law).• Generation of electron-hole pairs by radiation (light) .

Page 32: Power Electronic Devices

32

A B

Continuity equations (II)

• Different current density of holes across “A” and “B”.

-

+

+

-

+

+

jp_Ajp_B

jn_B

A B

+ -• Excess of carriers over the

equilibrium (mass action law).

A B

Light

-

+

• Generation of electron-hole pairs by radiation (light) .

Page 33: Power Electronic Devices

33

·jp/q

-

p/t = GL- [p(t)-p ]/p

Taking into account the three effects, we obtain the continuity equation for holes:

Continuity equations (III)

Variation due to the excess of carriers over the equilibrium

Total time variation of holes

Variation due to the generation of electron-hole pairs by light Variation due to the

different current density of holes across “A” and “B”GL: rate of generation of electron-hole pairs by light.

p: hole minority-carrier lifetime.p: hole concentration in steady-state.

·jn/q

+

n/t = GL- [n(t)-n ]/n

Similarly, we can obtain the continuity equation for electrons:

Page 34: Power Electronic Devices

34

• We generate an “excess” of electron-hole pairs by injecting light into a piece of N-type silicon and we reach the steady-state.

Time evolution of an “excess” of minority carries (I)

·jp/q

-

p/t = GL- [p(t)-p ]/p

00

Þ p0= GL·p + p

NN+ + + + ++ + + + +

p0+

+

+

+

+

+

+

+

p

• Now the light injected disappears. We want to compute the time evolution of the hole concentration afterwards.

N+ + + + +

p0+

+

+

+

+

+

+

+p(t)p

Page 35: Power Electronic Devices

35

Time evolution of an “excess” of minority carries (II)

• We can also compute the time evolution of the hole concentration from the continuity equation:

·jp/q

-

p/t = GL- [p(t)-p ]/p

00

After integrating Þ p(t) = p + (p- p)·e-tp

p p

p0

p(t)t

p

Tangent lineSame area

• Physical interpretation: There is an appreciable increase of holes during 3-5 times p.

Page 36: Power Electronic Devices

36

• We constantly inject an “excess” of holes into a surface of a piece of N-type silicon and we reach the steady-state. No electric field exists and the hole current is due to diffusion.

Spatial evolution of an “excess” of minority carries (I)

·jp/q

-

p/t = GL- [p(t, x)-p ]/p

00

Þ 0 = - [p(x)-p ]/p + Dp·2[p(x)-p ]/x2

x xN

+ + + ++

+

++

+ N

+

+

+

+

+

+ +

+ +

0

p0

p

After integrating Þ p(x) = p + C1·e-x/Lp + C2·ex/Lp

where : Lp=(Dp· p)1/2 is the minority hole diffusion length

Page 37: Power Electronic Devices

37

• Cases:

a) Lp << xN (wide crystal): Þ p(x) = p + (p- p)·e-xLp (decay exponentially).

b) Lp >> xN (narrow crystal): Þ p(x) = p + (p- p)·(xN-x)/xN (decay linearly).

c) Other cases Þ hyperbolic sine evolution.

Spatial evolution of an “excess” of minority carries (II)

p(x) = p + C1·e-x/Lp + C2·ex/Lp

xN: length of the N-type crystalLp: hole diffusion length

p(x)

p

p0

xxN

p(x)p

p0

xxN

Lp << xN (wide) Lp >> xN (narrow)

Tangent line

Lp

Page 38: Power Electronic Devices

38

What happens if we remove the barrier?

P-type silicon

-+

Al- Al- Al- Al-

Al- Al- Al- Al-

++

+

+

+

+

+

+

Barrier to avoid carrier diffusion

N-type silicon

Sb+ Sb+ Sb+ Sb+

Sb+ Sb+ Sb+ Sb+

-

+

--

-

-

---

-

Concept of PN junction (I)

Page 39: Power Electronic Devices

39

Are all the carriers to be diffused?

Al-

Al-

P-side

-+

Al- Al- Al-

Al- Al- Al-

++

+

+

+

+

N-side

Sb+ Sb+ Sb+ Sb+

Sb+ Sb+ Sb+ Sb+

+

-- -

---

-+

+

-

-Holes begin to diffuse from the P-side to the N-side. Similarly, electrons diffuse from the

N-side to the P-side

Concept of PN junction (II)

Page 40: Power Electronic Devices

40

Al-

Al-

P-side

-

+

Al- Al- Al-

Al- Al- Al-

N-side

Sb+ Sb+ Sb+ Sb+

Sb+ Sb+ Sb+ Sb+

+

-+

+-

-+

+

+

+

+

+

-

-

-

-

-

-

Are all the carriers to be diffused?

Is this situation “the final situation”? The answer is no

Non-neutral P-type region, but negatively charged

Non-neutral N-type region, but positively charged

Concept of PN junction (III)

Page 41: Power Electronic Devices

41

An electric field appears just in the boundary between both regions (we call this boundary

metallurgical junction)

+-E

Al-

Al-

P-side

-+

Al- Al- Al-

Al- Al- Al-

++

+

+

+

+

N-side

Sb+ Sb+ Sb+ Sb+

Sb+ Sb+ Sb+ Sb+

+

-- -

---

-+

+

-

-

Concept of PN junction (IV)

Page 42: Power Electronic Devices

42

The electric field limits the carrier diffusion

Al-

Al-

P-side

Al- Al- Al-

Al- Al- Al-

N-type

Sb+ Sb+ Sb+ Sb+

Sb+ Sb+ Sb+ Sb+

+

-+-

E

Due to diffusion ( ¬)

Due to drift (electric field) (¬)

+

+

-

-

Concept of PN junction (V)• Now, we do zoom over the metallurgical junction

Page 43: Power Electronic Devices

43

Depletion region, or space charge region, or transition regionUnbalanced charge exists because carriers barely exist

Neutral P-type region (holes are balanced by

negative ions )

Al- Al- Al-

Al- Al- Al-

+

+

+

+

+

+

Al-

Al-

Sb+

Sb+

+-E Neutral N-type region

(electrons are balanced by positive ions )

Sb+

Sb+

Sb+

Sb+

Sb+

Sb+

-

--

- -

-

Concept of PN junction (VI)• Steady-state situation near the metallurgical junction

Page 44: Power Electronic Devices

44

Many holes, but neutral

Many electrons, but neutral

P-side(neutral)

N-side(neutral)

+ -

Metallurgical junction

E

V0

Concept of PN junction (VII)• Summary and terminology

Depletion, or transition, or space charge region (non neutral)There is space charge and, therefore, there are electric field E and voltage V0.

However, there are almost no charge carriers

Page 45: Power Electronic Devices

45

Computing the built-in voltage V0 (I)

- +- +- +- +- +- +

- +- +

P-side

N-side

Net current passing through any section must be zero. As neither holes nor electrons are being accumulated in any parts of the crystal, net current due

to holes is zero and net current due to electrons is zero.

+ Due to drift

jp_Drift

+Due to diffusion

jp_Diff

-Due to drift

jn_Drift

- Due to diffusion

jn_Diff Currents must cancel each other

Currents must cancel each other

Page 46: Power Electronic Devices

46

Computing the built-in voltage V0 (II)

+ -+ -+ -+ -

- +N-side

Zona P

V0

jp_Drift = - jp_Diff

+

+

(hole concentration in N-side ) pN

+

pP (hole concentration in P-side )

+ + + +

+ + + +

+ + + +

+ + + +

+ + + +

+ + + +

+ + + ++ + + +

+

Due to drift

jp_Drift

+Due to diffusion

jp_Diff

Page 47: Power Electronic Devices

47

jp_Diff = -q·Dp·dp/dx

jp_Drift = q·p·p·E

E = -dV/dxE

jp_Drift = - jp_Diff

Equations:

Therefore: dV = -(Dp/p)·dp/p

Computing the built-in voltage V0 (III)

After integrating :

V0 = VN-side – VP-side = -(Dp/p)·ln(pN/pP) = (Dp/p)·ln(pP/pN) Repeating the same process with electrons, we obtain:

V0 = (Dn/n)·ln(nN/nP)It could be demonstrated:Dp/p = Dn/n = kT/q = VT (Einstein relation)

k = Boltzmann constant.VT = 26 mV at 300 K.

Page 48: Power Electronic Devices

48

+ -+ -+ -+ -

- +

N-side: many electrons

Zona P

V0

pN

+

pP

+ + + +

+ + + +

+ + + +

+ + + +

+ + + +

+ + + +

+ + + ++ + + +

+

+-

-P-side: many holes

- - - -- - - -- - - -- - - -- - - -- - - -

- - - -- - - -

nN

-

nP

V0 = VT·ln(pP/pN) and also V0 = VT·ln(nN/nP)

Computing the built-in voltage V0 (IV)Summary (I)

Almost no holesor electronsAlmost no electrons Almost no holes

Page 49: Power Electronic Devices

49

V0 = VT·ln(pP/pN) and also V0 = VT·ln(nN/nP)

Computing the built-in voltage V0 (V)

Summary (II)

P-side N-side+ -

V0

If NA >> ni (current case)

pP = NA nP = ni2/NA

NA, pP, nP

If ND >> ni (current case)

nN = ND pN = ni2/ND

ND, nN, pN

V0 = VT·ln(NA·ND/ni2), VT = 26 mV at 300 K

Page 50: Power Electronic Devices

50

P-side N-side

W0

Charge neutrality implies: NA·WP0 = ND·WN0

WN0

Sb+ Sb+

Sb+ Sb+

Sb+ Sb+ Sb+

Sb+

Sb+

--

-

ND

WP0

Al- Al-

Al-Al-

Al-

Al-

Al-

Al-

+

NA

+

The heavier doped a side, the narrower the depletion region in that side

Depletion width in P-side and in N-side

Page 51: Power Electronic Devices

51

Calculating the electric field E and the total depletion width W0 (I)

We already know: • The charge density in both sides inside the depletion region:rP-side = NA·q and rN-side = ND·q

• The relative width of the depletion region in the P-side and in the N-side:NA·WP0 = ND·WN0

• The built-in (contact) voltage: V0 = VT·ln(NA·ND/ni2)

We need to know: • The electric field E.

• The total depletion width W0.

E(x)+ -

P-side N-side- +

W0

WN0WP0

V0- +rN-side rP-side

We will use Gauss’ law and the relationship between electric field and voltage

Page 52: Power Electronic Devices

52

Calculating the electric field E and the total depletion width W0 (II)E(x)

+ -

P-side N-side- +

- V0 +

E(x) -Emax0

Electric field x

r(x)Charge density x

q·ND

-q·NA

V(x) V0Voltage x

W0

• Gauss’ law: ·E(x) = r(x)/e

• Voltage and electric field: E(x) = - V

Page 53: Power Electronic Devices

53

Calculating the electric field E and the total depletion width W0 (III)

-Emax0

Electric field x

Charge density x

q·ND

-q·NA

V0Voltage x

E(x)+ -

P-side N-side- +

- V0 +W0

After applying Gauss’ law and the relationship between electric field and voltage, we obtain:

2·e·(NA+ND)·V0W0 =q·NA·ND

e·(NA+ND)Emax0 =

2·q·NA·ND·V0

Page 54: Power Electronic Devices

54

Summary of the study of the PN junction with no external bias

Almost no holes or electrons, but space charge, electric

field and voltage

P-side: many holesAlmost no electrons

N-side: many electronsAlmost no holes

P-sideDoped NA

N-sideDoped ND

- +

W0

WN0WP0

Electric field at the metallurgical junction Emax0- V0 +

V0 = VT·ln(NA·ND/ni2)

2·e·(NA+ND)·V0W0 =q·NA·ND

e·(NA+ND)Emax0 =

2·q·NA·ND·V0

NA·WP0 = ND·WN0W0 = WP0 + WN0

Very important equations!!!

Page 55: Power Electronic Devices

Connecting external terminals to a PN junction

Therefore:V = 0, i = 0Hence:VmP – V0 + VNm = 0And:VmP + VNm = V0

V0- +

P-side N-side

+ -

VmP

-+VNm

-+

V = 0

i = 0

Conclusion:The built-in voltages across each metal-semiconductor contact cancel out the effect of V0 in such a way that V0 does not appear externally.

55

metal-semiconductor contacts

No energy can be dissipated here

Page 56: Power Electronic Devices

56

Vj

- +VmP

-+VNm

-+i 0

P-side N-side

+ -Vext

-+

Low resistivity:VN=0

Low resistivity:VP=0

VmP and VNm do not change and, therefore VmP+VNm= V0

Biasing the PN junction: forward bias

V0 becomes Vj now

Conclusion:The built-in voltage across the junction has decreased Vext volts

Vext = VmP - Vj + VNm = V0 - Vj

Therefore: Vj = V0 - Vext

Page 57: Power Electronic Devices

57

Vj

- +VmP

-+VNm

-+i 0

P-side N-side

+ - Vext

- +

Low resistivity:VN=0

Low resistivity:VP=0

Biasing the PN junction: reverse bias

Conclusion:The built-in voltage across the junction has increased Vext volts

Vext = -VmP +Vj - VNm = -V0 + Vj

Therefore: Vj = V0 + Vext

VmP and VNm do not change and, therefore VmP+VNm= V0

Page 58: Power Electronic Devices

58

Vext-+

=Vj

- +P-side N-side

+ -

i

Biasing the PN junction: notation for a general case

Conclusion: • Always: Vj = V0 - Vext, being: 0 < Vext < V0 (forward biased) Vext < 0 (reverse biased)

Page 59: Power Electronic Devices

59

Effects of the bias on the depletion region

We must replace V0 with Vj, that is, replace V0 with V0-Vext

Always: V0 = VT·ln(NA·ND/ni2)

Without bias

2·e·(NA+ND)·V0W0 =q·NA·ND

e·(NA+ND)Emax0 =

2·q·NA·ND·V0

Vj0 = V0

With bias

2·e·(NA+ND)·(V0-Vext)W(Vext) =q·NA·ND

e·(NA+ND)Emax(Vext) =

2·q·NA·ND·(V0-Vext)

Vj (Vext) = V0 - Vext

Page 60: Power Electronic Devices

60

P-side - + N-side

V0

W0

r(x)

x

E(x)

-Emax0

x

Vj(x)V0 x

-Emax

V0-V1

• Less spatial charge

V0-V1

P-side - + N-side

V1

W

Effects of the forward bias on the depletion

region

• Lower electric field

• Lower built-in voltage

Page 61: Power Electronic Devices

61

P-side - + N-side

V0

W0

r(x)x

E(x)

-Emax0

x

Vj(x)

V0x

V0+V2

-Emax

V0+V2

V2

P-side - + N-side

W

• More spatial charge

• Higher electric field

• Higher built-in voltage

Effects of the reverse bias on the depletion

region

Page 62: Power Electronic Devices

62

nNnP

No bias: V0 = VT·ln(nN/nP)

- +Zona P

P-side

- - -- - -- - -- - -- - -

------ - - -

- - --- - - -

-

-

-

+ -+ -+ -+ -

V0

Forward bias: V0-Vext =VT·ln(nNV/nPV)

nNVnPV

-

------

--

V0-Vext

Effects of the bias on the neutral regions (I)

For holes with forward bias: V0-Vext =VT·ln(pPV/pNV)

Page 63: Power Electronic Devices

nPV = nN·e -(V0-Vext)/ VT

Effects of the bias on the neutral regions (II)

• The quotients nNV/nPV and pPV/pNV strongly change with bias.

• In practice, nNV and pPV do not change appreciably (i.e., nNV »

nN and pPV » pP) for charge neutrality reasons.

• Therefore the concentration of minority carriers (i.e., pNV and nPV) strongly changes at the depletion region edges.

• The values of nPV and pNV can be easily obtained:V0-Vext =VT·ln(nN/nPV) Þ

V0-Vext =VT·ln(pP/pNV) Þ pNV = pP·e-(V0-Vext)/ VT

63

• As nN » ND and pP » NA, then:

nPV = ND·e -(V0-Vext)/ VT pNV = NA·e-(V0-Vext)/ VT

Page 64: Power Electronic Devices

Vext

-+ =

Vj- +

Vj = V0-Vext

Zona P Zona N

+ -

pP = NA nN = ND

Effects of the bias on the neutral regions (III)

64

pNV = NA·e -Vj/ VT

Biased junction

pN = ni2/ND = NA·e -V0/ VT

Non-biased junction

nPV = ND·e -Vj/ VT

Biased junction

nP = ni2/NA = ND·e-V0/ VT

Non-biased junction

Page 65: Power Electronic Devices

Vj = V0-Vext

Vj- +

P-side N-side

+ -

Effects of the bias on the neutral regions (IV)

65

pNV = NA·e -Vj/ VT nPV = ND·e -Vj/ VT

• Forward bias: The concentration of minority carriers at the depletion region edges increases, because Vj < V0

• Reverse bias: The concentration of minority carriers at the depletion region edges decreases, because Vj < V0

• Forward and reverse bias: The concentration of majority carriers in neutral regions does not change

Concentration of minority carriers :

Page 66: Power Electronic Devices

Vj- +

P-side N-side

+ -

Effects of the bias on the neutral regions (V)

66

What happens with the minority carriers along the neutral regions?

• This is a case of injection of an “excess” of minority carriers (see slide #36).

• Cases of interest:

a) Lp << xN (wide N-side)Þ decay exponentially

b) Lp >> xN (narrow N-side) Þ decay linearly

Page 67: Power Electronic Devices

67

Length

pNVnPV

0

Minority carrier concentration

pNnP

Length

pNVnPV

0

Minority carrier concentration

nP pN

Vext

P-side N-side

Wide P and N sides

Vext

P-side N-side

Narrow P and N sides

Effects of the bias on the neutral regions (VI)

The concentration of minority carriers along the neutral regions under forward biasing.

0.1 mm 0.001 mm

Excess of minority carriersIt plays a fundamental role evaluating the switching speed of electronic

devices.

Page 68: Power Electronic Devices

68

Length

pNVnPV

0

Minority carrier concentration

pNnP

Length

pNVnPV

0

Minority carrier concentration

nP pN

Vext

P-side N-side

Wide P and N sides

Vext

P-side N-side

Narrow P and N sides

Effects of the bias on the neutral regions (VII)

The concentration of minority carriers along the neutral regions under reverse biasing.

0.1 mm 0.001 mm

Deficit (negative excess) of minority carriers

Page 69: Power Electronic Devices

69

Carriers along the overall device

Properties of Si at 300 KDp=12.5 cm2/sDn=35 cm2/s p=480 cm2/V·sn=1350 cm2/V·sni=1010 carriers/cm3

er=11.8

Example of a silicon PN junction

V0=0.596 V

NA=1015 atm/cm3

p=100 ns

Lp=0.01 mm

ND=1015 atm/cm3

n=100 ns

Ln=0.02 mm

P -side N-side

Forward biased with Vext = 0.48 V

pNV

pP

nPV

nN

Carriers/cm3

104

1012

1014

1016

-0.3 -0.2 -0.1 0 0.1 0.2 0.3Length [mm]

1010

108

106 Log scaleThey decay exponentially

(log scale)

Page 70: Power Electronic Devices

70

Calculating the current passing through a PN junction (I)

• We have addressed a lot of important issues related the PN junction: Charge, electric field and voltage across the depletion

region. Concentration of majority and minority carriers along

the total device.

• However, the most important issue has not been addressed so far:

How can we compute the current passing through the device?

• Fortunately, we already have the tools to answer this question.

Page 71: Power Electronic Devices

71

several mm

Vext

Vj

0.3m

P N- +P-side N-side

• Two questions arise: What carrier must be evaluated to compute the overall current? Where?

Calculating the current passing through a PN junction (II)

jtotal = jp_total(x) + jn_total(x) = jp_Drift(x) + jp_Diff(x) + jn_Drift(x) + jn_Diff(x)

jtotal jtotal

Case of wide P and N sides

• Places: Depletion region 1 . Neutral regions far from the depletion region 2 . Neutral regions, but near the depletion region edges 3 .

122 3 3

Page 72: Power Electronic Devices

72

Carr

iers

/cm

3

nPpN

1014

1016

pNVnPVLog scale

1m

Calculating the current passing through a PN junction (III)

several mm

Vext

Vj

0.3mP N- +P-side N-side

jtotal jtotal

Computing the overall current from the current density due to carriers in the depletion region

jtotal = jp_Drift(x) + jp_Diff(x) + jn_Drift(x) + jn_Diff(x)

Currents due to drift (jp_Drift and jn_Drift) have opposite direction to currents due to diffusion. Both currents have extremely high values (very high electric field and carrier concentration gradient) and cannot be determined precisely enough to guarantee that the difference (which is the total current) is properly computed. Therefore, this is not the right place.

Page 73: Power Electronic Devices

73

Calculating the current passing through a PN junction (IV)

Vext

Vj

P N- +P-side

jtotal

Computing the overall current from the current density due to carriers in the neutral regions far from the depletion region

jtotal = jp_Drift(x) + jp_Diff(x) + jn_Drift(x) + jn_Diff(x)

Current is due to drift of majority carriers. However, it cannot be determined properly because we do not know the value of the “weak” electric field. Therefore, these are not the right places.

jp_Drift(x) = q·p·p(x)·E(x)

jn_Drift(x) = q·n·n(x)·E(x)

jp_Diff (x) = -q·Dp·dp(x)/dx

jn_Diff (x) = q·Dn·dn(x)/dx

» 0

» 0» 0

Few electrons in P-side

Constant concentration

Weak field High concentration

Page 74: Power Electronic Devices

74

Calculating the current passing through a PN junction (V)Computing the overall current from the current density due to carriers in

the neutral regions but near the depletion region edges (I)

Vext

Vj

P N- +P-side

jtotal

jtotal = jp_Drift(x) + jp_Diff(x) + jn_Drift(x) + jn_Diff(x)

We cannot compute the total current yet, but we can compute the current density due to minority carriers:jn_total (x) = jn_Drift(x) + jn_Diff(x) » jn_Diff (x) = q·Dn·dn(x)/dx

jp_Drift(x) = q·p·p(x)·E(x)

jn_Drift(x) = q·n·n(x)·E(x)

jp_Diff (x) = -q·Dp·dp(x)/dx

jn_Diff (x) = q·Dn·dn(x)/dx» 0

Few electrons in P-side

Weak field High concentration

Page 75: Power Electronic Devices

jp_total(x)

Length0Min

ority

ca

rrie

r co

ncen

trati

on

pNnP

75

Calculating the current passing through a PN junction (VI)Computing the overall current from the current density due to carriers in

the neutral regions but near the depletion region edges (II)

jn_total(x) = q·Dn·dnPV(x)/dx

We can do the same for the holes just in the opposite side of the depletion region

jp_total (x)= -q·Dp·dpNV(x)/dx

Vext Vj

P N- +P-side N-side

jn_total(x) jp_total(x)

pNVnPV

Length0Curr

ent d

ensit

y

jn_total(x)

Taking derivatives

Page 76: Power Electronic Devices

76

Calculating the current passing through a PN junction (VII)Computing the overall current from the current density due to carriers in

the neutral regions but near the depletion region edges (III)

Vext Vj

P N- +P-side N-side

jn_total(x) jp_total(x)

jp_total(x)

Length0Curr

ent d

ensit

y of

m

inor

ity ca

rrie

rs

jn_total(x)

The carrier density currents passing through the depletion region are constant because the probability of carrier recombination is very low, due to the low carrier concentration in that region.

What happens with carriers in the depletion region?

Page 77: Power Electronic Devices

• The total current density passing through the device can be computed as the addition of the two minority current densities at the edges of the depletion region 77

Calculating the current passing through a PN junction (VIII)Computing the overall current from the current density due to carriers in

the neutral regions but near the depletion region edges (IV)

Vext

Vj

P N- +P-side N-side

jn_total(x) jp_total(x)

jp_total(x)

Length0Curr

ent d

ensit

y

jn_total(x)

Now the total current density can be easily computed

jtotal

Very important conclusion!!!

Page 78: Power Electronic Devices

• We need to know the variation of the minority carrier concentrations at the depletion region edges.

• We have to calculate the gradients of these concentrations (taking derivatives).

• We have to calculate the current densities due to these minority carriers, which are diffusion currents.

• We must add both current densities to obtain the total current density, which is constant along all the device. This is the total current density passing through the device.

78

Calculating the current passing through a PN junction (IX)

Vj

P-side N-side- +

jn_total(x) jp_total(x)

Summary of the computing of the overall current density in a PN junction

Page 79: Power Electronic Devices

79

Calculating the current passing through a PN junction (X)

Vj

P-side N-side- +

jn_total(x) jp_total(x)

• Once the total current density and the minority-carrier current densities are known, the majority-carrier current density can be easily calculated by difference.

jp_total(x)

Length0Curr

ent d

ensit

y

jn_total(x)

jtotal

Majority-carrier currents, due to both drift and diffusion

Minority-carrier currents, only due to diffusion

Total current

Page 80: Power Electronic Devices

nP

80

Current passing through an asymmetrical junction (P+N-)

Vext Vj

- +P+-side (wide) N--side

jn_total(x)

Length0

Curr

ent d

ensit

y

pNV

nPV

Length0

pN

Conc

entr

ation

jp_total(x)

jn_total(x)

jtotal

P-side is heavily doped (P+) and wideN-side is slightly doped (N-) and narrow

This is a case of special interest, because it is directly related to the operation of Bipolar Junction Transistors (BJTs)

Page 81: Power Electronic Devices

Length0Min

ority

carr

ier

conc

entr

ation

pNnP

81

Qualitative study of the current in a forward-biased PN junction

Vext Vj

P N- +P-side N-side

jtotal

pNVnPV

jp_total(x)

Length0Curr

ent d

ensit

y

jn_total(x)

jtotal

High and positive total current density

High slope Þ High current density due to electrons in the depletion region

High slope Þ High current density due to holes in the depletion region

Page 82: Power Electronic Devices

Length0Min

ority

carr

ier

conc

entr

ation

pNnP

82

Qualitative study of the current in a reverse-biased PN junction

Vext Vj

P N- +P-side N-side

jtotal

nPV

Low and negative total current density

pNV

Low slope Þ Low current density due to electrons in the depletion region

Low slope Þ Low current density due to holes in the depletion region

Length0

Curr

ent d

ensit

y

jn_total(x)

jtotal

jp_total(x)

Page 83: Power Electronic Devices

Procedure: 1- Compute the concentration of minority holes (electrons) in the proper edge of the depletion region when a given voltage is externally applied.2- Compute the excess minority hole (electron) concentration at the above mentioned place. It is also a function of the externally applied voltage. 3- Compute the decay of the excess minority hole (electron) concentration (exponential, if the semiconductor side is wide, or linear, if it is narrow).4- Compute the gradient of the decay of the excess minority hole (electron) concentration just at the proper edge of the depletion region.5- Compute the diffusion current density due to the above mentioned gradient. 5- Once the current due to minority holes (electrons) has been calculated, repeat the same process with electrons (holes). 6- Add both current densities.

7- Compute the total current by multiplying the current density by the cross-sectional area.

83

Quantitative study of the current in a PN junction (I)

Page 84: Power Electronic Devices

The final results is:

i = IS·(eVext/VT - 1), where:

IS = A·q·ni2·[Dp/(ND·Lp)+Dn/(NA·Ln)]

(Is is called reverse-bias saturation current)

VT = kT/q

where:A = cross-sectional area.q = magnitude of the electronic charge (1.6·10-19 coulombs).ni = intrinsic carrier concentration.Dp = hole diffusion coefficient.Dn = electron diffusion coefficient.Lp = hole diffusion length in N-side.Ln = electron diffusion length in P-side.ND = donor concentration.NA = acceptor concentration.k = Boltzmann constant.T = absolute temperature (in Kelvin).

84

Quantitative study of the current in a PN junction (II)

PN

+

-

i

Vext(Shockley equation)

Page 85: Power Electronic Devices

i = IS·(eVext/VT - 1)

IS = A·q·ni2·[Dp/(ND·Lp)+Dn/(NA·Ln)]

VT = kT/q

85

Quantitative study of the current in a PN junction (III)

• Forward bias VO > Vext >> VT

• Reverse bias Vext << -VT

Þ exponential dependencei » IS·eVext

VT

i » -IS Þ constant (reverse-bias saturation current)

Vext [V]0

100

0.25- 0.25

i [mA]

0.5

-10

-0.5 0

i [nA]

Vext [V]

Page 86: Power Electronic Devices

86

Quantitative study of the current in a PN junction (IV)

Length

pNVnPV

0

Minority carrier concentration

pNnP

Length

pNVnPV

0

Minority carrier concentration

nP pN

Vext

P-side N-side

Wide sides Vext

P-side N-side

Narrow sides

Wide versus narrow P and N sides

XN XN >> Lp

XN XN << Lp

IS = A·q·ni2·[Dp/(ND·Lp)+Dn/(NA·Ln)] IS = A·q·ni

2·[Dp/(ND·XN)+Dn/(NA·XP)]

XP XP >> Ln

XP XP << Ln

Equation i = IS·(eVext/VT - 1) is valid in both cases

Page 87: Power Electronic Devices

Equation i = IS·(eVext/VT - 1) describes the operation in the range VO > Vext > -. However, three questions arise:

• What happens if Vext > VO?

• How does the temperature affect this characteristic?

• What is the actual maximum voltage that the junction can withstand?

87

Quantitative study of the current in a PN junction (V)The I-V characteristic in a real scale of use

0 1-4

3i [A]

Vext [V]

Vj

- +VmP

-+VNm

-+i 0

P-side N-side

+ -

VN 0VP 0

Vext

+ - + - When Vext appraches V0 (or it is even higher), the current passing is so high that the voltage drop in the neutral regions is not zero. This voltage drop is proportional to the current (it behaves as a resistor).

According to Shockley equation

Actual I-V characteristic

Page 88: Power Electronic Devices

88

Decreases with T

Increases with T

Forward bias: i » IS·eVext/VT = IS·eq·Vext/kT

Reverse bias: i » -IS

where: IS = A·q·ni2·[Dp/(ND·Lp)+Dn/(NA·Ln)].

It should be taken into account that ni strongly depends on the temperature.

Therefore:

Temperature dependence of the I-V characteristic (I)

Reverse current strongly increases when the temperature increases. It doubles its value when the temperature increases 10 oC.

In practice, forward current increases when the temperature increases. For extremely high currents, the dependence can become just the opposite.

Page 89: Power Electronic Devices

89

30

10

i [A]

Vext [V]

Forward bias

PN

+

-

i

V

37 0C

27 0C

-0.25

-10

Vext [V]

i [A]

Reverse bias

27 0C

370C

Temperature dependence of the I-V characteristic (II)

In both cases, the current increases for a given external voltage.

Page 90: Power Electronic Devices

90

• There are three different physical processes which limit the reverse voltage that a given PN junction can withstand:

Punch-through Zener breakdown Avalanche breakdown

Maximum reverse voltage that a PN junction can withstand

0

i

Vext

i+ Vext -

PN

+ -+ -

+ -

+

-

+

-+

-This phenomenon does not take place in power devices (two heavily doped regions are needs).

• Actual reverse current is higher than predicted due to the generation of electron-hole pairs by collisions with the lattice.

• If the electric field is high enough, this phenomenon becomes degenerative.

It will be explained later

Page 91: Power Electronic Devices

• As already known, both the electric field and depletion length increase.• When the maximum electric field is high enough, the avalanche

breakdown starts. 91

W0 = p P p N e

VU V

T

2·e·(NA+ND)·V0

q·NA·ND

Emax0=e·(NA+ND)

2·q·NA·ND·V0

No bias Reverse bias

W(Vrev) = p P p N e

VU V

T

2·e·(NA+ND)·(V0+Vrev)

q·NA·ND

Emax(Vrev) =e·(NA+ND)

2·q·NA·ND·(V0+Vrev)

W(Vrev)NP - +

V0+Vrev

-Emax(Vrev)

V0

P N- +

W0

-Emax0

Electric field in the depletion region with reverse bias

Page 92: Power Electronic Devices

Punch-through limit

92

Emax(Vrev) »e·(NA+ND)

2·q·NA·ND·|Vrev|

W(Vrev)

NP - +» |Vrev|

-Emax

WPN

W(Vrev) » p P p N e

VU V

T 2·e·(NA+ND)·|Vrev|

q·NA·ND p P p N e

VU V

T

Avalanche breakdown limit

-EBR

• We must design the semiconductor according to: Emax(Vrev) < EBR.

• The breakdown voltage is:

VBR = EBR2·e·(NA + ND)/(2q·NA·ND).

• Moreover, W(Vrev) < WPN to avoid the phenomenon called punch-through.

• Usually W(VBR) < WPN, which means that practical voltage limit is not due to punch-through, but to avalanche breakdown.

Limits for the depletion region with reverse bias

Page 93: Power Electronic Devices

93

• A high value of VBR is obtained if one of the two regions has been slightly doped (i.e., either NA or ND is relatively low).

• However, it should taken into account that low values of ND (NA) implies:

Wide WN (WP), which also implies wide XN (XP) to avoid punch-through.

Low nN (pP) and, therefore, low conductivity.

• If we have long length and low conductivity, then we have high resistivity.

• Hence, a trade-off between resistivity and breakdown voltage must be established.

What must we do to withstand high-voltage?

2·q·NA·ND

VBR =EBR

2·e·(NA + ND)NA2qVBR = ·( + )

EBR2·e 1 1

NDÞ

WN

XN

pP = NA nN = ND

P+ - N--side+ NDNA

NA >> ND

Page 94: Power Electronic Devices

9494

-Emax

x

Vrev

x

r(x) xq·ND

-q·NA

NA >> ND

P+ - N--side+ NDNA

Maximum electric field Emax with reverse bias Vrev

-EBR

The main part of the reverse voltage is dropping in the slightly doped region.

Vrev_P

Vrev_N

• Can we increase VBR for a given EBR value?

- Yes, we can. We must modify the electric field profile.

- The result is the PIN junctions.

VBR

Page 95: Power Electronic Devices

9595

PIN junctions (I)W(Vrev)

NP - +Vrev

-Emax(Vrev)

• Main idea: the voltage across the device is proportional to the dashed area (E(x) = - dV/dx).

• Can we have the same area (same voltage across the device) with a lower value of Emax(Vrev)?

• Yes, we can. We need another E(x) profile.

-Emax(Vrev) new profile (ideal)

-Emax(Vrev)

-Emax(Vrev) new profile (real)

-Emax(Vrev)

• To obtain this profile, we need a region without space charge (undoped) inside the PN junction.

Page 96: Power Electronic Devices

9696

P-side - N-side+

PIN junctions (II)

q·NDr(x)x

-q·NA

-Emax

x

Vrev x

Intrinsic

Many holes Many electronsA few holes

and electrons

• It means P-Intrinsic-N

Negative space charge

Positive space charge

Characteristics:

- Good forward operation due to conductivity modulation.

- Low depletion capacitance.

- Slow switching operation.

All these characteristics will be explained later.

Page 97: Power Electronic Devices

9797

Other structure to withstand high voltage: P+N-N+

P+ - + N- + N+

-q·NA

q·ND1

r(x)

x

q·(ND2-ND1)

x

-Emax(Vrev1)

-Emax(Vrev2)

Heavily doped P Heavily doped NLightly doped N

Vrev2 > Vrev1

Low reverse voltage Vrev1

Reverse voltage Vrev2

ND1NA ND2

q·ND2Partially depleted

Page 98: Power Electronic Devices

98

Forward-bias behaviour of structures to withstand high voltage

In both cases, there is a high-resistivity layer(called drift region)

• This means that, when forward biased, bad behaviour might be expected.

• However, a new phenomenon arises and the result is quite better than expected.

• This phenomenon is called conductivity modulation. In this case, high-level injection takes place.

P+ N+Intrinsic

Undoped

PIN

P+ N+N-

Lightly doped

P+N-N+

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99

Injection levels

Log scale

Carriers/cm3

104

1012

1014

1016

-0.3 -0.2 -0.1 0- 0+ 0.1 0.2 0.3Length [mm]

1010

108

106

P+-side N--side

nPV

nNpP

pNV

Low-level injection:nN(0+) >> pNV(0+)

Log scale

-0.3 -0.2 -0.1 0- 0+ 0.1 0.2 0.3Length [mm]

P+-sideN--sidenPV

nNpP

pNV

High-level injection:nN(0+) » pNV(0+)

• Low-level injection has been assumed so far, for PN and P+N- junctions.

• In the case of a P+N- junction, this assumption is only valid if the forward bias is not very intense. Else, high-level injection starts.

• If the forward voltage is high enough, pNV(0+) approaches nN(0+). In this case, nN does not remain constant any more, but it notably increases.

Not possible!

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100

Conductivity modulation

1016

106

10

1014

10

P+ N+N-

Drift region

P+N-N+

NA = 1019 ND2 = 1019ND1 = 1014

nP+ pN+

nN- » pN-Holes are injected from the P+-side

Electrons are injected from the N+-side

• There is carrier injection from both highly doped regions to the drift region. This is called double injection.

• This phenomenon substantially increases the carrier concentration in the drift region, thus dramatically reducing the device resistivity.

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101

Semiconductor junctions designed to withstand high voltage

PIN P+N-N+

• A high-resistivity region (drift region) is needed to withstand high voltage when the junction is reverse biased.

• Fortunately, this high-resistivity “magically” disappears when the junction is forward biased if the device is properly designed to have conductivity modulation.

• Due to this, devices where the current is passing through P-type and N-type regions (bipolar devices) have superior performances in on-state than devices where the current always passes through the same type (either P or N) of extrinsic semiconductor (unipolar devices).

• Unfortunately, bipolar devices have inferior switching characteristics than unipolar devices.

• Due to this, a trade-off between conduction losses and switching losses has to be established frequently selecting power semiconductor devices.

Summary

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102

If we change the bias conditions instantaneusly, can the current change instantaneusly as well?

• The answer is “no, it cannot”.

• This is due to the fact that the current conducted by a PN junction depends on the minority carrier concentration just at the edges of the depletion region and the voltage withstood by a PN junction depends on the depletion region width.

• In both cases, carriers have to be either generated or recombined or moved, which always takes time.

These non-idealities can characterize as:• Parasitic capacitances (useful for linear applications)

• Switching times (useful for switching applications)

Transient and AC operation of a PN junction

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103

Parasitic capacitances: depletion layer capacitance (I) (also known as junction capacitance)

This is the dominant capacitance in reverse bias

x

r(x)Vext

P-sideVO+Vext

- + Zona NVO+Vext+Vext

- + N-side

Vext + Vext

Carriers are pulled out from the depletion region when Vext is increased in Vext . Additional space charge has been generated.

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104

- +P N

Vext

PN junction

Vext

+ + +

- - -+ + + + +- - - - -

Vext + Vext

Capacitor

• Capacitor: new charges are located at the same distance Þ constant capacitance.• PN junction: new charges are located farther away

from each other Þ non-constant capacitance.

Vext + Vext

- +P N- +

Parasitic capacitances: depletion layer capacitance (II)

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105

In an “abrupt” PN junction (as we have considered so far), this capacitance is a K·(V0-Vext)-1/2 -type function

Cj=dQ/dV=e·A/W(Vext)

W(Vext) = p P p N e

VU V

T 2·e·(NA+ND)·(V0-Vext)

q·NA·ND

Cj = A· p P p N e

VU V

T 2·(NA+ND)·(V0-Vext)

e·q·NA·ND

W(Vext)-dQ

dQ• As it is a non-constant capacitance,

static and dynamic capacitances could be defined. The latter is defined as:

Then:

0

Vext

Cj

Parasitic capacitances: depletion layer capacitance (III)

As:

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106

This capacitance is the one dominant in forward bias

Reverse bias Forward bias

• Cj increases when the PN junction is forward biased.

• However, depletion layer capacitance only dominates the reactance of a PN junction under reverse bias.

• For forward bias, the diffusion capacitance (due to the charge stored in the neutral regions) becomes dominant.

0 Vext

Cj

Parasitic capacitances: diffusion capacitance (I)

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107

Increase of minority carriers due to a increase of 60mV in forward bias

1010

1012

1014

1016

Carr

iers

/cm

3

-3 -2 -1 0 1 2 3

Longitud [mm]

pP

pNV

nN

nPV

V=180mV

• This increase in electric charge is a function of the forward bias voltage.

• This means that a capacitive effect takes place in these conditions.

• The dynamic capacitance thus obtained is called diffusion capacitance.

V=240mV

Parasitic capacitances: diffusion capacitance (II)

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108

Switching times in PN junctions (I)

The diode behaviour seems to be ideal in this time scale.

Transition from “a” to “b” (switching off) in a wide time scale (ms or s).

a b

V1

V2

R i

v+

-i

v

t

t

V1/R

-V2

Let us consider a PN diode as PN junction. The results obtained can be generalized to PN junctions in other semiconductor devices.

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109

a b

V1

V2

R i

v+

-

Transition from “a” to “b” (switching off) in a narrow time scale (s or ns).

i

v

t

t

trr

V1/R

-V2/R

ts

tf (i= -0.1·V2/R)

-V2

ts = storage time. tf = fall time. trr = reverse recovery time.

Reverse recovery peak

Switching times in PN junctions (II)

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110

a b

V1

V2

R i

v+

-

Why does this evolution occur? • This is because the junction cannot

withstand voltage until all the excess of minoritary carriers disappears from the neutral regions.

V1/R

vt

i

t pNVnPV

Carriers/cm3

8·1013

4·1013

0

-0.1 0 0.1Length [mm]

t0t0

t3

t3

t1

t1

t2

t2

-V2

-V2/R

t4

t4

t0t0

Switching times in PN junctions (III)

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111

a b

V1

V2

R i

v+

-

pNVnPV

Carriers/cm3

8·1013

4·1013

0

-0. 1 0 0.1Length [mm]

i

td = delay time.

tr = rise time.

tfr = td + tr = forward recovery time.

tr

0,9·V1/R

td

0,1·V1/R

tfr

t0

t0

t1

t1

t2

t2

t3

t3

t4t4

Switching times in PN junctions (IV)

Transition from “b” to “a” (switching on) in a narrow time scale (s or ns).

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Trade-off between static and dynamic behaviour in PN junctions

• P+N-N+ and PIN structures allow us to combine high reverse voltage (due to a wide drift region) and low forward resistivity (due to conductivity modulation).

• However, these structures imply large excess of minority carriers (even majority carries due to conductivity modulation). This excess of carriers must be eliminated when the device switches off to allow the device to withstand voltage.

• The time to remove this excess of carriers depends on the width of the drift layer. If the drift layer is shorter than a hole diffusion length, then very little charge is stored and the device switches off fast. In this case, however, the device cannot withstand high reverse voltages.

1016

106

10

1014

10

P+ N+N-

NA = 1019 ND2 = 1019ND1 = 1014

nP+ pN+

nN- » pN-

Log scale

Excess of holes in N-

Excess of electrons in N-

Excess of electrons in P+

Excess of holes in N+

• The switching process can be made still faster by purposely adding “recombination centers”, such as Au atoms in Si, to increase the recombination rate. However, this fact can deteriorate the conductivity modulation.

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Introduction to the metal-semiconductor junctions (I)

Case #1: an N-type semiconductor transfers

electrons to a metal

N-type semiconductorMetal

N+++

+++

+ +-------

-N-type

Donor ions Electrons (thin sheet)

• Metals have many more electrons than semiconductors. However, metals and semiconductors are different materials. This is not the case of a PN junction, where the two sides (P and N) are made up of the same material.

• In a PN junction made up of a given semiconductor, electrons (holes) move from the N-side (P-side) to the P-side (N-side) due to diffusion, until the built-in voltage establishes an equilibrium between diffusion and drift currents.

• In a metal-semiconductor junction, the electron movement when the junction is being built strongly depends on the work function of both materials. The higher the work function, the more difficult for the electrons to eject the material.

• 4 possibilities exist when you build a Metal-Semiconductor (MS) junction:

Page 114: Power Electronic Devices

• In Case #1 and Case #2, a depletion region in the semiconductor side has been generated.

• This depletion region has a built-in voltage that stops the electron diffusion.

• This built-in voltage can be decreased by external forward bias (thus allowing massive electron diffusion) or increased by external reverse bias (avoiding electron diffusion).

• The final result is that it works like a rectifying contact (similar to a PN junction).

114

P-type semiconductorMetal

P---

---

- -+++++++

+

P-type

Acceptor ions

Lack of electrons (thin sheet )

Case #2: a metal transfers electrons to a P-type semiconductor

Introduction to the metal-semiconductor junctions (II)

Recombination between the transferred electrons and the P-side holes takes place in this edge.

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N-type semiconductorMetal

N-type+

++++

+

++

-----

-

--

Electrons (thin sheet)

Lack of electrons(thin sheet)

Case #4: a P-type semiconductor transfers electrons to a metal P-type semiconductorMetal

P-type+

++++

+

++

-----

-

--

Electrons (thin sheet)

Holes(thin sheet)

Introduction to the metal-semiconductor junctions (III)

Case #3: a metal transfers electrons to an N-type semiconductor

• We have an ohmic contact (non-rectifying contact) in both cases.

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116

Rectifying contacts (I)

• The width of the depletion region, the maximum electric field and the depletion layer capacitance can be calculated as in the case of a PN junction with an extremely-doped P side (i.e., NA ).

• Therefore:

eEmax0 =

2·q·ND·V02·e·V0W0 = q·ND

Cj0 = A· p P p N e

VU V

T 2·V0

e·q·ND

However, the built-in voltage and the I-V characteristic depend on the work function of both the semiconductor and the metal.

Case #1: an N-type semiconductor transfers

electrons to a metal

W0

MetalN+

++

+++

+ +-------

-N-type

ND

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117

Rectifying contacts (II)

• Built-in voltage:

V0 = (Fm - Fs_N)/q, where:

Fm = metal work function.

FS_n = N-type semiconductor work function.

• Barrier voltage to avoid electron diffusion without bias:

VB = (Fm - cS_n)/q, where:

cS_n = N-type semiconductor electron affinity.

• I-V characteristic:

i = IS·(eVext/VT - 1), as in a PN junction.

However, the value of Is has a very different value:

IS = A*·A·T2·e-VB/VT , where:

A* = Richardson constant (120 amps/(cm2·K2)).

To define these concepts properly, we should introduce others. This task, however, is beyond the scope of this course.

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Schematic Symbol

Rectifying contacts (III)

• There is a type of diode based on the operation of a rectifying contact. It is the Schottky diode. Schottky diodes are widely used in many applications, including RF (telecom) circuits and low-voltage, medium-power power converters.

• Main features: Lower forward voltage drop than a similar-range, PN-

junction diode. They are faster than PN diodes because minority carriers

hardly play any role in the current conduction process. They are majority carrier devices.

However, they always have a higher reverse current (this is not a big problem).

When they are made up of silicon, the maximum reverse voltage (compatible with reasonable drop voltage in forward bias) is about 200 V.

However, Schottky diodes made up of wide-bandgap materials (such as silicon carbide and gallium nitride) reach breakdown voltages as high as 600-1200 V.

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Ohmic contacts

• There are two different possibilities to obtain ohmic contacts:a) According to the previous slides, to have an MS junction corresponding to Case #3 or to Case #4.b) To have MS junctions corresponding to Cases #1 or #2, but with an extremely-doped semiconductor side (1019 atoms/cm3). In this situation, electrons can flow in both directions by a tunneling process.

P+ N+NNA1 = 1019 ND2 = 1019ND1 = 1016NA2 = 1016

P

N+NND2 = 1019ND1 = 1016

Ohmic contactsOhmic contacts

Rectifying contacts Ohmic contacts

PN diode

Schottky diode

Beyond the scope of this course, as well.