Presented by P.V.S.R. Bharadwaja

D. Praveen Kumar

Department of Electronics and Communication Engineering SREE VIDYANIKETHAN ENGINEERING COLLEGE

Objective Dadda Algorithm Comparison of different types of Multipliers Different types of convolution Zero Delay Convolution Proposed Model

Obtain a model which uses low power and also can be constructed in less area by using zero delay convolution technique integrating dadda multiplier

proposed model is accurate when compared to other models

Number of full adder required : N2– 4.N+3

Number of half adders required : N-1

Length of carry propagation stage :2N-2

Normal Multiplier

Vedic Multiplier

Dadda Multiplier

For 2 bit MultiplicationNumber of Multiplications

4 4 4

No. of additions 2 1 1 For 4 bit multiplicationNumber of Multiplications

16 16 16

Number of additions

15 9 6

For 8 bit multiplicationNumber of multiplications

64 64 64

Number of additions

77 53 42

Time domain convolution Frequency domain convolution

Convolution in time domain is multiplication in frequency domain

In this paper we discuss about the time domain convolution

Proposed by Gardner in the year 1995

It is a hybrid method which combines the direct FIR and block convolution techniques.

The resulting algorithm can exhibit zero input-output latency which makes it a suitable choice for high performance real-time convolution applications

Zero delay convolution satisfies the constraint of Low delay

Dadda Algorithm reduces the hardware used for implementation

Here we propose a model which satisfies both the conditions of low delay and low area

Here by we are using dadda algorithm to implement zero delay convolution