DMA CONTROLLER DMA CONTROLLER 82578257

Features:Features:It is a 4-channel DMA.It is a 4-channel DMA. So 4 I/O devices can be interfaced to So 4 I/O devices can be interfaced to

DMADMA It is designed by IntelIt is designed by Intel Each channel have 16-bit address and Each channel have 16-bit address and

14 bit counter14 bit counter It provides chip priority resolver that It provides chip priority resolver that

resolves priority of channels in fixed or resolves priority of channels in fixed or rotating mode.rotating mode.

It provide on chip channel inhibit It provide on chip channel inhibit logic.logic.

It generates a TC signal to It generates a TC signal to indicate the peripheral that the indicate the peripheral that the programmed number of data programmed number of data bytes have been transferred.bytes have been transferred.

It generates MARK signal to It generates MARK signal to indicate the peripheral that 128 indicate the peripheral that 128 bytes have been transferred.bytes have been transferred.

It requires single phase clock.It requires single phase clock.The maximum frequency is 3Mhz The maximum frequency is 3Mhz

and minimum frequency is 250 and minimum frequency is 250 Hz.Hz.

It execute 3 DMA cyclesIt execute 3 DMA cycles 1.DMA read 2.DMA write 1.DMA read 2.DMA write

3.DMA verify.3.DMA verify. It provide AEN signal that can It provide AEN signal that can

be used to isolate CPU and other be used to isolate CPU and other devices from the system bus.devices from the system bus.

It is operate in two modes.It is operate in two modes. 1.Master Mode1.Master Mode 2.Slave Mode2.Slave Mode

Pin Diagram of DMA Pin Diagram of DMA controllercontroller

Description of pin Description of pin diagramdiagram

D0-D7:D0-D7: it is a bidirectional ,tri it is a bidirectional ,tri

state ,Buffered ,Multiplexed data state ,Buffered ,Multiplexed data (D0-D7)and (A8-A15).(D0-D7)and (A8-A15).

In the slave mode it is a bidirectional In the slave mode it is a bidirectional (Data is moving).(Data is moving).

In the Master mode it is a In the Master mode it is a unidirectional (Address is moving).unidirectional (Address is moving).

IOR:IOR: It is active It is active

low ,tristate ,buffered ,Bidirectional low ,tristate ,buffered ,Bidirectional lines.lines.

In the slave mode it function as a In the slave mode it function as a input line. IOR signal is generated by input line. IOR signal is generated by microprocessor to read the contents microprocessor to read the contents 8257 registers.8257 registers.

In the master mode it function as a In the master mode it function as a output line. IOR signal is generated by output line. IOR signal is generated by 8257 during write cycle8257 during write cycle

IOW:IOW: It is active It is active

low ,tristate ,buffered ,Bidirectional low ,tristate ,buffered ,Bidirectional control lines.control lines.

In the slave mode it function as a In the slave mode it function as a input line. IOR signal is generated by input line. IOR signal is generated by microprocessor to write the contents microprocessor to write the contents 8257 registers.8257 registers.

In the master mode it function as a In the master mode it function as a output line. IOR signal is generated output line. IOR signal is generated by 8257 during read cycleby 8257 during read cycle

CLK:CLK: It is the input line ,connected with TTL clock It is the input line ,connected with TTL clock

generator.generator. This signal is ignored in slave mode.This signal is ignored in slave mode.RESET:RESET: Used to clear mode set registers and status registersUsed to clear mode set registers and status registersA0-A3:A0-A3:These are the tristate, buffer, bidirectional address These are the tristate, buffer, bidirectional address

lines.lines.In slave mode ,these lines are used as address inputs In slave mode ,these lines are used as address inputs

lines and internally decoded to access the internal lines and internally decoded to access the internal registers.registers.

In master mode, these lines are used as address In master mode, these lines are used as address outputs lines,A0-A3 bits of memory address on the outputs lines,A0-A3 bits of memory address on the lines. lines.

CS:CS: It is active low, Chip select input line.It is active low, Chip select input line. In the slave mode, it is used to select the In the slave mode, it is used to select the

chip.chip. In the master mode, it is ignored.In the master mode, it is ignored.A4-A7:A4-A7:These are the tristate, buffer, output address These are the tristate, buffer, output address

lines.lines.In slave mode ,these lines are used as address In slave mode ,these lines are used as address

outputs lines.outputs lines.In master mode, these lines are used as In master mode, these lines are used as

address outputs lines,A0-A3 bits of memory address outputs lines,A0-A3 bits of memory address on the lines. address on the lines.

READY:READY: It is a asynchronous input line.It is a asynchronous input line. In master mode,In master mode, When ready is high it is received the When ready is high it is received the

signal.signal. When ready is low, it adds wait state When ready is low, it adds wait state

between S1 and S3between S1 and S3 In slave mode ,this signal is ignored.In slave mode ,this signal is ignored.HRQ:HRQ: It is used to receiving the hold request It is used to receiving the hold request

signal from the output device.signal from the output device.

HLDA:HLDA: It is acknowledgment signal from microprocessor. It is acknowledgment signal from microprocessor. MEMR:MEMR: It is active low ,tristate ,Buffered control output It is active low ,tristate ,Buffered control output

line.line. In slave mode, it is tristated.In slave mode, it is tristated. In master mode ,it activated during DMA read In master mode ,it activated during DMA read

cycle. cycle. MEMW:MEMW: It is active low ,tristate ,Buffered control input line.It is active low ,tristate ,Buffered control input line. In slave mode, it is tristated.In slave mode, it is tristated. In master mode ,it activated during DMA write In master mode ,it activated during DMA write

cycle.cycle.

AEN (Address enable):AEN (Address enable): It is a control output line.It is a control output line. In master mode ,it is highIn master mode ,it is high In slave mode ,it is lowIn slave mode ,it is low Used it isolate the system Used it isolate the system

address ,data ,and control lines.address ,data ,and control lines.ADSTB: (Address Strobe)ADSTB: (Address Strobe) It is a control output line.It is a control output line. Used to split data and address line.Used to split data and address line. It is working in master mode only.It is working in master mode only. In slave mode it is ignore.In slave mode it is ignore.

TC (Terminal Count):TC (Terminal Count): It is a status of output line.It is a status of output line. It is activated in master mode only.It is activated in master mode only. It is high ,it selected the peripheral.It is high ,it selected the peripheral. It is low ,it free and looking for a new It is low ,it free and looking for a new

peripheral.peripheral.MARK:MARK: It is a modulo 128 MARK output line.It is a modulo 128 MARK output line. It is activated in master mode only.It is activated in master mode only. It goes high ,after transferring every It goes high ,after transferring every

128 bytes of data block.128 bytes of data block.

DRQ0-DRQ3(DMA Request):DRQ0-DRQ3(DMA Request): These are the asynchronous peripheral These are the asynchronous peripheral

request input signal.request input signal. The request signals is generated by The request signals is generated by

external peripheral device.external peripheral device.DACK0-DACK3:DACK0-DACK3: These are the active low DMA These are the active low DMA

acknowledge output lines.acknowledge output lines. Low level indicate that ,peripheral is Low level indicate that ,peripheral is

selected for giving the information (DMA selected for giving the information (DMA cycle).cycle).

In master mode it is used for chip select.In master mode it is used for chip select.

8257 BLOCK DIAGRAM8257 BLOCK DIAGRAM

DescriptionDescription It containing Five main Blocks.It containing Five main Blocks.1.1. Data bus bufferData bus buffer2.2. Read/Control logicRead/Control logic3.3. Control logic blockControl logic block4.4. Priority resolverPriority resolver5.5. DMA channels.DMA channels.

DATA BUS BUFFER:DATA BUS BUFFER: It contain tristate ,8 bit bi-directional buffer.It contain tristate ,8 bit bi-directional buffer. Slave mode ,it transfer data between Slave mode ,it transfer data between

microprocessor and internal data bus.microprocessor and internal data bus. Master mode ,the outputs A8-A15 bits of Master mode ,the outputs A8-A15 bits of

memory address on data lines memory address on data lines (Unidirectional).(Unidirectional).

READ/CONTROL LOGIC:READ/CONTROL LOGIC: It control all internal Read/Write operation.It control all internal Read/Write operation. Slave mode ,it accepts address bits and Slave mode ,it accepts address bits and

control signal from microprocessor.control signal from microprocessor. Master mode ,it generate address bits and Master mode ,it generate address bits and

control signal.control signal.

Control logic block:Control logic block: It contains ,It contains ,1.1. Control logicControl logic2.2. Mode set register and Mode set register and 3.3. Status Register.Status Register.CONTROL LOGIC:CONTROL LOGIC: Master mode ,It control the sequence of Master mode ,It control the sequence of

DMA operation during all DMA cycles.DMA operation during all DMA cycles. It generates address and control signals.It generates address and control signals. It increments 16 bit address and decrement It increments 16 bit address and decrement

14 bit counter registers.14 bit counter registers. It activate a HRQ signal on DMA channel It activate a HRQ signal on DMA channel

Request.Request. Slave ,mode it is disabled.Slave ,mode it is disabled.

MODE SET REGISTERS:MODE SET REGISTERS: It is a write only registers.It is a write only registers. It is used to set the operating modes.It is used to set the operating modes. This registers is programmed after This registers is programmed after

initialization of DMA channel.initialization of DMA channel.

DD77 DD66 DD55 DD44 DD33 DD22 DD11 DD00

ALAL TCTCSS

EWEW RPRP ENEN33

ENEN22

ENEN11

ENEN00

AL=1=Auto load modeAL=1=Auto load modeAL=0=Rotating modeAL=0=Rotating mode

TCS=1=Stop after TC (Disable Channel)TCS=1=Stop after TC (Disable Channel) TCS=0=Start after TC (Enable Channel)TCS=0=Start after TC (Enable Channel)

EW=1=Extended write modeEW=1=Extended write mode EW=0=normal mode.EW=0=normal mode.

RP=1=Rotating priorityRP=1=Rotating priority RP=0=Fixed priority.RP=0=Fixed priority.

ENEN33=1=Enable DMA CH-3=1=Enable DMA CH-3 ENEN33=0=Disable DMA CH-3=0=Disable DMA CH-3

ENEN22=1=Enable DMA CH-2=1=Enable DMA CH-2 ENEN22=0=Disable DMA CH-2=0=Disable DMA CH-2

ENEN11=1=Enable DMA CH-1=1=Enable DMA CH-1 ENEN11=0=Disable DMA CH-1=0=Disable DMA CH-1

ENEN00=1=Enable DMA CH-0=1=Enable DMA CH-0 ENEN00=0=Disable DMA CH-0=0=Disable DMA CH-0

STATUS REGISTERS:STATUS REGISTERS: It is read only registers.It is read only registers. It is tell the status of DMA channelsIt is tell the status of DMA channels TC status bits are set when TC signal is TC status bits are set when TC signal is

activated for that channel.activated for that channel. Update flag is not affected during read Update flag is not affected during read

operation.operation. The UP bit is set during update cycle . It is The UP bit is set during update cycle . It is

cleared after completion of update cycle.cleared after completion of update cycle.DD77 DD66 DD55 DD44 DD33 DD22 DD11 DD00

00 00 00 UPUP TCTC33 TCTC22 TCTC11 TCTCOO

UP=Update flagUP=Update flag UP=1=8257 executing update cycleUP=1=8257 executing update cycle UP=0=8257 executing DMA cycleUP=0=8257 executing DMA cycle

TCTC33=1=TC activated CH-3=1=TC activated CH-3 TCTC33=0=TC activated CH-3=0=TC activated CH-3

TCTC22=1=TC activated CH-2=1=TC activated CH-2 TCTC22=0=TC activated CH-2=0=TC activated CH-2

TCTC11=1=TC activated CH-1=1=TC activated CH-1 TCTC11=0=TC activated CH-1=0=TC activated CH-1

TCTC00=1=TC activated CH-0=1=TC activated CH-0 TCTC00=0=TC activated CH-0=0=TC activated CH-0

The address of status register is AThe address of status register is A33AA22AA11AA00=1000.=1000.

FIRST/LAST FLIP FLOP:FIRST/LAST FLIP FLOP: 8257 have 8bit data line and 16 bit address line.8257 have 8bit data line and 16 bit address line. 8085 it is getting 8-bit data in simultaneously.8085 it is getting 8-bit data in simultaneously. 8085 can not access 16-bit address in 8085 can not access 16-bit address in

simultaneously.simultaneously.

A0-A3 lines are used to distinguish A0-A3 lines are used to distinguish between registers ,but they are not between registers ,but they are not distinguish lower and higher address.distinguish lower and higher address.

It is reset by external RESET signal.It is reset by external RESET signal. It is also reset by whenever mode set It is also reset by whenever mode set

register is loaded.register is loaded. So program initialization with a So program initialization with a

dummy (00 H).dummy (00 H). FF=1=Higher byte of addressFF=1=Higher byte of address FF=0=Lower byte of address.FF=0=Lower byte of address.

Modes of Operation Rotating priority Mode: The priority of the channels has a

circular sequence. Fixed Priority Rotating Mode: The priority is fixed. TC Stop Mode Auto Load mode Extended Write mode

DMA Cycles DMA read: DMA write DMA Verify