practical de-embedding for gigabit fixtures

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    Practical De-embedding for

    Gigabit FixturesBen ChiaSenior Signal Integrity Consultant

    5/17/2011

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    Topics Why De-Embedding/Embedding? De-embedding in Time Domain De-embedding in Frequency Domain De-embedding example Compliance test examples Accuracy consideration

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    Terminalolgy De-Embedding Remove fixture effect from the measurement Example: remove probes, SMA+traces

    Embedding Add a cable to see what happen to the signal Example: test receiver sensitivity by adding a 4-inch cable between

    the driver and DUT

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    De-embedding Example

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    Measurement Reference Plane

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    6-meter cable de-embedding

    Does your scope show the real waveform? `6

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    Example: De-embedding Probes

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    More Example: DDR2 Device Fixture

    How to remove this fixture effect?8

    DDR2

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    DDR2 Fixture De-Embedding

    Scope performs de-embedding9

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    De-Embedding CalibrationBoth VNA/TDR have firmware to

    simplify de-embedding process

    Probe de-embedding

    Fixture de-embedding

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    Calibrate with SMA standard Short Load

    Connect Port 1 to SMA to measure S11

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    SMA

    How to capture S11 at the package ball?

    PCB trace

    TDR De-embedding Example

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    TDR De-embedding Example

    Agilent 54754A Option A Step 1: Capture fixture S4P ( Pad+trace +SMA )

    Calibrate using SMA standard and Probe standard Measure DUT

    Capture S4P of SMA+Trace in Time Domain

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    SMA

    Port1: Pad Probing

    Port2: Probing

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    Probing Example

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    TDR De-embedding

    Option A Step 1: Capture fixture S4P for trace with SMA at one end and

    PCB pads at the other end?

    Step 2: De-embedding fixture trace using ADS

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    TDR De-embedding

    Option B De-embedding including SMA using on-board calibration short

    and load standard

    Measurement

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    DUT

    short

    50 ohm load

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    Return Loss De-embedding

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    De-Embedding using VNA

    Equipment : Agilent ENA Calibration : SOLT DUT: Port 1, 2 - SMA Port 3, 4 - USB connectors

    Require TRL-like PCB calibration standard Fixture delay estimation use port extension to measure fixture delay

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    SMA USB

    Port1,2 Port3,4

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    USB3.0 De-embedding Example

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    A

    C

    HowtomeasureS4PfromAtoC?

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    USB3.0 De-embedding Example

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    HowtomeasureS4PfromAtoC?

    A

    C

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    De-embedding fixture andCalibration board

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    De-embedding fixture

    A

    C

    Calibration Board

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    Calibration Fixture

    Calibration Standard Open/Short/Load Port1, 3 use coaxial standard Port 2,4 use calibration board

    Delay/through Port 1-2 use coaxial standard Port 3-4 use 2x fixture trace Prot 1-3, 2-4, 1-4, 2-3 use 1x fixture trace

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    Open/Short/load1x fixture trace

    1x thru trace

    2x thru trace

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    Example : Return Loss Measurement

    Introduction Return loss measurement When return loss is not passing Return loss fixture removal

    How to fix the return loss problem Summary

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    Sata Interconnect

    23Return Loss Specification limits the reflected energy

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    Return Loss Definition

    Slide

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    Return Loss = or

    where

    Zo is the Tx/Rx differential output/inputimpedance

    ZL is the link differential impedance

    Vi is the differential voltage incident upon Rx/Tx

    Vr is the differential reflected voltage from Tx/Rx

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    Common Mode vs. Differential Mode

    Slide

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    Return Loss Measurement

    Many design can not meet return loss requirement Return loss accuracy and repeatability become crutial Both TDR ( time domain ) and VNA (frequency domain) can

    be used for return loss measurement

    Recommend VNA for marginal design Accuracy noise floor and calibration Repeatability - calibration standard

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    Return Loss Element

    Termination and IO circuit Ask circuit designer to reduce mismatch in both differential mode

    and common mode

    Differential driver circuit state Design special circuit to set IO to static 1 or 0 state Capable to set static de-emphasis state

    Pattern Blocking Capacitor

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    Blocking Caps

    The 100nF off chip coupling capacitor leads to a coupling timeconstant of 10 us. Such a long time constant is needed to limitbaseline wander with scrambled data

    Make sure DC blocking capacitor is in placed for activetransmitter return loss measurement - TDR/VNA port maygradually get damaged

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    How to Pass Return Loss

    Small IO capacitance less reflection Uniform impedance less reflection Shorter and uniform impedance fixture May not require fixture de-embedding if margin is large enough

    Long fixture trace and via will have better return loss numberbecause reflection are attenuated by the long trace Yougot wrong result

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    Vector Network Analyzer

    Frequency Domain Equipment Single ended measurement Convert to differential mode and common mode with

    software

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    How Return Loss Are Measured today

    VNA Setup 0 dbm (1mw)

    Tx Setup One driver on AC high state ( < Voh) Another driver on AC low state (> Vol)

    Rx Setup Activate terminator

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    Return Loss De-embedding

    Simulation to remove the SMA, PCB trace, via and fingers. The return loss after de-embedding are usually worse than the

    VNA data measured at the SMA or PCB fingers

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    SMA Anti-pad Optimization Antipad diameter under trace Antipad diameter above trace Signal via radius Trace moved to different layer Ground via distance

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    Optimized Anti-pad Design

    SMA

    Optimization critera-- 50 ohm-- low return loss

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    Return Loss Tuning Strategy : Simulation

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    PkgVia

    PkgTrace

    Pkg Stub

    BondWire

    RiCi

    Rterm

    Agilent ADS or any spice tool can make this simple model

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    Transmit Port B Return Loss Including PCB

    Red: ModelBlue: Measured

    An Example: XAUI

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    Receive Port B Return Loss Including PCB

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    Red: ModelBlue: Measured

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    Transmit Port B Return Loss

    Not Including Socket

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    Receive Port B Return Loss

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    Not Including Socket

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    Pink: Measured Rx Black: Model Rx

    Slide39

    Violations at 3Ghz

    What was wrong in this design?

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    Circuit for Return Loss Calculation

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    S11

    Z0

    CL

    RL RS

    CL: Cell Capacitance RS: Cell Series Resistance

    RL: Termination resistance Z0: Reference Resistance for S11 Calculation

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    Rx Return loss model vs measured

    Slide41

    83ps

    SMA

    Pcbvia

    PackagePad/ball/via

    Ci

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    Rx Return Loss Debugging

    Identify the elements from S11 plot 3GHz = 333ps Reflection at 180 degree 165ps Round trip delay 83ps Delay from PCB pad to Pakage pad ~83ps

    Fix: Increase the impedance to 50 ohm at the PCB via and package

    via in the model

    Slide42

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    Pink: measured Rx Black: modified Rx model

    Slide43

    Replace PCB via andPackage pads to 50 ohm

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    TX : Increase PCB and Pads to 50 ohm

    Slide44

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    Return Loss Summary

    Measurement based return loss provides accurateresults after de-embedding SMA and lead-in traceson the text fixture

    SMA Impedance discontinuity can affect return losssignificantly

    Optimized SMA anti-pad design can improve returnloss accuracy

    Return loss measurement can be verified by carefulmodeling the package and PCB interconnecttransistion

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    Hands-on Lab

    USB Compliance test Configuration Different fixture design comparison Insertion loss Eye diagram

    Conclusions

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    USB 3.0 Tx Compliance Channels

    Compliance Channels are definedto test Transmitter for worst caseconditions.

    Worst Case Channel for Hosts 5 Device PCB Trace 3M Cable

    Worst Case Channel for Devices 11 Device PCB Trace 3M Cable

    Host Tx

    TP0

    Device TxTP0

    Host Tx

    TP1

    Device TxTP1

    3 Meter

    USB 3.0

    Cable

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    GRL Case Study:Three USB 3.0 Probing Setups for Device Testing

    USB-IF Fixture with 4USB3.0 Cable

    Agilent Fixture with 4USB3.0 Cable

    LiTek Fixture with 0Cable

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    Scope

    TP0

    TP0

    TP0

    MeasurementPlane

    LITEK_TIER2.S4P

    FixtureX.S4P

    Measurement

    PlaneTP0

    (Device Connector)

    INTEL_TIER2.S4P

    AGILENT_TIER2.S4P

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    Compliance Test Point

    Embed of USB 3.0 Cable + HostChannel

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    Transmit ChannelTP1

    TP0

    CTLEIn Scope SW

    cascade_cable_back.s4p

    100mV

    Eye Mask

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    Differential Insertion Loss Comparison

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    2.5GHz Nyquist Frequency

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    Results

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    Agilent + 4 Cable Intel + 4 Cable

    @ Scope

    Inputs

    LiTek + 0 Cable

    @ TP0DUT

    Connector

    @ TP1-EqCompliance

    Point

    250mV

    234mV 228mV

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    Conclusions

    LiTek with 0 cable provides 6-9% Higher Voltage Margin than4 Cable based fixtures.

    Intel Fixture, which is recommended by the USB-IF provides theleast amount of margin and represents the worst case of the

    three fixtures tested.

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    Thank You

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    Contact Information

    Corporate Headquarters

    3500 Thomas Road, Suite ASanta Clara, CA 95054 USA

    GRL Company Confidential

    Johnson Tan, CEO

    [email protected]

    Mike Engbretson, Chief Technology [email protected]