©1990 Burr-Brown Corporation PDS-1081E Printed in U.S.A. August, 1997

OPA177

FEATURES LOW OFFSET VOLTAGE: 25 µV max

LOW DRIFT: 0.3µV/°C HIGH OPEN-LOOP GAIN: 130dB min

LOW QUIESCENT CURRENT: 1.5mA typ

REPLACES INDUSTRY-STANDARD OPAMPS: OP-07, OP-77, OP-177, AD707,ETC.

APPLICATIONS PRECISION INSTRUMENTATION

DATA ACQUISITION

TEST EQUIPMENT

BRIDGE AMPLIFIER

THERMOCOUPLE AMPLIFIER

PrecisionOPERATIONAL AMPLIFIER

14kΩ

500Ω

Trim8

V+7

Trim1

+In3

–In2

V–4

25Ω

30Ω

V 6O

20µA

500Ω

DESCRIPTIONThe OPA177 precision bipolar op amp feature verylow offset voltage and drift. Laser-trimmed offset,drift and input bias current virtually eliminate the needfor costly external trimming. The high performanceand low cost make them ideally suited to a wide rangeof precision instrumentation.

The low quiescent current of the OPA177 dramati-cally reduce warm-up drift and errors due to thermo-

electric effects in input interconnections. It providesan effective alternative to chopper-stabilized amplifi-ers. The low noise of the OPA177 maintains accuracy.

OPA177 performance gradeouts are available. Pack-aging options include 8-pin plastic DIPand SO-8 surface-mount packages.

®

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Bl vd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FA X: (520) 889-1510 • Immediate Product Info: (800) 548-6132

OPA177

OPA177

SBOS008

2®

OPA177

OPA177 SPECIFICATIONSAt VS = ±15V, TA = +25°C, unless otherwise noted.

OPA177F OPA177G

PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS

OFFSET VOLTAGEInput Offset Voltage 10 25 20 60 µVLong-Term Input Offset(1) 0.3 0.4 µV/Mo Voltage StabilityOffset Adjustment Range RP = 20kΩ ±3 mVPower Supply Rejection Ratio VS = ±3V to ±18V 115 125 110 120 dB

INPUT BIAS CURRENTInput Offset Current 0.3 1.5 2.8 nAInput Bias Current 0.5 ±2 ±2.8 nA

NOISEInput Noise Voltage 1Hz to 100Hz(2) 85 150 nVrmsInput Noise Current 1Hz to 100Hz 4.5 pArms

INPUT IMPEDANCEInput Resistance Differential Mode(3) 26 45 18.5 MΩ

Common-Mode 200 GΩ

INPUT VOLTAGE RANGECommon-Mode Input Range(4) ±13 ±14 VCommon-Mode Rejection VCM = ±13V 130 140 115 dB

OPEN-LOOP GAIN RL ≥ 2kΩLarge Signal Voltage Gain VO = ±10V(5) 5110 12,000 2000 6000 V/mV

OUTPUTOutput Voltage Swing RL ≥ 10kΩ ±13.5 ±14 V

RL ≥ 2kΩ ±12.5 ±13 VRL ≥ 1kΩ ±12 ±12.5 V

Open-Loop Output Resistance 60 Ω

FREQUENCY RESPONSESlew Rate RL ≥ 2kΩ 0.1 0.3 V/µsClosed-Loop Bandwidth G = +1 0.4 0.6 MHz

POWER SUPPLYPower Consumption VS = ±15V, No Load 40 60 mW

VS = ±3V, No Load 3.5 4.5 mWSupply Current VS = ±15V, No Load 1.3 2 mA

At VS = ±15V, –40°C ≤ TA ≤ +85°C, unless otherwise noted.

OFFSET VOLTAGEInput Offset Voltage 15 40 20 100 µVAverage Input Offset 0.1 0.3 0.7 1.2 µV/°C Voltage DriftPower Supply Rejection Ratio VS = ±3V to ±18V 110 120 106 115 dB

INPUT BIAS CURRENTInput Offset Current 0.5 2.2 4.5 nAAverage Input Offset Current 1.5 40 85 pA/°C Drift(6)

Input Bias Current 0.5 ±4 ±6 nAAverage Input Bias Current 8 40 15 60 pA/°C Drift(6)

INPUT VOLTAGE RANGECommon-Mode Input Range ±13 ±13.5 VCommon-Mode Rejection VCM = ±13V 120 140 110 dB

OPEN-LOOP GAINLarge Signal Voltage Gain RL ≥ 2kΩ, VO = ±10V 2000 6000 1000 4000 V/mV

OUTPUTOutput Voltage Swing RL ≥ 2kΩ ±12 ±13 V

POWER SUPPLYPower Consumption VS = ±15V, No Load 60 75 mWSupply Current VS = ±15V, No Load 2 25 mA

Same as specification for product to left.

NOTES: (1) Long-Term Input Offset Voltage Stability refers to the averaged trend line of VOS vs time over extended periods after the first 30 days of operation. Excludingthe initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2µV. (2) Sample tested. (3) Guaranteed by design. (4) Guaranteedby CMRR test condition. (5) To insure high open-loop gain throughout the ±10V output range, AOL is tested at –10V ≤ VO ≤ 0V, 0V ≤ VO ≤ +10V, and –10V ≤ VO ≤ +10V.(6) Guaranteed by end-point limits.

3®

OPA177

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumesno responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to changewithout notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrantany BURR-BROWN product for use in life support devices and/or systems.

PIN CONFIGURATION

Top View DIP/SOIC

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATICDISCHARGE SENSITIVITY

Any integrated circuit can be damaged by ESD. Burr-Brownrecommends that all integrated circuits be handled withappropriate precautions. ESD can cause damage rangingfrom subtle performance degradation to complete devicefailure. Precision integrated circuits may be more suscep-tible to damage because very small parametric changescould cause the device not to meet published specifications.

Burr-Brown’s standard ESD test method consists of five1000V positive and negative discharges (100pF in serieswith 1.5kΩ) applied to each pin.

Failure to observe proper handling procedures could resultin small changes to the OPA177’s input bias current.

1

2

3

4

8

7

6

5

Offset Trim

–In

+In

V–

Offset Trim

V+

V

No Internal Connection

O

Power Supply Voltage ....................................................................... ±22VDifferential Input Voltage ................................................................... ±30VInput Voltage ....................................................................................... ±VS

Output Short Circuit ................................................................. ContinuousOperating Temperature: Plastic DIP (P), SO-8 (S) .............................................. –40°C to +85°C

θJA (PDIP) ................................................................................. 100°C/WθJA (SOIC) ................................................................................. 160°C/W

Storage Temperature: Plastic DIP (P), SO-8 (S) ............................................ –65°C to +125°CJunction Temperature .................................................................... +150°CLead Temperature (soldering, 10s) P packages ........................... +300°C

(soldering, 3s) S package ............................... +260°C

PACKAGEDRAWING TEMPERATURE

PRODUCT PACKAGE NUMBER (1) RANGE

OPA177FP 8-Pin Plastic DIP 006 –40°C to +85°COPA177GP 8-Pin Plastic DIP 006 –40°C to +85°COPA177GS SO-8 Surface-Mount 182 –40°C to +85°C

NOTE: (1) For detailed drawing and dimension table, please see end of datasheet, or Appendix C of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

4®

OPA177

TYPICAL PERFORMANCE CURVESAt TA = +25°C, VS = ±15V, unless otherwise noted.

10 30 50 700 20 40 60

30

25

20

15

10

5

0

Abs

olut

e C

hang

e in

Inpu

tO

ffset

Vol

tage

(µV

)

Time (s)

OFFSET VOLTAGE CHANGEDUE TO THERMAL SHOCK

80

Device Immersed in 70°C Inert Liquid

Plastic DIP

CLOSED-LOOP RESPONSE vs FREQUENCY100

80

60

40

20

0

–2010 100 1k 10k 100k 1M 10M

Clo

sed-

Loop

Gai

n (d

B)

Frequency (Hz)

3

2

1

0

–1

–2

–3

Offs

et V

olta

ge C

hang

e (µ

V)

0 30 60 90 120

Time from Power Supply Turn-On (s)

WARM-UP OFFSET VOLTAGE DRIFT

15 45 75 105

17.5

15

12.5

10

7.5

5

2.5

0

VO

UT (

V)

0 6 12 18 24 30 36

IOUT (mA)

MAXIMUM VOUT vs IOUT(Positive Swing)

VS = ±18V

VS = ±15V

VS = ±12V

VS = ±15V

–17.5

–15

–12.5

–10

–7.5

–5

–2.5

0

VO

UT (

V)

0 –2 –4 –6 –8 –10 –12

–IOUT (mA)

MAXIMUM VOUT vs IOUT(Negative Swing)

VS = ±18V

VS = ±15V

VS = ±12V

VS = ±15V

1

0.1

0.01

0.001

TH

D +

N (

%)

1k 10k 100k

Frequency (Hz)

TOTAL HARMONIC DISTORTION AND NOISEvs FREQUENCY

A = 20dB, 3Vrms, 10kΩ load

30kHz low pass filtered

InvertingNoninverting

5®

OPA177

TYPICAL PERFORMANCE CURVES (CONT)At TA = +25°C, VS = ±15V, unless otherwise noted.

150

140

130

120

110

100

90

80

CM

RR

(dB

)

1 10 100 1k 10k 100k

Frequency (Hz)

CMRR vs FREQUENCYOPEN-LOOP GAIN/PHASE vs FREQUENCY160

140

120

100

80

60

40

20

0

Ope

n-Lo

op G

ain

(dB

)

0.01 1 10 100 1k 10k 100k 1M0.1

Frequency (Hz)

0

45

90

135

180

Pha

se S

hift

(Deg

rees

)

Phase

Gain

2

1

0

–1

–2–40 –15 10 35 60 85

Temperature (°C)

INPUT BIAS AND INPUT OFFSET CURRENTvs TEMPERATURE

Inpu

t Bia

s an

d In

put O

ffset

Cur

rent

(nA

)

IB

IOS

150

130

110

90

70

50

Pow

er S

uppl

y R

ejec

tion

(dB

)

1 10 100 1k 10k0.1

Frequency (Hz)

POWER SUPPLY REJECTIONvs FREQUENCY

1k

100

10

1

Inpu

t Noi

se V

olta

ge (

nV/√

Hz)

1

Frequency (Hz)

INPUT NOISE VOLTAGE DENSITY vs FREQUENCY

10 100 1k 10k

R = 0S

R = R = 200kThermal noise ofsource resistorsincluded.

S1 S2 Ω10

1

0.1

0.01

RM

S N

oise

(µV

)

100 1k 10k 100k

Bandwidth (Hz)

TOTAL NOISE vs BANDWIDTH(0.1Hz to Frequency Indicated)

6®

OPA177

TYPICAL PERFORMANCE CURVES (CONT)At TA = +25°C, VS = ±15V, unless otherwise noted.

40

35

30

25

20

15

Out

put S

hort

-Circ

uit C

urre

nt (

mA

)

0 1 2 3 4

Time from Output Being Shorted (min)

OUTPUT SHORT-CIRCUIT CURRENT vs TIME

SC

I –SC

I +

20

15

10

5

0

Max

imum

Out

put (

V)

100 10k

Load Resistance to Ground ( )

MAXIMUM OUTPUT VOLTAGE vs LOAD RESISTANCE

1k

Ω

NegativeOutput

PositiveOutput

32

28

24

20

16

12

8

4

0

Pea

k-to

-Pea

k A

mpl

itude

(V

)

1k 10k 100k 1M

Frequency (Hz)

MAXIMUM OUTPUT SWING vs FREQUENCY

G = +1R = 2kL Ω

100

10

1

Pow

er C

onsu

mpt

ion

(mW

)

0 10 20 30 40

Total Supply Voltage (V)

POWER CONSUMPTION vs POWER SUPPLY

7®

OPA177

APPLICATIONS INFORMATIONThe OPA177 is unity-gain stable, making it easy to use andfree from oscillations in the widest range of circuitry. Ap-plications with noisy or high impedance power supply linesmay require decoupling capacitors close to the device pins.In most cases 0.1µF ceramic capacitors are adequate.

The OPA177 has very low offset voltage and drift. Toachieve highest performance, circuit layout and mechanicalconditions must be optimized. Offset voltage and drift canbe degraded by small thermoelectric potentials at the op ampinputs. Connections of dissimilar metals will generate ther-mal potential which can mask the ultimate performance ofthe OPA177. These thermal potentials can be made to cancelby assuring that they are equal in both input terminals.

1. Keep connections made to the two input terminals closetogether.

2. Locate heat sources as far as possible from the criticalinput circuitry.

3. Shield the op amp and input circuitry from air currentssuch as cooling fans.

OFFSET VOLTAGE ADJUSTMENT

The OPA177 has been laser-trimmed for low offset voltageand drift so most circuits will not require external adjust-ment. Figure 1 shows the optional connection of an externalpotentiometer to adjust offset voltage. This adjustment shouldnot be used to compensate for offsets created elsewhere in asystem since this can introduce excessive temperature drift.

INPUT PROTECTION

The inputs of the OPA177 are protected with 500Ω seriesinput resistors and diode clamps as shown in the simplifiedcircuit diagram. The inputs can withstand ±30V differentialinputs without damage. The protection diodes will, of course,conduct current when the inputs are overdriven. This maydisturb the slewing behavior of unity-gain follower applica-tions, but will not damage the op amp.

NOISE PERFORMANCE

The noise performance of the OPA177 is optimized forcircuit impedances in the range of 2kΩ to 50kΩ. Total noisein an application is a combination of the op amp’s inputvoltage noise and input bias current noise reacting withcircuit impedances. For applications with higher sourceimpedance, the OPA627 FET-input op amp will generallyprovide lower noise. For very low impedance applications,the OPA27 will provide lower noise.

INPUT BIAS CURRENT CANCELLATION

The input stage base current of the OPA177 is internallycompensated with an equal and opposite cancellation cur-rent. The resulting input bias current is the differencebetween the input stage base current and the cancellationcurrent. This residual input bias current can be positive ornegative.

When the bias current is cancelled in this manner, the inputbias current and input offset current are approximately thesame magnitude. As a result, it is not necessary to balancethe DC resistance seen at the two input terminals (Figure 2).A resistor added to balance the input resistances may actu-ally increase offset and noise.

FIGURE 1. Optional Offset Nulling Circuit.

OPA177 V

2

3

1

8

Trim Range is approximately ±3.0mV

V+

20kΩ

OUTVIN

Op Amp

(a)

RB

OPA177

(b)

No bias currentcancellation resistor needed

Conventional op amp withexternal bias currentcancellation resistor.

OPA177 with no externalbias current cancellationresistor.

= R2 || R1

R2

R1

R2

R1

FIGURE 2. Input Bias Current Cancellation.

PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

OPA177FP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type OPA177FP

OPA177FPG4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type OPA177FP

OPA177GP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 OPA177GP

OPA177GPG4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 OPA177GP

OPA177GS ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR OPA177GS

OPA177GS/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR OPA177GS

OPA177GS/2K5E4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR OPA177GS

OPA177GS/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR OPA177GS

OPA177GSG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR OPA177GS

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Addendum-Page 2

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

OPA177GS/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

OPA177GS/2K5 SOIC D 8 2500 853.0 449.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 2

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

OPA177FP P PDIP 8 50 506 13.97 11230 4.32

OPA177FPG4 P PDIP 8 50 506 13.97 11230 4.32

OPA177GP P PDIP 8 50 506 13.97 11230 4.32

OPA177GPG4 P PDIP 8 50 506 13.97 11230 4.32

OPA177GS D SOIC 8 75 506.6 8 3940 4.32

OPA177GSG4 D SOIC 8 75 506.6 8 3940 4.32

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 3

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