Toward Automatic Synthesis of SOC

Test PlatformsWen-Cheng Huang, Chin-Yao Chang and Kuen-Jong Lee

Department of Electrical EngineeringNational Cheng Kung University, Tainan, Taiwan

Presenter : Shao-Chieh Hou

VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. 

Employing a test platform in an SOC design to execute test procedures can greatly simplify many SOC test problems. It, however, would require tremendous human efforts if the test platform would be generated manually. In this paper, we describe a design automation system, called DASTEP (Design Automation System for SOC Test Platform), that is aimed to help users build a test platform and incorporate their IP designs into the platform. DASTEP provides an interactive mode to allow users to modify individual IP cores into 1149.1- or 1500-compatible ones and integrate them into the test platform. For a hierarchical core, DASTEP can synthesize a hierarchical test control architecture such that each core in the hierarchy can be efficiently tested in a 1149.1-compatible manner. All of the test procedures using this test platform are carried out on the chip through the cooperation of an embedded processor that usually exists in an SOC design and a dedicated test-access-mechanism (TAM) controller that can be automatically generated. Appropriate simulation environment that allows the simulation of the entire test flow is also created in conjunction with the generation of the test hardware/software, hence the verification of both core design and test plan can be readily carried out. A friendly graphic user interface tool is also developed that can greatly simplify the generation and simulation of the test platform.

Abstract

With the increase complexity, many problems happened in SoC Design Manufacture bugs Test problems

。Too many pins。Too many registers

For effective debugging, a SW/HW base platform is needed Trace HW information, show with SW GUI

Automatic method is necessary

What’s the problem?

Related work

This Paper

SoC testing architectures

[1]-[3]

Software-base testing[4]-[6]

SOC test platform

concept[7]

Scan-base HW method[9]

Test platform Real case

My Related Work Tree

SW/HW Co-Debug

Bus Tracer Debug Platform

SW Debug HW Debug Platform Case

ARM CoreSight DASTEP

Embedded processor base test platform

Low cost test platform

This paper SW/HW Co-debug

platform

Test Platform Architecture1. Functionally test the

embedded processor.2. Built-in self-test or

functionally test (i.e., using a test program) the embedded memory

3. Functionally test design-for-testability components.

4. Load a block of test data from external memory to embedded memory.

5. Set up test status of the TAM controller.

6. Apply test data and perform core-level testing.

7. Verify test responses.8. Repeat Steps 4 to 7 until

all blocks of test data are processed.

TAM Controller

Break-Point Setup Controller

Generate 1149.1 control signal for scan

Calculated address and allows TAM controller to access memory

Send enable signal to core while TAM like a slave

For scan wrapper setup and output

SW/HW Co-Debug platform

ARM CoreSightTM

Design Automation tools(DASTEP)

HW

SW

HW SW

Graphic User Interface

The paper propose a automation system to help user build a test environment - DASTEP HW part

。TAMC。1500WRAPPER。TAPC

SW part 。Test program for each part in system

Conclusions

Automation is a important issue User just need click

Those papers give me some idea In GUI

。Function。Display

Steps to build a platform。We have

Tracer, open OCD, checker, wrapper-ICE, ICE…etc。We don’t have

Integrated GUI, platform controller, Mechanism

My Comment