primetime: introduction to static timing analysis … · primetime: introduction to static timing...

PrimeTime: Introduction to Static Timing Analysis Unit i: Welcomei-1

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WelcomePrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16

PrimeTime: Introduction to Static Timing Analysis Workshop

34000-000-S16

Synopsys Customer Education Services© 2002 Synopsys, Inc. All Rights Reserved


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First Things First

� Welcome and Introductions

� Materials you should have:� Student Guide� Lab Guide� PrimeTime Quick Reference� Synopsys Online Documentation (SOLD) CD

� Breaks

� Facilities


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Use PrimeTime to perform Static Timing Analysis (STA)

on a “Functional Core” prior to Place and Route (P&R).

Obtain the prerequisite knowledge to attend the

“PrimeTime: Chip Level STA” workshop.

Use PrimeTime to perform Static Timing Analysis (STA)

on a “Functional Core” prior to Place and Route (P&R).

Obtain the prerequisite knowledge to attend the

“PrimeTime: Chip Level STA” workshop.

Workshop Goal

A/D

Processor_CORE

USB RAMMPEG

CODECDSP

Functional Core Core Clock

Design Assumptions:1. STA is performed on the Functional core only; Block level STA has been done in DC. (See Flow

Diagram)2. No scan chains yet (Flow diagram in PT:Chip level STA workshop)3. Functional Core routing parasitic RCs (detailed SPEF) and sub block WLMs are available from

early design planning (Chip level floor plan) 4. No clock tree synthesis yet (Flow diagram in PT:Chip level STA workshop)5. Blocks may be either synthesized netlist or QTMs (will be covered if class time permits) 6. Functional Core has Logical hierarchical partitions (blocks)7. No I/O pads, no BSD, no clock generation logic yet (Definition of Functional Core)8. Chip specification is available (in Constraints modules)9. Multiple Synch/Asynch clocks (in Constraints modules)10. Multicycle paths (in Constraints modules)11. Hold Time analysis is performed using Worst case PVT (as opposed to Best case PVT) (in

Constraints modules)12. No case analysis (absence of scan chains); no functional modes (Flow diagram in PT:Chip level

STA workshop -- although it may apply to Functional CORE but is not discussed in this PT: ISTA)


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� Design or Verification engineers who perform STA at the “functional core” level

� Little or no formal experience with PrimeTime

� Little or no formal experience with Design Compiler

� Planning to take the “PrimeTime: Chip level STA” workshop

Workshop Target Audience

PrimeTime:ISTA

CHIP Synthesis(Design Compiler)

PrimeTime:CHIP Level

You are here

Design or Verification engineers who perform STA at the “functional core” level.In addition to block level STA, you will handle functional core integration.

Little or no formal experience with Design Compiler.If you have taken “CHIP Synthesis” or have experience using Design Compiler, do not attend this workshop: Take “PrimeTime: Chip Level STA”

If your expectation is to learn DC as you’re expanding your portfolio to include synthesis, you should take the CHIP Synthesis workshop next and then PrimeTime: Chip Level STA.

“PT:Chip Level STA Workshop” focuses on final, full chip, post route STA in order to achieve Timing closure.


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What is Functional Core on a CHIP?

� Functional CORE constitutes “most” of the CHIP containing: � Synthesized logic blocks (Gate level netlist) and Models (RAMs)� Functional core constraints are derived from Chip-level constraints� Functional core level parasitics are extracted

� Extraction is done after a CHIP level floorplan and global routing

MID

TOP

JTAG/BSDLogic

CLOCK-GENPLL FUNC_CORE

ASYNCHLOGIC

SynthesizedBlock3

SynthesizedBlock2

RAM (Timingmodel)

SynthesizedBlock1(wlm)

Parasitics are supplied in SPEF (Standard Parasitic Extraction Format).

At the full-chip level one must consider the following issues:

Model clock generation circuitryAnalyze latch-based versus flip-flop design stylesFunctional vs. Test modes (Case analysis)Analyze PVT corners

These issues are addressed in the “PrimeTime: Chip level STA” workshop.


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Read required files

Write Top-Levelconstraints and

exceptions

Errors/Warnings?Fix data

Place&Route

Generate STAReports

Fully synthesizedFunctional Core.

Chip-Level floorplanand constraints.

Functional core inter-block RC parasitics

extracted.

no

yes

Timingviolations

Design CompilerResynthesis

Functional Core Integration – Pre-Layout

Units 4-6

Unit 3

Units 1,8

After synthesis of all sub-blocks, perform Chip level floorplan, global routing and extract the parasitic RCs between blocks within the Functional core.QTMs (or Timing models) may be used for the blocks for which synthesized gate level netlist is not available.

Day-1: Objective: Using the basic 5 step STA flow, constrain all the Register to Register (Internal) timing paths within the functional core

Day-2: Objectives:Using the 5 step STA flow, constrain all the I/O (interface) timing paths within the functional core and apply the necessary single clock cycle timing exceptions


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PT Compatibility with other Tools

PrimeTime

Design Compiler Physical Compiler

CHIP Architect

3rd Party LayoutPathMill

Placed netlistMapped netlist(using WLM)

STAMP Parasitics, SDF


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What Will Be Covered

� Performing basic 5 step Static Timing Analysis (STA) flow on a functional core prior to P&R using PrimeTime GUI and shell (Units 1-3)

� Applying required constraints and exceptions and checking for missing constraints and ignored exceptions (Units 4-6)

� Creating a Quick Timing Model (Unit 7)

� Analyzing in detail for timing, design rules and timing bottlenecks (Unit 8)


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Workshop Prerequisites

� Understanding of digital IC design

� Familiarity with UNIX, X-Windows and Unix-based text editor


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Agenda: Day One

DAY1111 Register to Register Paths LabUnit

Reading Data3

Constraining Internal Reg-Reg Paths4

Writing Basic Tcl Constructs in PT 2

Introduction to Static Timing Analysis1

Welcome0i

Unit 1 Objective:

Is to introduce Static Timing Analysis in PrimeTime by: Defining the 2 steps performed by a Static Timing Analyzer; Understanding under the hood calculation of cell and net delays based on NLDM (Non-Linear Delay Model) and WLM (Wire Load Model); Listing 4 types of timing paths; Identifying the path with the WNS (worst negative slack) or longest delay using the report_timing command; Interpreting results of the report_delay_calculation command and for cell and net timing arcs and Finding specific topics in SOLD using key word search.Unit 2 Objective:

Is to find Tcl syntax errors using the Tcl Syntax checker, to fix these errors and to obtain command and variable syntax information.Unit 3 Objective:

Is to create a basic PT setup file, read all the required files for STA and resolve errors and warnings associated with reading the files.Unit 4 Objective:

Is to create a Tcl script, which fully constrains internal Register-to-Register paths by Applying clock constraints and design environmental attributes; Modeling multiple synchronous/asynchronous clocks, Modeling pre-layout non ideal clocks, Invoking appropriate report commands to verify the correctness of constraints and Invoking a report to verify the completeness of constraints.


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Agenda: Day Two

DAY2222 I/O Paths and Exceptions LabUnit

Introduction to Timing Models (QTM)7

8

Specifying Timing Exceptions6

Constraining I/O Interface Paths5

Summary9

Performing STA

Customer Support10

Unit 5 Objective:Is to create a Tcl script which fully constrains the Input/Output interface paths by applying port constraints and environmental attributes, modeling I/O data paths between multiple synchronous and asynchronous clock domains, modeling pre-layout non ideal clock effects, Invoking appropriate report commands to verify the correctness of constraints, Invoking a report to ensure the completeness of constraints and Identifying the effect of constraints on the path reported by a timing report.Unit 6 Objective:Is to Efficiently constrain a design for non-single-clock cycle behavior by Defining Timing exceptions, Modeling multi cycle path, Modeling logically false paths, Writing efficient constraints to model the above and Identifying any ignored exceptions and remove them.Unit 7 Objective:Is to Create a Quick Timing model using a given specification for use in PT by Defining what QTM is, Writing a QTM script to create a QTM library cell for the given specification and Modifying the link_path to use the QTM just created.Unit 8 Objective:Is to Apply three techniques in a systematic approach to analyze timing and design rule violations by Listing the 3 techniques in the appropriate order, Obtaining summary reports of all constraint violations and determining the next course of action, Identifying timing bottleneck blocks for re-synthesis. Enabling generation of Divide and conquer Timing reports to investigate what types of timing paths are causing violations (group_path) and Generating timing reports for setup check, hold check and showing the fanout, capacitance and transition time along the path.Unit 9 Objective:Is to list ways to improve the runtime and memory when using the STA flow in PT and summarize the workshop.Unit 10 Objective:Is to introduce you to our Customer Support Services.


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� In this class, what are the 2 types of blocks which you assume are contained within the floor-planned Functional Core?

__________________________________________

� In this class, how are the net parasitics (RC values) within Functional Core modeled prior to Place and Route?

Nets within a block __________________________Nets between blocks __________________________

� After attending this class, you will be able to perform Static Timing Analysis on: (Circle all that apply)

a. Block (Module) level design that is either a mapped netlist or a timing modelb. Functional CORE level design containing synthesized gate level blocksc. Functional CORE level design with some blocks described as an RTL

verilog/VHDL filed. CHIP level design that has been placed and routed (P&R)

Test For Understanding


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Abbreviations and Acronyms

AcronymAcronym MeaningMeaning AcronymAcronym MeaningMeaning

STASTA

DCDC

PTPT

GUIGUI

TclTcl

SOLDSOLD

QTMQTM

PVTPVT

WLMWLM

WNSWNS

SPEFSPEF

DRCDRC

NLDMNLDM

--


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Icons used in this workshop

Conventions used in this workshop

The Synopsys “Physical SynthesisHierarchical Design Flow”

Appendix


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Icons Used in This Workshop (1/2)

Lab Exercise

Recommendation

Group Exercise

Acronyms

For further reference


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Icons Used in This Workshop (2/2)

Question

Checklist Caution

Remember

Hint, Tip or Suggestion Note


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Conventions Used in this Workshop

Indicates a path to a menu command, such as opening the Edit menu and choosing Copy.

Edit > CopyIndicates levels of directory structure or design’s hierarchy./

Indicates a continuation of a command line.\

Indicates a keyboard combination, such as holding down the Control key and pressing c.

Control-c

Indicates a choice among alternatives, such as low | medium | high(This example indicates that you can enter one of three possible values for an option: low, medium, or high.)

|

Denotes optional parameters, such as pin1 [pin2 ... pinN][ ]

Indicates user input—text you type verbatim—in Synopsys syntax and examples. (User input that is not Synopsys syntax, such as a user name or password you enter in a GUI, is indicated by regular text font bold.)

Courier bold

Indicates a user-defined value in Synopsys.Courier italic

Indicates command syntax.Courier

DescriptionConvention


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The Synopsys Physical Synthesis Flow

STARTSTART

RTL and Chip

Constraints

RTL and Chip

Constraints

Design Planning

Design Implementation

Design Refinement and Chip Finishing

ENDEND

Develop a realizable floorplan for the chip and realistic design budgets for blocks

Create a placed design which passes STA. Perform an initial detail route of chip

ECO the P&R until it meets required performance specs for tapeout

Objectives

RTL (Register Transfer Level)

The Synopsys Physical Synthesis hierarchical design flow was created by the Synopsys Design Flow Group to help promote and ease the adoption of Synopsys design tools, as well as to provide feedback and drive enhancements of product performance and usability. The Synopsys Design Flow Group engages in customer partnerships from RTL to tapeout to drive success for multi-million gate designs.

The flow encourages top-level floorplanning, power planning and global routing early in the flow followed by successive refinement of data and design until timing closure (i.e. the Design Planning, Design Implementation, and Design Refinement phases).


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STARTSTART

RTL, Chip

constraints

RTL, Chip

constraints

Design Planning


Design

Refinementand Chip Finishing

ENDEND

RTL, chip constraints

compile datapath synthesis with scancompile datapath synthesis with scan

Die InitializationDie Initialization

IO Pad AssignmentIO Pad Assignment

Floor-planning,hierarchy manipulation

reshaping

Floor-planning,hierarchy manipulation

reshaping

Power AnalysisPower Analysis

Initial pin assignmentInitial pin assignment

Top-levelglobal routing andcongestion analysis

Top-levelglobal routing andcongestion analysis

Top-level repeater insertion

Top-level repeater insertion

Initial blocktiming budget

Initial blocktiming budget

MC,

ACS

CA

CA

CA

CA

CA

CA

FV

PP

A

JTAG insertionJTAG insertionBSDC

Power PlanningPower Planning

CA

Vera

RTL verificationObtain target RTL and toggle coverage

RTL verificationObtain target RTL and toggle coverage

CoverMeter VCS

ILM

ILM

ILM

New in 2.2

Top-level route estimationTop-level route estimation

FR

An Overview of Design Planning

VCS VCS Verilog SimulatorCA Chip ArchitectPP PrimePowerFR Flex RouteBSDC BSD Compiler, Boundary Scan SynthesisFV Formal Verification (FM Formality)MC Module CompilerACS Automatic Chip SynthesisILM Interface Logic Model


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An Overview of Design Implementation

STARTSTART

RTL, Chip

constraints

RTL, Chip

constraints

Design Planning

DesignImplementation

Chip Finishing and Design

RefinementENDEND

Block Level physical synthesis

Low Power Optimization

One Pass ScanPlacement

Block Level physical synthesis



ILM GenerationILM Generation

RC-correlation

Blocklevel IPO

RC-correlation

Blocklevel IPO

Block LevelRC ExtractionBlock LevelRC Extraction

Full Chip STA Placement handoff

Full Chip STA Placement handoff

Block Level CTSBlock Level CTS

Block Level Detail RoutingBlock Level Detail Routing

Block Level STA and

ILM creationBlock Level

STA andILM creation

Chip Integration Chip Integration

Top Level CTSTop Level CTS

Top Level Detail RouteTop Level Detail Route

PC

PT

PC

PC

CA

CTC

FV

FV

timing OK ?

Top Level physical synthesis



Top Level physical synthesis



PC

FV

timing OK yes no

Arcadia

noyes

PT

ATPG

ECORoute

ECORoute

A

FV

DetailRouter Detail

Router

CTC, STAMP

ILM

ILM

DetailRouter

New in 2.2

ILM

PT

CTS Clock Tree SynthesisECO Engineering Change OrderPC Physical CompilerCTC ClockTree CompilerATPG Automatic Test Pattern GenerationIPO In-Place Optimization


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An Overview of Design Refinement

STARTSTART

RTL, Chip

constraints

RTL, Chip

constraints

Design Planning


Design

Refinement andChip Finishing

ENDEND

Top Level ExtractionTop Level Extraction

Full Chip STAFull Chip STAILM GenerationILM Generation

Blocks/Top RC ExtractionBlocks/Top RC Extraction

Block Level ECO RouteBlock Level ECO Route

Full Chip STAFull Chip STA

Block level IPO, hold fixBlock level IPO, hold fix

Top level IPO, hold fixTop level IPO, hold fix

CaptureBlock LevelConstraints

CaptureBlock LevelConstraints

DRCDRC

Chip FinishingChip Finishing

Arcadia

PTPT

Arcadia

PT

DetailRouter

Final Power Analysis Final Power Analysis

Top Level ECO RouteTop Level ECO Route

timing OK

PT

timing OKyes no

yes

PP

PC GDSII MergeGDSII Merge

DetailRouter

SLE

Crosstalk AnalysisCrosstalk Analysis

PT-SI

Crosstalk RepairCrosstalk Repair

ILM

ILM

ILM

PC

Calibre

New in 2.2

LVSLVSCalibre

SLE

DetailRouter

SLE Synopsys Layout EditorLVS Layout vs. SchematicDRC Design Rule CheckerGDSII Graphics Design Standard Format II

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