6868405 static timing analysis

8/3/2019 6868405 Static Timing Analysis

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1

STATIC

TIMING

ANALYSIS

STATIC

TIMING

ANALYSIS


2/71

2

Introduc

tion

Introduc

tion

Effectivemethodology

forverifyingthetim

ingcharacteristicsofadesign

Effectivemethodology

forverifyingthetim

ingcharacteristicsofadesign

withouttheuseoftest

vectors

withouttheuseoftest

vectors

Co

nventionalverificationtechniquesareinadequateforcomp

lex

Co

nventionalverificationtechniquesareinadequateforcomp

lex

de

signs

designs

Simulationtimeus

ingconventionalsimulators

Simulationtimeus

ingconventionalsimulators

Thousandsof

testvectorsarereq

uiredtotestalltimingpaths

Thousandsof

testvectorsarereq

uiredtotestalltimingpaths

usinglogicsim

ulation

usinglogicsim

ulation

Increasingdesign

complexity&smallerprocesstechnolo

gies

Increasingdesign

complexity&smallerprocesstechnolo

gies

Increasesthe

numberofiterationsforSTA

Increasesthe

numberofiterationsforSTA


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3

Simulat

ionvs.S

tatictim

ing

Simulat

ionvs.S

tatictim

ing

0%0%

100%

100%

TimingSimulation

(a

ddingvectors)

Statictimin

ganalysis

(eliminatingfalsepaths)

Truetimingpaths

Truetimingpaths

Falsetimingpaths

Falsetimingpaths

STAapproachtypicallytak

esafractionofthe

timeittakestorun

logicsimulationonalarge

designandguarantees100%coverage

ofalltr

uetimingpathsinthedesignwithouthavingtogeneratete

st

vectors


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OVERVIEW

OVERVIEW

Pr

eviousVerific

ationFlow


5/71

5

Requiresextensivevectorcreation

ValidforFPGAsand

smallerASICs

Fallsa

partonmulti-m

illiongateASICs

OVERVIEW

OVERVIEW


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6

Wh

atisSta

ticTimin

gAnaly

sis?

StaticTimingAnalysisisameth

odfordeterminingifa

cir

cuitmeetstimingconstraints

withouthaving

to

sim

ulate

Muchfastertha

ntiming-driven,gate-levelsimulation

Propercircuitfunctionalityisn

otchecked

VectorgenerationNOTrequir

ed


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7

S

TAinASICDesignFlow

Pre

S

TAinAS

ICDesignFlow

Pre

layou

t

layou

tL

ogicSynthesis

DesignFortest

Floorplanning

Constraints

(clocks,inputdrive,

outputload)

StaticTimingAnalysis


(esti

matedparasitics)


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STAin

ASICDe

signFlo

w

STAinASICDe

signFlo

w

PostLayout

PostLayout

Floorplanning

ClockTreeSynthesis

P

laceandRoute

Pa

rasiticExtraction

SDF

(e

xtractedparasitics)

Constraints

(clocks,inputdrive,

outputload)


(estimatedparasitics)


(extractedparasitics)


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9

2

Typeso

fTiming

Verifica

tion

DynamicTim

ingSimulatio

n

Advantages

Canbevery

accurate(spice-level)

Disadvantag

es

Analysisqualitydependso

nstimulusvec

tors

Non-exhaus

tive,slow

Examples:

VCS,Spice,ACE


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StaticTimingAna

lysis(STA)

Advantages

Fast,exhaustive

Be

tteranalysisch

ecksagainsttimingrequirem

ents

Disa

dvantage

Lessaccurate

Mu

stdefinetimingrequirements

/exceptions

Dif

ficultyhandling

asynchronousdesigns,false

paths

2T

ypesof

TimingVerificat

ion


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Thre

eSteps

inStatic

Timing

Analysis

Circuitisbrokendownintosetsoftimingpaths

Delayofeach

pathiscalcula

ted

Pathdelaysarecheckedtoseeiftimingco

nstraints

havebeenme

t


12/71


13/71

13

OrganizingT

imingPathsInto

Groups

Timingpathsare

groupedintopathgroupsby

the

clockscontrollingtheirendpoin

ts

Synthesistools

likePrimeTim

eandDesign

Compilerorgan

izetimingrep

ortsbypathgroups


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14

N

etandC

ellTimingArcs

Theactualpa

thdelayisthe

sumofnetandcell

delaysalongthetimingpath


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15

Ne

tandCe

llDelay

NetD

elayrefersto

thetotaltimeneededtochargeor

dischargeallofthep

arasiticsofag

ivennet

Tota

lnetparasiticsareaffectedb

y

netlength

netfanout

Net

delayandparasiticsaretypic

ally

Back-Annotated(Post-Layout)fromdataobtainedfrom

anextractionto

ol

Estimated(Pre-Layout)


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CellDelay

InASICs,thedelayofa

cellisaffected

by:

The

inputtransitiontime(orslew

rate)

The

totalloadsee

nbytheoutputtransistors

Netcapa

citanceanddownstreampin

capacitances

The

sewillaffecthowquicklytheinputandoutputtransistors

cans

witch

Inhe

renttransistor

delaysandinternalnetdela

ys


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Tr

ansparentLatch,L

evelSensitive

datapassesthroughwhenclockhigh,latchedwhenclocklow

ClockedStorageElements

D-TypeRegisterorFlip-Flop,Edge-Trig

gered

d

atacapturedonrisingedgeofclock

,heldforrestofcycle


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Flip-Flop

s


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19

Bas

icterminologies

Bas

ictermin

ologies

PulseWidth

PulseWidth

Se

tup&Holdtimes

Se

tup&Holdtimes

Si

gnalslew

Signalslew

Clocklatency

Clocklatency

ClockSkew

ClockSkew

In

putarrivaltime

In

putarrivaltime

Outputrequiredtim

e

Outputrequiredtim

e

Sl

ackandCriticalp

ath

SlackandCriticalpath

R

ecovery&Rem

ovalti

R

ecovery&Rem

ovaltim

F

alsepaths

F

alsepaths

M

ulti-cyclepath

s

M

ulti-cyclepath

s


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PulseW

idth

PulseW

idth

Pu

lsewidth

Pu

lsewidth

Itisthetimebetweentheactiveandinactivestatesofthe

same

Itisthetimebetweentheactiveandinactivestatesofthe

same

signal

signal


21/71

21

Setu

pandH

oldtime

Setu

pandH

oldtime

Setuptime

Setuptime

Foranedgetriggeredsequentialelem

ent,thesetuptimeisthetime

Foranedgetriggeredsequentialelement,thesetuptimeisthetime

intervalbeforethe

activeclockedgeduringwhichthedata

should

intervalbeforetheactiveclockedgeduringwhichthedata

should

remainunchanged

remainunchanged

Holdtime

Holdtime

Timeintervalafter

theactiveclockedg

eduringwhichthedata

Timeintervalaftertheactiveclockedg

eduringwhichthedata

shouldremainunchanged

shouldremainunchanged

Boththeabove

2timingviolationscanoccurinadesig

nwhen

Boththeabove

2timingviolationsc

anoccurinadesig

nwhen

clockpathdelay>datapathdelay

clockpathdelay>datapathdelay


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SignalS

lew

SignalS

lew

Signal(Clock/Data)slew

Signal(Clock/Data)slew

Amountoftimeittakesforasignaltra

nsitiontooccur

Amountoftimeittakesforasignaltra

nsitiontooccur

Accountsforunce

rtaintyinRiseandf

alltimesofthesignal

Accountsforunce

rtaintyinRiseandfalltimesofthesignal

Slewrateismeasuredinvolts/sec

Slewrateismeasuredinvolts/sec


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C

lockLatency

C

lockLatency

ClockLatency

ClockLatency

Differencebetwee

nthereference(source)clockslewtotheclock

Differencebetwee

nthereference(source)clockslewtot

heclock

treeendpointsign

alslewvalues

treeendpointsignalslewvalues

Riselatencyandfalllatencyarespecified

Riselatencyandfalllatencyarespecified

INV

Rise=7

Rise=7

Fall=4

Fall=4

Rise=7

Rise=7

Fall=4

Fall=4

Rise=7

Rise=7

Fall=4

Fall=4

R

ise=7

R

ise=7

Fall=4

Fall=4

R

ise=7

R

ise=7

F

all=4

F

all=4

Rise=7

Rise=7

Fall=4

Fall=4

R

ise=7

R

ise=7

F

all=4

F

all=4

CLK

CLK

CLKA

CLKA

CLKB

CLKB

CLKC

CLKC

INVINV

INVINV

INVINV

INVINV

INVINV

BUF

BUF

BUF

BUF


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C

lockLatency

C

lockLatency


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ClockS

kew

ClockS

kew

ClockSkewisameas

ureofthedifferenceinlatencybetween

anytwo

ClockSkewisameas

ureofthedifferenceinlatencybetween

anytwo

lea

fpinsinaclocktree.

lea

fpinsinaclocktree.

betweenCLKAan

dCLKB

betweenCLKAan

dCLKB

rise=2

2-8=14

rise=2

2-8=14

fall=22-14=8

fall=22-14=8

betweenCLKBan

dCLKC

betweenCLKBan

dCLKC

rise=

8-7=1

rise=

8-7=1

fall=14-4=10

fall=14-4=10

betweenCLKAan

dCLKC

betweenCLKAan

dCLKC

rise=2

2-7=15

rise=2

2-7=15

fall=22-4=18

fall=22-4=18

It

isalsodefinedasthedifferenceintimethatasingleclock

signal

It

isalsodefinedasthedifferenceintime

thatasingleclock

signal

takestoreachtwo

differentregisters

takestoreachtwo

differentregisters


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InputArriv

altime

InputArriv

altime

Inp

utArrivaltime

Inp

utArrivaltime

Anarrivaltimedefinesthetimeintervalduringwhichada

tasignal

Anarrivaltimedefinesthetimeintervalduringwhichada

tasignal

canarriveatanin

putpininrelationto

thenearestedgeo

ftheclock

canarriveataninputpininrelationto

thenearestedgeo

ftheclock

signalthattriggers

thedatatransition

signalthattriggers

thedatatransition


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Outputrequ

iredtime

Outputrequ

iredtime

Ou

tputrequiredtime

Ou

tputrequiredtime

Specifiesthedata

requiredtimeonou

tputports.

Specifiesthedata

requiredtimeonou

tputports.


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Slack

andCriticalpat

h

Slack

andCriticalpath

Slack

Slack

Itisthedifference

betweentherequired(constraint)time

andthe

Itisthedifference

betweentherequired(constraint)time

andthe

arrivaltime(inputs

anddelays).

arrivaltime(inputs

anddelays).

Negativeslackind

icatesthatconstraintshavenotbeenm

et,while

Negativeslackind

icatesthatconstraintshavenotbeenm

et,while

positiveslackindicatesthatconstraintshavebeenmet.

positiveslackindicatesthatconstraintshavebeenmet.

Slackanalysisisu

sedtoidentifytimin

gcriticalpathsina

designby

Slackanalysisisu

sedtoidentifytimin

gcriticalpathsina

designby

thestatictiminganalysistool

thestatictiminganalysistool

Criticalpath

Criticalpath

Anylogicalpathin

thedesignthatviolatesthetimingconstraints

Anylogicalpathin

thedesignthatviolatesthetimingconstraints

Pathwithanegativeslack

Pathwithanegativeslack


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SlackA

nalysis

DataP

ath

SlackA

nalysisDataP

ath

types

types


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Slackanalysis

datap

ath

Slackanalysis

datap

ath

type

s

type

s

Primaryinput-to-registerpaths

Primaryinput-to-registerpaths

Delaysoff-chip+Combinationallogic

delaysuptothefirst

Delaysoff-chip+Combinationallogic

delaysuptothefirs

t

sequentialdevice.

sequentialdevice.

Re

gister-to-primaryou

tputpaths

Re

gister-to-primaryou

tputpaths

Startatasequentialdevice

Startatasequentialdevice

CLK-to-Qtransitio

ndelay+thecombinationallogicdelay

+external

CLK-to-Qtransitio

ndelay+thecombinationallogicdelay

+external

delayrequirements

delayrequirement

s

Re

gister-to-registerpa

ths

Re

gister-to-registerpa

ths

Delayandtimingconstraint(Setupan

dHold)timesbetween

Delayandtimingc

onstraint(Setupan

dHold)timesbetwe

en

sequentialdevicesforsynchronousclocks+sourceanddestination

sequentialdevices

forsynchronousclocks+sourceanddestination

clockpropagation

times.

clockpropagation

times.

Primaryinput-to-prima

ryoutputpaths

Primaryinput-to-prima

ryoutputpaths

Delaysoff-chip+combinationallogicdelays+externaldelay

Delaysoff-chip+combinationallogicdelays+externalde

lay

requirements.

requirements.


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Hold

Slackcalculation

Hold

Slackca

lculation

Ac

tualdataarrivaltimedefinition

Ac


D

ataInputArrivalTim

emin+Datapathdelaymin

D

ataInputArrivalTim

emin+Datapathdelaymin

Ifthedatapathstartsinaprimaryin

put,

Ifthedatapaths

tartsinaprimaryin

put,

DataInputa

rrivalmin=Inputarrivaltimemin

DataInputa

rrivalmin=Inputarrivaltimemin

Ifthedatapathstartsataregister,

Ifthedatapaths

tartsataregister,

(SourceClo

ckEdgemin+SourceClockPathDelaymin)=

(SourceClo

ckEdgemin+SourceClockPathDelaymin)=

DataInpu

tArrivalmin

DataInpu

tArrivalmin

Re

quiredStabilitytime

definition

Re

quiredStabilitytime

definition

(D

estinationClockEdgemax+DestinationClockPathDelaymax)+

(D

estinationClockEdgemax+DestinationClockPathDelaymax)+

Hold=RequiredS

tabilityTimemax

Hold=RequiredS

tabilityTimemax

Ho

ldSlackdefinition

Ho

ldSlackdefinition

A

ctualDataArrivalmin-RequiredStabilityTimemax

A

ctualDataArrivalmin-RequiredStabilityTimemax


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Calculatetheholdslac

k

Calculatetheh

oldslac

k

Source

Clocksignaltiming

parameters:

MinEd

ge=8.002ns

Minclo

ckpathdelay=0.0

02ns

DestinationClocksignaltimingparameters:

MaxEdge=2.020ns

Maxclockpathdelay=0.5

00ns

MinDatapathdelay=

0.802ns

Ho

ldtimeconstraint=

1.046ns


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Hold

slackca

lculation

Hold

slackca

lculation


34/71

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Setup

Slackc

alculatio

n

Setup

Slackc

alculatio

n

Ac


Ac


D

ataInputArrivalTim

emax+Datapath

delaymax

D

ataInputArrivalTim

emax+Datapath

delaymax

Ifthedatapathstartsinaprimaryin

put,

Ifthedatapaths

tartsinaprimaryin

put,

DataInputa

rrivalmax=Inputarrivaltimemax

DataInputa

rrivalmax=Inputarrivaltimemax

Ifthedatapathstartsataregister,

Ifthedatapaths

tartsataregister,

(SourceClo

ckEdgemax+SourceClockPathDela

ymax)=

(SourceClo

ckEdgemax+SourceClockPathDela

ymax)=

DataInpu

tArrivalmax

DataInpu

tArrivalmax

Re

quiredStabilitytime

definition

Re

quiredStabilitytime

definition

(D

estinationClockEdgemin+Destinatio

nClockPathDelay

min)-

(D

estinationClockEdgemin+Destinatio

nClockPathDelaymin)-

Setup=Required

StabilityTimemin

Setup=Required

StabilityTimemin

Se

tupslackdefinition

Se

tupslackdefinition

R

equiredStabilityTim

emin-ActualData

Arrivalmax

R

equiredStabilityTim

emin-ActualData

Arrivalmax


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Calcul

atethes

etupsla

ck

Calculatethes

etupsla

ck

Source

Clocksignaltiming

parameters:

MaxEdge=2.002ns

Maxclockpathdelay=0.0

02ns

DestinationClocksignaltimingparameters:

MinEd

ge=20.02ns

Minclo

ckpathdelay=0.5

00ns

MinDatapathdelay=

13.002ns

Setuptimeconstraint=0.046ns


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Setup

slackcalculatio

n

Setup

slackcalculatio

n


37/71

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Recove

ryandR

emoval

time

Recove

ryandR

emoval

time

Re

coverytime

Re

coverytime

Likesetuptimeforasynchronousport(set,reset)

Likesetuptimeforasynchronousport(set,reset)

Re

movaltime

Re

movaltime

Likeholdtimeforasynchronousport(set,reset)

Likeholdtimeforasy

nchronousport(set,reset)

Re

coverytime

Re

coverytime

It

isthetimeavailablebetweentheasynchronoussignalgoinginactive

It

isthetimeavailablebetweentheasynchronoussignalgoinginactive

totheactiveclock

edge

totheactiveclock

edge

Re

movaltime

Re

movaltime

It

isthetimebetween

activeclockedgeandasynchronouss

ignal

It

isthetimebetween

activeclockedgeandasynchronouss

ignal

goinginactive

goinginactive


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FalsePaths

FalsePaths

Fa

lsepaths

Fa

lsepaths

Pathsthatphysica

llyexistinadesign

butarenotlogic/functional

Pathsthatphysica

llyexistinadesign

butarenotlogic/functional

paths

paths

Thesepathsneve

rgetsensitizedund

eranyinputconditions

Thesepathsnevergetsensitizedund

eranyinputconditions

Mux1

C

C1

C2

AB

Mux2

S

B1

B2

OUT


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Multi-cycle

paths

Mu

lti-cycle

paths

Mu

lti-cyclepaths

Mu

lti-cyclepaths

DataPathsthatre

quiremorethanoneclockperiodforexecution

DataPathsthatre

quiremorethanoneclockperiodforex

ecution

2clockperio

ddelay


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Sequen

tialCirc

uitTiming

Sequen

tialCirc

uitTimin

g

Objectiv

es

Objectives

Thissectioncoversseveraltimingconsidera

tionsencounteredinthedesign

Thiss

ectioncoversseveraltimingconsiderationsencounteredinthedesign

ofsyn

chronoussequentialcircuits.Ithasthe

followingobjectives:

ofsyn

chronoussequentialcircuits.Ithasthe

followingobjectives:

Definethefollowingg

lobaltimingparame

tersandshowhow

theycanbe

Definethefollowingglobaltimingparame

tersandshowhow

theycanbe

de

rivedfromthebasictimingparameters

offlip-flopsandgates.

de

rivedfromthebasictimingparameters

offlip-flopsandgates.

MaximumClockFrequency

MaximumClockFrequency

Maximumallowableclockskew

Maximumallowableclockskew

GlobalSetupand

HoldTimes

GlobalSetupand

HoldTimes

Discusswaystocontroltheloadingofdataintoregistersand

showwhy

Discusswaystocontr

oltheloadingofdataintoregistersand

showwhy

ga

tingtheclocksigna

ltodothisisapoordesignpractice.

ga

tingtheclocksigna

ltodothisisapoordesignpractice.


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MaximumClock

Frequency

Maximu

mClock

Frequency

Theclockfrequencyforasynchronoussequentialcircuitislimitedby

Theclockfrequencyforasynchronoussequentialcircuitislimitedby

th

etimingparametersofitsflip-flopsand

gates.Thislimitiscalled

th

etimingparametersofitsflip-flopsand

gates.Thislimitiscalledthethe

maximumclockfrequency

maximumclockfrequencyforthecircuit.

The

forthecircuit.

Theminimumclock

period

minimumclock

periodisis

th

ereciprocalofthisfrequency.

th

ereciprocalofthisfrequency.

Relevanttimingparameters

Relevanttimingparameters

Gates:

Gates:

Propagationdelays:mint

Propagationdelays:mintPLH

PLH,min

t

,min

tPHLPHL,maxt

,maxtPLH

PLH,max

t

,max

tPHL

PHL

Flip-Flops:

Flip-Flops:

Propagationdelays:mint

Propagationdelays:mintPLH

PLH,min

t

,min

tPHLPHL,maxt

,maxtPLH

PLH,max

t

,max

tPHL

PHL

Setuptime:t

Setuptime:tsusu

Holdtime:t

Holdtime:thh


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Example

Example

TWmaxtPFF+tsu

Forthe7474,

maxtPLH=25ns,ma

xtPHL=40ns,tsu=20ns

TWmax

(maxtPLH+tsu,max

tPHL+tsu)

TWmax

(25+20,40+20)=6

0

D

QQ

CK

Q


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Example

Example

D

Q

CK

Q

TW

maxtPFF+maxtPINV

+tsu


44/71

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Example

Example

D

QQ

D

QQ

MUX

01

Q0

Q1

CK

TWm

axtPFF+maxtPMUX+tsu


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Example

Example

PathsfromQ1toQ1:

PathsfromQ1toQ2:

PathsfromQ2toQ1:

PathsfromQ2toQ2:

N

one

TWmaxtPDFF+tJKsu=

20+10=30ns

TWmaxtPDFF+max

tAND+tJKsu=20+12+10=42ns

TWmaxtPJKFF+tOR+

TDsu=25+10+5=

40ns

TWmaxtPJKFF+max

tAND+tJKsu=25+12

+10=47ns

TW47ns


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Ifaclockedgedoesnotarriveatdiffe

rentflip-flopsatexa

ctlythesame

Ifaclockedgedoesnotarriveatdiffe

rentflip-flopsatexa

ctlythesame

time,thenthecloc

kissaidtobe

time,thenthecloc

kissaidtobeskew

ed

skew

edbetweentheseflip-flops.The

betweentheseflip-flops.The

differencebetweenthetimesofarriva

lattheflip-flopsissaidtobethe

differencebetweenthetimesofarriva

lattheflip-flopsissaidtobethe

amountof

amountofclocksk

ew

clocksk

ew..

Clockskewisdue

todifferentdelaysondifferentpathsfromtheclock

Clockskewisdue

todifferentdelaysondifferentpathsfromtheclock

generatortothevariousflip-flops.

generatortothevariousflip-flops.

Differentlengthwires(wireshave

delay)

Differentlengthwires(wireshave

delay)

Gates(buffers

)onthepaths

Gates(buffers

)onthepaths

Flip-Flopsthatclockondifferente

dges(needtoinvertclockfor

Flip-Flopsthatclockondifferente

dges(needtoinvertclockfor

someflip-flops)

someflip-flops

)

Gatingtheclocktocontrolloading

ofregisters(avery

badidea)

Gatingtheclocktocontrolloading

ofregisters(avery

badidea)

ClockSkew

ClockSkew


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Example(Effectofclockskewonclockrate

)

Example(Effectofclock

skewonclockrate

)

ClockC2skewedafterC1


Q1

Q2

D

QQ

DQQ

CK

C1

C2 D2

TW

maxT

PFF+maxtOR

+tsu

(ifclocknotskewed,i.e.,tINV=0)

TWm

axT

PFF+maxtOR+

tsu-mintINV

(ifcloc

kskewed,i.e.,tINV>

0)


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Q1

Q2

D

QQ

D

QQ

CK

C1

C2

D2

TWmaxT

PFF+maxtOR+tsu

(ifclo

cknotskewed,i.e.,

tINV=0)

TWmaxT

PFF+maxtOR

+tsu+maxtINV

(ifclo

ckskewed,i.e.,tINV>0)


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49

Sum

maryofmaximumclockfrequencycalc

ulations

Sum

maryofmaximumclockfrequencycalc

ulations

D

Q

Logic

Network

D

Q

C1

C2

Q1

D2

C1

Q1

D2

C2

TW

tPFF

tOR

tsu

tSK=tINV

C1

Q1

D2

C2

TW

tPFF

tOR

tsu

tSK=tINV

C2skewedafterC1:T

WmaxT

PFF

+maxtNET+tsu-m

intINV

C2skewedbeforeC1:T

WmaxT

P

FF+maxtNET+tsu+

maxtINV


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50

M

aximum

AllowableClockSkew

M

aximum

Allowab

leClockSkew

Howmuchskewbetw

eenC1andC2can

betoleratedinthe

following

Howmuchskewbetw

eenC1andC2can

betoleratedinthe

following

circuit?

circuit?

Case1:C2delay

edafterC1

Case1:C2delay

edafterC1

D

QQ

D

QQ

C2

Q1

D2

C

1

tPFF>th+

tSK

tSK


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51

Case2:C1delayed

fromC2

Case2:C1delayed

fromC2

D

QQ

D

QQ

C2

Q1

D2

C1


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52

How

doesadditionaldelaybetweentheflip-flopsaffecttheskew

How

doesadditionaldelaybetweentheflip-flopsaffecttheskew

calc

ulations?

calc

ulations?

tSKmintPFF-th

tskmintPFF+m

intMUX-th


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53

Sum

maryofallowableclockskewcalculations

Sum

maryofallowableclockskewcalculations

tSK+thtPFF+tNET

tSKmintPFF+mintNET-th


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54

Example:Whatisthem

inimumclockperiodforthefollowingcircuitunder

Example:Whatisthem

inimumclockperiod

forthefollowingcircuitunder

theassumptionthatthe

clockC2isskewed

afterC1(i.e.,C2is

delayed

theassumptionthatthe

clockC2isskewed

afterC1(i.e.,C2is

delayed

from

C1)?

from

C1)?

N1

N2

C1

C2

Q1

D

2

Q2

D1

D

QQ

D

QQ


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55

Firstcalculatethem

aximumallowableclockskew.

Firstcalculatethem

aximumallowablec

lockskew.

Nextcalculatethem

inimumclockperiodduetothepathfromQ1toD2.

Nextcalculatethem

inimumclockperiodduetothepathfro

mQ1toD2.

Finallycalculatethe

minimumclockper

iodduetothepathfromQ2to

Finallycalculatethe

minimumclockperiodduetothepathfromQ2to

D1D1

N1

N2

C1

C2

Q1

D2

Q2

D1

D

QQ

D

QQ

tSKmaxtPFF+

maxtN1+tsu-mintSK

TW>maxtPFF+

maxtN1+tsu+maxtSK

TW>maxtPFF+

maxtN2+tsu+(min

tPFF+mintN1-th)

TW>maxtPFF+

mintPFF+maxtN2+

mintN1+tsu-th


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56

GlobalS

etupTim

e,Hold

Time

GlobalS

etupTim

e,Hold

Time

andPropag

ationDelay

andPropag

ationDelay

Globalsetupandholdtimes(datadela

yed)

Globalsetupandholdtimes(datadela

yed)

TSU=tsu+m

axtNET

TH

=th-mintNET

D

QQ

X

CK

NET

D

CLK


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57

Glob

alsetup&holdtime(clockdelayed)

Glob

alsetup&holdtime(clockdelayed)

D

QQ

CK

D

CLK

TSU=tsu-m

intC

TH=

th+maxtC


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58

Glob

alsetup&holdtime(data&clockdela

yed)

Glob

alsetup&holdtime(data&clockdela

yed)

D

QQ

X

CK

NET

D

CLK

TSU=

+max=-098765

4321\-min.

TH=th-mintNET+maxtC


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59

Glob

alpropagationdela

y

Glob

alpropagationdela

y

D

QQ

CK

NET

CLK

Y

Q

TP=tC+tFF+tNET


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60

Sum

maryofglobaltimin

gparameters

Sum

maryofglobaltimin

gparameters

TSU=tsu+maxtPN-min

tPCtsu+maxtPN

TH=

th+maxtPC-mintPN

th+maxtPC

TP=

tPFF+tPN+tPC


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61

Example

Example

FindT

FindT

SUSUandT

andT

HHforinputsignalLDrelativetoCLK.

forinputsignalLDrelativetoCLK.

LDD

CLK

C

K

Q

D

QQ

TSU=tsu+max

tNET-mintC

TH=th-mintNET

+maxtC

=tsu+maxtINV+maxtNAND+m

axtNAND-mintINV

=th-mintNAND-mintNAND+maxTIN

V


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62

Registerload

control

(gating

thecloc

egisterload

control

(gatingthecloc

Ave

rybadwaytoadda

loadcontrolsignalLDtoaregistertha

tdoesnot

Ave

rybadwaytoadda

loadcontrolsignalLDtoaregistertha

tdoesnot

have

oneisshownbelow

have

oneisshownbelow

The

reasonthisissuch

abadideaisillustratedbythefollowing

timing

The

reasonthisissuch

abadideaisillustra

tedbythefollowing

timing

diag

ram.

diagram.

The

flip-flopseestworisingedgesandwilltriggertwice.Theonlyonewe

The

flip-flopseestworisingedgesandwilltriggertwice.Theonlyonewe

wantisthesecondone.

wantisthesecondone.

D

L

D

CLK

CK

D

QQ


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63

IfLD

wasconstrainedto

onlychangewhen

theclockwaslow,thentheonly

IfLD

wasconstrainedto

onlychangewhen

theclockwaslow,thentheonly

prob

lemwouldbetheclockskew.

prob

lemwouldbetheclockskew.


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64

Ifga

tingtheclockisthe

onlywaytocontroltheloadingofregis

ters,thenuse

Ifga

tingtheclockisthe

onlywaytocontroltheloadingofregisters,thenuse

thefollowingapproach:

thefollowingapproach:

Thereisstillclockskew,butatleastwe

onlyhaveonetrigg

eringedge.

Thereisstillclockskew,butatleastwe

onlyhaveonetrigg

eringedge.

DLD CLK

D

QQ


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65

Theb

estwaytoaddaLD

controlsignalisasfollows:

Theb

estwaytoaddaLD

controlsignalisas

follows:

LDD

CLK

D

QQ


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66

Tips&T

ricks

Tips&T

ricks

Usetimingdiagramstodeterminethetiming

propertiesofsequentialcircuits

Usingtypicaltimingvaluesfromthedatasheet(useonlymaxa

nd/ormin

value

s)

Gatin

gtheclock


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67

Detectin

gtiming

violatio

ns

Detectin

gtiming

violatio

ns

CASE

1

CASE

1

clk10Mhtz

clk10Mhtz

clk20Mht

zref

clk20Mht

zref

Delay(min)=5ns

Delay(min)=5ns

DFF2

DFF2

DFF1

DFF1

DataData

(a)Holdtimeforcloc

ksis1.5ns

Determineifthereare

anytimingviolation

sinthisdesign

De

termineifthereare

anytimingviolation

sinthisdesign


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68

Detectin

gtiming

violatio

ns

Detectin

gtiming

violatio

ns

CASE

2

CASE

2

Delay(min)=5ns

Delay(min)=5ns

clk10Mhtz

clk10Mhtz

clk20Mht

zref

clk20Mht

zref

DFF2

DFF2

DFF1

DFF1

DataData

(a)Holdtimeforcloc

ksis1.5ns

(b)Clockskewof3.7

2nsbetweenclk20

mrefandclk10mz

Determineifthereare

anytimingviolation

sinthisdesign

De

termineifthereare

anytimingviolation

sinthisdesign


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69

Detectin

gtiming

violatio

ns

Detectin

gtiming

violatio

ns

CASE

3

CASE

3

(a)Holdtimeforclocksis

1.5ns

(b)Clockskewof3.72ns

betweenclk20mrefandclk10mz

clk10Mhtz

clk10Mhtz

clk20Mht

zref

clk20Mht

zref

DFF2

DFF2

DFF1

DFF1

DataData

Delay(min)=5ns

Delay(min)=5ns


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70

Detectin

gtiming

violatio

ns

Detectin

gtiming

violatio

ns

CASE

4

CASE

4

Cons

ider

(b)C

lockskewof3.72nsbetweenclk20mr

efandclk10mz

(c)C

locknetworkdelay

s

clk10Mhtz

clk10Mhtz

clk20Mhtzref

clk20Mhtzref

DFF2

DFF2

DFF1

DFF1

Data

Data

D

elay(min)=5ns

D

elay(min)=5ns

Prop

agationdelay=2ns

Prop

agationdelay=2ns

(thru

clocktreebuffers)

(thru

clocktreebuffers)

Propaga

tiondelay=4ns

Propaga

tiondelay=4ns

(thruclocktreebuffers)

(thruclocktreebuffers)


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Thank

you

Thank

you

6868405 static timing analysis

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