smiPROCEEDINGS

ofThe Technical Program

San Jose, CA'August 23-27, 1998San Jose Convention Center

UB/TIB Hannover115 243 755

89

TABLE OF CONTENTS

BGA TECHNOLOGYV ' • • • — • • ' — — — — — ^ — - - • - 'I

Track Organizers: Mike Petrucci, Compaq Computer;Andrew Mawer, Motorola Semiconductor Products Sector

Technical Session BGA1: BGA Package AdvancementsChair: Paul Hoffman, Amkor TechnologyCo-Chair: Keith Newman, Sun Microsystems

Assembly Process Development of Laminate Flip Chip BGA Package 1Kumar Nagarajan, Lan Hoang, KishorDesai and Sunil Patel, LSI Logic Corporation

Design & Process Optimization for 1.0mm Pitch CCGA 7Marie Cole, Louis Achard, Kimberly Berger,Peter Brofman, Ellyn Ingalls, Cindy Milkovich,Dan Monast, Brenda Peterson and Jim Stack, IBM Microelectronics

A Moisture Induced Failure in FCBGA Packaging During Multiple Reflow 14Dr. Fay Hua and Bill Leong, Hewlett-Packard Company

Technical Session BGA2: BGA Assembly IssuesChair: Helen Lowe, Celestica, Inc.Co-Chair: Paul Williams, Intel Corporation

Assembly and Interconnect Reliability of BGA Assembledonto Blind Micro and Through-Hole Drilled Via in Pad 21Andrew Mawer, Kennon Simmons, Terry Burnette, and Billy Oyler,

Motorola Semiconductor Products Sector

Fine Pitch BGA Package Assembly 29Barry Miles, Jim Fusaro, Tony Panczak and Robert Darveaux, Amkor Technology

Technical Session BGA3: Area Array Process AdvancesChair: Marie Cole, IBM MicroelectronicsCo-Chair: Leah Miller, LSI Logic

Identifying Sources of Solder Defects in PrintedCircuit Assemblies Incorporating BGA Packages 37David Moore, Celestica, Inc.; Steve Butkovitch, Cisco Systems, Inc.

Ball Detachment Evaluation for Tape Ball Grid Array Packages 46Steven Lee and J. Wu, Hong Kong University of Science and Technology;E. Law and M. Papageorge, Advanced Semiconductor Assembly Technology

Reworking and Rebelling BGAs 54Steve Stach, Process Sciences, Inc.

Technical Session BGA4: BGA Reliability IChair: Andrew Mawer, Motorola Semiconductor Products SectorCo-Chair: Barry Miles, Amkor Technology

Effects of Board Surface Finish on Failure Mechanisms and Reliability of BGAs 59Dr. Reza Ghaffarian, Jet Propulsion Laboratory

Reliability Performance Assessment andCharacterization of Fine Pitch Mold Array BGA 70Trent Thompson, Elisa Huang, Jeannie Millef, and Chris Vargas,Motorola Semiconductor Products Sector

Effects of Microstructural Heterogeneity on BGA Reliability 76Michael K. Neilsen, Steven N. Burchett, H. Eliot Fang, and Paul T. Vianco,Sandia National Laboratories

Technical Session BGA5: BGA Reliability IIChair: Ping Seto, Chrysler ElectronicsCo-Chair: Dr. Jean-Paul Clech, EPSI, Inc.

The Impacts of Eutectic Solder Ball Co-planarftyof PBGA Package on the Reliability of Solder Ball Joints 87Tony Huang and Joe Chu, Adaptec, Inc.

Effect of Large Connector Insertion on theSolder Joint Reliability of PBGA on PCB 95Arthur May, Sun Microsystems, Inc.;John Lau, Ray Chen, Livia Hu and Tony Chen, Express Packaging Systems, Inc.

Effect of Test Board Design on the 2nd LevelReliability of a Fine Pitch BGA Package 105Robert Darveaux and Jim Heckman, Amkor Electronics;Andrew Mawer, Motorola Semiconductor Products Sector

CONTRACT MANUFACTURING |

Track Organizer: Greg Reed, IHS Publishing

Technical Session CMS1: Contract Manufacturers as Technology Drivers?Chair: Sandy Ruroede, IHS PublishingCo-Chair: Sandra Fox, High Tech Business Decisions

Electronic Manufacturing Services Providers Must Take the Technology Lead 117Nicholas Brathwaite, Flextronics Int'l

Technology Management in a Cost Sensitive, Quick to Market Environment 124John Yealland, Celestica, Inc.

Four Hard Lessons in Contract Manufacturing 131Edwin B. Smith,m, KTEC Electronics

Small Lot Processing and Other Necessary Conditionsfor Build-to-Order Manufacturing 137Brian Tracey, EFTC Corporation

I COMPONENTS _

Track Organizer: Bernard Aronson, EIA

Technical Session COM1: Component TechnologyChair: Bernard Aronson, EIACo-Chair: Tim Ginzburg, Artesyn Technologies

PowerPAD™ - A Method to Create ThermallyEnhanced Plastic Package Solutions for Semiconductors 151Milton L. Buschbom, Mark Peterson,Shih-Fang Chuang, David Kee and Buford Carter, Texas Instruments, Inc.

SMT Power Thermistors 158Theodore J. Krellner, Keystone Thermometrics, Inc.

Application Advantages of IntegratedPassiveDevices (IPDs) in Chip Scale Packages 164Satish Kumar and Kenny Kumar, Microelectronics Components Corporation

) CHIPSCALE TECHNOLOGY SYMPOSIUM |

Track Organizer: Dr. Reza Ghaffarian, Jet Propulsion Laboratory

Technical Session CSP1: Current Status of CSP TechnologyChair: Steve Greathouse, Intel Corporation

Advances in Chip Scale Packaging 173Ron Bauer and James Malatesta, Intel Corporation

Ceramic CSP - Current Status of Technology 179Shoji Uegaki, Seigo Matsuzono, Shingo Sato, Takeshi Kubota,Shin Matsuda and Masahiro Fukui, Kyocera Corporation

Development of MF-BGA (Mounting Frame BGA) 187Noriaki Taketani, Osamu Yoshioka, Gen Murakamiand Atsushi Fujisawa, Hitachi Cable, Ltd.;Takafumi Konno; Hitachi Hokkai Semiconductor, Ltd.

Making Sense of CSPs and BGAs Through Technical Cost Modeling 191Adam T. Singer and Ted A. Hannibal, IBIS Associates, Inc.

Technical Session CSP2: CSP Packaging, Assembly, and Reliability ExperienceChair: Alex Chen, Celestica, Inc.

CSP Consortia Activities: Program Objectives and Status... 203E. J. Simeus, S. Stegura and R. Smedley, Raytheon Systems Company;I. Sterian, A. Chen, C. Quan, R. Mohabir, J. Bragg and K. Chang,Celestica, Inc.; M. Chan, T. Buschor and D. Norton, Harris Corporation;R. Ghaffarian and J.K. Bonner, Jet Propulsion Laboratory

CSP Design and Microvia PWB Fabrication 210Emmanuel J. Simeus, S. Stegura and G.W. Smedley, Raytheon Systems Company

CSP Implementing: An OEM Perspective 216M. Chan, T. Buschor and D. Norton, Harris Corporation

Compatibility of CSPs in SMT Assembly 225I. Sterian, A. Chen, C. Quan, R. Mohabir, J. Bragg and K. Chang, Celestica, Inc.

Technical Session CSP4: CSP Reliability IssuesChair: Dr. Namsoo Kim, Boeing Information, Space & Defense

The Reliability Study of Lead-Free Solder Ball for Chip Scale Package (CSP) 233Masako Watanabe and Kazuaki Ano, Texas Instruments, Japan, Ltd.

Assembly-Level Reliability of Flex-Substrate BGA,Elastomer-on-Flex Packages and 0.5mm Pitch Partial Array Packages 238Pradeep Lall and Kingshuk Banerji, Motorola

Application Specific Reliability of IC Packages 256Patrick Counihan and Steve Greathouse, Intel Corporation

DIRECT CHIP ATTACH

Track Organizer: Ajit Trivedi, IBM Microelectronics

Technical Session DCA1: Flip Chip Processes and ApplicationChair: Ajit Trivedi, IBM MicroelectronicsCo-Chair: Jeff Kennedy, Manufacturers' Services Ltd.

Low Cost Wafer Bumping with Maskless Process 265Yashuhisa Kaga, The Furakawa Electric Co., Ltd.; Jie Zhang, Motorola, Inc.

The Tools You Need for Development andProduction When Using Underfill Materials 270John A. Emerson and Carol L. Jones Adkins, Sandia National Laboratories

Process Limit Testing on Fluxes Used for Flip Chip Soldering 275Paul Novak, Wayne Sozansky and Geoff Walker,Delphi Delco Electronics Systems

Thermo-Mechanical Deformation and InterfacialAdhesion in Underfilled Flip Chip Packages 281Xiang Dai, Robert T. Mar, Ning Jiang and Paul S. Ho, The University of Texas at Austin

Technical Session DCA3: Advances in Underfill and Tools for Flip ChipChair: Ernie Sorongon, Semitech/IntelCo-Chair: Michael Roesch, Hewlett-Packard Company

No-Underfill Flip-Chip Encapsulation 291M. Albert Capote and Sherry Zhu, Ph.D., Aguila Technologies, Inc.;R. Wayne Johnson, Ph.D., Auburn University

Flip Chip Underfill Characterization Methods developing aTest Methodology for Success in the Harsh Automotive Environment 295James M. Rosson, Robert A. Clawson and David W. JJims,Delphi Delco Electronics Systems

Enhancement of Underfill Encapsulants for Flip Chip Technology 303M.B. Vincent and C.P. Wong, Georgia Institute of Technology(Winner Surface Mount Council Student Paper Contest)

Technical Session DCA4: Flip Chip ReliabilityChair: Donald Banks, W.L. GoreCo-Chair: Rick Eklund, Motorola

Flip Chip/CSP Assembly Reliability and Solder Volume Effects 315Jean-Paul Clech, EPSI, Inc.

Cleaning for High Reliability Flip-Chip-on-Laminate Assembly 325Robin L. Sellers, Michael Gibson and Douglas Gullion,Delphi Delco Electronics Systems

Electromigration Studies of Flip Chip Bump Solder Joints 337Scott Brandenburg and Shing Yeh, Delphi Delco Electronics Systems

In Process Stress Analysis of Flip Chip Assemblies During Underfill Cure 345Prema Palaniappan, Paul J. Selman and Daniel F. Baldwin, Ph.D.,Georgia Institute of Technology(Winner Surface Mount Council Student Paper Contest)

INVITATIONAL PAPER |

Track Organizer: Martin Barton, Preferred Designs

Technical Session: Invitational PaperChair: Martin Barton, Preferred Designs

Reliability Verification of Printed Board Assemblies:A Critical Review of Test Methods and Future Test Strategy 359Dr. Per-Erik Tegehall, TVF — The Swedish Institute of Production Engineering Research

SURFACE MOUNT COUNCIL

Track Organizer: David Bergman, JPC

Technical Session SMC1: Surface Mount Council White PaperChair: Martin Freedman, AMP, Inc.

Results of the Surface Mount Council's Vision2010 Industry Technology Roadmap Analysis .~ 387Greg Munie, Lucent Technologies, Inc.

SMT MANUFACTURING

Track Organizer: Ron Boyce, Tektronix, Inc.

Technical Session SMT1: Advances in Fine Pitch Screen PrintingChair: Richard Clouthier, AMTX, Inc.Co-Chair: Ron Boyce, Tektronix, Inc.

Paste Printing and Characterization for Chip Scale Package Assemblies 405Julian Partridge and Rick Gunn, XeTel Corporation

Printing Guidelines for BGA and CSP Assemblies 417Don Burr, General Dynamics

Technical Session SMT2: Control and Optimization of the SMT ProcessChair: Gerald Adams, Dade Behring, Inc.Co-Chair: Vianney Shiel, AEDC

Process Improvement Strategies: Implementation of A No-Clean Process 427Vincente Martinez Mir and Juan Ros Monzo, Manufacturers' Services, Ltd.

Optimizing Reflow Profile Via Defect Mechanisms Analysis 435Dr. Ning-Cheng Lee, Indium Corporation of America

Process Control Strategies in Miniature, Highly Complex PCB Assembly 445Sean Griffin, Mike Stenson and Jer Mulrooney,Manufacturers' Services Ltd.

Reliability Study of Through-Hole Solder JointsProcessed Via Alternative Assembly Reflow Technology (AART) 453R. Seeniraj and K. Srihari, Binghamton University;D. Manessis and G.R. Westby, Universal Instruments Corporation

Technical Session SMT4: ESD Considerations in SMT HandlingChair: Wayne Tan, Advanced Micro DevicesCo-Chair: Larry Fromm, Hewlett-Packard Company

ESD Consideration for Automated Handling of SMT Devices 463Joe Bernier, Harris Semiconductor

Minimizing ESD Effects of Labeling in the Electronics Assembly Environment 469Vicki Heideman and Dennis Polinski, Brady USA, Inc.

Zap Your SMD? Using Ionization for ESD Controlin Automated Equipment for SMT Production 478Arnold Steinman, Ion Systems

Technical Session SMT6: Manufacturing Equipment for Tomorrow's Technology NeedsChair: Jim Walker, IPACCo-Chair: David Raby, Soldering Technology Int'l

The Dual Lane Factory: Considerations forImplementing Dual Lane Manufacturing 485Dennis O'Neal, Speedline

Process Capability Coefficient and Placing Accuracyas Benchmarking Values of SMT Placement Systems 489W. Sauer, H. Wohlrabe and T. Zerna,Dresden University of Technology

Technical Session SMT7: Advances in Manufacturing EquipmentChair: Mike Buseman, Manufacturers' Services Ltd.Co-Chair: Phil Zarrow, ITM, Inc.

The Future of Vacuum Dispensing for Chip Scale Packages 503Allen Duck and Glenn Wyllie, Speedline Technologies

Precision Placement Challenges for Fine-Pitch Components 507Richard Boulanger, Universal Instruments Corp.

Changing Assembly Equipment Requirements for Evolving Packaging Techniques 512Brian Blades, Laurier, Inc.

Technical Session SMT8: Yield ImprovementChair: John Maxwell, John Maxwell, Inc.Co-Chair: Greg Evans, Indium Corporation of America

The Search for Yield Improvement: Quality Metricsin the Electronics Manufacturing Services Industry 525Brian Coll, Manufacturers' Services Ltd.

Economic Impact of Product Yield Improvement 534Emanuel J. Tucker, Benchmark Electronics, Inc.

Reduction of BGA Eutectic Ball Solder Joint Voiding 541William Casey, MCMS, Inc.

Technical Session SMT9: Area-Array and Chip-Scale Rework & RepairChair: Ron Daniels, Circuits AssemblyCo-Chair: John Yealland, Celestica, Inc.

Selection of BGA/CSP Rework Equipment 551Marc DeRuiter, Miquest Electronics

Successful Rework Process for Chip-Scale Packages 555Paul Wood, OK International

Rework System Placement Capability forAdvanced Package Types—uBGA, CSP 561Donald J. Spigarelli, SRT/Spectra

SOLDER MATERIALS AND SOLDERING

Track Organizer: Dr. Paul Vianco, Sandia National Laboratories

Technical Session SOLI: Interconnect Materials and ProcessesChair: Dr. Jennie Hwang, H-Technologies Group, Inc.Co-Chair: Ron Boyce, Tektronix, Inc.

Decision Aid for Functional Materials in Interconnection Technologies 575H.-J. Albrecht, J. Gamalski, T. Kirmse andG. Petzold, Siemens AG

Process and Material Characterization for Lead-Free Tin-Copper Solder Alloy 589Ronald E. Pratt, IEC Electronics Corporation; Bill Trumble, Nortel Technology

Quantifying the Printability of SMT Adhesives 603Richard R. Lathrop, Jr., Heraeus, Inc.

Effect of Solder Paste Residues on RF Signal Degradation 609Brian A. Smith and Laura J. Turbini, Georgia Institute of Technology;Jurgen Gamalski, Siemens AG(Winner Surface Mount Council Student Paper Contest)

Technical Session SOL2: Board and Component Solderability IssuesChair: F. Michael Hosking, Sandia National LaboratoriesCo-Chair: Dr. Puligandla Viswanadham, Raytheon Systems Company

Solderability of Printed Wiring Boards with OrganicPreservation and Ni-Pd Components under Nitrogen Atmosphere. ...............................617Torsten Zachert, Jens Tauchmann, Tilman Schwinn, Messer Griesheim GmbH;Karl-Heinz Schaller, Siemens AG

Solderability and Board Level Reliability ofPalladium Plated, Fine Pitch Components 624Elizabeth Elias Benedetto, Compaq Computer Corp.

Immersion White Tin, the Ideal Solderable Finish 632Richard Edgar, Florida Cirtech, Inc.

Technical Session SOL3: Solder and Flux DevelopmentsChair: Dr. Ning-Cheng Lee, Indium Corporation of AmericaCo-Chair: Dale Lee, Iomega Corporation

No-Clean Solder Paste Benchmarking from a Material Suppliers Viewpoint 641Richard R. Lathrop, Jr., Heraeus, Inc.

Lead Free Solders in Electronics 648Angela Grusd, Heraeus, Inc.

Generating of Solid Solder Bumps on Printed Circuit Boards.......... ............................... 662K.-J. Wolter and R. Biedorf, Dresden University of Technology

Technical Session SOL4: Alternative Surface FinishesChair: Paul Vianco, Sandia National LabsCo-Chair: Gary Tanel, Raytheon Systems Company

Evaluation of Ni / Pd / Au as an Alternative Metal Finish on PCB 669Zequn Mei and Ali Eslambolchi, Hewlett-Packard Company

Thermal Cycle Reliability of Solder Joints to Alternate Plating Finishes 681R. Wayne Johnson, Vickie Wang and Michael Palmer, Auburn University

Palladium Surface Finish for Soft TouchSwitches and High Density SMT Assemblies 687Ping Seto and John Evans, Ph.D., ChryslerHuntsville ElectronicsS. Bishop, Photocircuits Corporation

Technical Session SOL5: International Developments in SolderingChair: Dr. Armin Rahn, Rahn-Tec ConsultantsCo-Chair: Richard Rasp, Rasp & Associates

European Trends in Reflow Soldering Technology 693Robert V. Burress, SEHO USA Inc.Rolf L. Diehm, SEHO Seitz and Hohnerlein GmbH

Manufacture and Reliability of Alternate Solder Alloys 699S. Wege, G. Habenicht and R. Bergmann, Technical University of Munich

Global Update on Lead-Free Solders 705Peter Biocca, Multicore Solders, Inc.

HIGH-DENSITY SUBSTRATES |

Track Organizer: David Bergman, JPC

Technical Session SUB1: Flex CircuitsChair: Joe Fjelstad, Tessera, Inc.Co-Chair: Klaus-Jurgen Wolter, Dresden Technical University

Polymide Substrates as an Enabler For Leading Edge DCA Applications 715Timothy Patterson, Smartftex Systems

Flexible Interconnect Technologies for Enhanced SMT Assembly 720Joseph A. DiPalermo, Parlex Corporation

High Volume, Low Cost Flip Chip Assembly on Polyester Flex 725Dr. Ken Gilleo, Alpha Metals - Packaging Materials;Bob Boyes, Steve Corbett, Gary Larson and Dave Price, Poly-Flex Circuits, Inc.

Technical Session SUB2: Microvias, The Fourth GenerationChair: Jack Fisher, ITRICo-Chair: Rich Freiberger, GSS Array Technology

Flip Chip on Large Area Panel Laminate with Reliability Results 737P. Nerio, J. Lykins, M. Skinner, D. Chazan, S. Westbrook,

MicroModule Systems, Inc.

Optimizing BGA to PCB InterconnectionsUsing Multi-Depth Laser Drilled Blind Vias-in-Pad 743Larry W. Burgess, LaserVia Drilling Centers;Fabrizio Pauri, Pluritec Italia S.p.A.

Limits of Copper Plating in High Aspect Ratio Microvias 748Steve Castaldi and Dennis Fritz, MacDermid, Inc.;Ron Schaeffer, PhotoMachining, Inc.

THERMAL MANAGEMENT j

Track Organizer: Martin Barton, Preferred Designs

Technical Session THM1: Thermal ManagementChair: Bruce Inpyn, Pitney BowesCo-Chair: Tom Borkes, Medisense, Inc., an Abbott Laboratories Company

New High Thermal Conductivity Materials forThermal Management of Surface Mount Electronic Assemblies 759Steve Dunford, Raytheon Systems Company

Floating Metal Plane on Thermal and ElectricalPerformance of an Enhanced Plastic Ball Grid Array Package 769Humayun Kabir, Richard Groover, David Tovar and Joe Joroski, ChipPAC Inc.

Assembly Multi-Chip COB Module with Metal Heat Sink 777Hahnjong Hsiung and Zhao-Feng Shi,Gintic Institute of Manufacturing Technology

ALTERNATE PAPERS

Evaluation of Eutectic Solder Bump InterconnectTechnology for Direct Chip Attach Applications 789Craig Beddingfield, Qing Tan and Addi Mistry,Motorola Semiconductor Products Sector

Structure and Material Analysis of PBGA Packages 794Torsten Kirmse, Dresden University of Technology; H.-J. Albrecht, Siemens AG