ISOCC 2016

Process Variation-aware Bridge Fault Analysis

Heetae Kim, Inhyuk Choi, Jaeil Lim, Hyunggoy Oh and Sungho Kang Electrical & Electronic Engineering

Yonsei University Seoul, Korea

{kht2161, ihchoi, limji, kyob508}@soc.yonsei.ac.kr and shkang@yonsei.ac.kr

Abstract— Bridge faults are important that cause a reliability concern. Since process variation affects the bridge faults, it should be considered for bridge fault analysis. This paper proposes a new analysis method for resistive bridge faults considering process variation. The proposed method analyzes defect coverage for resistive bridge faults by using circuit level modeling. The proposed method uses the lower level analysis and it reduces redundant test patterns for bridge test.

Keywords; Bridge fault; bridge resistance; process variation;

I. INTRODUCTION

Bridge faults are unexpected resistive connections between two or more wires and they decrease the reliability as various faulty behaviors. Moreover, process variation makes new types of faulty behavior caused by one bridge fault [1]. The new types of bridge behaviors generated by the process variation can make test escapes by traditional method [2, 3]. Therefore, a new method for the bridge fault test under process variation is needed.

The work in [2] presented a circuit level bridge fault modeling and analyzed the logic behaviors of bridge faults as the bridge resistance. However, it didn’t consider the process variation, so it couldn’t solve the test escape problem by the process variation. In [3], defect coverage was defined which considered the relationship between the logic behaviors for one bridge fault. One bridge fault can be observed as various logic behaviors and [3] analyzed the logic behaviors including the new types of logic behaviors by process variation. However, since it analyzed the bridge faults by using logic behavior level, only the types which have the same victim nodes can be considered.

This paper proposes a bridge fault analysis method using circuit level analysis. The proposed method can consider the types of bridge behaviors when the victim nodes or the value of two nodes are exchanged. Since the proposed method extends the analysis level from behavior level to circuit level, it allows more reduction of bridge test patterns.

II. BRIDGE FAULT BEHAVIOR

A bridge fault is observed as various logic behaviors. To make the defected circuit as fault-free, the bridge resistance(Rbr) should be large enough and the minimum value of the bridge resistance for normal operations is called critical resistance(CR). Fig. 1 shows an example of a bridge fault

between node A and B. Th1, Th2 and Th3 are logic threshold of driven gates, NAND, NOR and NOT gates, respectively, and CR1, CR2 and CR3 are critical resistances corresponding to the logic thresholds.

Fig. 1(b) shows three types of logic behaviors(LBs) without process variation, LB1, LB2 and LB3. The value which doesn’t satisfied the logic threshold has faulty value at the corresponding gate inputs, therefore the intervals of the LBs are decided by CRs. For instance, since the interval of LB1 is lower than all CRs, all gate inputs for Th1, Th2 and Th3 have faulty values in LB1.

Process variation can generate new types of LBs which can’t observed when nominal case. Fig 2(a) shows an example when Th2 is increased by process variation. In this example, CR2 becomes larger than CR1 and it generates the new types of behaviors, LB4, LB5 which intervals are [CR3.norm, CR1.norm] and [CR1.norm, CR2.PV], respectively. Therefore, process variation may cause test escapes and decreases the reliability of the test.

III. BRIDGE FAULT ANALYSIS

This paper proposes a new method for bridge fault test by analyzing the defect coverage which is proposed in [3]. This paper defines the defect coverage as bridge resistance based defect coverage(BRDC) which is defined as covered bridge resistance interval(CBRI) over global bridge resistance interval(GBRI). The CBRI and GBRI are union intervals of the covered and detectable LBs, respectively.

Table 1 shows the detectable LBs from Fig. 1 and Fig. 2. Assume a test pattern that excites LB1 – LB5 and observes only Th2. Since the effect of LB3 can’t be observable by Th2, the test pattern can check only LB1 – LB5 except LB3. For this

Figure 1. Example of a bridge fault (a) Circuit level modeling

(b) Voltages of node A and B without process variation

978-1-5090-3219-8/16/$31.00 ©2016 IEEE 148 ISOCC 2016

ISOCC 2016

test pattern, CBRI is calculated as [0, CR2.PV] by union of LB1, LB2, LB4 and LB5. Since GBRI for LB1 – LB8 is calculated as [0, max(CRs)], BRDC for the test pattern is CR2.PV over max(CRs).

The example test pattern can’t cover LB3, so another test pattern is needed for LB3 in logic behavior level analysis. However, in circuit level analysis, the range of LB3 is covered by that of LB4. Testing the bridge fault means checking whether the bridge resistance is larger than the critical resistance. For instance, a test pattern for LB4 checks that the bridge resistance is larger than the range of LB4. Since the range of LB3 is included by LB4, the test pattern for LB4 also can test LB3. This relationship also can be considered between types when the value of bridged two nodes are exchanged. Table 1 also shows LB6 – LB8, which are logic behaviors when the value of node A and B are exchanged with each other. If CR1.VE is smaller than CR2.PV, LB6 – LB8 are covered by LB1, LB4 and LB5. Therefore, in the circuit level analysis, the test pattern that can detect LB5 covers all types of LBs on Table 1.

Table 2 shows that the number of test patterns for LBs in Table 1. The work in [2] doesn’t consider the process variation. Therefore [2] needs 7 patterns for LB1 – LB8, because LB2 and LB4 are distinct only in the proposed method. The work [3] considers the process variation and behavior level analysis. Therefore [3] needs three patterns which cover LB1 – LB4, LB5 and LB6 – LB8 respectively. However, the proposed method needs only one pattern for LB1 – 8 as shown above.

Since the process variation is not always the same amount, another LB that is different with LBs from Table 1 can be

generated. For instance, LB9 can be generated by increasing Th1 under the process variation. But we can’t assure that LB9 is covered by LB5 or LB5 is covered by LB9. In this case, test patterns for both LB5 and LB9 are needed.

The pseudo code for calculating the proposed BRDC which considers circuit level analysis is presented in Fig. 3. In CBRI calculation, the proposed analysis method under circuit level is considered. If a test pattern can detect the LB totally, 1 is added to CBRI. However when the pattern can’t detect the LB, the amount of interval that detectable LB covers is added to CBRI.

IV. CONCLUSION

Bridge faults are important manufacturing faults and the process variation brings test escapes for bridge fault testing. This paper proposed the analysis method for the bridge faults under the process variation. Since the proposed method analyzes the bridge faults on the circuit level, it allows reduction of test patterns for bridge faults.

ACKNOWLEDGMENT

This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC].

REFERENCES [1] H. Villacorta, J. G. Gervacio, J. Segura and V. Champac, “Low VDD

and body bias conditions for testing bridge defects in the presence of process variations,” Microelectronics Jounal, Vol. 46, pp.398-403, 2015.

[2] Z. Li, X. Lu, W. Qui, W. Shi and D. M. H. Walker, “A circuit level fault model for resistive bridges,” ACM Trans. Design Automation of Electronic Systems, Vol. 8, pp.546-559, 2003.

[3] U. Ingelsson, B. M. Al-Hashimi, S. Khursheed, S. M. Reddy and P. Harrod, “Process variation-aware test for resistive bridges,” IEEE Trans. Computer-Aided Design Integration Circuits and Systems, Vol. 28, pp.1269-1274, 2009.

TABLE I. LOGIC BEHAVIORS FOR NOMINAL, PROCESS VARIATION(PV) AND VALUE EXCHANGED(VE) CASES.

Nominal PV VE

LB1 LB2 LB3 LB1 LB4 LB5 LB6 LB7 LB8

Th1 0 x 0 x 0 x 0 x 0 x 1√ 1 x 1 x 1 x Th2 0 x 0 x 1√ 0 x 0 x 0 x 1 x 0√ 0√ Th3 1 x 0√ 0√ 1 x 0√ 0√ 0 x 0 x 1√

TABLE II. NUMBER OF TEST PATTERNS FOR TABLE 1 [2] [3] Proposed

# of test patterns 7 3 1

Figure 3. Various logic behaviors. (a) under process variation (b) the values of node A and B are exchanged with each other

Figure 2. Pseudo code for calculating BRDC

Input: A test pattern tp, Set of process variation P Output: BRDC(tp, P) for a bridge fault 1 for all bridged node i 2 for all driven gate threshold th 3 GBRI = GBRI+1 4 Calculate the left and right end of CR

LCRi,th RCRi,th under process variation P 5 for all bridged node i 6 for all driven gate threshold th 7 if tp can detected th 8 CBRI = CBRI+1 9 DLCR = max(DLCR, LCR) 10 else 11 CBRI = max(0, (RCR-LCR)/DLCR) 12 return CBRI/GBRI

978-1-5090-3219-8/16/$31.00 ©2016 IEEE 149 ISOCC 2016