prof. wahied gharieb ali abdelaal faculty of engineering computer and systems engineering department...
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Prof. Wahied Gharieb Ali Abdelaal
Faculty of EngineeringComputer and Systems Engineering Department
Master and Diploma Students
CSE 502: Control Systems (1)
Topic# 9
Digital Control Design (PID)
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Outline
Introduction
Indirect Control Design
Digital PID control design
Design Examples
Direct Control Design
Direct Design using Root Locus
Deadbeat Control Design
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Introduction
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Indirect control Design
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Indirect Control Design
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Indirect Control Design
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Approximations to Integration
Indirect Control Design
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Euler’s Approximation
Indirect Control Design
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Indirect Control Design
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Indirect Control Design
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Indirect Control Design
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Indirect Control Design
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Indirect Control Design
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Indirect Control Design
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Digital PID Control Design
A proportional controller (P) reduces error responses to disturbances, but still allows a steady-state error.
When the controller includes a term proportional to the integral of the error (I), then the steady state error to a constant input is eliminated, although typically at the cost of deterioration in the dynamic response.
A derivative control typically makes the system better damped and more stable.
Controller Effects
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Digital PID Control Design
Rise timeMaximum overshoot
Settling time
Steady-state error
PDecreaseIncreaseSmall change
Decrease
IDecreaseIncreaseIncreaseEliminate
DSmall change
DecreaseDecreaseSmall change
Note that these correlations may not be exactly accurate, because P, I and D gains are dependent of each other.
Closed-loop Response
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Digital PID Control Design
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Digital PID Control Design
PID controller with integral anti-windup
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Digital PID Control Design
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Digital PID Control Design
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Digital PID Control Design
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Digital PID Control Design
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Digital PID Control Design
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Digital PID Control Design
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Digital PID Control Design
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Discrete time equivalent of analog controller using Euler’s forward method (sampling period =T)
Example
Design Examples
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Discrete-time controllers when T = 0.4 s, which is relatively large as compared to the continuous-time controller’s fastest mode e−2t, the discrete-time controller approximation deviates significantly from the continuous-time controller.
As the sampling interval is decreased, the step responses of the analog and discrete-time controllers are the same.
Design Examples
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If we use the trapezoidal method, the transfer function of the digital controller becomes
Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Design Examples
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Direct Control Design
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Direct Control Design
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Direct Design using Root Locus
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Direct Design using Root Locus
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Direct Design using Root Locus
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Direct Design using Root Locus
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Direct Design using Root Locus
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Direct Design using Root Locus
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Direct Design using Root Locus
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Direct Design using Root Locus
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Direct Design using Root Locus
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Direct Design using Root Locus
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Direct Design using Root Locus
N= Number of samples per oscillation
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Direct Design using Root Locus
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Deadbeat Control Design
One difference between a continuous-data control system and a discrete-data control system is that the latter is capable of exhibiting a deadbeat response. A deadbeat response is one that reaches the desired reference trajectory in a minimum amount of time without error. In contrast, a continuous-data system reaches the final steady-state trajectory or value theoretically only when time reaches infinity. The switching operation of sampling allows the discrete-data systems to have a finite transient period.. The output response reaches the desired steady state with zero error in a minimum number of sampling periods without inter sampling oscillations.
Design with Deadbeat Response
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Deadbeat Control Design
For the sampled system with ZOH
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Example: Consider the forward-path transfer function of the uncompensated system is given by
Deadbeat Control Design
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Deadbeat Control Design
Closed loop poles at the origin, so it
is so fast
Steady state after two samples without error
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Deadbeat Control Design
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Deadbeat Control Design
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Deadbeat Control Design
The output is delayed one sample than the input
Explain
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Deadbeat Control Design
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Deadbeat Control Design
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Deadbeat Control Design
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Deadbeat Control Design
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Deadbeat Control Design
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Deadbeat Control Design
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Deadbeat Control Design
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Deadbeat Control Design
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Deadbeat Control Design
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Deadbeat Control Design
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Deadbeat Control Design