programmable system level integration on your desktop atmel’s north america logic seminar series
TRANSCRIPT
Programmable System Level Integration
on your desktopAtmel’s North America Logic Seminar Series
AT94 Training 2001Slide 2
Facilities and Employees
• San Jose, CA (1,200 employees)– Headquarters, Test and Qualification, R / D
• Colorado Springs, CO (1,900 employees)– Fabrication Assembly & Test, R / D– Two 0.35 6 inch Wafer Fabs
• Rousset, France (600 employees)– Fabrication Assembly & Test, R / D– 0.5 6 inch Wafer Fab and 0.35 8 inch Wafer Fab
• Temic: Heilbronn, Germany (900 Employees)– 0.5 6 inch Bipolar / Si-Ge Wafer Fab, Assembly, Test, R / D
• Temic: Nantes, France (650 employees) – 0.5 6 inch Wafer Fab, Assembly, Test, R / D
• ASIC / ASSP Design Centers– Columbia, MD; Colo. Spgs.; San Jose; Paris; Munich; Camberley UK; Tokyo;
Shanghai; Raleigh, NC; Berkeley, CA; Helsinki; Trondheim – All Facilities Registered ISO 9001 & 9002
• 7 North American & 15 International Sales Offices
Total 6,100 Employees
AT94 Training 2001Slide 3
Atmel Product Design Centers
IP Expertise
NVM, 8, 16, 32-bit MCUs, DSP Core, Analog, RF, Rotating Storage, RFID, Data Security Wireless
Voice/Data, Image/Sound Processing, Power Measurement, Battery Management, Automotive, Smart Card,
TV/Radio, USB, Wired/Wireless L A N, I R D A, Bluetooth
San JoseColo Spgs Raleigh
Chesapeake
Camberley Paris
Rousset
Dijon
Trondheim
PortugalGreece
Tokyo
Shanghai
Hong KongMalaysia
Minneapolis
NantesHeilbronn
HelsinkiE. Killbride
AT94 Training 2001Slide 4
User-Defined Logic Spectrum
ATF22V10ATF16V8ATF20V8
ATV2500BATF1500 FamATV750B
AT6000AT40K
ATL25 SeriesATL35 Series ATL50 SeriesATL60 Series
Decoders,Glue Logic
State machines,Timing, Control
RAM/Logic,Computing,Co-processing System Level Integration
De
nsi
ty
Macrocells0.25, 0.35, 0.5, 0.6 Analog / Digital
Analog / Digital/NV Memory, RF
Total CustomizationVery High Volume
PAL-Type
CPLD
FPGA
GateArray
Custom ASIC
FPSLIC
AT94K
Cell based ASIC
High Volume/Low Cost
ProgrammableSLI with AVR
AT94 Training 2001Slide 5
Atmel’s Flash MCU FamiliesPrice vs Performance
AVR
ARM-7Laser Printer
$1 $2 $5 $10 $20
Keyless Entry
Appliances
Auto Elect.
Cellphones
Settop Boxes
Internet
Disk Drives
Engine Control
C51
Performance
Price
AT94 Training 2001Slide 6
SLI Products
Microcontrollers
– 80C51
– AVR™
– ARM™
ASIC
– FPGA
– Gate Array/Embedded Array
– Cell Based IC
– Custom
ASSP
– Multimedia
– Storage Products
– Smart Cards
– Wireless Communications
– Wireline Communications
– Power MCU
AT94 Training 2001Slide 7
ASSP
Power MCU
– Power Meters– Battery Chargers
Storage Products
– DVD/CD-ROM– Floppy Disk– Hard Disk
Multimedia
– Sound; Dolby AC3,Voice Recorder andDigital Answering Machine
– Image Processing; MPEG2and Video Conferencing
– Image Capture
WirelessCommunications
– Cellular; GSM and CDMA (Baseband)
– Networking; Wireless LAN and Bluetooth
– RFID; Asset ID and Remote Keyless Entry
Smart Cards
– Secure Memories– Secure Microcontrollers
Wireline
Communications
– USB; Function, Hostand Hub
– Ethernet; 10T/100 MAC and PHY
– Cable Modem; QPSKand QAM
AT94 Training 2001Slide 8
Fab Processes• 0.6µ CMOS in Production• 0.5µ CMOS in Production• 0.35µ CMOS in Production• 0.25µ CMOS in Production• 0.18µ CMOS in Development• 0.8µ BiCMOS in Production• 0.6µ BiCMOS in Development• 0.8µ Si-Ge in Production• 0.35µ Si-Ge BiCMOS in Development
AT94 Training 2001Slide 9
FPGAGlue Logic
MemorySRAM
CPUAnalogue
PowerManagement
Clock
ASSPLogic
NVM
System-On-Chip Issues
• $250K+ NRE
• $100K+ design tools
• Large volume requirements
• Custom product
• Long design time
• High risk
• IP issues (availability, cost implementation)
>> System level integration not viable for most customers
AT94 Training 2001Slide 10
Configurable SRAM
8 Bit RISC MCUAT40K FPGA
Monolithic SRAM Based FPSLIC
20 MIPS* - 8bit RISC MCU
Up to 36K bytes of SRAM
From 5K Up to 40K gates FPGA
*30 MIPS version available Q4 2001
AT94 Training 2001Slide 11
Configurable SRAM
SRAM interface
AVR/AT40
K inte
rface
FPSLIC Embedded Blocks
• Software configurable interface between blocks already implemented• Pre-implemented Interface blocks save 2000-5000 FPGA gates
AT40K FPGA8 Bit RISC MCU
AT94 Training 2001Slide 12
FPGA Designs
•IDS supports Schematic, VHDL or Verilog Design Entry•It generates a BST file for programming the Configurator
AT40K FPGA
AT17
Figaro IDS
FPGA Development Tools
AT94 Training 2001Slide 13
AVR Designs
•AVR Studio can be used with Assembly or C to debug code•A HEX file is then used to program the AVR
AVR Studio
Instruction Set Simulator
Requires an Assembly or C Compiler
8 Bit RISC MCU
AT94 Training 2001Slide 14
FPSLIC Designs System Designer for FPSLIC designs includes FPGA and AVR design flows with Co-verification
Configurable SRAM
8 Bit RISC MCU
AT40K FPGA