Weighted Priority Arbiter

Weighted Priority Arbiter

DECLARATION

We hereby declare that the project entitled WEIGHTED PRIORITY ARBITER submitted in partial fulfillment of the requirements for the award of degree of Bachelor of Technology in Electronics and Communication Engineering. This dissertation is our original work and the project has not formed the basis for the award of any degree, associate ship, fellowship or any other similar titles and no part of it has been published or sent for the publication at the time of submission.

PARAAG A MEGHARAJ(1GA11EC054)

ACKNOWLEDGEMENT

We wish to take this opportunity to express our deep gratitude to all those who helped, encouraged, motivated and have extended their cooperation in various ways during our project work. It is a pleasure to acknowledgement the help of all those individuals who were responsible for foreseeing the successful completion of the project.We would like to thank Mr. L. VASUDEVA MURTHY (Head, CED) and express our gratitude with great admiration and respect to our project guide Mr. SOURABH SHUKLA, Mr. GAUTHAM AND Ms. Y LAKSHMI DEEPTHI for their valuable advice and help throughout the development of this project by providing with the required information without whose guidance, cooperation and encouragement, this project couldnt have been materialized.Last but not the least; we would like to thank the entire respondents for extending their help in all circumstances.

PARAAG A MEGHARAJ(1GA11EC054)

CONTENTS

1. Organization profile 041. Verilog .071. Abstract ....151. Introduction 161. Project Definition .........171. Project overview .181. PIN description ....191. Finite state machine .201. Functional Description of FSM ..211. State diagram 221. Working ...231. Waveforms .241. Features ...281. Application ....281. Conclusion ..291. Bibliography ..29

ORGANISATION PROFILEECIL was setup under the department of Atomic Energy in the year 1967 with a view to generate a strong indigenous capability in the field of professional grade electronic. The initial accent was on self-reliance and ECIL was engaged in the Design Development Manufacture and Marketing of several products emphasis on three technology lines viz. Computers, control systems and communications. ECIL thus evolved as a multi-product company serving multiple sectors of Indian economy with emphasis on import of country substitution and development of products and services that are of economic and strategic significance to the country.Electronics Corporation of India Limited (ECIL) entered into collaboration with OSI Systems Inc. (www.osi-systems.com) and set up a joint venture "ECIL_RAPSICAN LIMITED". This Joint Venture manufacture the equipments manufactured by RAPSICAN, U.K, and U.S.A with the same state of art Technology, Requisite Technology is supplied by RAPSICAN and the final product is manufactured at ECIL facility.Recognizing the need for generating quality IT professionals and to meet the growing demand of IT industry, a separate division namely CED has been established to impart quality and professional IT training under the brand name of ECIT. ECIT, the prestigious offshoot of ECIL is an emerging winner and is at the fore front of IT education in the country.

MissionECILs mission is to consolidate its status as a valued national asset in the area of strategic electronics with specific focus on Atomic Energy, Defense, Security and such critical sectors of strategic national importance.

Objectives To continue services to the countrys needs for the peaceful uses Atomic Energy. Special and Strategic requirements of Defence and Space, Electronics Security System and Support for Civil aviation sector. To establish newer Technology products such as Container Scanning Systems and Explosive Detectors. To re-engineer the company to become nationally and internationally competitive by paying particular attention to delivery, cost and quality in all its activities. To explore new avenues of business and work for growth in strategic sectors in addition to working realizing technological solutions for the benefit of society in areas like Agriculture, Education, Health, Power, Transportation, Food, Disaster Management etc.

DivisionsThe Company is organized into divisions serving various sectors, national and Commercial Importance. They are Divisions serving nuclear sector like Control & Automation Division (CAD), Instruments & Systems Division (ISD), Divisions Serving defence sector like Communications Division (CND), Antenna Products Division (APD), Servo Systems Division (SSD) etc., Divisions handling Commercial Products are Telecom Division (TCD), Customer Support Division (CSD), Computer Education Division (CED). ExportsECIL is currently operating in major business EXPORT segments like Instruments and systems design, Industrial/Nuclear, Servo Systems, Antenna Products, Communication, Control and Automation and several other components.

ServicesThe company played a very significant role in the training and growth of high calibre technical and managerial manpower especially in the fields of Computers and Information Technology. Though the initial thrust was on meeting the Control & Instrumentation requirements of the Nuclear Power Program, the expanded scope of self-reliance pursued by ECIL enabled the company to develop various products to cater to the needs of Defense, Civil Aviation, Information & Broadcasting, Tele communications, etc.

VERILOG Verilog is a hardware description language (HDL). HDL is used to describe a digital system for example, a network switch, a microprocessor or a memory or simple flip flop. Verilog is case sensitive. All verilog keywords are lower case. Identifiers are name used to given an object, such as a register or a function or a module, a name so that it can reference from other places in a description. 2.1. Design Styles . Bottom up Design . Top down Design 2.2. Abstraction Level of Verilog . Behavioral level . Register Transfer level . Gate level 2.2.1. Behavioral level The level describes a system by concurrent algorithms (Behavioral). Each algorithm itself sequential, that means it consists of instructions that executed one after the other. Functions, tasks, always blocks are the main elements. 2.2.2 Register Transfer level Designs using the register transfer level specify the characteristics of a circuit by operations and the transfer of data b/w registers. Modern definition of RTL code is any code that is synthesizable is called RTL code. RTL design contains exact timing possibility, operations are scheduled to occur at certain times. 2.2.3 Gate level Within the logic level the characteristics of a system are described by logical links and their timing properties. All signals are discrete signal. They can only have definite logical values (0,1,X,Z). The usable operation are predefined logic primitives (AND, OR, NOT). Using gate level modeling might not be a good idea for any level of logic design. Gate level code is generated by tools like synthesis tools and this net list is used for gate level simulation and for backend. Verilog has built in primitives like gates, transmission gates and switches. Gates have one scalar O/P and multiple scalar I/P. The 1 st terminal in the list of gate terminals is an O/P and other terminals are I/P. transmission gates are bi directional and can be resistive or non resistive. Transmission gate tran and rtran are permanently on and do not have a control line. Tran used to interface two wire with separate drives and rtran can be used to weaken signals. Resistive devices reduce the signal strength which appears on the output by one level. All the switches only pass signals from source to drain, incorrect wiring of the devices will result in high impedance output. 2.3. Gate and Switch delays 2.3.1. Rise delays Rise delay is associated with a gate output transition to 1 from another value (0, X, Z). 2.3.2. Fall delays The fall delay is associated with a gate O/P transition to 1, X, Z from another value. 2.3.3. Turn off delays Gate output transition to Z from another value (0, 1, X). 2.3.4. Minimal delays Minimum delay value that the gate is expected to have. 2.3.5. Typical delays Typical delay value that the gate is expected to have. 2.3.6. Maximum delays Maximum delay value that the gate is expected to have. Verilog has built in primitives like gates, transmission gates and switches. This is rather small number of primitives, if we need more complex primitives, then verilog provides UDP or simply user defend primitives. By using UDP we can model Combinational logic and sequential logic. 2.4. Identifiers Identifiers must start begin with an alphabetic character or the underscore character (_). Identifiers may contain (a z, A Z, _ , $). Identifier can be long up to 1024 character. 2.5. Data Types 2.5.1. Nets Represents structural connections between components.

2.5.2. Registers Represent variable used to store data. 2.5.3. Register data types Register store the last value assigned to them until another assignment statement changes their value. Register represent data storage constructs. You can create arrays of register called memories. Register data types are used as variables in procedural blocks. A register data type is required if a signal is assigned a value with in a procedural block. Procedural blocks begin with keyword initial and always. reg: unsigned variable. integer: signal variable 32 bits. time: unsigned integer 64 bits. Real: Double precision floating point variable. 2.5.4. String A string is a sequence of characters enclosed by double quotes and all contained on signal line. One eight bit ASCII value representing one character. No extra bits are required to hold a termination character. \n New line character. \t Tab character. \\ Back slash (\) character. \ Double quote () character. \ddd A character specified in 1 3 octal digits. %% Percent (%) character. 2.5.5. Operators 2.5.5.1. Logical Operators ! (NOT), && (AND), || (OR). 2.5.5.2. Bit wise Operators ~ (Negation), & (AND), | (Inclusive OR), ^ (Exclusive OR), ^~ or ~^ (Exclusive NOR).

2.5.5.3. Reduction Operators & (AND), ~& (NAND), | (OR), ~| (NOR), ^~ or ~^ (XNOR), ^ (XOR). 2.5.5.4. Shift Operators > (Right Shift). The left operand is shifted by the number of bit positions given by the right operand. The vacated bit positions are filled with zeroes. 2.5.5.5 Concatenation Operators {}. 2.5.5.6. Replication Operators {{}}. 2.5.5.7. Conditional Operators Cond_expr ? True_expr : False_expr. 2.5.6. Procedural Blocks: Two type of procedural blocks in verilog. 2.5.6.1: Initial: Initial blocks execute only once at time zero. 2.5.6.2: Always: Always blocks loop to execute over and over again, in other words as name means, it executes always. Always blocks waits for the event, here positive edge of clock, where as initial block without waiting just executed all the statements within begin and end statement. If a procedure block contain more than one statement, those statement must be enclosed within: a) Sequential begin end Block. b) Parallel Fork join Block. 2.6. Blocking Assignment: Blocking assignment are executed in the order they are coded, hence they are sequential. Since they block the execution of next statement, till current statement is executed, they are called blocking assignments. Symbol ( = )

2.7 Non Blocking Assignment: Non Blocking assignment are executed in parallel. Since the execution of next statement is not blocked due to execution of current statement, they are called non blocking statement. Symbol ( next state=B flaga=0 => next state=C

2: State B: The first task is to initial the weight registers (wt) with the input weights (wgt). wt[0]=wgt1 wt[1]=wgt2 wt[2]=wgt3 wt[3]=wgt4Another set of weight registers (w) are used to hold the updated value of the weights i.e. the value after they are decremented. If the value of all the w registers is zero, then their values are re-initialized from the wt register. Request registers (r) are used to implement the masking concept. To illustrate the masking process let us consider 4 requests- req1, req2, req3, req4. Hence the value of request register will be r=1111 where the LSB bit and MSB bit represent req1 and req4 respectively. If req4 has the highest priority, it will be given the grant first. After the grant signal is provided, req4 is masked i.e. value of r=0111. This ensures that the higher priority request will not be given grant continuously.Flagb is set high signaling that the arbiter can now proceed to state C.

3: State C: This state determines which of the requests is having the highest weight. If two requests are found to have the same highest priority, then the request which has been granted least number of times is given the grant. The weights of masked requests are not compared. The selected request is stored a register named la. If a request having weight zero is selected in this state, then the control is immediately transferred to state A and hence it is not provided with the grant signal.The value of the count register is decremented by one.The next state depends on the value of flagc. Flagc=1 => next state=D Flagc=0 => next state=A4: State D: Grant is provided to the request selected in state C. Weight of that request is decremented by 1 and the request is masked.Value of flag register flagd is updated according to the value of the count register. Flagd=1 for a non-zero value of the count register.The next state is determined from the value of flagd. Flagd=1 => next state=C Flagd=0 => next state=A

Waveform

Reset is set high for 150 nsec. As soon as the reset is set low, requests are asserted by all the four requestors req1, req2, req3 and req4 with weights 10, 15, 9 and 7 respectively. Since req2 has the highest weight, it is granted first at 180 nsec. At the same time req2 is masked and its weight is decremented to 14. Subsequently the next requestor with the highest weight is provided grant, its weight is decremented and the request is masked and so on.At 240 nsec all the requestors are granted once and hence all the requests are masked. At 260 nsec the requests are again unmasked and the process continues.

At 650 nsec req3 withdraws its request. Hence it is not serviced. The remaining requestors whose requests are still asserted are serviced in the similar fashion.

At 1150 nsec req3 gets asserted again and the all other requestors withdraw their requests. As only one request is asserted, it is provided with grant signal continuously. As weight of the request is decremented each time it is given grant, at 1540 nsec the weight of all the requests is 0. Hence at 1560 nsec, weights of all the requestors are re-initialized.

Weighted Priority ArbiterThe purpose of a weighted arbiter is to allow each requestor a share of the common resource which is relative to his predefined weight. For example, if only two requestors have the weight of 3 and 4 respectively, then over a long period of time, assuming both requestors always have their request asserted, the first one will get 3/7 of the grants and the second will get 4/7 of the total grants.The weight is therefore a mean for setting specific priorities to the different requestors. Contrary to the strict priority arbitration, the weighted arbiter maintains the fairness for all requestors and prevents starvation by serving all requestors according their relative predefined weight, preventing one requestor from dominating the shared resource indefinitely. Using this arbiter results in the number of acknowledges for each valid requestor being relative to its proportional weight with the exception that an inactive requestor is skipped regardless of its weight.

Weighted Priority Arbiter Features:1. Ensure fair access to a shared resource in a system e.g. system bus.2. This arbiter has its input requests scalable.3. Synchronous reset capability.4. Weight of each request represents its priority level.5. Weights set to be initial state value when all N weights become zero.6. Masking capability to prevent starvation of lower priority requests.

ApplicationComplex System-on-Chip (SoC) architecture comprises multiple master and slave modules. Master modules such as processors and hardware accelerators send requests or data to slave modules like memories or register banks. Efficient communications between master and slave modules require adequate on-chip interconnected architectures with arbitration that features content resolution, prioritization, and fairness.

Conclusion The design of a Weighted Priority round robin arbiter using Finite State Machine (FSM), is both simple and efficient, making the seemingly complicated features of a round robin arbiter a straight forward task. The usage of masking concept for blocking the request which has been given the grant once and unmasking it when all the requests are serviced once is the best way to implement the round robin functionality.The overall design is robust, scalable, and easy to extend to any number of requests and simple for pipeline integration.

Bibliography www.tkt.cs.tut.fi/kurssit/9636/K05/Chapter18.pdfwww.sciencedirect.com/science/article/pii/0165607482900102cseweb.ucsd.edu/classes/sp08/cse140L/lab2/starter_files/ch1to12.pdfwww.imit.kth.se/courses/IL2207/0506/Lectures/2B1448_L3_Buses.pdfwww.wolesinski.net/Publications/Papers/10SLJ.pdfhttp://en.wikipedia.org/wiki/Finite-state_machine

Global Academy of TechnologyPage 3