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IEEE C802.16m-09/0102r4

Project IEEE 802.16 Broadband Wireless Access Working Group <http://ieee802.org/16>

Title Proposed Text of Enhanced Structured LDPC coding with rate matching for the IEEE 802.16m Amendment

Date Submitted 2009-01-13

Source(s) Dr. Wu ZhanjiBeijing University of post and telecommunication (BUPT)

Wataru Matsumoto, Toshiyuki Kuze Mitsubishi Electric Corporation Philip V. Orlik, Andreas F. Molisch, Zhifeng (Jeff) Tao, Jinyun Zhang Mitsubishi Electric Research Laboratories

Xu jin, Sun BoZTE

Luo Zhendong, Du YingCATR

[email protected]@163.com

[email protected]

[email protected], [email protected] <[email protected]>

luozhendong, [email protected]

Re: “802.16m amendment text”: IEEE 802.16m-08/042, “Call for Contributions on Project 802.16m Draft Amendment Content”. Target topic: “11.13 Channel Coding and HARQ”.

Abstract Proposed Text of LDPC coding with rate matching for the IEEE 802.16m Amendment

Purpose To be discussed and adopted by TGm for the 802.16m amendment.

NoticeThis document does not represent the agreed views of the IEEE 802.16 Working Group or any of its subgroups. It represents only the views of the participants listed in the “Source(s)” field above. It is offered as a basis for discussion. It is not binding on the contributor(s), who reserve(s) the right to add, amend or withdraw material contained herein.

ReleaseThe contributor grants a free, irrevocable license to the IEEE to incorporate material contained in this contribution, and any modifications thereof, in the creation of an IEEE Standards publication; to copyright in the IEEE’s name any IEEE Standards publication even though it may include portions of this contribution; and at the IEEE’s sole discretion to permit others to reproduce in whole or in part the resulting IEEE Standards publication. The contributor also acknowledges and accepts that this contribution may be made public by IEEE 802.16.

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IEEE C802.16m-09/0102r4

Proposed Text of Enhanced Structured LDPC coding with rate matching for the IEEE 802.16m Amendment

Wu ZhanjiBeijing University of Posts and Telecommunications(BUPT)

Wataru Matsumoto, Toshiyuki Kuze Mitsubishi Electric Corporation

Philip V. Orlik, Andreas F. Molisch, Zhifeng (Jeff) Tao, Jinyun Zhang

Mitsubishi Electric Research Laboratories

Xu jin, Sun BoZTE

Luo Zhendong, Du YingCATR

1. Introduction

In this contribution, we proposed the parity-check matrix construction of LDPC codes to achieve good performance for wide range of code word length and code rate. We informed the parity-check matrix construction method which can support the code rate range from 1/3, 1/2,2/3,3/4 to 5/6, the information length from 192bits to 9040bits. Through expanding and puncturing one predefined uniform base matrix, the structured LDPC codes defined here can be used to support any rate and any code size defined above. ZTE and Mitsubishi are two prominent spearheads to push structured LDPC codes in 3GPP LTE meetings, and they have made some brilliant contributions about it[1-4].On their shoulders, we further optimize the parity-check matrix construction of LDPC to improve its error performance, which is called “enhanced structured LDPC codes with rate matching” in the following.

2. Enhanced Structured LDPC coding

2.1 Code structure and code description

2.1.1 Basic description of structured LDPC codes

The parity check matrix of structured LDPC Codes is defined by a matrix H of size m-by-n, where n is the length of the codeword and m is the number of parity bits in the code. The number of information bits is k=n-m.

IEEE C802.16m-09/0102r4The matrix H is defined as:

where is one of a set of z-by-z permutation or a z-by-z zero matrix. The matrix H is expanded from a

binary base matrix of size , where .The base matrix is expanded by replacing each 1 in the base matrix with a z-by-z permutation matrix, and each 0 with a z-by-z zero matrix. Through changing the expand factor z, a LDPC set of variable information length and certain code rate can be obtained.

If integer ,define .

If integer , define and

P is a standard permutation matrix of the form:

And of size has the form:

Due to the structured characteristic of parity check matrix, the parity check matrix of LDPC codes can be fully described by small set parameters, which results in very low complexity implementations. Actually we only need base matrix , instead of parity check matrix H, to perform encoding and decoding. The encoding

and decoding algorithms become the matrix calculation of size , the basic structure of encoder and decoder only depends on the positions of the non-negative-one elements in the base matrix.

2.1.2 Structured LDPC Mother Code set with different code sizes

To generate a LDPC code set of a certain code rate and various code sizes, a uniform base matrix is defined. In order to obtain the base matrix of certain code size, the uniform base matrix has to be modified to generate a modified base matrix , which will really be used in the encoder/decoder of the LDPC code of certain code size.

IEEE C802.16m-09/0102r4The code rate of the designed mother code sets is always 1/2, and the designed information block sizes

increase from 192 to 9040, and the increasing step is 16, That is to say, K=192,192+16,192+2*16,192+3*16,…, 9040. The size of base matrix is 16×32，namely, and . So expand factors z =12:1:565. One

uniform base matrix of rate 1/2 LDPC code set is defined as following:

To obtain the LDPC code of certain code size, the uniform base matrix above has to be modified and then can be regarded as the base matrix , which together with expand factor z can be used to define the parity check matrix H of the LDPC code.

For each non-negative-one elements of the uniform base matrix above, the value should be modified.

Let represents the i-th row, j-th column element of modified base matrix ,

represents the i-th row, j-th column element of the uniform base matrix given by us. Then

is the largest expand factor, here equals to 565, and z is the currently used expand factor uniquely corresponding to the currently used code size. denotes the operation that rounds the elements in it to the

IEEE C802.16m-09/0102r4nearest integers towards minus infinity.

2.2 Multi-rate support of LDPC

By puncturing parity bits from the LDPC mother code block, LDPC codes of rate higher than 1/2 can be generated.

Assume that k denotes the information block size, n means the codeword block size, the number of parity bits (or equalization) equals to m = n-k, whereas n, k and m all are integers larger than zero. Define that

denotes the number of rows of base matrix , denotes the number of columns of base matrix , and

, and z means the expand factor of structured LDPC codes.

2.1 Puncturing operations to obtain LDPC codes of rate higher than 1/2

Puncturing operations to rate 1/2 LDPC mother codes are needed, while obtaining LDPC code of rate lager than 1/2. The basic design principle is that information block size of mother LDPC codes should be close to m as possibly as we can, which may better utilize the characteristic of structured LDPC mother codes of variable code sizes. If the information block size of mother code is always larger than k, a little zeros bits need to be added before the information block of size k. Then the encoder of LDPC mother code shall be performed. Finally, these added zero bits need to be deleted, and further certain amount codeword bits still need to be deleted to generate the codeword of size n.

There are three steps to perform the encode process of (n, k) Punctured LDPC codes.

Step 1: Compute the expand factor . Based on the uniform base matrix and the expand

factor z, LDPC mother code can be obtained, here = 16 and = 32.

Step 2: Add zero bits before the information bits of size k, and constitute bits

information block of mother code. Perform the encode process of mother code, and parity bits will be generated, here is always less than z.

Step 3: Delete the added zero bits in Step 2. If the number of codeword bits after the deletion doesn’t equal to N, parity bits in the predefined position of codeword need to be punctured.

The puncture positions are one of the key elements of the performance of punctured LDPC codes, thus the puncture position need to be selected carefully. Figure 2.1 is an example of puncture position of code rate 2/3 . The mother code is divided into parts, and each part contains z bits. Label the positions of the bits of the

mother codeword block from 0 to .

Figure 2.1 Puncture position of code rate 2/3 LDPC

These three processes of code puncturing are depicted in Figure 2.2. The new codeword length of the code is n. The corresponding information length is given as k. Consequently, the code rate r equals to k/n.

Figure 2.2 LDPC Mother Codeword and punctured LDPC codeword

IEEE C802.16m-09/0102r4

Mother Codeword

Punctured Codeword

2.2.2 LDPC codes of supporting any rate and any code size

Finally, there are three steps operation as following can cover all cases.

Step 1: Compute the expand factor according to the formula: .

Then, based on the uniform base matrix and the expand factor z, LDPC mother code

can be obtained, here = 16, = 32,and .

Step 2: Add zero bits before the information bits of size K, and constitute bits

information block of mother code. Perform the encode process of mother code, and parity bits can be generated.

Step 3: Delete the added zero bits in Step 2. If the number of codeword bits after the deletion doesn’t equal to N, bits in the predefined position of codeword need to be deleted.

When code rate ,y bits in the tail of codeword block shall be deleted.

When code rate

Define puncture pattern vector P of size as following:

The elements of vector P are different integers from to , and the permutation order of these

elements in vector P shall be predefined. Here, the size of is , vector P is defined as

P=[17，19，21，23，25，27，31，29，18，24，22，28，30，20，26]。The following parameters are defined:

and

Label the positions of the bits of the mother codeword block from 0 to , then the puncturing positions of y deleted bits in the mother codeword block have been defined:

, (1-th z bits deleted)

IEEE C802.16m-09/0102r4, (2-th z bits deleted)

, (k-th z bits deleted)

. (m bits deleted)

2.2.3 Extending operations to obtain LDPC codes of rate lower than 1/2

Extending operations to rate 1/2 LDPC mother codes are needed, while obtaining LDPC code of rate lower than 1/2. The structure of the extended parity-check is shown as follows:

Figure 2.3 Extended parity-check matrix structure

There are three steps to perform the encode process of (n, k) Extended LDPC codes.

Step 1: Compute , and then rows and columns shall be added to the last row and

the last column of to generate an extended base matrix of size ,

here . is depicted by Figure 2.3.The whole extended base matrix

after expanding is shown as follows:

IEEE C802.16m-09/0102r4

Step 2: Compute the expand factor .

Step 3: can be modified into by .

is the base matrix of LDPC code.

2. Performance of rate matching LDPC code

In this proposal, we compare the FER performance of higher rate LDPC codes and lower rate LDPC codes with the following codes.,respectively. Turbo codes in 3GPP[1] LDPC codes in Mitsubishi[2] Enhanced Structured LDPC codes.Table 3.1 gives the parameters used in the comparisons.

Table 3.1 Parameters

Parameter Value

Information block size (k) 530,1060,2020,5114

Coding rate 1/2,2/3,3/4,5/6

Modulation scheme QPSK

Channel model AWGN

Decoding scheme Turbo: Log-MAP MaxIterner=8LDPC: Log-BP MaxIterner=50

Fig3.1 to fig3.4 are the comparison results between turbo codes and Enhanced Structured LDPC codes

IEEE C802.16m-09/0102r4with higher rate.

0 1 2 3 4 5 6 710

-4

10-3

10-2

10-1

100

Eb/N0

FER

AWGN,QPSK,K=530,Turbo:Log-MAP(ite=8),LDPC:Log-BP(ite=50)

LDPC r=1/2LDPC r=2/3LDPC r=3/4LDPC r=5/6Turbo r=1/2Turbo r=2/3Turbo r=3/4Turbo r=5/6

r=1/2 r=2/3

r=3/4r=5/6

Fig3.1 k=530, coding rate =1/2,2/3,3/4,5/6

0 1 2 3 4 5 610

-4

10-3

10-2

10-1

100

Eb/N0

FER



r=1/2 r=2/3 r=3/4 r=5/6

Fig3.2 k=1060, coding rate =1/2,2/3,3/4,5/6

IEEE C802.16m-09/0102r4

0 1 2 3 4 5 610

-4

10-3

10-2

10-1

100

Eb/N0

FER



r=1/2 r=2/3 r=3/4 r=5/6

Fig3.3 k=2020, coding rate =1/2,2/3,3/4,5/6

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.510

-6

10-5

10-4

10-3

10-2

10-1

100

Eb/N0

FER



r=1/2 r=2/3

r=3/4 r=5/6

Fig3.4 k=5114, coding rate =1/2,2/3,3/4,5/6

IEEE C802.16m-09/0102r4

Fig3.5 to fig3.8 are the comparison results between LDPC in Mitsubishi and Enhanced Structured LDPC codes with higher rate.

0.5 1 1.5 2 2.5 3 3.5 4 4.5 510

-4

10-3

10-2

10-1

100

Eb/N0

BE

RK=570,compare between our result and Mitsubishi

LDPC r=1/2LDPC r=2/3Mitsubishi r=1/2Mitsubishi r=2/3

r=1/2 r=2/3

Fig3.5 k=570, coding rate =1/2,2/3

0.5 1 1.5 2 2.5 3 3.5 4 4.5 510

-4

10-3

10-2

10-1

100

Eb/N0

FER

K=570,compare between our result and Mitsubishi


r=1/2 r=2/3


IEEE C802.16m-09/0102r4

0.5 1 1.5 2 2.5 3 3.5 4 4.510

-4

10-3

10-2

10-1

100

Eb/N0

BE

R



r=1/2 r=2/3


0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.510

-4

10-3

10-2

10-1

100

Eb/N0

FER



r=1/2 r=2/3


IEEE C802.16m-09/0102r4Fig3.9 are the comparison between Turbo codes and Enhanced Structured LDPC codes with lower rate.

-0.5 0 0.5 1 1.5 2 2.5

10-4

10-3

10-2

10-1

100

Eb/N0

FER

Rate=1/3,Fer Comparision between BUPT and Turbo

Turbo530NewBUPT 530Turbo1060NewBUPT 1060TurboNewBUPT 2020Turbo5114NewBUPT 5114

Fig 3.9 rate=1/3,length=530,1060,2020,5114

3. Conclusion

As compared with turbo codes, when code rate is higher than 1/2 or the code size is large, the error performance of the enhanced structured LDPC codes is obviously better than that of turbo codes; As compared with turbo codes, when code rate is lower, the error performance of the enhanced structured LDPC codes is better and successfully overcomes the error floor effect, especially when the code size is large.

As compared with Mitsubishi’s LDPC codes, our enhanced structured LDPC exhibit superior error performance for mother half rate and similar performance for higher rate.

LDPC codes are cutting-edge coding scheme, so the improvement of LDPC codes still exists. Structured LDPC codes can support flexible code rate and code size, and exhibit the better error performance than turbo codes for large code size and high code rate. In addition, thanks to its nature parallel decoding scheme, it can achieve much higher throughput than Turbo codes for decoding hardware implementations, which is very crucial for the future communication system. In a word, we think these advantages will make it a wining rival that exceeds turbo codes in the future channel coding method. In addition, the combinations of LDPC codes and other technologies, such as coding-modulation, HARQ, and AMC, are becoming the hot research topics recently. Based on our proposed LDPC codes, we will make our contributions on these fields in the future.

4. Acknowledgement

IEEE C802.16m-09/0102r4This research is sponsored by the National Natural Science Foundation of China (grant No. 60702050).

5. Reference

[1] ZTE. Structured LDPC coding with rate matching. 3GPP TSG RAN WG1 #44bis R1-061019 .Athens, Greece, 27– 31 March, 2006Mar. 2006[2] Mitsubishi Electric Corporation Performance improvement of the rate-compatible LDPC codes. 3GPP TSG RAN WG1 Meeting #44 R1- 060525 Denver, USA, 13 – 17 February, 2006[3] J. Hagenauer, “Rate-compatible punctured convolutional codes (RCPC codes) and their applications,” IEEE Trans. Commun., vol. 36, pp.389–400, Apr. 1988.[4] J. Li and K. Narayanan, “Rate-compatible low density parity check codes for capacity-approaching ARQ scheme in packet data communications,” presented at the Int. Conf. on Comm., Internet, and Info. Tech.(CIIT), Nov. 2002.

6. Text proposal for inclusion in the 802.16m amendment

[In Section 11.13.1 Insert the following text]

===================Start of Proposed Text====================15.3.X Channel Coding and HARQ

15.3.X.X LDPC Code structure and code description

15.3.X.X.1 Basic description of structured LDPC codes

The parity check matrix of structured LDPC Codes is defined by a matrix H of size m-by-n, where n is the length of the codeword and m is the number of parity bits in the code. The number of information bits is k=n-m.

The matrix H is defined as:

where is one of a set of z-by-z permutation or a z-by-z zero matrix. The matrix H is expanded from a

binary base matrix of size , where .The base matrix is expanded by replacing each 1 in the base matrix with a z-by-z permutation matrix, and each 0 with a z-by-z zero matrix. Through changing the expand factor z, a LDPC set of variable information length and certain code rate can be obtained.

IEEE C802.16m-09/0102r4

If integer ,define .

If integer , define and

P is a standard permutation matrix of the form:

And of size has the form:

Due to the structured characteristic of parity check matrix, the parity check matrix of LDPC codes can be fully described by small set parameters, which results in very low complexity implementations. Actually we only need base matrix , instead of parity check matrix H, to perform encoding and decoding. The encoding

and decoding algorithms become the matrix calculation of size , the basic structure of encoder and decoder only depends on the positions of the non-negative-one elements in the base matrix.

15.3.X.X.2 Structured LDPC Mother Code set with different code sizes

To generate a LDPC code set of a certain code rate and various code sizes, a uniform base matrix is defined. In order to obtain the base matrix of certain code size, the uniform base matrix has to be modified to generate a modified base matrix , which will really be used in the encoder/decoder of the LDPC code of certain code size.

The code rate of the designed mother code sets is always 1/2, and the designed information block sizes increase from TBD to TBD, and the increasing step is TBD, That is to say, K=TBD. The size of base matrix is TBD，namely, and . So expand factors z =TBD. One uniform base matrix of rate 1/2 LDPC code set is defined as following:

TBD (the below matrix is one example),

IEEE C802.16m-09/0102r4

TBD (the below matrix is one example),

To obtain the LDPC code of certain code size, the uniform base matrix above has to be modified and then can be regarded as the base matrix , which together with expand factor z can be used to define the parity check matrix H of the LDPC code.

For each non-negative-one elements of the uniform base matrix above, the value should be modified.

Let represents the i-th row, j-th column element of modified base matrix ,

represents the i-th row, j-th column element of the uniform base matrix given by us. Then

is the largest expand factor, here equals to TBD, and z is the currently used expand factor uniquely corresponding to the currently used code size. denotes the operation that rounds the elements in it to the nearest integers towards minus infinity.

15.3.X.X.3 Base Matrix Generation for LDPC encode process

The maximum number of soft channel bits available in the virtual buffer is which is signaled from higher

layers from each HARQ transmission. is the maximum possible codeword size for the encode of k

information bits in the scenario of full Incremental Redundancy.

IEEE C802.16m-09/0102r4

Here, and let .

Let . There are three steps to generate the needed base matrix. If ，Step 1 is needed;

Otherwise, Step 1 is neglect, and and .

Step 1: Compute , and then rows and columns shall be added to the

last row and the last column of to generate an extended base matrix

of size , here . is depicted by Figure 3.The whole

extended base matrix after expanding is shown as follows: TBD (the below matrix is one example),

TBD

or its splitted matrix

IEEE C802.16m-09/0102r4

Step 2: Compute the expand factor .

Step 3: can be modified into by .

is the base matrix of LDPC code.

15.3.X.X.4 LDPC encode process

The LDPC HARQ mother codeword shall be generated and then sent to HARQ buffer. There are two steps for encode process:

Step 1 Pad zero bits before K bits information block and perform the encode process of

LDPC code. parity bits shall be generated.

Step 2 Delete the padded zero bits in Step 1. If the number of codeword bits after the deletion doesn’t equal to

, parity bits in the tail shall be deleted.

15.3.X.X.5 HARQ mother codeword permutations

Permute puncturing parity bits of LDPC HARQ mother codeword and keep the order of systematic bits and

extending parity. Let the coded bits before the permutation be , let the coded bits after the

permutation be . The permutation is defined by

(15.3.x.x.5-1)

Here, indicates the i-th element of the puncturing pattern vector , . PV=TBD;

IEEE C802.16m-09/0102r415.3.X.X.6 HARQ codeword bits selection

(The HARQ codeword bits selection method is TBD)

====================End of Proposed Text====================

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