psoc®creator™ projectdatasheetforcy8ckit- 059...

PSoC® Creator™Project Datasheet for CY8CKIT-

059_DDS_BeaconCreation Time: 09/27/2016 11:54:37

User: koseki-7\kosekiProject: CY8CKIT-059_DDS_Beacon

Tool: PSoC Creator 3.3 CP3

Cypress Semiconductor198 Champion Court

San Jose, CA 95134-1709Phone (USA): 800.858.1810Phone (Intl): 408.943.2600

http://www.cypress.com

Copyright

CY8CKIT-059_DDS_Beacon Datasheet 09/27/2016 11:54

CopyrightCopyright © 2016 Cypress Semiconductor Corporation. All rights reserved. Any design information orcharacteristics specifically provided by our customer or other third party inputs contained in this document are notintended to be claimed under Cypress's copyright.

TrademarksPSoC and CapSense are registered trademarks of Cypress Semiconductor Corporation. PSoC Creator is atrademark of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referencedherein are the property of their respective owners.

Philips I2C Patent RightsPurchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a licenseunder the Philips I2C Patent Rights to use these components in an I2C system, provided that the systemconforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 PhilipsSemiconductors has a new trade name, NXP Semiconductors.

DisclaimerCYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THISMATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY ANDFITNESS FOR A PARTICULAR PURPOSE. While reasonable precautions have been taken, Cypress assumesno responsibility for any errors that may appear in this document. Cypress reserves the right to make changeswithout further notice to the materials described herein. Cypress does not assume any liability arising out of theapplication or use of any product or circuit described herein. Cypress does not authorize its products for use ascritical components in life support systems where a malfunction or failure may reasonably be expected to result insignificant injury to the user. The inclusion of a Cypress product in a life support systems application implies thatthe manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Flash Code ProtectionCypress products meet the specifications contained in their particular Cypress PSoC Datasheets. Cypressbelieves that its family of PSoC products is one of the most secure families of its kind on the market today,regardless of how they are used. There may be methods, unknown to Cypress, that can breach the codeprotection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. NeitherCypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protectiondoes not mean that we are guaranteeing the product as 'unbreakable.'Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection isconstantly evolving. We at Cypress are committed to continuously improving the code protection features of ourproducts.

Contents

CY8CKIT-059_DDS_Beacon Datasheet 09/27/2016 11:54

Table of Contents

1 Overview............................................................................................................................................... 12 Pins....................................................................................................................................................... 4

2.1 Hardware Pins........................................................................................................................... 52.2 Hardware Ports.......................................................................................................................... 72.3 Software Pins............................................................................................................................. 9

3 System Settings.................................................................................................................................. 113.1 System Configuration............................................................................................................... 113.2 System Debug Settings........................................................................................................... 113.3 System Operating Conditions.................................................................................................. 11

4 Clocks................................................................................................................................................. 124.1 System Clocks......................................................................................................................... 134.2 Local and Design Wide Clocks................................................................................................ 13

5 Interrupts and DMAs........................................................................................................................... 155.1 Interrupts.................................................................................................................................. 155.2 DMAs....................................................................................................................................... 15

6 Flash Memory..................................................................................................................................... 167 Design Contents................................................................................................................................. 17

7.1 Schematic Sheet: Page 1........................................................................................................ 177.2 Schematic Sheet: Page 2........................................................................................................ 187.3 Schematic Sheet: ........................................................................................................ 19

8 Components....................................................................................................................................... 208.1 Component type: Comp [v2.0]................................................................................................. 20

8.1.1 Instance Comp_1.......................................................................................................... 208.1.2 Instance Comp_2.......................................................................................................... 208.1.3 Instance Comp_3.......................................................................................................... 20

8.2 Component type: Counter [v3.0].............................................................................................. 218.2.1 Instance Counter........................................................................................................... 21

8.3 Component type: CyControlReg [v1.80].................................................................................. 228.3.1 Instance Control_Reg_1................................................................................................228.3.2 Instance Control_Reg_Sel............................................................................................ 238.3.3 Instance Control_Reg_Tx..............................................................................................23

8.4 Component type: CyStatusReg [v1.90]....................................................................................248.4.1 Instance Status_Reg_1................................................................................................. 248.4.2 Instance Status_Reg_Sel.............................................................................................. 248.4.3 Instance Status_Reg_Tx............................................................................................... 25

8.5 Component type: I2C [v3.50]................................................................................................... 258.5.1 Instance I2C_1.............................................................................................................. 26

8.6 Component type: OpAmp [v1.90].............................................................................................278.6.1 Instance Opamp_1........................................................................................................ 27

8.7 Component type: PWM [v3.30]................................................................................................ 278.7.1 Instance PWM_Window................................................................................................ 27

8.8 Component type: SPI_Master [v2.50]...................................................................................... 298.8.1 Instance SPIM............................................................................................................... 29

8.9 Component type: VDAC8 [v1.90]............................................................................................. 308.9.1 Instance VDAC8_1........................................................................................................ 308.9.2 Instance VDAC8_2........................................................................................................ 30

9 Other Resources.................................................................................................................................32

1 Overview

CY8CKIT-059_DDS_Beacon Datasheet 09/27/2016 11:54 1

1 Overview

The Cypress PSoC 5 is a family of 32-bit devices with the following characteristics:

• High-performance 32-bit ARM Cortex-M3 core with a nested vectored interrupt controller (NVIC)and a high-performance DMA controller

• Digital system that includes configurable Universal Digital Blocks (UDBs) and specific functionperipherals, such as USB, I2C and SPI

• Analog subsystem that includes 20-bit Delta Sigma converters (ADC), SAR ADCs, 8-bit DACsthat can be configured for 12-bit operation, comparators, op amps and configurable switchedcapacitor (SC) and continuous time (CT) blocks to create PGAs, TIAs, mixers, and more

• Several types of memory elements, including SRAM, flash, and EEPROM• Programming and debug system through JTAG, serial wire debug (SWD), and single wire

viewer (SWV)• Flexible routing to all pins

Figure 1 shows the major components of a typical CY8C58LP family member PSoC 5 device. Fordetails on all the systems listed above, please refer to the PSoC 5 Technical Reference Manual .

Figure 1. CY8C58LP Device Family Block Diagram

http://www.cypress.com/go/CY8C58LP

http://www.cypress.com/go/psoc5lp_trm

1 Overview


Table 1 lists the key characteristics of this device.

Table 1. Device CharacteristicsName Value

Part Number CY8C5888LTI-LP097Package Name 68-QFNArchitecture PSoC 5Family CY8C58LPCPU speed (MHz) 80Flash size (kBytes) 256SRAM size (kBytes) 64EEPROM size (Bytes) 2048Vdd range (V) 1.71 to 5.5Automotive qualified No (Industrial Grade Only)Temp range (Celcius) -40 to 85JTAG ID 0x2E161069

NOTE: The CPU speed noted above is the maximum available speed. The CPU is clocked by BusClock, listed in the System Clocks section below.

Table 2 lists the device resources that this design uses:

Table 2. Device ResourcesResource Type Used Free Max % Used

Digital Clocks 4 4 8 50.00 %Analog Clocks 0 4 4 0.00 %CapSense Buffers 0 2 2 0.00 %Digital Filter Block 0 1 1 0.00 %Interrupts 4 28 32 12.50 %IO 23 25 48 47.92 %Segment LCD 0 1 1 0.00 %CAN 2.0b 0 1 1 0.00 %I2C 1 0 1 100.00 %USB 0 1 1 0.00 %DMA Channels 0 24 24 0.00 %Timer 0 4 4 0.00 %UDBMacrocells 43 149 192 22.40 %Unique P-terms 74 310 384 19.27 %Total P-terms 81Datapath Cells 6 18 24 25.00 %Status Cells 9 15 24 37.50 %Status Registers 3StatusI Registers 4Sync Cells (x1) 1Routed Count7 Load/Enable 1

Control Cells 6 18 24 25.00 %Control Registers 5Count7 Cells 1

Opamp 1 3 4 25.00 %Comparator 3 1 4 75.00 %Delta-Sigma ADC 0 1 1 0.00 %LPF 0 2 2 0.00 %SAR ADC 0 2 2 0.00 %

1 Overview


Resource Type Used Free Max % UsedAnalog (SC/CT) Blocks 0 4 4 0.00 %DACVIDAC 2 2 4 50.00 %

2 Pins


2 Pins

Figure 2 shows the pin layout of this device.

Figure 2. Device Pin Layout

2 Pins


2.1 Hardware Pins

Table 3 contains information about the pins on this device in device pin order. (No connection ["n/c"]pins have been omitted.)

Table 3. Device Pins

Pin Port Name Type Drive Mode Reset State1 P2[6] ROT_B Software

InputRes pull up HiZ Analog Unb

2 P2[7] GPIO [unused] HiZ Analog Unb3 P12[4] SIO [unused] HiZ Analog Unb4 P12[5] SIO [unused] HiZ Analog Unb5 VSSB VSSB Dedicated6 IND IND Dedicated7 VB VB Dedicated8 VBAT VBAT Dedicated9 VSSD VSSD Power10 XRES_N XRES_N Dedicated11 P1[0] Debug:SWD_IO Reserved12 P1[1] Debug:SWD_CK Reserved13 P1[2] GPIO [unused] HiZ Analog Unb14 P1[3] Debug:SWV Reserved15 P1[4] MON_1 Software

OutputStrong drive HiZ Analog Unb

16 P1[5] MON_2 Dgtl Out Strong drive HiZ Analog Unb17 VDDIO1 VDDIO1 Power18 P1[6] MON_3 Dgtl Out Strong drive HiZ Analog Unb19 P1[7] FQ_UD Dgtl Out Strong drive HiZ Analog Unb20 P12[6] M_SCLK Dgtl Out Strong drive HiZ Analog Unb21 P12[7] SIO [unused] HiZ Analog Unb22 P15[6] USB IO [unused] HiZ Analog Unb23 P15[7] USB IO [unused] HiZ Analog Unb24 VDDD VDDD Power25 VSSD VSSD Power26 VCCD VCCD Power27 P15[0] GPIO [unused] HiZ Analog Unb28 P15[1] GPIO [unused] HiZ Analog Unb29 P3[0] RX_SIG Analog HiZ analog HiZ Analog Unb30 P3[1] CAR_DET Analog HiZ analog HiZ Analog Unb31 P3[2] GPIO [unused] HiZ Analog Unb32 P3[3] GPIO [unused] HiZ Analog Unb33 P3[4] GPIO [unused] HiZ Analog Unb34 P3[5] DDS_CLK_IN Analog HiZ analog HiZ Analog Unb35 VDDIO3 VDDIO3 Power36 P3[6] GPIO [unused] Reserved37 P3[7] GPIO [unused] HiZ Analog Unb38 P12[0] SCL Dgtl I/O OD, DL HiZ Analog Unb39 P12[1] SDA Dgtl I/O OD, DL HiZ Analog Unb40 P15[2] GPIO [unused] HiZ Analog Unb41 P15[3] GPIO [unused] HiZ Analog Unb42 VCCA VCCA Power43 VSSA VSSA Power44 VDDA VDDA Power

2 Pins


Pin Port Name Type Drive Mode Reset State45 VSSD VSSD Power46 P12[2] SIO [unused] HiZ Analog Unb47 P12[3] M_MOSI Dgtl Out Strong drive HiZ Analog Unb48 P0[0] GPIO [unused] HiZ Analog Unb49 P0[1] GPIO [unused] HiZ Analog Unb50 P0[2] GPIO [unused] HiZ Analog Unb51 P0[3] GPIO [unused] HiZ Analog Unb52 VDDIO0 VDDIO0 Power53 P0[4] GPIO [unused] HiZ Analog Unb54 P0[5] GPIO [unused] HiZ Analog Unb55 P0[6] GPIO [unused] HiZ Analog Unb56 P0[7] GPIO [unused] HiZ Analog Unb57 VCCD VCCD Power58 VSSD VSSD Power59 VDDD VDDD Power60 P15[4] TX_OUT Dgtl Out Strong drive HiZ Analog Unb61 P15[5] Ext_LED Dgtl Out Strong drive HiZ Analog Unb62 P2[0] GPIO [unused] HiZ Analog Unb63 P2[1] LED Software


64 P2[2] GPIO [unused] HiZ Analog Unb65 P2[3] SEL Software


66 P2[4] TX SoftwareInput

Res pull up HiZ Analog Unb

67 VDDIO2 VDDIO2 Power68 P2[5] ROT_A Software


Abbreviations used in Table 3 have the following meanings:• Res pull up = Resistive pull up• HiZ Analog Unb = Hi-Z Analog Unbuffered• Dgtl Out = Digital Output• HiZ analog = High impedance analog• Dgtl I/O = Digital In/Out• OD, DL = Open drain, drives low

2 Pins


2.2 Hardware Ports

Table 4 contains information about the pins on this device in device port order. (No connection ["n/c"],power and dedicated pins have been omitted.)

Table 4. Device Ports

Port Pin Name Type Drive Mode Reset StateP0[0] 48 GPIO [unused] HiZ Analog UnbP0[1] 49 GPIO [unused] HiZ Analog UnbP0[2] 50 GPIO [unused] HiZ Analog UnbP0[3] 51 GPIO [unused] HiZ Analog UnbP0[4] 53 GPIO [unused] HiZ Analog UnbP0[5] 54 GPIO [unused] HiZ Analog UnbP0[6] 55 GPIO [unused] HiZ Analog UnbP0[7] 56 GPIO [unused] HiZ Analog UnbP1[0] 11 Debug:SWD_IO ReservedP1[1] 12 Debug:SWD_CK ReservedP1[2] 13 GPIO [unused] HiZ Analog UnbP1[3] 14 Debug:SWV ReservedP1[4] 15 MON_1 Software


P1[5] 16 MON_2 Dgtl Out Strong drive HiZ Analog UnbP1[6] 18 MON_3 Dgtl Out Strong drive HiZ Analog UnbP1[7] 19 FQ_UD Dgtl Out Strong drive HiZ Analog UnbP12[0] 38 SCL Dgtl I/O OD, DL HiZ Analog UnbP12[1] 39 SDA Dgtl I/O OD, DL HiZ Analog UnbP12[2] 46 SIO [unused] HiZ Analog UnbP12[3] 47 M_MOSI Dgtl Out Strong drive HiZ Analog UnbP12[4] 3 SIO [unused] HiZ Analog UnbP12[5] 4 SIO [unused] HiZ Analog UnbP12[6] 20 M_SCLK Dgtl Out Strong drive HiZ Analog UnbP12[7] 21 SIO [unused] HiZ Analog UnbP15[0] 27 GPIO [unused] HiZ Analog UnbP15[1] 28 GPIO [unused] HiZ Analog UnbP15[2] 40 GPIO [unused] HiZ Analog UnbP15[3] 41 GPIO [unused] HiZ Analog UnbP15[4] 60 TX_OUT Dgtl Out Strong drive HiZ Analog UnbP15[5] 61 Ext_LED Dgtl Out Strong drive HiZ Analog UnbP15[6] 22 USB IO [unused] HiZ Analog UnbP15[7] 23 USB IO [unused] HiZ Analog UnbP2[0] 62 GPIO [unused] HiZ Analog UnbP2[1] 63 LED Software


P2[2] 64 GPIO [unused] HiZ Analog UnbP2[3] 65 SEL Software


P2[4] 66 TX SoftwareInput


P2[5] 68 ROT_A SoftwareInput


P2[6] 1 ROT_B SoftwareInput


P2[7] 2 GPIO [unused] HiZ Analog Unb

2 Pins


Port Pin Name Type Drive Mode Reset StateP3[0] 29 RX_SIG Analog HiZ analog HiZ Analog UnbP3[1] 30 CAR_DET Analog HiZ analog HiZ Analog UnbP3[2] 31 GPIO [unused] HiZ Analog UnbP3[3] 32 GPIO [unused] HiZ Analog UnbP3[4] 33 GPIO [unused] HiZ Analog UnbP3[5] 34 DDS_CLK_IN Analog HiZ analog HiZ Analog UnbP3[6] 36 GPIO [unused] ReservedP3[7] 37 GPIO [unused] HiZ Analog Unb

Abbreviations used in Table 4 have the following meanings:• HiZ Analog Unb = Hi-Z Analog Unbuffered• Dgtl Out = Digital Output• Dgtl I/O = Digital In/Out• OD, DL = Open drain, drives low• Res pull up = Resistive pull up• HiZ analog = High impedance analog

2 Pins


2.3 Software Pins

Table 5 contains information about the software pins on this device in alphabetical order. (Onlysoftware-accessible pins are shown.)

Table 5. Software Pins

Name Port Type Reset StateCAR_DET P3[1] Analog HiZ Analog UnbDDS_CLK_IN P3[5] Analog HiZ Analog UnbDebug:SWD_CK P1[1] ReservedDebug:SWD_IO P1[0] ReservedDebug:SWV P1[3] ReservedExt_LED P15[5] Dgtl Out HiZ Analog UnbFQ_UD P1[7] Dgtl Out HiZ Analog UnbGPIO [unused] P3[7] HiZ Analog UnbGPIO [unused] P0[7] HiZ Analog UnbGPIO [unused] P0[4] HiZ Analog UnbGPIO [unused] P3[6] ReservedGPIO [unused] P3[3] HiZ Analog UnbGPIO [unused] P3[4] HiZ Analog UnbGPIO [unused] P3[2] HiZ Analog UnbGPIO [unused] P0[1] HiZ Analog UnbGPIO [unused] P0[5] HiZ Analog UnbGPIO [unused] P0[3] HiZ Analog UnbGPIO [unused] P0[2] HiZ Analog UnbGPIO [unused] P15[3] HiZ Analog UnbGPIO [unused] P15[2] HiZ Analog UnbGPIO [unused] P0[0] HiZ Analog UnbGPIO [unused] P0[6] HiZ Analog UnbGPIO [unused] P15[1] HiZ Analog UnbGPIO [unused] P2[2] HiZ Analog UnbGPIO [unused] P2[0] HiZ Analog UnbGPIO [unused] P1[2] HiZ Analog UnbGPIO [unused] P15[0] HiZ Analog UnbGPIO [unused] P2[7] HiZ Analog UnbLED P2[1] Software

OutputHiZ Analog Unb

M_MOSI P12[3] Dgtl Out HiZ Analog UnbM_SCLK P12[6] Dgtl Out HiZ Analog UnbMON_1 P1[4] Software

OutputHiZ Analog Unb

MON_2 P1[5] Dgtl Out HiZ Analog UnbMON_3 P1[6] Dgtl Out HiZ Analog UnbROT_A P2[5] Software

InputHiZ Analog Unb

ROT_B P2[6] SoftwareInput

HiZ Analog Unb

RX_SIG P3[0] Analog HiZ Analog UnbSCL P12[0] Dgtl I/O HiZ Analog UnbSDA P12[1] Dgtl I/O HiZ Analog UnbSEL P2[3] Software

InputHiZ Analog Unb

SIO [unused] P12[5] HiZ Analog Unb

2 Pins


Name Port Type Reset StateSIO [unused] P12[4] HiZ Analog UnbSIO [unused] P12[7] HiZ Analog UnbSIO [unused] P12[2] HiZ Analog UnbTX P2[4] Software

InputHiZ Analog Unb

TX_OUT P15[4] Dgtl Out HiZ Analog UnbUSB IO [unused] P15[7] HiZ Analog UnbUSB IO [unused] P15[6] HiZ Analog Unb

Abbreviations used in Table 5 have the following meanings:• HiZ Analog Unb = Hi-Z Analog Unbuffered• Dgtl Out = Digital Output• Dgtl I/O = Digital In/Out

For more information on reading, writing and configuring pins, please refer to:• Pins chapter in the System Reference Guide

o CyPins API routines• Programming Application Interface section in the cy_pins component datasheet

http://www.cypress.com/go/comp_cy_boot

http://www.cypress.com/go/comp_cy_pins

3 System Settings


3 System Settings

3.1 System Configuration

Table 6. System Configuration SettingsName Value

Device Configuration Mode CompressedEnable Error Correcting Code (ECC) FalseStore Configuration Data in ECC Memory TrueInstruction Cache Enabled TrueEnable Fast IMO During Startup TrueUnused Bonded IO Allow but warnHeap Size (bytes) 0x800Stack Size (bytes) 0x2000Include CMSIS Core Peripheral Library Files True

3.2 System Debug Settings

Table 7. System Debug SettingsName Value

Debug Select SWD+SWV (serialwire debug and

viewer)Enable Device Protection FalseEmbedded Trace (ETM) FalseUse Optional XRES False

3.3 System Operating Conditions

Table 8. System Operating ConditionsName Value

Variable VDDA FalseVDDA (V) 5.0VDDD (V) 5.0VDDIO0 (V) 5.0VDDIO1 (V) 5.0VDDIO2 (V) 5.0VDDIO3 (V) 5.0Temperature Range 0C - 85/125C

4 Clocks


4 Clocks

The clock system includes these clock resources:• Four internal clock sources increase system integration:

o 3 to 74.7 MHz Internal Main Oscillator (IMO) ±1% at 3 MHzo 1 kHz, 33 kHz, and 100 kHz Internal Low Speed Oscillator (ILO) outputso 12 to 80 MHz clock doubler output, sourced from IMO, MHz External Crystal Oscillator

(MHzECO), and Digital System Interconnect (DSI)o 24 to 80 MHz fractional Phase-Locked Loop (PLL) sourced from IMO, MHzECO, and DSI

• Clock generated using a DSI signal from an external I/O pin or other logic• Two external clock sources provide high precision clocks:

o 4 to 25 MHz External Crystal Oscillator (MHzECO)o 32.768 kHz External Crystal Oscillator (kHzECO) for Real Time Clock (RTC)

• Dedicated 16-bit divider for bus clock• Eight individually sourced 16-bit clock dividers for the digital system peripherals• Four individually sourced 16-bit clock dividers with skew for the analog system peripherals• IMO has a USB mode that synchronizes to USB host traffic, requiring no external crystal for

USB. (USB equipped parts only)

Figure 3. System Clock Configuration

4 Clocks


4.1 System Clocks

Table 9 lists the system clocks used in this design.

Table 9. System ClocksName Domain Source Desired

FreqNominalFreq

Accuracy(%)

Startat

Reset

Enabled

BUS_CLK DIGITAL MASTER_CLK ? MHz 66 MHz ±0.25 True TrueMASTER_CLK DIGITAL PLL_OUT ? MHz 66 MHz ±0.25 True TruePLL_OUT DIGITAL IMO 66 MHz 66 MHz ±0.25 True TrueUSB_CLK DIGITAL IMO 48 MHz 48 MHz ±0.25 False TrueIMO DIGITAL 24 MHz 24 MHz ±0.25 True TrueDigital Signal DIGITAL DDS_CLK 10 MHz 10 MHz ±0 False TrueILO DIGITAL ? MHz 100 kHz -55,+100 True TrueXTAL 32kHz DIGITAL 32.768

kHz? MHz ±0 False False

XTAL DIGITAL 24 MHz ? MHz ±0 False False

4.2 Local and Design Wide Clocks

Local clocks drive individual analog and digital blocks. Design wide clocks are a user-definedoptimization, where two or more analog or digital blocks that share a common clock profile (frequency,etc) can be driven from the same clock divider output source.

Figure 4. Local and Design Wide Clock Configuration

Table 10 lists the design wide clocks used in this design.

Table 10. Design Wide ClocksName Domain Source Desired

FreqNominalFreq

Accuracy(%)

Startat

Reset

Enabled

Dds_Clock DIGITAL DDS_CLK 10 MHz 10 MHz ±0 True True

Table 11 lists the local clocks used in this design.

Table 11. Local ClocksName Domain Source Desired

FreqNominalFreq

Accuracy(%)

Startat

Reset

Enabled

I2C_1_BusClock DIGITAL BUS_CLK ? MHz 66 MHz ±0.25 True TrueCNTR_CLK DIGITAL MASTER_CLK ? MHz 33 MHz ±0.25 True TrueREG_CLK DIGITAL MASTER_CLK ? MHz 33 MHz ±0.25 True True

4 Clocks


Name Domain Source DesiredFreq

NominalFreq

Accuracy(%)

Startat

Reset

Enabled

Clock_1 DIGITAL MASTER_CLK 1 MHz 1 MHz ±0.25 True True

For more information on clocking resources, please refer to:• Clocking System chapter in the PSoC 5 Technical Reference Manual• Clocking chapter in the System Reference Guide

o CyPLL API routineso CyIMO API routineso CyILO API routineso CyMaster API routineso CyXTAL API routines



5 Interrupts and DMAs


5 Interrupts and DMAs

5.1 Interrupts

This design contains the following interrupt components: (0 is the highest priority)

Table 12. InterruptsName Priority Vector

I2C_1_I2C_IRQ 7 15ISR_Compare 7 0SPIM_RxInternalInterrupt 7 1SPIM_TxInternalInterrupt 7 2

For more information on interrupts, please refer to:• Interrupt Controller chapter in the PSoC 5 Technical Reference Manual• Interrupts chapter in the System Reference Guide

o CyInt API routines and related registers• Datasheet for cy_isr component

5.2 DMAs

This design contains no DMA components.



http://www.cypress.com/go/comp_cy_isr

6 Flash Memory


6 Flash Memory

PSoC 5 devices offer a host of Flash protection options and device security features that you canleverage to meet the security and protection requirements of an application. These requirementsrange from protecting configuration settings or Flash data to locking the entire device from externalaccess.

Table 13 lists the Flash protection settings for your design.

Table 13. Flash Protection SettingsStart

AddressEnd

AddressProtection Level

0x0 0x3FFFF U - Unprotected

Flash memory is organized as rows with each row of flash having 256 bytes. Each flash row can beassigned one of four protection levels:

• U - Unprotected• F - Factory Upgrade• R - Field Upgrade• W - Full Protection

For more information on Flash memory and protection, please refer to:• Flash Protection chapter in the PSoC 5 Technical Reference Manual• Flash and EEPROM chapter in the System Reference Guide

o CyWrite API routineso CyFlash API routines



7 Design Contents


7 Design Contents

This design's schematic content consists of the following 3 schematic sheets:

7.1 Schematic Sheet: Page 1

Figure 5. Schematic Sheet: Page 1

This schematic sheet contains the following component instances:• Instance Comp_1 (type: Comp_v2_0)• Instance I2C_1 (type: I2C_v3_50)• Instance SPIM (type: SPI_Master_v2_50)• Instance VDAC8_2 (type: VDAC8_v1_90)

7 Design Contents




This schematic sheet contains the following component instances:• Instance Comp_2 (type: Comp_v2_0)• Instance Comp_3 (type: Comp_v2_0)• Instance Control_Reg_1 (type: CyControlReg_v1_80)• Instance Control_Reg_Sel (type: CyControlReg_v1_80)• Instance Control_Reg_Tx (type: CyControlReg_v1_80)• Instance Opamp_1 (type: OpAmp_v1_90)• Instance Status_Reg_1 (type: CyStatusReg_v1_90)• Instance Status_Reg_Sel (type: CyStatusReg_v1_90)• Instance Status_Reg_Tx (type: CyStatusReg_v1_90)• Instance VDAC8_1 (type: VDAC8_v1_90)

7 Design Contents




This schematic sheet contains the following component instances:• Instance Counter (type: Counter_v3_0)• Instance PWM_Window (type: PWM_v3_30)

8 Components


8 Components

8.1 Component type: Comp [v2.0]

8.1.1 Instance Comp_1

Description: Analog voltage comparator.Instance type: Comp [v2.0]Datasheet: online component datasheet for Comp

Table 14. Component Parameters for Comp_1ParameterName

Value Description

Hysteresis Enable Enable to add output hysteresis.Pd_Override Disable Power down override to allow

comparator to continueoperating during sleep.

Polarity Non Inverting Allows output to be inverted.Speed Fast Set comparator response

speed.Sync Bypass Allows synchronization with

clock.




Value Description

Hysteresis Enable Enable to add output hysteresis.Pd_Override Disable Power down override to allow

comparator to continueoperating during sleep.

Polarity Non Inverting Allows output to be inverted.Speed Fast Set comparator response


clock.




Value Description

Hysteresis Enable Enable to add output hysteresis.

http://www.cypress.com/go/comp_Comp



8 Components


ParameterName

Value Description

Pd_Override Disable Power down override to allowcomparator to continueoperating during sleep.

Polarity Non Inverting Allows output to be inverted.Speed Slow Set comparator response


clock.

8.2 Component type: Counter [v3.0]

8.2.1 Instance Counter

Description: 8, 16, 24 or 32-bit CounterInstance type: Counter [v3.0]Datasheet: online component datasheet for Counter

Table 17. Component Parameters for CounterParameter Name Value Description

CaptureMode Rising Edge Defines the functionality of thecapture input. Default is Nonewhich does not have a capture

input pinClockMode Up Counter Defines the operation of the

counter. \nBasic: Count isincremented on the rising edgeof the clock input. \n Clock_-And_Direction: Clock is

incremented or decremented onthe rising edge of the clock inputbased on the direction of theinput. \nClock_And_UpCnt_-

DwnCnt: Clock is anoversampling clock. On therising edge of UpCnt, the

counter is incremented and onthe rising edge of DwnCnt, the

counter is decremented.CompareMode Software

ControlledSpecifies the compare output

mode.CompareStatusEdgeSense true Specifies whether rising edge

sense for interrupt generationwith the Compare output will be

used. May be disabled toreduce resource usage.

CompareValue 255 Defines the compare value.Valid vales are from 0 to the

period value.EnableMode Software Only Choose which enable controls

the enable of the counter. Thiscan be either through softwarewith the control register, throughhardware with the input pin or acombination of both where bothmust be active for the counter to

be enabled.

http://www.cypress.com/go/comp_Counter

8 Components


Parameter Name Value DescriptionFixedFunction false Defines whether Fixed Function

Block usage is required.InterruptOnCapture false Enables the counter status

register to produce an interruptoutput signal on a capture

event.InterruptOnCompare false Enables the counter status

register to produce an interruptoutput signal on compare true.

InterruptOnOverUnderFlow false Enables the counter statusregister to produce an interruptoutput signal on over flow or

under flow.InterruptOnTC false Enables the counter status

register to produce an interruptoutput signal on terminal count.

Period 65535 Defines the counter periodvalue in clock counts from 1 to

2^Width-1.ReloadOnCapture true Reloads the counter value to a

set value on a capture inputevent.

ReloadOnCompare false Reloads the counter value to aset value on a compare equal

event.ReloadOnOverUnder false Reloads the counter value to a

set value when overflow orunderflow is detected.

ReloadOnReset true Reloads the counter value to aset value when reset input is

high.Resolution 24 Defines the width of the counter.

It can be 8, 16, 24 or 32 (24 or32 cannot use Fixed Function

block).RunMode Continuous Define the hardware operation

to run continuously or run till aterminal count.

UseInterrupt true Allows for complete optimizationof resource usage down to

removing the status register ifnot required by the user.

8.3 Component type: CyControlReg [v1.80]

8.3.1 Instance Control_Reg_1

Description: The Control Register allows the firmware to set values for to use for digitalsignals.Instance type: CyControlReg [v1.80]Datasheet: online component datasheet for CyControlReg

Table 18. Component Parameters for Control_Reg_1Parameter Name Value DescriptionBit0Mode DirectMode Defines bit 0 modeBit1Mode DirectMode Defines bit 1 modeBit2Mode DirectMode Defines bit 2 mode

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8 Components


Parameter Name Value DescriptionBit3Mode DirectMode Defines bit 3 modeBit4Mode DirectMode Defines bit 4 modeBit5Mode DirectMode Defines bit 5 modeBit6Mode DirectMode Defines bit 6 modeBit7Mode DirectMode Defines bit 7 modeBitValue 0 Defines bit valueBusDisplay false Displays the output terminals as

busExternalReset false Shows the reset terminalNumOutputs 1 Defines the number of outputs

needed (1-8)

8.3.2 Instance Control_Reg_Sel


Table 19. Component Parameters for Control_Reg_SelParameter Name Value DescriptionBit0Mode DirectMode Defines bit 0 modeBit1Mode DirectMode Defines bit 1 modeBit2Mode DirectMode Defines bit 2 modeBit3Mode DirectMode Defines bit 3 modeBit4Mode DirectMode Defines bit 4 modeBit5Mode DirectMode Defines bit 5 modeBit6Mode DirectMode Defines bit 6 modeBit7Mode DirectMode Defines bit 7 modeBitValue 0 Defines bit valueBusDisplay false Displays the output terminals as


needed (1-8)

8.3.3 Instance Control_Reg_Tx


Table 20. Component Parameters for Control_Reg_TxParameter Name Value DescriptionBit0Mode DirectMode Defines bit 0 modeBit1Mode DirectMode Defines bit 1 modeBit2Mode DirectMode Defines bit 2 modeBit3Mode DirectMode Defines bit 3 modeBit4Mode DirectMode Defines bit 4 modeBit5Mode DirectMode Defines bit 5 modeBit6Mode DirectMode Defines bit 6 modeBit7Mode DirectMode Defines bit 7 mode



8 Components


Parameter Name Value DescriptionBitValue 0 Defines bit valueBusDisplay false Displays the output terminals as


needed (1-8)

8.4 Component type: CyStatusReg [v1.90]

8.4.1 Instance Status_Reg_1

Description: The Status Register allows the firmware to read values from digital signals.Instance type: CyStatusReg [v1.90]Datasheet: online component datasheet for CyStatusReg

Table 21. Component Parameters for Status_Reg_1ParameterName

Value Description

Bit0Mode Transparent Bit Mode for Bit 0 of the StatusRegister








BusDisplay false Displays the input terminals asbus

Interrupt false Shows the interrupt terminalMaskValue 0 Defines the value of the

interrupt maskNumInputs 1 Defines the number of status

inputs (1-8)

8.4.2 Instance Status_Reg_Sel


Table 22. Component Parameters for Status_Reg_SelParameterName

Value Description



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8 Components


ParameterName

Value Description










inputs (1-8)

8.4.3 Instance Status_Reg_Tx


Table 23. Component Parameters for Status_Reg_TxParameterName

Value Description












inputs (1-8)

8.5 Component type: I2C [v3.50]


8 Components


8.5.1 Instance I2C_1

Description: Standard I2C communication interfaceInstance type: I2C [v3.50]Datasheet: online component datasheet for I2C

Table 24. Component Parameters for I2C_1Parameter Name Value Description

Address_Decode Hardware Determines either hardware orsoftware address match logic.

BusSpeed_kHz 100 I2C Data Rate in kbps.Standard settings are 50, 100,400 or 1000. The value must be

between 1 and 1000.EnableWakeup false Determines if I2C is selected as

wakeup source.ExternalBuffer false Exposes scl and sda in and out

terminals outside thecomponent.

Externi2cIntrHandler false Allows I2C interrupt handler tobe set outside the I2Ccomponent. This feature

intended only for PM/SM bususage.

ExternTmoutIntrHandler false Allows I2C timeout interrupthandler to be set outside theI2C component. This featureintended only for PM/SM bus

usage.Hex false Indicates that address has been

input in hexadecimal format.I2C_Mode Master Determines I2C mode

(Slave/Master/Multi-Master/Multi-Master-Slave).

I2cBusPort Any Determines which I2C pins havebeen selected. Select I2C0/I2C1and connect to correspondingpins to be able use I2C as

wakeup source.Implementation FixedFunction Determines either I2C

implementation Fixed Functionor UDB.

NotSlaveClockMinusTolerance 25 Internal component clocknegative tolerance value inMaster, Multi-Master or Multi-

Master-Slave mode.NotSlaveClockPlusTolerance 5 Internal component clock

positive tolerance value inMaster, Multi-Master or Multi-

Master-Slave mode.PrescalerEnabled false Enables prescaler (7-bit

counter) to expand timeouttimer range.

PrescalerPeriod 1 Prescaler period of timeouttimer.

SclTimeoutEnabled false Enables low time monitoring ofscl line.

http://www.cypress.com/go/comp_I2C

8 Components


Parameter Name Value DescriptionSdaTimeoutEnabled false Enables low time monitoring of

sda line.Slave_Address 8 7-bits I2C slave address.SlaveClockMinusTolerance 5 Internal component clock

negative tolerance value inSlave mode.

SlaveClockPlusTolerance 50 Internal component clockpositive tolerance value in Slave

mode.TimeoutImplementation UDB Determines either timeout timer

feature implementation as UDBor Fixed Function. The FixedFunction implementation only

available for PSoC5LP.TimeOutms 25 Determines maximum time

allowed for scl or sda to be lowstate (in mS). The timeout timergenerates interrupt after timeout

expires.TimeoutPeriodff 1563 Period of timeout timer (Fixed

Function).TimeoutPeriodUdb 39999 Period of timeout timer (UDB).UdbInternalClock false Determines either internal or

external clock source for I2CUDB.

UdbSlaveFixedPlacementEnable false Enables fixed placement for I2CUDB. Only available in slave

mode.

8.6 Component type: OpAmp [v1.90]

8.6.1 Instance Opamp_1

Description: OpampInstance type: OpAmp [v1.90]Datasheet: online component datasheet for OpAmp

Table 25. Component Parameters for Opamp_1ParameterName

Value Description

Mode Follower Selects between uncommittedop-amp or follower mode.

Power Low Power Selects the device power level.

8.7 Component type: PWM [v3.30]

8.7.1 Instance PWM_Window

Description: 8 or 16-bit Pulse Width ModulatorInstance type: PWM [v3.30]Datasheet: online component datasheet for PWM

Table 26. Component Parameters for PWM_Window

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8 Components


Parameter Name Value DescriptionCaptureMode None Defines the functionality of the

capture Input. The parameterdetermines which signal on thecapture input is required to

capture the current count valueto the FIFO.

CompareStatusEdgeSense true Enables edge sense detectionon compare outputs for use in

edge sensitive interruptsCompareType1 Less or

EqualSets the compare value

comparison type setting for thecompare 1 output

CompareType2 Less Sets the compare valuecomparison type setting for the

compare 2 outputCompareValue1 22849 Compares Output 1 to valueCompareValue2 63 Compares Output 2 to valueDeadBand Disabled Defines whether dead band

outputs are desired or not.DeadTime 1 Defines the number of required

dead band clock cyclesDitherOffset 0.00 Allows the user to implement

dither to get more bits out of a 8or 16 bit PWM.

EnableMode SoftwareOnly

Specifies the method ofenabling the PWM. This can beeither hardware or software.

FixedFunction false Determines whether the fixedfunction counter timer is used or

the UDB implementation isused.

InterruptOnCMP1 false Enables the interrupt oncompare1 true event

InterruptOnCMP2 false Enables the interrupt oncompare2 true event

InterruptOnKill false Enables the interrupt on a killevent

InterruptOnTC true Enables the interrupt onterminal count event

KillMode Disabled Parameter to select the killmode for build time.

MinimumKillTime 1 Sets the minimum number ofclock cycles that a kill must beactive on the outputs when

KillMode is set to Minimum KillTime mode

Period 27419 Defines the PWM period valuePWMMode One

OutputDefines the overall mode of the

PWMResolution 16 Defines the bit width of the

PWM (8 or 16 bits)RunMode One Shot

with SingleTrigger

Defines the run mode options tobe either continuous or one shot

TriggerMode None Determines the mode of startingthe PWM, i.e. triggering the

PWM counter to start

8 Components


Parameter Name Value DescriptionUseInterrupt true Enables the placement and

usage of the status register

8.8 Component type: SPI_Master [v2.50]

8.8.1 Instance SPIM

Description: Serial Peripheral Interface MasterInstance type: SPI_Master [v2.50]Datasheet: online component datasheet for SPI_Master

Table 27. Component Parameters for SPIMParameter Name Value Description

BidirectMode false Bidirectional mode settingClockInternal false Allow use of the internal clock

and desired bit rate or anexternal clock source

DesiredBitRate 1000000 Desired Bit Rate in bpsHighSpeedMode false Enables using of the High

Speed ModeInterruptOnByteComplete false Set Initial Interrupt Source to

Enable Interrupt on ByteTransfer Complete

InterruptOnRXFull false Set Initial Interrupt Source toEnable Interrupt on RX FIFO

FullInterruptOnRXNotEmpty true Set Initial Interrupt Source to

Enable Interrupt on RX FIFONot Empty

InterruptOnRXOverrun false Set Initial Interrupt Source toEnable Interrupt on RX FIFO

OverrunInterruptOnSPIDone false Set Initial Interrupt Source to

Enable Interrupt on SPI DoneInterruptOnSPIIdle false Set Initial Interrupt Source to

Enable Interrupt on SPI IdleInterruptOnTXEmpty false Set Initial Interrupt Source to

Enable Interrupt on TX FIFOEmpty

InterruptOnTXNotFull true Set Initial Interrupt Source toEnable Interrupt on TX FIFO

Not FullMode CPHA =

0, CPOL= 0

SPI mode defines the ClockPhase and Clock Polarity

desiredNumberOfDataBits 8 Set the Number of Data bits 3-

16RxBufferSize 5 Defines the amount of RAM Set

asside for the RX BufferShiftDir LSB First Set the Shift Out DirectionTxBufferSize 5 Defines the amount of RAM Set

asside for the TX BufferUseRxInternalInterrupt true Defines whether Rx internal

interrupt is used or notUseTxInternalInterrupt true Defines whether Tx internal

interrupt is used or not

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8 Components


8.9 Component type: VDAC8 [v1.90]

8.9.1 Instance VDAC8_1

Description: 8-Bit Voltage DACInstance type: VDAC8 [v1.90]Datasheet: online component datasheet for VDAC8

Table 28. Component Parameters for VDAC8_1Parameter Name Value DescriptionData_Source CPU or DMA (Data Bus) Selects the method in which the

data is written to the vDAC.Initial_Value 25 Configures the initial vDAC

output voltage. The output usesthe following relation: Initial

output voltage =value*(FullRange/255). This

calculated output voltage valueis invalid if DAC Bus is used.

Strobe_Mode Register Write Selects how the data is strobedinto the DAC. For a registerwrite, the data is strobed intothe DAC on each CPU or DMAwrite. If operating in Externalmode, an external data strobe

signal is required.VDAC_Range 0 - 1.020V (4mV/bit) Specifies the full voltage scale

range of the vDACVDAC_Speed Low Speed Specifies the vDAC settling

speed. Note that the 'SlowSpeed' selection consumes less

power.Voltage 100 This parameter sets the voltage

value.

8.9.2 Instance VDAC8_2

Description: 8-Bit Voltage DACInstance type: VDAC8 [v1.90]Datasheet: online component datasheet for VDAC8

Table 29. Component Parameters for VDAC8_2Parameter Name Value DescriptionData_Source CPU or DMA (Data Bus) Selects the method in which the

data is written to the vDAC.Initial_Value 137 Configures the initial vDAC

output voltage. The output usesthe following relation: Initial

output voltage =value*(FullRange/255). This

calculated output voltage valueis invalid if DAC Bus is used.

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8 Components


Parameter Name Value DescriptionStrobe_Mode Register Write Selects how the data is strobed

into the DAC. For a registerwrite, the data is strobed intothe DAC on each CPU or DMAwrite. If operating in Externalmode, an external data strobe

signal is required.VDAC_Range 0 - 1.020V (4mV/bit) Specifies the full voltage scale

range of the vDACVDAC_Speed Low Speed Specifies the vDAC settling

speed. Note that the 'SlowSpeed' selection consumes less

power.Voltage 548 This parameter sets the voltage

value.

9 Other Resources


9 Other Resources

The following documents contain important information on Cypress software APIs that might berelevant to this design:

• Standard Types and Defines chapter in the System Reference Guideo Software base typeso Hardware register typeso Compiler defineso Cypress API return codeso Interrupt types and macros

• Registerso The full PSoC 5 register map is covered in the PSoC 5 Registers Technical Reference

Manualo Register Access chapter in the System Reference Guide§ CY_GET API routines§ CY_SET API routines

• System Functions chapter in the System Reference Guideo General API routineso CyDelay API routineso CyVd Voltage Detect API routines

• Power Managemento Power Supply and Monitoring chapter in the PSoC 5 Technical Reference Manualo Low Power Modes chapter in the PSoC 5 Technical Reference Manualo Power Management chapter in the System Reference Guide§ CyPm API routines

• Watchdog Timer chapter in the System Reference Guideo CyWdt API routines

• Cache Managemento Cache Controller chapter in the PSoC 5 Technical Reference Manualo Cache chapter in the System Reference Guide§ CyFlushCache() API routine


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