pyxis spt hep

Technical MarketingDeep Submicron Division

Pyxis Self Paced Tutorialwith Generic Design Kit

July, 2013

2 2013 Mentor Graphics Corp. Company Confidentialwww.mentor.com

Pyxis Self Paced TurtorialContents

Tutorials1. Pyxis_SPT_Stage_1_Data_Management2. Pyxis_SPT_Stage_2_Design_Capture3. Pyxis_SPT_Stage_3_Analog_Simulation4. Pyxis_SPT_Stage_4_Mixed_Signal_Verification5. Pyxis_SPT_Stage_5_Analysis_of_Layout_Parasitics6. Pyxis_SPT_Stage_6_Layout_Viewing_and_Editing7. Pyxis_SPT_Stage_7_Floorplanning_and_Assembly8. Pyxis_SPT_Stage_8_Schematic_Driven_Layout9. Pyxis_SPT_Stage_9_Automated_Layout

Quick Start Recipes1. Pyxis_QSR_Setup_Hotkey_Example2. Pyxis_QSR_Customizing_the_Pyxis_GUI3. Pyxis_QSR_Register_Custom_Data_Type_and_Tool

Pyxis QSR April, 2013

3 2013 Mentor Graphics Corp. Company Confidentialwww.mentor.comPyxis SPT April 2013

Pyxis Self Paced Tutorialwith Generic Design Kit

Tutorials


Pyxis Self Paced Tutorial

Pyxis Design Environment

Physical Verification

DRC, LVS, xRC

Schematic Design

Hierarchical Schematics

Design Verification

Mixed Signal

High Level Design and Verification

Floorplanning and

Assembly

Physical Layout Implementation

Full-Custom Layout

Automated Layout

HDL Compilation and Registration

Analog

RF

Parasitic Modeling Area EstimationDesign Configuration

Pyxis SPT/HEP, July 2013


Pyxis Self Paced Tutorial Stage 1: Design Data Management



DRC, LVS, xRC

Design Capture


Design Verification

Mixed Signal


Floorplanning and

Assembly


Full-Custom Layout

Automated Layout

HDL Compilation and Registration

Analog

RF

Parasitic Modeling Area EstimationDesign Configuration



Stage 1: Design Data ManagementIn this session, you will

See overview of Pyxis Design Manager

Perform the following tasks: Open online

documentation Navigate and open

design data Create a new project Copy hierarchical data



Stage 1: Design Data ManagementData Management Requirements for Custom ICs

Organized structure Support language models

PROJECT ONE

Design Library(Digital)

Design Library(Analog)

Design Library(Testbenches)

Design Library(Stimuli)

PROJECT TWO

Design Library(DSP)

Design Library(ADC/DAC)

Design Library(RF)

Design Library(Simulations)

REFERENCE LIBRARIES

Technology Design Kit

Standard Cell Library

Pad Cell Library

Analog Cell Library

Hierarchy Management Revision Control



Stage 1: Design Data ManagementPyxis Project Manager

Project Based Data Management - intuitive Windows style navigation

LCV Style Data Organization

Register 3rd Party Tools and Data

API for Revision Control Subversion 1.4.6



Stage 1: Design Data ManagementOrganized Structure



Hierarchy Management Updates design references upon rename Design references automatically

corrected on copied set Build Hierarchical Configurations and

Releases Hierarchical Copy, Move, Delete

Multi-project Support View Multiple Projects in One Session

Project Cloning

View and Sort by Data Attributes

Object Type, Description, Size, Permissions, Date Modified, Lock

Stage 1: Design Data ManagementKey Features

User and Site wide Customization

Customize Toolbars, Hotkeys, Menus

Register custom data types

Register custom tools Scripting



Stage 1: Design Data ManagementStep 1: Open Pyxis_SPT Project Data

1. From the Pyxis_SPT directory, run the ./open_Pyxis_SPT script

NOTES:The Pyxis_SPT tarball will unpack into a directory called Pyxis_SPT. There are two script files:

setup_Pyxis_SPT will reset the Pyxis_SPT project to the original state. Only use this to initialize or reset your data

open_Pyxis_SPT will open the Pyxis_SPT project as it was last saved

open_Pyxis_SPT will take two options:-mysettings will use your current tool home directory-default will use default tool settings



Stage 1: Design Data ManagementStep 2: Getting Help Users Manual

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1. In the Pyxis Project Navigator window, select the pull-down menu item Help->Open Users Manual

NOTE:Help in the form of documentation, tutorials and live support is available at all IC design stages when using Pyxis.



Stage 1: Design Data ManagementStep 3: Viewing Object Attributes

The Pyxis Project Navigator has two primary windows for viewing IC design data the explorer pane on the left and the view pane on the right

1. In the Pyxis Project Navigator window, position your mouse over the column header and use the RMB (Right Mouse Button) pop-up menu to view object types for the explorer pane and the view pane as shown

NOTE:Each object type has its own distinctive icon.

1:RMB

Explorer Pane View Pane



Stage 1: Design Data ManagementStep 4: Hierarchical Object Types

1. Select the GenericPLL Library under the Pyxis_SPT project

2. Examine the object types shown in both the explorer and view panes

NOTES:Pyxis Hierarchical Objects include:Project A design project.Library - A design library within a project that contains IC design data. This is generally where new designs are created.External Library A reference library containing IC design data. This is generally static.Logic Library - A reference library containing only logic (process independent) data.Technology Library - A technology design kit with one or more technology configurations that specify the symbols, parameterized devices, rule decks and simulations.Category A container within a Library containing IC design data.Component Set A virtual grouping of cells.Cell A piece of a hierarchical IC design containing Schematic, Symbol, Layout and other relevant views.

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Stage 1: Design Data ManagementStep 5: Design View Types

1. Select the cell Pyxis_SPT/ GenericPLL/ charge_pump_ub

2. Examine the view types shown in the view panes

3. Double Click on the Schematic view type to open the schematic

NOTE:Shown are generally the most common IC Design view types. Additional view types can be managed in Pyxis, including custom views that require custom tools.

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3


Stage 1: Design Data ManagementStep 6: Opening a Schematic

1. Briefly examine the charge_pump_ub schematic in Pyxis Schematic before closing the window

NOTE:There are 4 tutorials in the Pyxis SPT covering the Pyxis Schematic editor on the topics of Design Capture, Mixed Signal Verification, Analog Simulation and Analysis of Post-Layout Parastics.


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Stage 1: Design Data ManagementStep 7: Opening a Layout

1. Double Click on the Layout view type to open the charge_pump_ub_layout view


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Stage 1: Design Data ManagementStep 8: Opening a Layout

1. Briefly examine the charge_pump_ub_layout in Pyxis Layout before closing the window

NOTES:There are 4 tutorials in the Pyxis SPT covering the Pyxis Layout editor on the topics of Layout Editing and Viewing, Floorplanning and Assembly, Schematic Driven Layout and Layout Automation. Additionally, you may want to view the tutorial on Analysis of Post-Layout Parastics.


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Stage 1: Design Data ManagementStep 9: View Message and Transcript Areas

1. In the Pyxis Project Manager, click on the Transcript Area tab to display the detailed transcript log

2. Examine the Transcript Area window

3. Repeat for the Message Area window

NOTES:The Message Area displays key messages to the user regarding tool commands while the Transcript Area window provides a detailed log of the commands executed and the results.

The Transcript Area and Message Area windows can be collapsed and expanded, pinned at the bottom or top of the Pyxis window, or detached as a separate window.

1Pyxis SPT/HEP, July 2013


Stage 1: Design Data ManagementStep 10: Create a New Project

1. Select the Pyxis_SPT project

2. Click on the New Project icon in the toolbar on the left hand side

3. Append the Project path with MyProject to specify the name of the new project

4. Enable the Derive Settings from Existing Project option and OK the New Project form

NOTES:The new project will have the same Technology Library and Configuration (settings) as the Existing Project as specified in step 1.

A Technology Library can have multiple Configurations - this addresses the need for process variants

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Stage 1: Design Data ManagementStep 11: Specify Reference Libraries

1. OK the Manage External/Logic Libraries form to use the default reference libraries from the original project

NOTE:Reference Libraries can be changed on a selected project or external library using the pull-down menu item Edit-> External/Logic Libraries command.

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Stage 1: Design Data ManagementStep 12: Create Design Library

1. Click on the New Library icon in the toolbar on the left hand side

2. Enter MyLibrary as the new library name and OK the form

NOTE:Multiple projects can be viewed inside of the Project Navigator even when they are attached to different technology libraries or technology configurations.

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Stage 1: Design Data ManagementStep 13: Copy Design Object

1. In Project Navigator select the Pyxis_SPT/ GenericPLL/ FreqSynth cell and select the popup menu item: RMB (Right Mouse Button)-> Copy

NOTE:The Pyxis Project Navigator window supports common hotkeys for copying and moving dataControl+c CopyControl+x CutControl+v - PasteControl+Shift+v Paste Special for special options like hierarchical copy.

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Stage 1: Design Data ManagementStep 14: Paste Design Hierarchy (Follow references)

1. Select the newly created MyLibrary library

2. With you mouse hovering of the MyLibrary library, select the popup menu item: RMB->Paste Special menu

3. In the Copy Object form, enable the Follow references option, then OK the form

NOTE:If you do not want to change the name of the copied object, you can leave the Name field blank.

2:RMB

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1



Stage 1: Design Data ManagementStep 15: Check References

1. Examine the results of the copy

You should see the copied cell FreqSynth, as well as a new library under your project named GenericPLL. This contains the leafs of the FreqSynth design.

2. Select the FreqSynth cell under MyLibrary

3. Click on the Check References icon

NOTE:Pyxis Design Manager preserves the data hierarchy structure of copied hierarchical data.

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3



Stage 1: Design Data ManagementStep 16: Examine Copied Design References

1. Examine the hierarchical references of the newly copied FreqSynth design in the Change/Fix References form before clicking on the Cancel button to close the form

You will see references to leaf cells that have been copied into the GenericPLL library under the MyProject project. You should also see references to external libraries, logic libraries and the technology library generic13.

NOTE:The Change/Fix References form helps us to see what references are in the selected objects and to quickly change or fix them.

1Pyxis SPT/HEP, July 2013


Stage 1: Design Data ManagementStep 17: Select and Cut Leaf Cells

1. Select the MyProject/ GenericPLL library in the explorer pane

2. Select one of the cells in the view pane,

3. Enter the hotkey Control-A to select all of the cells under the MyProject/ GenericPLL library

4. Select the pop-up menu item: RMB->Cut

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4:RMB

3: Control-a


Stage 1: Design Data ManagementStep 18: Create New Category for Leaf Cells

1. Select the MyLibrary library

2. Click on the New Category icon

3. In the New Category form, specify the object name to be PLL_Leafs

NOTE:Like directories in a file system, categories can be created inside of libraries and inside of other categories

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Stage 1: Design Data ManagementStep 19: Paste Leaf Cells into New Category

1. Select the newly created PLL_Leafs category

2. Select the pop-up menu item: RMB-> Paste

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2:RMB


Stage 1: Design Data ManagementStep 20: Check Design References

The references to the moved data will be updated automatically by Pyxis. We can verify this by looking at the Check References form again

1. Select the FreqSynth cell

2. Click on the Check References icon

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2



Stage 1: Design Data ManagementStep 21: Verify Updated Design References

1. Examine the hierarchical references of the updated FreqSynth design in the Change/Fix References form before clicking on the Cancel button to close the form

You will see references to leaf cells are now updated to point to the new location in the MyProjects/MyLibrary/PLL_Leafs category

This concludes the Design Data Management tutorial. Please feel free to explore this data further or move on to the next stage in the Pyxis_SPT.



Stage 1: Design Data ManagementSummary

Pyxis Project Manager provides:

Intuitive and structured design organization

Support for all major IC design formats including the Schematic, Symbol, and Layout

Interactive data management on individual components or full design hierarchies



Pyxis Self Paced Tutorial Stage 2: Design Capture



DRC, LVS, xRC

Transistor Level Schematics

Design Verification

Mixed Signal


Floorplanning and

Assembly


Full-Custom Layout

Automated Layout

Block-Level and HDL Modeling

Analog

RF

Parasitic Modeling Area Estimation

Design Capture


Design Configuration

Pyxis SPT HEP, 2013


Stage 2: Design CaptureIn This Session, you will

See a quick overview of Pyxis Schematic Perform the following tasks:

Create a new schematicInstantiate transistors Use object editor with cycle selection toolbar

Generate a new symbol Instantiate the new symbol into a schematic Perform a transient simulation

Pyxis SPT HEP, 2013


Stage 2: Design CapturePyxis Schematic

Single environment for Design capture Interactive simulation

setup Simulation and analysis of

digital, analog, and/or RF Display DCOP data to

schematic

Back Annotate Post layout spice & DSPF Interactive parasitic

debugging

Language modeling Verilog, VHDL Verilog-AMS, VHDL-AMS SPICE, VerilogA

Hierarchical Model SelectorPyxis SPT HEP, 2013


Stage 2: Design CaptureEdit Object

Technology rule driven device parameter editor dialog box tied to q hotkey

Also available as a dockable, direct edits without extra clicks to Apply

Edit multiple devices at once or use Selection Toolbar to cycle selected objects

Available for existing instances or during add instance

Same editor for both Pyxis Schematic and Layout

Pyxis SPT HEP, 2013


Frames Create CASE/IF/FOR Frames

to configure your design based on the design stage (for example pre-layout, post-layout, LVS)

Implicit Pins Configure a symbols

connectivity with properties enables better support for multiple power supplies

Function Blocks Create more consolidated and

readable designs using Function Blocks to define design hierarchy

Stage 2: Design CaptureAdvanced Constructions

Single-bit adder schematic

8-bit adder schematic

8-bit adder function block

N-bit counter using FOR frame and standard cells with implicit pins

Pyxis SPT HEP, 2013


Stage 2: Design CapturePyxis Schematic User Interface

All Pyxis Session Windows provide Pull-Down and Pop-Up Menus as well as moveable and detachable Toolbars, Palettes and Area Windows

Customizable by user or site-wide

Menubar

PaletteRight Mouse Button Pop-Up Menu

Toolbar

Area Windows

Pyxis SPT HEP, 2013


Stage 2: Design CapturePyxis Schematic Hotkeys

All Pyxis Session Windows provide hotkeys Customizable by user or site-wide

Pyxis SPT HEP, 2013


Stage 2: Design CapturePyxis Schematic Strokes

All Pyxis Session Windows provide Strokes Customizable by user or site-wide

Pyxis SPT HEP, 2013


Stage 2: Design CaptureStep 1: Open Pyxis_SPT Project Data

Pyxis SPT HEP, 2013

If your project is already open, you can skip this step

1. From the Pyxis_SPT directory, source the open_Pyxis_SPT script

NOTES:The Pyxis_SPT tarball will unpack into a directory called Pyxis_SPT. There are two script files:

setup_Pyxis_SPT will reset the Pyxis_SPT project to the original state. Only use this to initialize or reset your data

open_Pyxis_SPT will open the Pyxis_SPT project as it was last saved

open_Pyxis_SPT will take two options:-mysettings will use your current tool home directory-default will use default tool settings


Stage 2: Design CaptureStep 2: Create New Library

1. Select the Pyxis_SPT project

2. Click on the New Library icon in the Project Navigator toolbar

3. Specify the library name to be MyLib and OK the New Library dialog

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3

Pyxis SPT HEP, 2013


Stage 2: Design CaptureStep 3: Create New Schematic

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2

3

1. Select the newly create MyLib library

2. Click on the New Schematic icon in the Project Navigator toolbar

3. Specify the new Cell name to be buffer (leave the Schematic name as schematic) and OK the New Schematic dialog

NOTE:This will open Pyxis Schematic see next slide.

Pyxis SPT HEP, 2013


Stage 2: Design CaptureStep 4: Instantiate a Device Symbol

1

1. Click on the Instance icon in the Edit toolbar

2. In the File Browser, select the symbols category under the generic13 technology library

3. Select the nmos device and OK the dialog

NOTE:You can also use the hotkey i to add an instance.

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3

Pyxis SPT HEP, 2013


Stage 2: Design CaptureStep 5: Place NMOS Instance

(Prior to placing device in canvas)

1. Show the Add Instance dialog by typing q in the schematic canvas

2. Change the Width property to 0.6u(Hit the TAB key to register the change in the dialog, Dont hit Apply or OK)

3. Place the NMOS device in the schematic canvas

NOTES:When adding instances, you dont need to click on the Apply button to save changes the placement click performs the apply.

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3

Pyxis SPT HEP, 2013

1: q


Stage 2: Design CaptureStep 6: Copy NMOS Instance and Edit

1. Select the NMOS instance

2. Enter the hotkey c for copy

3. Place the copy to the right of the first placement

4. Type q to open the Edit Object dialog

The focus will be on the Width property which is the most often edited property.

5. Enter 1.8u and type return

NOTES:Use the mouse wheel to zoom in and zoom out. You can also use diagonal MMB strokes to zoom to an area.

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Pyxis SPT HEP, 2013

5

2: c

1

4: c


In mid-command zooming and panning can be performed by doing a MMB stroke or using your mouse wheel.

Take a moment to become familiar with zooming and panning using MMB (Middle Mouse Button) strokes and if available, your middle mouse scroll wheel before moving to the next step

NOTES:Pyxis Layout recognizes inputs from the mouse scroll wheel on all of its major forms.

Shift +

Control +

Zoom-In Zoom-Out

Pan Horizontal

Pan Vertical

Pyxis SPT January, 2013

Stage 2: Design CaptureZooming and Panning with Middle Mouse Wheel


Stage 2: Design CaptureStep 7: Browse for PMOS Device

1. Type i to open the Add Instance File Browser

2. Select the pmosdevice as shown and click OK

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Pyxis SPT HEP, 2013

1: i


Stage 2: Design CaptureStep 8: Place PMOS Devices

1.Place the M3 pmosinstance as shown

2.Use the same sequence you did for the nmos to copy the pmos

3.Use the q hotkey to edit the width of the second pmos to be 6u

Pyxis SPT HEP, 2013

1 2

3


Stage 2: Design CaptureStep 9: Select All Devices

1. Hold down the shift key and select all four devices (if they arent already selected)

NOTE:The Status toolbar indicates how many total objects are selected.

1:Shift-LMB

Pyxis SPT HEP, 2013

1:Shift-LMB

1:Shift-LMB 1:Shift-LMB


Stage 2: Design CaptureStep 10: Change Common Property

1. Type q to bring of the Edit Object dialog

2. Hit the tab key once to set the focus to the Length property value and then enter 0.14u

3. Hit the Enter key to apply the changes and take down the Edit Object form

NOTE:All the length properties on the instances will be changed together.

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Pyxis SPT HEP, 2013

1: q

3: Enter


Stage 2: Design CaptureStep 11: Cycle Selection

1. Click on the Select and Center icon in the Selection toolbar

2. Click on the Cycle Next icon in the Selection toolbar to view the individual property settings of each device in the selection set

NOTE: Cycle selection has 3 viewing modes:

Select

Select and Zoom

Select and Center

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Pyxis SPT HEP, 2013

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Stage 2: Design CaptureStep 12: Reset Selection

1. Click on the Reset Cycle icon in the Selection toolbar to select and center the original selection set

2. Click on an empty part of the schematic canvas to unselect everything

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Pyxis SPT HEP, 2013

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Stage 2: Design CaptureStep 13: Add Wires

1. Click on the Zoom Out (2x) icon2. Click on the Add Wire icon or type w to add wires3. Draw the wires as shown

Add Wire Tips:-The add wire command remains active until you hit the escape key-Use hotkey f to flip the wire corner

vs

-Use x hotkey to toggle orthogonal wire routing-Use Backspace to delete the last segment if you make a mistake

NOTE:Mouse wheel zooms in/outHotkey w starts Add Wire.

Pyxis SPT HEP, 2013

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Stage 2: Design CaptureStep 15: Add Net Names

1. Click in open space to unselect everything

2. Hold the Shift key and select the four nets shown (segments highlight red when you hover over them)

3. Type l to label the nets

4. Enter these names:a. vdd_imp (return)b. Ain (return)c. Zout (return)d. vss_imp (return)

NOTE:When Multiple nets are selected, the naming order is determined by the top most net, then the left most net.

4c

4a

4d

4b

4

Pyxis SPT HEP, 2013

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Stage 2: Design CaptureStep 16: Add Ports

1. Expand the add ports icon and select Add Port In...

2. Add a Port In to the Ainnet

3. Repeat steps 1 and 2 to add a Port Out to the Zoutnet

4. Click on the Check and Save icon or enter the hotkey Control-x to check for errors and then save the schematic

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Pyxis SPT HEP, 2013

4

NOTE:If there are errors, a report window will appear. You can select object names or handles in the text to find the object. When done, close the report window using the red X icon.


Stage 2: Design CaptureStep 17: Create Symbol

1. Select the pull-down menu item Add->Generate Symbol

2. In the Generate Symbol dialog, click on the Choose Shape button

3. In the Choose a Symbol Shape dialog, specify the shape to be Buffer then OK

4. Click on the Choose Implicit Pins button

5. Enable the two entries in the Set Implicit Pins dialog then OK all the forms

NOTE: To be an implicit pin candidate, a net needs to be named and not attached to a port.

Pyxis SPT HEP, 2013

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Stage 2: Design CaptureStep 18: Check and Save Symbol

1. With the symbol canvas active, click on the Check and Save icon

2. Observe the Transcript Area and Message Area for Check and Save warnings and errors

3. Close the buffer symbol by clicking on the red X icon in its tab

NOTE: If there are errors in the design, a report window is generated.

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Pyxis SPT HEP, 2013

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Stage 2: Design CaptureStep 19: Open Existing Schematic

1. Click on the Browse icon to open an existing schematic

2. Select the schematic view under the Pyxis_SPT/ GenericPLL / Simulations / comparator / tb_comparator cell

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Pyxis SPT HEP, 2013


Stage 2: Design CaptureStep 20: Open Down to a Schematic

1. Use the MMB (Middle Mouse Button) down stroke to descend into the comparator_lc cell

NOTE: You can also select the instance and use the hotkey Shift-e or select the pull-down menu item Context->Open Down.

Pyxis SPT HEP, 2013

1:MMB


Stage 2: Design CaptureStep 21: Instantiate Buffer Symbol

1. Type i to add an instance

2. Browse for the new buffer component (under the Pyxis_SPT / MyLib / buffer cell ) and click OK

3. Type q and notice the properties vdd_imp and vss_imp

You can change these to the name of a net at the level the symbol is placed to configure the inherited connection. This allows control of the power and ground to the devices on the buffer.

4. Place the instance at the output as shown

NOTE: The FSout wire will automatically open when the buffer symbol is placed.

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Pyxis SPT HEP, 2013

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1:i


Stage 2: Design CaptureStep 22: Check and Save

1. Check and Save the updated comparator_lcschematic

There will be two warnings in the log file indicating that implicit connections exist within the schematic.

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Pyxis SPT HEP, 2013


1. Click on the Enter Simulation Mode icon

2. OK the Entering Simulation Mode dialog with the default settings

NOTE: The transient design viewpoint configuration is already setup for a transient simulation.

Stage 2: Design CaptureStep 23: Enter Simulation Mode

Pyxis SPT HEP, 2013

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Stage 2: Design CaptureStep 24: Run Simulation

1. Click on the Run Simulator icon

The simulation Log window will appear showing information on the simulation run.

2. After the Simulation is completed, select the minus, plus and fsout nets

3. Click on the Cross Probe Selected Items toolbar icon

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Pyxis SPT HEP, 2013

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Stage 2: Design CaptureStep 26: View Waveforms

1. Examine the simulation wave form results

This concludes the Design Capture tutorial. Please feel free to continue exploring this material or move on to the next tutorial.

NOTE: Initially, the waveforms are selected, clicking on an empty space will unselect the waveforms to show you the view to the left.

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Pyxis SPT HEP, 2013


Stage 2: Design CaptureSummary

Pyxis Schematic enables users to quickly create and simulate schematics and supports: Fast device placement with streamlined call-back support Multiple device editing

Cycle selection Change common properties on multiple instances

Add wires, net names and ports Symbol generation

Implicit Pins enable designs with multiple powers and grounds

Analog and Mixed-Signal simulation environments

Pyxis SPT HEP, 2013




DRC, LVS, xRC

Transistor Level Schematics

Design Verification

Mixed Signal


Floorplanning and

Assembly


Full-Custom Layout

Automated Layout

Block-Level and HDL Modeling

Analog

RF

Parasitic Modeling Area Estimation

Design Capture

Pyxis Self Paced Tutorial Stage 3: Analog Simulation


Design Configuration




This tutorial stage provides examples of analog simulation techniques using Pyxis Schematic. These examples include:

An introduction to Baselines, Configurations, and States Creating a User Baseline Creating a new configuration for VCO testing Creating a new state for VCO optimum bias setup Creating a new state for VCO frequency measurement Creating a new state for VCO phase noise measurement Creating a new state for VCO Process/Voltage/Temperature corner verification Creating a new configuration for comparator testing and hysteresis measurement Creating a new configuration for op amp testing and phase margin measurement Creating a new state for Monte Carlo op amp phase margin measurement





All the examples demonstrated in stage 3 assume that:

The user has installed the Pyxis Self Paced Tutorial. Refer to Stage 1 of this tutorial.

The environment variable $SPT_HOME has been set to the location of the Pyxis Self Paced Tutorial installation.

The environment variable $AMPLE_PATH has been set to the location of the userware directory. In this tutorial, the userware directory is located at $SPT_HOME/ic_reflibs/tech_libs/userware.

The user has invoked Pyxis Project Navigator. Refer to Stage 1 of this tutorial.

RMB = click the right mouse buttonLMB = click the left mouse buttonMMB = click the middle mouse button



Typical hotkeys used in Schematic Mode:

f view all

i add instance

s enter Simulation Mode

w add wire

x add EZwave cross-probe

Typical hotkeys used in Simulation Mode:

a open Setup Simulation Analysis panel

F open Setup Simulation Forces panel

g open Setup Simulation form

l open Setup Simulation Libraries panel

p open Setup Simulation Params/Sweep panel

r run simulation

s setup environment


71 2013 Mentor Graphics Corp. Company Confidentialwww.mentor.comPyxis SPT/HEP, July 2013

New Concept

Baselines Configurationsand States


Stage 3: Analog SimulationBaselines Configurations and States


During the current Unsaved Session [A], the user edits various simulation settings [D]. Simulation settings may include analysis types, definitions, and parameters. The aggregation of simulation settings is known as the Design Configuration [B]. The simulation settings contained within the Design Configuration directly control the operation of the SimMode Functionality (software) [C].

The Unsaved Session is located within volatile memory. Therefore, Pyxis Schematicprovides the ability to save a snapshot of the current Design Configuration [B]. This snapshot is known as a state [E].

A

E

B

D

C




A state [C] is a snapshot of the Design Configuration [A] at time tn. Where tn is the moment the user invokes the Save State function. The state includes information such as: analysis types, force definitions, measurement definitions, sweep parameters, PVT corner parameters, and initial conditions [D]. Every state has a state_name [B]. This allows the user to take multiple snapshots at different points in time.

Note: A state does not include simulation results. It only includes the simulation settings.

B

A

DC




A state [C] can also return the Design Configuration [A] to a previous time tn. Whenever the user invokes the Load State function, the selected state snapshot overwrites the current Design Configuration simulation settings [B].

The combination of Save State and Load State functions allow the user to: Explore new simulation settings, then return to a known good state. Define initial conditions and return to that state. Define re-usable stimuli and measurement setups.

B

C

A




An aggregation of state snapshots [A] is known as a configuration [B]. A configuration is analogous to a photo album (a collection of snapshots). A configuration always includes 1 or more state snapshots. Note: Do not confuse the term configuration (an aggregation of states) with the term Design Configuration (simulation settings in the Unsaved Session).

Whenever the user loads a state [A] from a configuration [B], the selected state snapshot overwrites the current simulation settings in the Design Configuration.

The user selects the type of simulator (Eldo, ADMS, ADiT) that is used during the Unsaved Session. A configuration always includes the Simulator Selection at t0 [D] when the configuration was created. The Simulator Selection at t0 is the default simulator whenever the user opens a configuration. The user may choose to override the default Simulator Selection.

Every configuration has a confiiguration_name [C]. This allows the user to have different setups for different types of simulators. Multiple configurations also allow the user to define re-usable stimuli and measurement settings for different designs. Configurations are stored in the Design Configuration Database [E].

DB

A

C E




Every configuration includes a special state snapshot, named default [C]. Default is different than the other state snapshots. This is because default is not created by the Save State function. Instead, the default snapshot [B] is automatically created whenever the user exits Simulation Mode at time texit [A].

In the context of Pyxis Schematic, it is more accurate to think of the default state as the Design Configuration state when the user exited Simulation Mode.

C

B

A




Whenever the user invokes the Enter Simulation Mode function [B], the Design Configuration is initially undefined [A]. Normally, the user selects an existing configuration from the Design Configuration Database [D]. This causes the configurations default state @ texit [C] to be automatically loaded into the Design Configuration [A].

The end result is that the Design Configuration returns to the previous state when the user exited Simulation Mode.

D

A

C

B




B

D

A

The baseline is analogous to a staging area, where the initial Design Configuration [D] will be assembled. When the user creates a new configuration at time t0 [A], a sequence of automatic steps occur. First, the simulation settings contained within the Default Baselinefile [B] are automatically loaded [C] into the Design Configuration [D].

The Default Baseline file [B] contains a collection of AMPLE functions that define simulation settings such as: analysis types, measurements, and parameters. The Default Baseline file is supplied by Mentor Graphics and is not accessible to the user.

C




Next, if the Kit Baseline file exists [A], the simulation settings contained within the Kit Baseline file are automatically loaded [B] into the Design Configuration [D]. Note that the Kit Baseline settings can override some (or all) of the Default Baseline settings [C]. If the Kit Baseline file does not exist, then the Design Configuration remains unchanged.

The Kit Baseline file contains a collection of AMPLE functions that define simulation settings specific to the Process Design Kit (PDK). The Kit Baseline file is supplied by the PDK vendor and is usually not accessible to the user.

A

B

DC




Next, if the User Baseline exists [A], the simulation settings contained within the User Baseline are automatically loaded [B] into the Design Configuration [D]. Note that the User Baseline settings [D]can override some (or all) of the Default Baseline [C] and Kit Baseline settings [E]. If the User Baseline does not exist, then the Design Configuration remains unchanged.

The User Baseline contains user defined AMPLE functions that define simulation settings specific to the user. The User Baseline AMPLE functions are added to the daic_sim_mgr.ample file using a text editor.

A

B

EC D




The entire sequence appears to be instantaneous to the user. The user requests a newconfiguration [A]; and the Design Configuration [C] is initialized to a pre-defined state. This pre-defined state can be customized by the user through the User Baseline [B].

C

A B




This is an example of how baselines, configurations, and states are used in a typical design environment.

The user enters Simulation Mode, requests a newconfiguration, and selects a simulator (Eldo, ADMS, ADiT) [A]. The simulator selection will be the default simulator whenever the new configuration is opened. However, the user can override this selection.

The Default, Kit, and User Baselines [B] sequentially initialize the Design Configuration [C]. The Design Configuration is now ready for simulation.

The user modifies the simulation settings [D]. This changes the simulation settings created at t0 [C]. The user runs simulations and views the results.

The user exits Simulation Mode at t1. The new configuration [E] requested at t0 is created in the Design Configuration Database. The Simulator Selection at t0 [F] is added to the new configuration. A snapshot of the Design Configuration, named default [G], is added to the new configuration.

C

F

B

D

G

E

A




When the user exits Simulation Mode, the Design Configuration becomes undefined [B].

At time t2, the user enters Simulation Mode once more [E]. The user selects the existing configuration [D]. This causes the default state snapshot [G] to be automatically loaded into the Design Configuration [F]. At this time, the user may also choose to override the Simulator Selection at t0stored within the configuration [C].

The Design Configuration now contains the Simulation Settings at t1 [F]. The end result is that the simulation settings return to the state when the user exited Simulation Mode [A]. To the user, it appears that exiting Simulation Mode has no affect on the simulation settings.

BD

E

GF

A

C




The user continues to modify the simulation settings and run simulations. This changes the simulation settings restored at t2 [C].

At time t3, the user decides that the current Design Configuration [B] should be re-usable. The user invokes the Save State function [A]. A snapshot of the current Design Configuration is saved as a new state [E] in the configuration [D]. The user assigns a name to the new snapshot (bias_setup in this example). The configuration now contains 2 states: bias_setup [E] and default [F].

The user continues to modify the simulation settings and run simulations. This changes the simulation settings that were saved at t3 [I].

At time t4, the user decides to return to a previous Design Configuration. The user invokes the Load State function [G] and selects the bias_setup state snapshot [J] in the configuration . The simulation settings contained in the bias_setup snapshot are loaded into the current Design Configuration [H].

C

A

E

F

B

D

I

G

JH




The user continues to modify the simulation settings and run simulations. This changes the simulation setup restored at t4 [A].

At time t5, the user exits Simulation Mode [B]. This automatically overwrites the default state snapshot [C]. The default state now represents the Design Configuration at t5.

A

BC




SummaryThe following concepts were demonstrated in this section:

A state is a snapshot of the Design Configuration in the Unsaved Session. The state contains the simulation settings at a point in time. States do not contain simulation results; they only contain the simulation settings.

Multiple state snapshots can be created and named by the user. A state snapshot can be re-loaded into the Design Configuration at some point in the future. State snapshots are typically used to return to known good simulation settings; and to define re-usable stimuli and measurement setups.

A configuration is a collection of state snapshots and the user simulator selection (Eldo, ADMS, ADiT). Other settings, such as model selections and back annotation properties are also stored within the configuration. These other settings are beyond the scope of this tutorial.

Multiple configurations can be created and named by the user. Configurations are typically used to setup the environment for the simulator (Eldo, ADMS, ADiT); and to define re-usable stimuli and measurement setups for various types of circuits.

Every configuration contains a state snapshot named default. The default snapshot is automatically taken whenever the user exits Simulation Mode. When the user enters Simulation Mode and selects an existing configuration; the default state automatically returns the Design Configuration to its previous settings.

When the user creates a new configuration; the Design Configuration is initialized by the baseline. The baseline is a composite of the Default Baseline, Kit Baseline, and User Baseline AMPLE functions. The baseline ensures that all new Design Configurations have consistent initial simulation settings. The UserBaseline can be customized by the user.


Example

Create A User Baseline


Stage 3: Analog SimulationCreate The User Baseline


In the previous section , we learned that the baseline is used to initialize the Design Configuration [E] whenever the user creates a new configuration [A].

We learned that the baseline is a composite of 3 independent baselines: the Default Baseline [B], Kit Baseline [C], and User Baseline [D]. The User Baseline is the only baseline that can be modified by the user. The User Baseline simulation settings can overwrite any (or all) settings from the Default Baseline and Kit Baseline.

We learned that the User Baseline is a collection of user defined AMPLE functions added to the daic_sim_mgr.ample file.

A

B C D

E




Task: Create the User Baseline.

1. Open a Linux terminal and create directory $SPT_HOME/ ic_reflibs / tech_libs / userware / da_ic.

2. Set the $AMPLE_PATH environment variable to $SPT_HOME/ ic_reflibs / tech_libs / userware .

3. Create a new file using a text editor. Copy the code shown on the left, and paste it into the file.

4. Save the file in the $AMPLE_PATH /da_ic directory and name the file daic_sim_mgr.ample .

5. Close the file and text editor.

The User Baseline now exists inside the daic_sim_mgr.ample file.

// Start of User Baseline //

//********* Eldo specific function **********//function $eldo_user_baseline(), INDIRECT{

// Eldo simulator settings$simulator_args("-x64", @true); // use 64bit$netlister_args("-ground_nodes", ["GROUND"]);$option(@convergence, @gmin, 1e-12);

// $option(@output, @stat, "1"); // report run-time statistics

// general simulation environment settings$temp(27);$enable_probe_all(@V); // save all voltages

}//********* ADMS specific function **********//

function $adms_user_baseline(), INDIRECT{

$eldo_user_baseline(); // re-use the Eldo baseline setup// ADMS simulator settings// Note: not used in this SPT.//$converter_hook("defmodel_0");//$converter_hook("defmodel_1");// general simulation environment settings$temp(85);

}// End of User Baseline //




The functions used to create the User Baselineare standard AMPLE functions. A description of available AMPLE functions can be found in the Pyxis Schematic Reference Manual For The Pyxis Custom Design Platform, v10.2. Refer to the Function Dictionary chapter.

Lines 5-6,16 specify that:IF the user selects the Eldo simulator in the New Configuration form, THEN the enclosed AMPLE functions are applied to the Design Configuration.

Lines 8-11 define Eldo specific arguments and options.

Lines 14-15 define general simulation settings. Typically, the User Baseline includes many more settings; this example only has 2.




Lines 20-21,31 specify that:IF the user selects the ADMS simulator in the New Configuration form, THEN the enclosed AMPLE functions are applied to the Design Configuration.

Simulator specific baseline definitions often duplicate the same general simulation settings. The user may choose to duplicate these settings in each Eldo, ADMS, and ADiT baseline definition. However, there is an easier method. Line 22 invokes the $eldo_user_baselinefunction (lines 5-16) from within the $adms_user_baseline function. Note: This must precede the other ADMS baseline definitions.

Now, when the ADMS simulator is selected for a new configuration, the Eldo simulation settings are first applied to the Design Configuration. Then the remaining ADMS simulation settings are applied.




Lines 26-27 define ADMS specific arguments. Note that these lines are commented out, because they are not used in this tutorial.

Line 30 defines that ADMS simulations use a temperature value of 85C. This overrides the Eldo temperature value of 27C that had been set by line 22.

This example is complete.




SummaryThe following concepts were demonstrated in this section:

The User Baseline is created by adding AMPLE functions to the daic_sim_mgr.ample file. This file is saved in the $AMPLE_PATH / da_ic directory.

The available AMPLE commands are documented in the Pyxis Schematic Reference Manual For The Pyxis Custom Design Platform, v10.2, Function Dictionary chapter.

A unique User Baseline may be defined for each type of simulator the user may select (Eldo, ADMS, ADiT).

Typically, a simulator specific baseline definition contains simulator specific arguments and options; followed by general purpose (simulator agnostic) simulation settings.

Simulator specific baselines can be invoked within other simulator specific baselines. This allows the user to avoid duplicating the general purpose simulation settings.


Example: Create A New Configuration

VCO Test


Stage 3: Analog SimulationCreate A New Configuration: VCO Test


In this example, we will demonstrate how to create a new configuration, named vco_test. This configuration will contain state snapshots. These snapshots allow the user to initialize the Design Configuration for various re-usable VCO (Voltage Controlled Oscillator) tests.

We begin by requesting a new configuration and selecting a simulator [C]. This will initialize the Design Configuration with the contents of the baseline [B]. Next, we will edit the Design Configuration to add parameters, and define stimuli [A].

Finally, we will exit Simulation Mode [D]. This will automatically create the vco_testconfiguration [F] and store a snapshot of the current simulation settings as the default state [E].

CBA

D

E F




The figure on the left shows an overview of the tasks performed in this example. Creating the vco_test configuration requires 7 tasks:

1. Request a new configuration and select a simulator type.

2. Edit the netlister settings.

3. Select model languages.

4. Add global parameters.

5. Define stimuli on nets.

Continued on next page.




Overview continued

6. Copy transcript text to script template file (optional).

7. Exit Simulation Mode.




Task 1: Request a new configuration and select a simulator type.

1. In the Project Navigator window, navigate to the GenericPLL / Simulations / vco / sim_vcodirectory [D].

2. Double LMB the schematic folder [A]. This will invoke Pyxis Schematic [C]and open the sim_vco schematic [E].

The particular buttons displayed in the toolbar [F] indicate that Pyxis Schematic is currently in Schematic Mode.

3. Optional: minimize the Project Navigator window [B].

D

A

C

B

E

F




Task 1: continued

4. In the Pyxis Schematic window, LMB the Enter Simulation Mode* button [G]. This will open the Entering Simulation Modeform [A].

5. LMB the New Design Configuration button [B]. This will open the New Design Configuration form [D].

6. Enter the name of the new configuration in the Name field [C]. In this example, the configuration is named vco_test. The vco_test configuration will include various VCO simulation settings.

7. LMB the Eldo radio button [E]. This selects the default simulator associated with the vco_test configuration.

8. LMB the OK button [F]. This closes the New Design Configuration form [D].

A

B

D

C

F

G

E

* Hotkey = s




Task 1: continued

9. The vco_test configuration is now displayed in the Design Configuration list [B].

10. LMB the OK button [C]. This closes the Entering Simulation Mode form [A]. The baseline settings are automatically loaded into the Design Configuration.

At this point, Pyxis Schematic is in Simulation Mode; and the Design Configuration has been initialized. Note that the toolbar changes to Simulation Mode buttons [D].

Task 1 is complete.

B

C

A

D




Task 2: Setup the simulation environment.

1. LMB the Setup Environment* button [A]. This will open the Setup Environment form [C].

2. LMB the Netlister Panel [D]. This will display the Netlister Argument Switches [B].

3. LMB the global argument switch [E]. This switch defines the global nets.

4. Enter the names of the global nets in the Value field [F]. In this example, the vdd_diff and vss_diff nets are defined as global simulation nets.

5. LMB the OK button [G]. This applies the simulation environment settings to the Design Configuration and closes the Setup Environment form [C].

At this point, the simulation environment is defined. Task 2 is complete.

A

C

D

E F

B

G

* Hotkey = s




Task 3: Select model languages.

1. LMB the Hierarchy Navigator button [E]. This will open the Hierarchy Navigatorpanel [A]. Note that the prescaler instance is currently using Verilog language models [C], and the vco instance is using Verilog-A language models. In this example, we will use schematic models.

2. LMB the prescaler instance name [B] to select it. Shift-LMB the vco instance name [F] to add it to the selection.

3. RMB to display the cascading menu. LMB the Change Model menu button [D] to display the next cascading menu. LMB the SCHEMATIC menu button [G].

E

A

CB

F

D

G




Task 3: continued

4. Note that the language model for both instances is now SCHEMATIC [B].

5. Note that both schematic instances are now SCHEMATIC [C, D].

6. Optional: close the Hierarchy Navigator panel [A].

At this point, all the VCO simulation models use the schematic. Task 3 is complete.

B

A

C

D




Task 4: Add global parameters.

1. LMB the Setup Simulation* button [B]. This will open the Setup Simulationform [A].

2. LMB the Params/Sweeps panel [C]. This panel is used to define various simulation parameters, sweep parameter ranges, and Monte Carlo runs.

Note that the nominal Temperatureparameter [D] is currently defined as 27 degrees. This initial value was set by the User Baseline line 14. Refer to example Create The User Baseline.

B

A

C

D

* Hotkey = g




Task 4: continued

3. LMB the Global radio button [A]. This sets the scope of the simulation parameters we will define in the following steps.

4. LMB the Parameter field [B]. Enter the positive supply voltage name VDD. LMB the Value field [C]. Enter the parameter value of 1. LMB the Add button [E]. Note that the summary table [D] shows that the VDD global parameter has a nominal value of 1.

5. LMB the Parameter field [B]. Enter the negative supply voltage name VSS. LMB the Value field [C]. Enter the parameter value of 0. LMB the Addbutton [E]. Note that the summary table [D] shows that the VSS global parameter has a nominal value of 0.

A

B C

ED




Task 4: continued

6. LMB the Parameter field [A]. Enter the control voltage name CNTRL. LMB the Value field [B]. Enter the parameter value of 0.5. LMB the Add button [D]. Note that the summary table [C] shows that the CNTRL global parameter has a nominal value of 0.5.

7. LMB the Parameter field [A]. Enter the VCO bias current name IBIAS_VCO. LMB the Value field [B]. Enter the parameter value of -800u. LMB the Add button [D]. Note that the summary table [C] shows that the IBIAS_VCO global parameter has a nominal value of -800u.

8. LMB the Parameter field [A]. Enter the prescaler bias current name IBIAS_PRE. LMB the Value field [B]. Enter the parameter value of -1.5m. LMB the Addbutton [D]. Note that the summary table [C] shows that the IBIAS_PRE global parameter has a nominal value of-1.5m.

B

D

A

Task 4 is complete.

C




Task 5: Define stimuli.

1. LMB the Forces panel [B]. This panel is used to define stimuli sources for target nets in the Pyxis Schematic window [A].

Tip: Position the Setup Simulation form as shown [C]. This will allow you to easily switch between the two displays as you select nets.

B

C

A




Task 5: continued

2. In the Pyxis Schematic window, LMB the vctrl_vco net [A]. Note that the net name is displayed in the Selection from Schematic list [B].

3. LMB the DC source in the Source Typelist [C]. Enter the string{CNTRL} into the Magnitude (V/A) field [D].

4. Verify that GROUND is selected in the Reference field [E]. Verify that the Voltage radio button is selected [F].

5. LMB the Add button [G]. The source definition is now displayed in the summary table [H].

At this point, the vctrl_vco net will be driven by a DC voltage source referenced to GROUND. The magnitude of the voltage source is specified by the CNTRL parameter defined in Task 4: step 6.

A B

CD

E F

G

H




Task 5: continued

6. In the Pyxis Schematic window, LMB the PDbar net [A]. Note that the net name is displayed in the Selection from Schematic list [B].

7. LMB the DC source in the Source Typelist [C]. Enter the string{VDD} into the Magnitude (V/A) field [D].

8. Verify that GROUND is selected in the Reference field [E]. Verify that the Voltage radio button is selected [F].

9. LMB the Add button [G]. The source definition is now displayed in the summary table [H].

At this point, the PDbar net will be driven by a DC voltage source referenced to GROUND. The magnitude of the voltage source is specified by the VDD parameter defined in Task 4: step 4.

B

C

F

G

H

A

D

E




Task 5: continued

10. In the Pyxis Schematic window, LMB the ibias_vco net [E]. Shift-LMB the vdd_diff net [A]. Note that both net names are displayed in the Selection from Schematic list [B].

11. LMB the DC source in the Source Typelist [C]. Enter the string{IBIAS_VCO}into the Magnitude (V/A) field [D].

12. LMB the VDD_DIFF signal [G] in the Selection from Schematic list [B]. LMB the Fill from Signals button [H]. Note that /vdd_diff is now displayed in the Reference field [I].

13. LMB the Current radio button [J].

14. LMB the IBIAS_VCO signal [F] in the Selection from Schematic list [B].

15. LMB the Add button [K]. The source definition is now displayed in the summary table [L].

G

C

I

L

DA

E

B

H J

K

F

At this point, the ibias_vco net is driven by a DC current source referenced to vdd_diff. The magnitude of the current source is specified by the IBIAS_VCO parameter defined in Task 4: step 7.




Task 5: continued

16. In the Pyxis Schematic window, LMB the ibias_pre net [E]. Shift-LMB the vdd_diff net [A]. Note that both net names are displayed in the Selection from Schematic list [B].

17. LMB the DC source in the Source Typelist [C]. Enter the string{IBIAS_PRE}into the Magnitude (V/A) field [D].

18. LMB the VDD_DIFF signal [G] in the Selection from Schematic list [B]. LMB the Fill from Signals button [H]. Note that /vdd_diff is now displayed in the Reference field [I].

19. Verify that the Current radio button [J]is selected.

20. LMB the IBIAS_PRE signal [F] in the Selection from Schematic list [B].

21. LMB the Add button [K]. The source definition is now displayed in the summary table [L].

G

C

I

L

D

A

E

B

H J

K

F

At this point, the ibias_pre net is driven by a DC current source referenced to vdd_diff. The magnitude of the current source is specified by the IBIAS_PRE parameter defined in Task 4: step 8.




Task 5: continued

22. In the Pyxis Schematic window, LMB-drag to select both vdd_diff and vss_diff nets [A]. Note that the net names are displayed in the Selection from Schematic list [C].

23. LMB the DC source in the Source Typelist [D]. Enter the string{VDD} into the Magnitude (V/A) field [E].

24. Select GROUND in the Reference list [G]. LMB the Voltage radio button [H].

25. LMB the VDD_DIFF signal [B] in the Selection from Schematic list [C].

26. LMB the Add button [I]. The source definition is now displayed in the summary table [F].

D

H

F

E

G

At this point, the vdd_diff net is driven by a DC voltage source referenced to GROUND. The magnitude of the voltage source is specified by the VDD parameter defined in Task 4: step 4.

AC

B

I




Task 5: continued

27. LMB the VSS_DIFF signal name [A] in the Selection from Schematic list [B].

28. LMB the DC source in the Source Typelist [C]. Enter the string{VSS} into the Magnitude (V/A) field [D].

29. Verify that GROUND is selected in the Reference field [F]. Verify that the Voltage radio button [G] is selected.

30. LMB the Add button [H]. The source definition is now displayed in the summary table [E].

At this point, the vss_diff net is driven by a DC voltage source referenced to GROUND. The magnitude of the voltage source is specified by the VSS parameter defined in Task 4: step 5.

C

G

E

D

F

B

H

A




Task 5: continued

31. Verify that the summary table [A]appears as shown.

32. LMB the Apply button [B]. This will apply all the parameter and stimuli definitions defined in Task 4 and Task 5 to the Design Configuration.

Note that the source definitions[C, D, E] now appear next to their associated nets in the Pyxis Schematicwindow.

33. Minimize the Setup Simulation form (optional).

At this point, the VCO simulationparameters and sources are defined.

Task 5 is complete.

A

B

C

D

E




Task 6: Copy transcript text to script template file (optional).

IF the Transcript Area is not currently visible at the bottom of the Pyxis Schematicwindow [A], THEN:

1. LMB the Setup [B] cascade pull-down menu.

2. LMB the Windows [C] cascade menu item.

3. LMB the Transcript Area [D] menu item.

The Transcript Area should now be displayed at the bottom of the Pyxis Schematic window [A].

B

C

D

A




Task 6: continued

4. Create a new template file using a text editor. The file will contain AMPLE commands. Therefore, the file extension must be ample. In this tutorial, the new file is named script_templates.ample [B].

5. Copy blocks of useful commands in the Transcript Area [A], and paste them into the script_templates.ample file [B].

6. Create a directory $SPT_HOME/scripts. Save the script_templates.ample file in the scripts directory.

At this point, blocks of AMPLE commands have been saved in a template file. These commands can be used to re-create the steps performed in Tasks 2-5.

Task 6 is complete.

A

B




Task 7: Exit Simulation Mode.

1. LMB the Exit Simulation Modebutton [E]. When the Query window is displayed, LMB the Yes button [C]. This will cause an automatic sequence of events to occur:

The vco_test configuration will be created in the Design Configuration Database.

A snapshot of the Design Configurationwill be saved as state default.

The Setup Simulation form will close.

The design viewpoint [A] is replaced by the schematic [B].

The side toolbar menu changes from simulation buttons to schematic buttons [D].

Task 7 is complete. This example is complete.

E

C

D

A

B




SummaryThe following concepts were demonstrated in this example:

A new configuration named vco_test was created using the New Design Configuration form.

Netlister global arguments were defined using the Setup Environment form.

Simulation language models were specified using the Hierarchy panel.

Global parameters were defined using the Params/Sweeps panel.

Net driving sources were defined using the Forces panel.

AMPLE commands were copied from the Transcript Area and pasted into a script template file.

A state snapshot named default was automatically saved when the user exited Simulation Mode.


Example: Create A New State

Optimum VCO Bias


Stage 3: Analog SimulationCreate A New State: Optimum VCO Bias


In this example, we will demonstrate how to create a new state snapshot, named bias_setup. This snapshot will allow the user to initialize the Design Configuration at the optimum VCO bias point at any time in the future.

We begin by selecting the vco_test configuration [D]. This will automatically load the defaultstate [E] into the Design Configuration . This restores the parameter and source definitions to their previous settings at texit [A].

Next, we run an Eldo simulation while sweeping the vdd_diff and ibias_vco parameters [B]. The optimum parameter values are determined from the simulation results.

Finally, we set the vdd_diff and ibias_vco parameters to their optimal values [C]. Then we save [F] the current Design Configuration as a new state, named bias_setup [G].

E

A

B

C

FD

G




The figure on the left shows an overview of the tasks performed in this example. Optimizing the bias settings requires 8 tasks:

1. Load an existing configuration.

2. Run an initial DC operating point simulation. Evaluate the results.

3. Modify the simulation settings to use sweep parameters.

4. Run a DC sweep simulation and evaluate the results using EZwave. Determine the optimum bias voltage and current values.

Continued on next page.




Overview continued

5. Modify the simulation settings to use the optimum bias voltage and current values.

6. Save the simulation settings as a new state, named bias_setup.

7. Copy transcript text to script template file (optional).

8. Exit Simulation Mode.




Task 1: Load an existing configuration.

IF the sim_vco schematic is currently closed, THEN do steps 1, 2, and 3.

1. In the Project Navigator window, navigate to the GenericPLL / Simulations / vco / sim_vcodirectory [D].

2. Double LMB the schematic folder [A]. This will invoke Pyxis Schematic and open the sim_vco schematic [C].

3. Optional: minimize the Project Navigator window [B].

D

A

C

B




Task 1: continued

4. LMB the Enter Simulation Mode* button [E]. This will open the Entering Simulation Modeform [A].

5. LMB select the vco_test configuration [B] that was created in the previous example.

Note that the default simulator is Eldo [C]. This simulator selection was made when the vco_testconfiguration was created. The user may choose to override the default simulator selection by LMB one of the Simulator type [D] radio buttons. We will continue to use the Eldosimulator in this example.

6. LMB the OK button [F]. This will close the Entering Simulation Mode form [A]. The default state snapshot will be loaded into the Design Configuration.

At this point, the simulation settings have been restored to the time the user previously exited the vco_test configuration.

Task 1 is complete.

E

A

B C

D

F

* Hotkey = s




VCO Design Constraints.

The circuit designer specifies the following constraints for this VCO design:

The pbias voltage [B] must be 500 mV to 600 mV in order for the VCO to oscillate.

The nbias voltage [D] must be 600 mV to 700 mV in order for the VCO to oscillate.

The pbias [B] and nbias [D] voltages are sensitive to changes in vdd_diffvoltage [A]. The acceptable range of vdd_diff voltage is 1.0 V to 1.4 V.

The pbias [B] and nbias [D] voltages are determined by the current on the Ibias_vco pin [C]. The acceptable range of Ibias_vco current is -800 uA to -1.5 mA.

AB

CD

The figure shown above is for reference purposes.It is not displayed in the Pyxis Schematic GUI at this time.




Task 2: Run an initial DC operating point simulation.

1. LMB the Setup Simulation button [A]. This will open the Setup Simulationform [E].

2. LMB the Analysis Simulation Panel [B].

3. Verify that OP [C] is the only analysis type checked in the Analysis Selector list. Verify that Enable DCOP [D] is checked. If any changes are made, then LMB the Apply button.

4. Optional: minimize the Simulation Setup form [E].

At this point, we have verified that the simulator is setup to run a DC operating point analysis.

5. LMB the Run Simulator* button [F]. This will start the DC operating point analysis.

B

A

CD

E

F

* Hotkey = r




Task 2: continued

When the simulation is complete, the Logtab [E] will be displayed at the bottom of the Pyxis Schematic window.

7. LMB the Log tab [E]. This will open the Log Area [A].

8. Scroll the Log Area to verify that the simulation terminated normally [B].

9. Scroll the Log Area to verify that there are no fatal errors [D].

10. Optional: hide the Log Area [C].D

E

B

A

C




Task 2: continued

To inspect the voltages on the pbias and nbias nets; we must descend a level of hierarchy into the VCO schematic.

11. In the Pyxis Schematic window, double LMB* the VCO instance [A]. This will open a new tab containing the VCO schematic [B].

A

B

* Stroke = select + MMB downward stroke




Task 2: continued

12. Zoom in on the left side of the VCO schematic [A]. The vco_bias block is the source of the pbias and nbias nets.

13. LMB select the pbias net [B]. Shift-LMB the nbias net [E] to add to the selection.

14. LMB the DCOP/Transient button [C] to display the cascading menu. LMB the Add Monitors On Selection button [D]. The pbias and nbias nets will un-select.

Note: The new monitors might or might not appear in the schematic window. This is normal behavior. As we will see in the next slide; the monitors have been added to the nets.

A

E

B

D

C




Task 2: continued

15. Pan and zoom along the pbias and nbias nets until you locate the monitors [A, C]. In this example, the monitors are attached near DIFF_BUFFER3 [B].

16. Examine the pbias voltage [A]. Using the existing simulation settings, the pbias voltage is 383.18 mV. This does not meet the 500 mV to 600 mV design constraint.

17. Examine the nbias voltage [C]. Using the existing simulation settings, the nbias voltage is 560.14 mV. This does not meet the 600 mV to 700 mV design constraint.

Task 2 is complete.

In the next task, the simulation settings will be modified to meet the VCO design constraints.

B

A

C




Task 3: Modify the simulation settings to use swept parameters.

We will use a nested parameter sweep of ibias_vco and vdd_diff to determine the optimum bias voltage and current.

1. LMB the Setup Simulation button [A]. This will open the Setup Simulationform [B].

2. LMB the Analysis [C] Simulation Panel.

3. LMB check the DC [D] Analysis Selector checkbox.

4. Select Source (Force) [E] in the first level Sweep Type pull-down list.

5. LMB the cross-hair button [G]. This will open the Force Selection form [F].

6. LMB the FORCE__ibias_vco instance [H] entry. LMB the OK button [I]. This will close the Force Selection form [F].

BA

DC

E G

F

H

I




Task 3: continued

Note that the FORCE__ibias_vco instance name appears in the first sweep level field [A].

7. Enter the value -800u in the Startfield [B]. This is the upper ibias_vcodesign constraint.

8. Enter the value -1.5m in the Stop field [C]. This is the lower ibias_vcodesign constraint.

9. Enter the value -100u in the Step field [D].

At this point, the DC current source driving the ibias_vco net is specified to sweep from -800 uA to -1.5 mA in steps of -100 uA. This will cover the entire range of valid ibias_vco design constraint values. The sweep will include 8 current points.

A B C D




Task 3: continued

10. Select Source (Force) [A] in the second level Sweep Type pull-down list.

11. LMB the cross-hair button [C]. This will open the Force Selection form [B].

12. LMB the FORCE__vdd_diff instance [D]entry. LMB the OK button [E]. This will close the Force Selection form [B].

BA

D

C

E




Task 3: continued

Note that the FORCE__vdd_diff instance name appears in the second sweep level field [A].

13. Enter the value 1.0 in the Startfield [B]. This is the lower vdd_diffdesign constraint.

14. Enter the value 1.4 in the Stop field [C]. This is the upper vdd_diffdesign constraint.

15. Enter the value 0.2 in the Step field [D].

16. LMB the Apply button [E]. This applies the simulation settings to the Design Configuration.

At this point, the DC voltage source driving the vdd_diff net is specified to sweep from 1.0 V to 1.4 V in steps of 0.2 V. This will cover the entire range of valid vdd_diff design constraint values in 3 voltage curves. Task 3 is complete.

A B C D

E




Task 4: Run a sweep simulation and determine optimum values.

1. LMB the Run Simulator* button [A]. This will start the DC sweep analysis. When the simulation is complete, the Log tab [E] will be displayed at the bottom of the Pyxis Schematic window.

2. LMB the Log tab [E]. This will open the Log Area [B].

3. Scroll the Log Area to verify that the simulation terminated normally [C].

4. Scroll the Log Area to verify that there are no fatal errors [D].

5. Optional: hide the Log Area.

* Hotkey = r

B

A

E

C

D




Task 4: continued

6. LMB the /VCO1 vco tab [A]. This will display the VCO schematic. Zoom in on the left side of the VCO schematic [B].

7. LMB select the pbias net [C]. Type the x hotkey to add an EZwave cross-probe. This will also open the EZwavewindow [D].

B

A

C

D




Task 4: continued

The simulation results show 3 curves[E, F,

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