q45 cd seedy 1207.schematic.bak
TRANSCRIPT
-
ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
DATE
APPDENG
DATE
APPDCK
ECNZONEREV
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTIOND
SIZE
APPLICABLENOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
OFSHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Apple Computer Inc.
12345678
12345678
B
C
D
A
B
C
D
A
REV.
DESCRIPTION OF CHANGE
CSACSA
AIRPORT EXTREME & BLUETOOTH
PCM3052A AUDIO CODEC
GRAPHICS VREGS
TABLE ITEMS
GPU FRAME BUFFER
31CPU VREGCPU VREG
U3LITE MEMORYSERIES TERMINATIONDIMMS
VTT VREG
26
2120
I2C CONNECTIONS
VESTA POWER
2.5V VREGSIGNAL ALIAS8
9
POWER BLOCK DIAGRAM
49 GPU DVI & DACSEXT VGA & TMDSU3LITE HYPERTRANSPORTSHASTA HYPERTRANSPORT
MODEM
7
1011
PROCESSOR
98*
91* USB HOST INTERFACE92
FIREWIRE
TABLE OF CONTENTSCIRCUIT
3
109
3
55
5354
51PDF
GPU STRAPS
BLOCK
5 5
8
1
6
2
4
1
7
4
BLOCK
6
2
11
FUNC TEST
REVISION HISTORY
* PAGES WHERE MASTER PAGE IS IN A DIFFERENT SCHEMATIC
MEMORY
GRAPHICS
SHASTA SERIAL
NEO APPLE PI
PULSAR CLOCKSU3LITE APPLE PI
NEO POWER & BYPASS
CPU VREG OUTPUT CAPS
PARALLEL TERMINATION
CPU BYPASS
CPU DIODE CONDITIONER
PARALLEL TERMINATION
GPU AGPU3LITE AGP
SHASTA CORE
SMU12
1614
1817
22
2423
30
27
2928
32
3433
35
31
40
363738
444546484950
12
15
1314
1617
2524
19
22
18
26
23
3332
29
27
34
3635
28
30
3738
4039
4142
4344454647
PCI
DISK
48
SHASTA ETHERNET
PCI SERIES TERMINATIONSHASTA PCI
USB2 PCI
DISK CONNECTORSSHASTA DISK
52
55
51
5657
50
5453
59
62*60
647374*
765859
6160
80*
SHASTA FIREWIREETHERNET CONNECTOR87
88*
AUDIO
FIREWIRE CONNECTORS
AUDIO POWER SUPPLIES
LINE OUT AMPLINE IN AMP
94
90
95*
102*
100*
96*
VESTA FIREWIRE PHY
6263
6667
6564
6970717273
68
7475
ETHERNET
GRAPHICS
86*
89*
52FRAME BUFFER TERMINATION
BOOT ROM75*
SYSTEM BLOCK DIAGRAM
PDF
HT
21
GRAPHICS DDR SDRAM A
POWER CONNECTOR / POWER ALIAS
VESTA ETHERNET PHYU3LITE MISC
PULSAR POWER
HYPERTRANSPORT LA CONNECTORS
INDICATOR LED / AMBIENT LIGHT SENSOR 8384*
AUDIO CONNECTORS101*
GRAPHICS DDR SDRAM B
USBMODEM CONNECTORCPU STRAPS
SPEAKER AMP
USB DEVICE INTERFACE
77*FAN 2 AND HARD DRIVE TEMP SENSORFAN 0, 1 AND SYSTEM TEMP SENSORCPU LOGIC ANALYZER CONNECTOR
5658
TOP
GPU CORE POWER
1.2V VREG3.3V/5V PWRON SWITCHING
13*
CIRCUIT
SEEDY
1.5V VREG / U3LITE CORE
25*
12/07/0404
051-6772
ENGINEERING RELEASED354713 12/07/04 ?
04
SCH,MLB,SEEDY
1 102
Prelim
inary
-
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
OPTICAL
HARD DRIVE
FOR DEVELOPMENT ONLY
PAGE 86 PAGE 89
VESTA
SHASTA
GIG ETHERNET FIREWIRE A
U8600PCM3052A
1.2V/800MHZ
2.6V/400MHZ
2.6V/400MHZ RV351LE
FRAME BUFFER
AIRPORTEXTREMEBOOTROM
CONNECTOR
PAGE 24
J9401
CTL-LESS /NCs
S/PDIF
U1300
SMU
PAGE 13
U1301
PAGE 13
RTC
1394 OHCI (3.3V/98MHz)
LINE OUTAMP
AUDIO CODEC
CONNECTOR
TERM
PARALLEL
PAGES 44&45
BLUETOOTHCONNECTOR
CONNECTORS
PAGE 92
PAGE 92
J9210/J9220/J9230
USB
J9240
54
USB 2.0
PAGE 91USB
321
uPD720101
U7700
AMP
J9800
LINE IN
PAGE 97
PAGE 98
CONNECTORLINE IN
PAGE 98
MICJ9802
J9801
CONNECTORSPEAKER
PAGE 98
LINE OUT
OPTICAL OUTJ9803COMBO OUTCONNECTOR
PAGE 98
PAGE 97
SPEAKER
PAGE 97
AMP
PAGE 95
U9500
CONNECTOR
GPUU4900
PAGE 49
PAGE 94
SOFT MODEM
32-bit PCI (5V-3.3V/33MHz)
J7600
PAGE 76
SERIES
PCI
PAGE 54
FREQUENCIES LISTED ARE MAXIMUM DATA TRANSFER RATES SUPPORTED BY U3LITE
PAGE 25
PAGE 25
PAGE 80
PAGE 80
CONNECTORSETHERNET
POWER
PAGE 26
U2600
PULSARCLOCKS
PAGE 27
PAGE 87
4 Diff pairs
J8700
CONNECTOR
8-bit TX & 8-bit RX
GMII (3.3V/125MHz)
0
FIREWIRE A
1
J9000, J9001
PAGE 90
2 Diff pairs
8-bit TX/RX
SCCBSCCAI2S1
I2S
I2S0 I2S2PAGE 88
FIREWIREETHERNET
PAGE 84
PAGE 23
CORE GPIO/P
CI64
PAGE 74
PCI
U7500
PAGE 75 PAGE 77
PAGE 83
CONNECTOR 3.3V/133MHZ
UATA
J8302
PAGE 83
J8301
UATA
PAGE 83
JXXXX
SATA
SATA DEVCONNECTOR
CONNECTOR
SATA/150
UATA/133
SATA/150
1.2V/1.5GHZ
1.2V/1.5GHZ
SATA2
SATA1
U2300
SATA
AGPU3
17",20" INVERTER
J5902, J5903
PAGE
MISC
DIMMS
J4001J4000
PAGE 62
PAGE 91
FRAME
PAGE 55
8X AGP
J5900, J5901
TMDS
BUFFER AFRAME
U5400, U5401
FRAME BUFFER
64-BIT
BUFFER B
MAIN MEMORY64/128-BIT
2.6V/400MHZ
SYSTEM BLOCK DIAGRAM
APPLE PI
32-BIT
PAGE 29
APPLE PIPAGE 28
MAIN MEMORY
PAGE 37
TERM
PAGE 40
PAGE 38
8-BITHYPERTRANSPORT
CONTROL = 2.5V
PAGE 60
CORE
PAGE 22
J6400J6401
32-BIT
I/O = 1.5V4X = 1.5V
J6402
0.8V/533MHZ48
HYPERTRANSPORT
HYPERTRANSPORT
U3LITE
PAGE 18
CPUU2900
PAGE 64
HT
PAGE 59EXT VGA
64-BIT
DEBUG
NEO 10S
ELASTIC INTERFACE1.2V/900MHZ
I2C
U5500, U5501
051-6772 04
2 102
Prelim
inary
-
ALIAS
IN
IN IN
IN
LM339AV+
GND
IN
LM339AV+
GND
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
20" PANEL POWER
POWER BLOCK DIAGRAM
AUDIO CODEC PCI BUS
PP5V_ALL HDD & OPTICAL
PP5V_RUNPP12V_RUN
20" LCD INVERTER
PP24V_RUN
20" LCD INVERTER FW CONN
PAGE 7J700
5V
PAGE 10
SMU
SYS_POWERUP_L
(PWR_GOOD_PP2V5)
(TURN_ON_VTT)
FET SWITCH
(PWR_GOOD_SB_CORE)
SYS_POWERUP_L
POWER SEQUENCE PIN
PP3V3_RUN
POWER CONNECTOR
GPUL
SC1211*4SC2643VX*1
SWITCHERPAGE 33
0.8~1.2V
CPU CORE
HP/LINEOUT AMP
LINEAR
LINEARPP4V5_RUN_AUDIO
PP5V_RUN_AUDIO
AUDIO CODEC
5VPAGE 99
4.5VPAGE 99
LINEAR
PULSAR CORE
PP1V5_PWRON
1.5VPAGE 50
SHASTA HT
USB CONN
FET SWITCHPP5V_PWRON
PAGE 11
5V
DDR DIMM
IRU3037CSSWITCHER
2.59V
RAM VTT
PP2V5_PWRON
PAGE 9IRU3037CS
U3LITE CORE
LINEAR
AGP BUS
PAGE 50
POWER SWPP1V5_RUN
1.3V
PP1V25_RAM_VTT
PAGE 46
CPU AVDD
LINEARPP2V5_RUN_CPU_AVDD
U3LITE CORESWITCHER
PAGE 31
2.8V
1.53VPAGE 22
RAM TERM
PP2V5_RUNFET SWITCH
GRAPHIC FB
PAGE 9
SMU FW PHY
LINEAR
PP3V3_PWRON
PAGE 11
3.3VPAGE 11
PP3V3_ALL
3.3V
IRU3037ACS
PAGE 50
LINEARPP1V8_GPU
GPU
ENET PHY
USB2 HOST MODEM & BT
RV351
IRU3037ACS
GPU CORE
PAGE 50
1.20V
VESTA CORE
PP1V2_ALL
SWITCHERFET SWITCHPAGE 50
PP2V5_GPU_A2VDD
1.2VPAGE 10
SWITCHER
PAGE 50
PP1V5_VDDC_CT
LINEAR
PAGE 50
LINEAR
PP1V8_TPVDD
GPU GPU
GPU
PP1V2_PWRON
LINEAR
HT BUS
PP1V2_RUN
PAGE 10
FET SWITCH
SHASTA COREPWRON_SDPWRON_DISK_SB
402CERM16V20%0.01UF
2
1 C340
10 10
PP2V5_PWRON
402MF-LF1/16W5%150K
2
1R342
100K5%1/16WMF-LF4022
1R343
5%1/16WMF-LF
10K
4022
1R341
5%1/16WMF-LF
10K
4022
1R331
PP5V_ALL
PP3V3_ALL
SOI
3
14
9
8
12
U1100
PP3V3_ALL
46
SOI
3
1
7
6
12
U1100
402MF-LF1/16W5%
100K21
R330
20%16VCERM402
0.01UF2
1 C330
23 7 6
402MF-LF1/16W5%
100K21
R340
3 102
04051-6772
=PPVCORE_PWRON_SB
TURN_ON_PP1V2_PWRON_L
PWR_GOOD_PP2V5
TP_SMU_PWRSEQ_P1_0MAKE_BASE=TRUE
TURN_ON_VTT
CPU_AVDD_EN
=PP5V_RUN_CPU
=PULSAR_POWER_DOWN
PULSAR_POWER_DOWNMAKE_BASE=TRUE
SMU_PWRSEQ_P1_4
SMU_PWRSEQ_P1_0
PWR_GOOD_SB_CORE
SMU_PWRSEQ_P1_2
SMU_PWRSEQ_P9_6
SMU_PWRSEQ_P9_5
SMU_PWRSEQ_P1_1
COMPARE_SB_CORE
RAIL_CTL_NEG
PS_2V_REF
COMPARE_PP2V5
31 8 7
31
6
27
13
13
13
13
13
13
11
Prelim
inary
-
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(P 83) OPTICAL DRIVE CONNECTOR CHANGED TO 516S0235
MOVED GPU ZENER DIODES TO VREG PAGE SINCE THEY SHOULD BE PLACED NEAR THE VREGS
REDUCED CAPACITANCE OF C1100 & C1102
CONNECTED GPU POWER AND POWER FILTERS
(P 76) FIXED PCI_CBE_L CONNECTIONMORE PHYSICAL & SPACING UPDATES
CHECKIN 02003
(P 76) ADDED STANDOFFS FOR Q85 CARD(PP 16,17) NEW FAN CIRCUIT CAPS (C1603, C1653, C1703)
(P 59) LED 3 NOW DRIVEN FROM FPD_PWR_ON
(P 49) CONNECTED AGPTEST RESISTOR TO VDDP11/22/04
(P 12) VESTA_ENET_LOWPWR UPDATE(P 50) TP_VDD SET TO 1.80V(P 50) VDDC_CT SET TO 1.50V
(P 91) USB CAP COST REDUCTION
(P 56) ADDED PADS FOR STRAPPING RESISTORS TO GPU_GPIO
(PP 10, 22, 34, 50) USED COMPARATOR FOR LOW VOLTAGE RAIL LEDS
REPLACED EMC FERRITES WITH 0 OHM RESISTORS FOR GRAPHICS AND FANS
CONNECTED FRAME BUFFER
11/20/04
(P 62) SHASTA HT_PLL FILTER COST REDUCTION(P 25) NEW SHASTA XTAL(PP 56, 58) CONNECTED PWM FROM RV351LEP & PUT IN PROTO WORKAROUND
(P 36) CONNECTED NEW CPU DIODE REFERENCE(P 77) USB2 IDESEL - NOW FROM USB2 SIDE(P 56) ADDED BOMOPTIONS FOR MEMORY STRAPS
(P 91) CHANGED USB2 CHIP GROUNDING(P 8) ALIASED VESTA JTAG TO TEST POINT NETS
REMOVED NV18/34 GPU
11/18/04
REMOVED BCM5231 ETHERNET PHY
10/21/04
(P 7) ADDED PLATED HOLE ZH710 FOR TMDS GROUNDING
REMOVED P50 AIRPORT AND Q23 BLUETOOTH CONNECTORS, HOLES, & STANDOFFS11/16/04
REMOVED EXTERNAL S/PDIF TRANSMITTER
ADDED Q85 AIRPORT & BLUETOOTH CONNECTOR
(PP 16,17) REPLACED FAN CONTROL WITH NEW CIRCUIT
ADDED TEST POINTS TO GRAPHICS FOR EXOR TESTING
CHECKIN 01005
ADDED RESISTORS TO STUFF AROUND USB FILTERSCHECKIN 01001
CONNECTED GPU GPIOS
ADDED 8MX32 GRAPHICS MEMORY
FRAME BUFFER SWAPS FOR CLEANER ROUTING
(P 5) NEW BOOTROM P/N
(P 76) FINISHED CONNECTING Q85 CONNECTOR
ADDED POWER SEQUENCING FOR GRAPHICS REGULATORSADDED REGULATOR FOR GPU TPVDD
(P 90) CHANGED R9090 TO 665 OHM
11/15/04
CHECKIN 01003 2.5V VREG COST REDUCTION
SET GPU VDDC_CT VREG TO 1.55V
REGULATOR COST REDUCTIONS
REMOVED OUTPUT CAP ON 1.2V_ALL VREG
GPU CORE VREG COST REDUCTION SHASTA FILTER COST REDUCTION
WHITE LED - CHANGED INDUCTORS TO 0 OHM RESISTORS
ADDED GPU STRAPS
CHECKIN 00009ADDED GIGABIT ETHERNET CONNECTOR
MASTER PAGE SYNC:
CHANGED FL5900-2 TO 220 OHM
CHEAPER SMU CRYSTAL
STUFFED AROUND TMDS FILTERS
11/01/04
CHECKIN 00008
REMOVED 1.6GHZ PROCESSORSCHANGED VOLTAGE SETTING OF 2.5V VREG TO 2.588V FROM 2.62V
11/06/04
ADDED SPACING & PHYSICAL CONSTRAINTS TO FRAME BUFFER
U2850 - REMOVED MAXIM AS AN ALTERNATE
11/04/04
CHECKIN 00003
REMOVED AGP VREG (VR5001)
CHECKIN 00005
GPU CORE POWER UPDATES
CHECKIN 00004
REMOVED GPU VTT VREG
ADDED RV351LE GPU
ADDED 2.5V VREG FOR A2VDD
REVISION HISTORY
ADDED 2.5V LDO FOR VESTA
10/26/04
10/22/04
ADDED VESTA
10/28/04
CHECKIN 00007
11/03/04
DESCRIPTION
REMOVED VESTA CORE REGULATOR
MOVED SMU RESET BUTTON TO DEVELOPMENT BOM
CHANGED FETS IN GPU CORE FOR COST REDUCTION
REMOVED VESTA ROM
AUDIO 3052A CODECADDED 1.55V VREG FOR GPU VDDC_CT
TIED PPVCORE_NB DIRECTLY TO PP1V5_PWRON (REMOVED R707)
CONNECTED GPU TEMP SENSORADDED AMBIENT LIGHT SENSOR CONNECTOR
ADDED 1.8V GPU VREG
AUDIO COST REDUCTIONS
ADDED MORE GPU CONSTRAINTS
STUFFED AROUND RGB FILTERS
5V & 3.3V PWRON FET COST REDUCTIONS 1.2V, 1.5V RUN FET COST REDUCTIONS 2.5V RUN FET COST REDUCTION
CHECKIN 00010ADDED DEVELOPMENT LEDS TO REGULATORS
11/09/04
CHEAPER USB2 CRYSTAL
CHANGED SOURCE OF Q1003 TO PP1V2_ALLRGB TERMINATION NOW CONNECTED TO DIGITAL GROUND
2.5V VREG COST REDUCTIONS
11/10/04
UPDATED POWER BLOCK DIAGRAM
CHECKIN 01002
MOVED VTT VREG TO 2.5V PWRON TO REDUCE CURRENT THROUGH Q903
1.2V VREG COST REDUCTIONS - Q1002 TO NTD60N02R; C1002/3 TO 10UF CERM
REMOVED ON BOARD POWER SUPPLY TEMP SENSOR
REMOVED CPU VREG 4TH PHASE
11/07/04
CHANGED FW LATE VG CIRCUITRY TO MATCH Q78 & Q86
CHECKIN 00006
REMOVED MICRODASH CONNECTORREMOVED FW PORT POWER CIRCUITRYREMOVED FW802A FW PHY
ADDED FW LATE VG PROTECTION
ADDED 1.2V REGULATOR FOR VESTA CORE
DATE
10/20/04CHECKIN 00002
CHECKIN 01004
CHECKIN 01006
(P 58) REPLACED THERMAL SENSOR WITH LM63
(P 22) CHANGED Q2250 TO 376S0143
(P 59) TIED UNUSED BUFFER ENABLE PINS HIGH
(P 46) SLEEP SIGNAL TURNS OFF VTT VREG
(P 12) VESTA_ENET_LOWPWR UPDATE(P 9) ADDED EXTRA 10UF INPUT CAP
ADDED VESTA ETHERNET LOWPWR CIRCUIT
REMOVED EXTERNAL TMDS TRANSMITTER
(P 7) TIED BOTH EI RAILS TO 1.5V
(P 18) MOVED SMU I2C E BUS
(P 90) FIXED FW PORT NAMING
CHECKIN 01007 / BOM RELEASE REV 02(P 9) ADDED PAD FOR 1NF CAP TO GATE OF Q903
ADDED PHYSICAL CONSTRAINTSAUDIO STUFFING CHANGESCHECKIN 02001
CONNECTED GPU TMDS AND VGA
ADDED VOLTAGE, LINE WIDTH, AND NECK WIDTH PROPERTIES FOR GRAPHICS (IN MM)
REPURPOSED 1.2V REGULATOR FOR VESTA AND SHASTA
MOVED SMU DOWNLOAD CONNECTOR TO DEVELOPMENT BOM
CLONED DESIGN FROM GILA (Q45 A/B) REV G
CHECKIN 02002
ADDED DEVELOPMENT LEDS FOR VESTA ENET
(P 3) CONNECTED SHASTA CORE POWER FOR POWER SEQUENCING
(P 58) ADDED CONSTRAINT SETS(P 59) STUFFED AROUND Q5900 PANEL PWR SEQUENCING
12/02/04
(P 76) TABLED IN NEW STANDOFFS FOR Q85 CARD
CHECKIN 02004
(P 76) NOW HAVE CORRECT SYMBOL FOR STANDOFFS
11/23/04
(P 76) J7650 - NEW TO ALLOW 5MM CONNECTED HEIGHT
CHECKIN 03002
(P 83) REMOVED SECOND SATA CONNECTOR
(P 90) FIXED ALIAS PROBLEM WITH FW_TPB2_PD
MADE ON & VISHAY FETS TRUE ALTERNATES(P 56) ADDED OPTION OF USING PWM FROM SHASTA
(P 16) C1653 - REPLACED WITH LOWER HEIGHT CAP(P5) ADDED U3L W/ NEW LAMINATE AS ALTERNATE
PROTO RELEASE (REV 3)
(P 90) FIXED FW_CPS SHORT(P 35) REMOVED DS3500 & DS3501
CONVERTED DISCRETES TO LEAD FREE
CHANGED U7700 BACK TO LEADED PART(P 5) REMOVED ORIGINAL U3LITE (NEW LAMINATE ONLY FOR C/D)(P 49) CHANGED GPU TO RV351LEP (338S0231)
12/07/04
CHECKIN 03001
UPDATE OF 2.5V RUN FET COST REDUCTIONFRAME BUFFER PIN SWAPS11/08/04
BOM RELEASE REV 01
BOM RELEASE REV 04
051-6772 04
4 102
Prelim
inary
-
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_11_HEAD
REFERENCE DESIGNATOR(S) BOM OPTIONQTY DESCRIPTION VALUE VOLT. WATT. TOL.PART # PACKAGEDEVICE
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_11_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#TABLE_5_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#TABLE_5_ITEM
TABLE_ALT_ITEM
ALTERNATES
MISC PARTS
PROCESSORS
VOLTAGE
QUALIFIED
ASICS
TABLE ITEMS
1.20V
1.25VWAVE3
WAVE5
1.25VWAVE5
WAVE3
U2300IC,ASIC,SHASTA,V1.1,PBGA1343S0283
051-6772 04
5 102
IC,GPUL,DD3,1.8G,BRA337S2969337S2970 CPU_DD30_1_8GHZ U2900
337S2981 IC,GPUL,DD3,1.8G,BPL337S2969 CPU_DD30_1_8GHZ U2900
337S2982 IC,GPUL,DD3,1.8G,BRL337S2969 CPU_DD30_1_8GHZ U2900
42W337S2969 CPU_DD30_1_8GHZ1 ? U2900PROCESSOR 1.8GHZ 1.20VIC,GPUL,10S,DD3,1.8G,85C,BPACBGA-576-1MM
U8600IC,ASIC,VESTA,V1.3343S0324 1
U75001341T1667 IC,FLASH,1MX8,3.3V,90NS
MLB11 PCB,FAB,MLB820-1747
1 LBL1BARCODE LABEL, MLB, Q45825-6447
343S0321 U3L,NEW LAM,200MMU3343S0320
1 U3343S0320 IC,U3LITE,NEW LAM,300MM,PBGA
1 SCH1PCB,SCHEM,MLB051-6772
PURCH ASSY, SMU BIG U1300341T1395 1
HEAT SINK ASSEMBLY 17 IN603-6015 1 17_INCH_LCDCRITICAL MECH17
HEAT SINK ASSEMBLY 20 IN603-6016 1CRITICAL 20_INCH_LCDMECH20
378S0114 KINGBRIGHT LEDLED700,LED702,LED5900
378S0119Q3310,Q3320,Q3410
MOSFET,N-CH,VISHAY376S0130376S0204Q3311,Q3321,Q3411
376S0146376S0207 MOSFET,N-CH,VISHAY
1062-2082 VPP1SPEC,VENDOR PACKAGING PROCEDURE
Prelim
inary
-
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
2 TEST POINTS
2 TEST POINTS
2 TEST POINTS2 TEST POINTS
FUNC TEST
2 TEST POINTS
2 TEST POINTS
2 TEST POINTS
10 TEST POINTS
5 TEST POINTS
5 TEST POINTS
12 TEST POINTS
5 TEST POINTS
5 TEST POINTS
5 TEST POINTS
5 TEST POINTS
2 TEST POINTS
GENZ SHOULD USE J1400 FOR THE FOLLOWING NETS:
2 TEST POINTS
I307
I337
I338
I344
I345
I346
I347
I348
I349
I350
I354
I355
I356
I357
I358
I359
I360
I361
I362
I363
I364
I365
I371
I372
I373
I374
I375
I376
I377
I378
I379
I380
I381
I382
I383
I384
I385
I386
I387
I388
I389
I390
I391
I392
I393
I394
I395
I396
I397
I398
I399
I400
I401
I402
I403
I404
I405
I406
I407
I408
I428
I429
I430
I431
I432
I433
I434
I435
I436
I437
I438
I439
I440
I441
I442
I443
I444
PP5V_ALL
PP12V_RUN PP5V_RUN
PP3V3_PWRON
PP5V_PWRONPP2V5_RUN
PP1V5_RUN
PP1V2_PWRON
PP3V3_RUN
11 7
18 11 10 7
50 34 22 18 11 10 7
83 7
7 83
18 11
58 27 18 11
13 8 7
31 8 7 3
7 33 34 35
22
34 33
33
33
8 7
13 7
7
7
13 8
46 22 11 10 8 9
33 13 11 10 7
13 8
22
9
59 58
59 58
59 58
83 80
83 80
83 80
83 80
83
83 80
83 80
83 80 6 83 80
6
83 80
83
83
83
83
33 8
36
36
36
36 33
36
36 33
59
59
59
59
59
59
59 58
59
59
59
59
59
59
77 76 75 74 73
77 76 74 73
8
76 74
76 74
76 25
77 76 74 73
74 56 8
77 76 74 73
77 76 74 73
77 76 74 73
77 76 74 73
77 76 74 73
76 75 74
76
76 75 74
76 75 74
76
76 75
76
76
92
92
92
92
92
92
92
92
92
94 25
94 25
94 25
94 25
94 25
94 25
94 25
92 91
92 91
25
25
59
59
59
59
59
59
59
59
59
59
59
59
59 7
101 25
75
PP24V_RUN
36 31
I781
I782
I784
I785
I786
I787
I788
I789
I790
I791
I792
I793
I794
I795
I796
I797
I798
I799
I800
I801
I802
I803
I804
I805
I806
I807
I808
I809
I810
101
90
101
101
18 17
18 17
25 18
25 18
36 33 31
36 33 31
83
051-6772102604
PP5V_ALL FUNC_TEST=YESPP12V_RUN FUNC_TEST=YES
PP5V_RUN FUNC_TEST=YES
GND FUNC_TEST=YES
PP3V3_PWRON FUNC_TEST=YESPP5V_PWRON FUNC_TEST=YES
PP2V5_RUN FUNC_TEST=YESFUNC_TEST=YESPP1V5_RUN
PP1V2_PWRON FUNC_TEST=YES
FUNC_TEST=YESPP3V3_RUNPP24V_RUN FUNC_TEST=YES
UATA_CS1_L FUNC_TEST=YES
UATA_STOPUATA_STOP FUNC_TEST=YES
FUNC_TEST=TRUEUATA_DASP_LTDIODE_NEG FUNC_TEST=YES
FUNC_TEST=TRUEUATA_DD
FUNC_TEST=YESROM_WP_LAUDIO_LO_DET_L FUNC_TEST=YES
SMU_RESET_L FUNC_TEST=YES
UATA_CS0_L FUNC_TEST=YESFUNC_TEST=TRUEUATA_DA
UATA_CSEL_PD FUNC_TEST=YESUATA_IOCS16_PU FUNC_TEST=YES
UATA_DMARQ_R FUNC_TEST=YES
UATA_RESET_L FUNC_TEST=YES
ANALOG_RED FUNC_TEST=YESU2200_FEEDBACK FUNC_TEST=YESU900_FEEDBACK FUNC_TEST=YES
SYS_POWERFAIL_L FUNC_TEST=YES
POWER_BUTTON_L FUNC_TEST=YES
PCI_CLK33M_AIRPORT FUNC_TEST=YESFUNC_TEST=TRUEPCI_CBE_L
PCI_SLOTA_REQ_L FUNC_TEST=YES
FUNC_TEST=TRUEI2C_SB_SDAFUNC_TEST=TRUEKPGND2FUNC_TEST=TRUEKPVDD2
FUNC_TEST=TRUETMDS_DCC_DATFUNC_TEST=TRUETMDS_DCC_CLK
FUNC_TEST=TRUEI2C_SB_SCL
AUD_MIC_IN_N_CONN FUNC_TEST=TRUEAUD_MIC_IN_P_CONN FUNC_TEST=TRUEFW_VP FUNC_TEST=TRUEGND_AUDIO_MIC_CONN FUNC_TEST=TRUEI2C_HD_TEMP_SCL FUNC_TEST=TRUEI2C_HD_TEMP_SDA FUNC_TEST=TRUE
FUNC_TEST=TRUEPCI_AD
FUNC_TEST=YESPP5V_USB2_PORT1_F
PCI_PAR FUNC_TEST=YES
USB_BT_P FUNC_TEST=YES
USB2_PORT1_P_F FUNC_TEST=YES
USB2_PORT3_P_F FUNC_TEST=YES
USB2_PORT2_N_F FUNC_TEST=YESUSB2_PORT2_P_F FUNC_TEST=YESUSB2_PORT3_N_F FUNC_TEST=YES
I2S1_RESET_L FUNC_TEST=YES
I2S1_MCLK FUNC_TEST=YESI2S1_BITCLK FUNC_TEST=YES
TP_NB_PM_SLEEP0NO_TEST=YES
PCI_RESET_L FUNC_TEST=YES
ROM_ONBOARD_CS_L FUNC_TEST=YES
PCI_SLOTA_GNT_L FUNC_TEST=YESPCI_SLOTA_INT_L FUNC_TEST=YES
PCI_IRDY_L FUNC_TEST=YESPCI_STOP_L FUNC_TEST=YESPCI_DEVSEL_L FUNC_TEST=YES
FUNC_TEST=YESPP5V_USB2_PORT3_F
ANALOG_BLU FUNC_TEST=YES
NO_TEST=YES PLS_CLK_66M_1_RNO_TEST=YES PLS_CLK_66M_0_R
EI_CPU1_SYNCNO_TEST=YESTP_PROC_TRIGGER_OUTNO_TEST=YESSYNCENABLENO_TEST=YESRI_LNO_TEST=YESMCP_LNO_TEST=YESI2C_SMU_A_SDA_OUT_LNO_TEST=YESI2C_SMU_A_SCL_OUT_LNO_TEST=YESEI_SENO_TEST=YESEI_QREQ_LNO_TEST=YESEI_QACK_LNO_TEST=YESEI_CPU1_CLK_PNO_TEST=YESEI_CPU1_CLK_NNO_TEST=YESCPU1_HTBENNO_TEST=YESCPU_INT_LNO_TEST=YESCPU_HRESET_LNO_TEST=YESCHKSTOP_LNO_TEST=YES
NO_TEST=TRUE EI_NB_TO_CPU_SR_NNO_TEST=TRUE EI_NB_TO_CPU_SR_P
NO_TEST=YES EI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_ADNO_TEST=TRUEEI_NB_TO_CPU_CLK_NNO_TEST=YES
EI_CPU_TO_NB_SR_PNO_TEST=TRUENO_TEST=TRUE EI_CPU_TO_NB_SR_N
EI_CPU_TO_NB_CLK_PNO_TEST=YESEI_CPU_TO_NB_CLK_NNO_TEST=YES
NO_TEST=TRUE EI_CPU_TO_NB_AD
TP_J4000_SJRESET_LNO_TEST=YESTP_J4001_SJRESET_LNO_TEST=YES
U2100_UNUSEDNO_TEST=YES
TP_RAM_MUXEN4NO_TEST=YES
TP_RAM_CKE_RNO_TEST=YES
SMU_MANUAL_RESET_L FUNC_TEST=YES
FUNC_TEST=YES=PPVCORE_PWRON_SB=PP3V3_ALL_SMU FUNC_TEST=TRUE
FUNC_TEST=YESSYS_POWER_BUTTON_L
FUNC_TEST=YES=PP5V_DISKFUNC_TEST=YES=PP12V_DISK
I2S1_DEV_TO_SB_DTI FUNC_TEST=YES
I2S1_SB_TO_DEV_DTO FUNC_TEST=YES
I2S1_SYNC FUNC_TEST=YES
TP_RAM_CKE_RNO_TEST=YES
TP_RAM_CKE_RNO_TEST=YESTP_RAM_CKE_RNO_TEST=YES
TP_RAM_CS_L_RNO_TEST=YESTP_RAM_CS_L_RNO_TEST=YES
TP_RAM_CS_L_RNO_TEST=YESTP_RAM_CS_L_RNO_TEST=YES
TP_AFNNO_TEST=YES
TP_AGP_MB_AGP8X_DET_LNO_TEST=YESTP_ATTENTIONNO_TEST=YES
TP_DUMMY_ANO_TEST=YESTP_DUMMY_BNO_TEST=YES
TP_FBBCS1_LNO_TEST=YES
TP_NEC_AMCNO_TEST=YESTP_NEC_NANDTESTNO_TEST=YESTP_NEC_NTEST1NO_TEST=YESTP_NEC_SMCNO_TEST=YESTP_NEC_SMI_LNO_TEST=YESTP_NEC_SRCLKNO_TEST=YESTP_NEC_SRDATANO_TEST=YESTP_NEC_SRMODNO_TEST=YESTP_NEC_TEBNO_TEST=YESTP_NEC_TESTNO_TEST=YESTP_PLS_CLK_66M_0NO_TEST=YESTP_PLS_CLK_66M_1NO_TEST=YESTP_PLS_REF_CMLNO_TEST=YESTP_PLS_TEST1NO_TEST=YESTP_PLS_TEST2NO_TEST=YESTP_PLS_TEST3NO_TEST=YES
TP_PSRO1NO_TEST=YESTP_PSRO2NO_TEST=YESTP_PSYNCOUTNO_TEST=YES
TP_RAM_MUXEN0NO_TEST=YES
TP_SATA_CLK25MNO_TEST=YES
TP_SB_FSTESTNO_TEST=YES
TP_SB_NC_P7NO_TEST=YESTP_SB_NC_P8NO_TEST=YESTP_SB_NC_R3NO_TEST=YESTP_SB_NC_R4NO_TEST=YESTP_SB_NC_R5NO_TEST=YESTP_SB_NC_R6NO_TEST=YESTP_SB_NC_R7NO_TEST=YESTP_SB_NC_R8NO_TEST=YESTP_SB_NC_T1NO_TEST=YESTP_SB_NC_T2NO_TEST=YESTP_SB_NC_T3NO_TEST=YESTP_SB_NC_T4NO_TEST=YESTP_SB_NC_T5NO_TEST=YESTP_SB_NC_T6NO_TEST=YESTP_SB_NC_T7NO_TEST=YESTP_SB_NC_T8NO_TEST=YESTP_SB_NC_U1NO_TEST=YESTP_SB_NC_U2NO_TEST=YESTP_SB_NC_U3NO_TEST=YESTP_SB_NC_U4NO_TEST=YESTP_SB_NC_U5NO_TEST=YESTP_SB_NC_U6NO_TEST=YESTP_SB_NC_V1NO_TEST=YESTP_SB_NC_V2NO_TEST=YESTP_SB_NC_V3NO_TEST=YESTP_SB_NC_V4NO_TEST=YESTP_SB_NC_W1NO_TEST=YESTP_SB_NC_W3NO_TEST=YESTP_SB_NC_Y1NO_TEST=YES
TP_SB_NC_Y3NO_TEST=YES
TP_SB_PLLTESTNO_TEST=YES
TP_USB2_PWRENNO_TEST=YESTP_USB2_PWRENNO_TEST=YES
TP_USB2_PWRENNO_TEST=YESTP_USB2_PWRENNO_TEST=YESTP_USB2_PWRENNO_TEST=YES
TP_VREF_CGNO_TEST=YES
UATA_DMACK_L FUNC_TEST=YES
FUNC_TEST=YESUSB2_PFUNC_TEST=YESUSB2_N
USB2_PORT1_N_F FUNC_TEST=YES
ANALOG_GRN FUNC_TEST=YES
CORE_ISNS_M FUNC_TEST=YESCORE_ISNS_P FUNC_TEST=YES
FILT_ANALOG_BLU FUNC_TEST=YESFILT_ANALOG_GRN FUNC_TEST=YESFILT_ANALOG_RED FUNC_TEST=YES
GND_17_INV FUNC_TEST=YES
GND_20_INV FUNC_TEST=YES
GND_CHASSIS_TMDS FUNC_TEST=YES
INV_17_CUR_HI_F FUNC_TEST=YES
INV_17_LCD_PWM_F FUNC_TEST=YES
INV_20_CUR_HI_F FUNC_TEST=YESINV_20_LCD_PWM_ FUNC_TEST=YES
MODEM_RING2SYS_L FUNC_TEST=YES
MON_DETECT FUNC_TEST=YES
PCI_SLOTA_IDSEL FUNC_TEST=YES
PP12V_INV FUNC_TEST=YES
PP24V_INV FUNC_TEST=YES
PP3V3_DDC FUNC_TEST=YES
FUNC_TEST=YESPP5V_USB2_PORT2_F
PPVCC_TMDS FUNC_TEST=YES
ROM_CS_L FUNC_TEST=YESROM_OE_L FUNC_TEST=YES
TCKP FUNC_TEST=YES
TD0M FUNC_TEST=YESTD0P FUNC_TEST=YESTD1M FUNC_TEST=YESTD1P FUNC_TEST=YESTD2M FUNC_TEST=YESTD2P FUNC_TEST=YES
TDIODE_NEG_FMAX FUNC_TEST=YESTDIODE_POS_FMAX FUNC_TEST=YES
FUNC_TEST=YESI2C_TMDS_SDA
UATA_DSTROBE_R FUNC_TEST=YES
UATA_INTRQ_R FUNC_TEST=YES
UDASH_RESET_L FUNC_TEST=YES
FUNC_TEST=YESVCORE_SENSE_GND
FUNC_TEST=TRUECPU_VID_R
AIRPORT_CLKRUN_L_PD FUNC_TEST=YES
UDASH_SDOWN FUNC_TEST=YES
TCKM FUNC_TEST=YES
FUNC_TEST=YESI2C_TMDS_SCL
PP5V_AGP_RL FUNC_TEST=YES
KPVDD2_FMAX FUNC_TEST=YESKPGND2_FMAX FUNC_TEST=YES
UATA_HSTROBE FUNC_TEST=YES
FUNC_TEST=YESSYS_SLEEP
VCORE_SENSE_VOUT FUNC_TEST=YESUSB_BT_N FUNC_TEST=YES
ROM_WE_L FUNC_TEST=YES
FUNC_TEST=YESSYS_POWERUP_L
RESET_BUTTON_L FUNC_TEST=YES
PCI_TRDY_L FUNC_TEST=YESPCI_FRAME_L FUNC_TEST=YES
=PP5V_RUN_CPU FUNC_TEST=YESPPVCORE_NB FUNC_TEST=YESPPVCORE_CPU FUNC_TEST=YESPP12V_CPU FUNC_TEST=YES
30
30
30
30
30
18
18
29
29
29
29
30
29
29
29
29
29
29
29
29
29
29
29
27
29
29
29
29
14
14
28
28
28
27
27
25
29
14
28
28
28
28
28
28
28
28
28
28
24
27
27
14
14
14
14
14
13
13
14
14
14
14
14
14
14
14
8
14
14
14
14
14
14
14
14
14
14
40
40
21
8
8
8
8
8
8
8
8
8
29
48
29
24
24
52
77
77
77
77
77
77
77
77
77
77
27
27
27
27
27
27
29
29
29
8
27
25
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
25
92
92
92
92
92
48
Prelim
inary
-
ALIAS
ALIAS
ALIAS
ALIAS
125
ALIAS
ALIAS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
CHASSIS GND
ALL RAILSALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
SDF700 IS USED FOR CPU HEATSINK MOUNTING
POWER CONN / ALIAS
SILKSCREEN:2
RUN RAILS
SMU RESET
SILKSCREEN:POWER
SILKSCREEN:1
PIN 13,19,11,22 ARE DIFFERENCE FROM ATX .
RESET
ALWAYS ON (TRICKLE)
ONLY ON IN RUN
RTC BATTERY
SILKSCREEN:RUN
805-5664
516S0248FOXCONN
P/N 518-0159
POWER
GND RAILS
ON IN RUN AND SLEEP
PWRON RAILS
PP5V_RUN
PP3V3_PWRON
PP1V5_PWRON
PP2V5_PWRON
PP1V2_PWRON
PP24V_RUN
PP5V_ALL
PP5V_ALL PP3V3_RUN
PP2V5_RUN
PP5V_PWRON
PP1V5_RUN
PP5V_RUNPP3V3_RUN
PP5V_RUNPP12V_RUN
SM21
XW700
SM21
XW701
315R1381
ZH700
SM21
XW702
SM21
XW703
402CERM10V20%0.1UF
2
1 C70420%10V
402CERM
0.1UF2
1 C705
PP12V_RUN
SPSTSM
43
21
SW702
5%
1K
402MF-LF1/16W
21
R713
SPST
DEVELOPMENT
SM
43
21
SW7015%402
1K
1/16WMF-LF
DEVELOPMENT
21R712
DEVELOPMENT
SPSTSM
43
21
SW700
315R1381
ZH701
7R4.151
ZH702
6.00MM-PTH1
ZH703
1/16WMF-LF402
5%
1K21
R702
SHLD-IO-CONNQ45-TH1
4
32
1
SH700
SOD-123
B0530WXF
2 1
DS700
PP1V2_RUN
74LCX125
TSSOP
CRITICAL
314
17
2
U700402CERM10V20%0.1UF
2
1 C700
SYS_PWR_BTN_FILT
FERR-EMI-100-OHM
SM
21
L700
SM
FERR-EMI-100-OHM21
L701
DEVELOPMENT
GREEN2.0X1.25A
2
1
LED7012.0X1.25A
GREEN
2
1
LED702
PP3V3_PWRON
5%MF-LF
330
6031/10W
21
R700
GREEN2.0X1.25A
2
1
LED700
F-RT-THHM96110-P2
CRITICAL
9
8
7
6
5
4
3
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J700
SM21
XW704
SM21
XW705
SM21
XW706
SM21
XW707
HSK-NUT-6.5MMTH
NOSTUFF
1
SDF700
PP12V_RUN
PP24V_RUN
CRITICAL
ST-SM3PWR-BUTT
2
1
54
3
SW703
PP3V3_RUN
805MF-LF1/8W5%
0
NOSTUFF
21
R720
315R1381
ZH710
MF-LF5%
1/10W
330
603
21
R710
10VCERM
20%0.1UF
4022
1 C703
1/10W5%MF-LF
DEVELOPMENT
330
603
21
R701
PP5V_ALL
CRITICAL
TH
BB10209-A51 2
J702
051-6772
1027
04
VOLTAGE=3.3V
_PP5V_PWRON_USB
_PP3V3_PWRON_BT=PP3V3_PWRON_CPU
=PP5V_PATA
=PP3V3_PWRON_VESTA
SYS_POWERUP_L_BUF
=PP3V3_PWRON_EI
=PPPCI64_PWRON_SB
POWER_BUTTON_L
SMU_MANUAL_RESET_L
=PP1V5_PWRON_NB_AVDD
=PPVCORE_NB=PPVCORE_PWRON_PULSAR
=PP1V2_ENETFWPP1V2_VESTA
MIN_LINE_WIDTH=25MILMAKE_BASE=TRUEPP1V2_ALLVOLTAGE=1.2VMIN_NECK_WIDTH=15MIL
PP5V_AUDIO
ITS_RUNNING
=PP5V_AGP=PP5V_RUN_CPU
=PP3V3_AGP
=PP3V3_RUN_CPU
GND_SYS_PWR_BTN_FILT
RESET_BUTTON_L
SYS_POWER_BUTTON_L
ITS_PLUGGED_IN
POWER_GOOD
=PP1V2_PWRON_SB
=PP3V3_ALL_RTC
MAKE_BASE=TRUE
PP3V3_ALL_RTC
MIN_NECK_WIDTH=10MILMIN_LINE_WIDTH=25MILVOLTAGE=3.3V
=PP1V2_PWRON_HT=PP1V2_PWRON_DISK_SB
=PP3V3_SB_PCI
=PP2V5_PWRON_HT
=PP2V5_PWRON_RAM=PP2V5_HT
SYS_POWERUP_L
PP3V3_ALL_BATT
MIN_NECK_WIDTH=10MILMIN_LINE_WIDTH=25MILVOLTAGE=3.3V
MIN_NECK_WIDTH=10MILMIN_LINE_WIDTH=25MILVOLTAGE=3.3V
PP3V3_ALL_BATT_SAFETY
PP3V3_ALL
GND_AUDIO_SPKRAMP
ITS_ALIVE
=PP24V_GRAPHICS
PP12V_AUDIO_CODEC
PP12V_AUDIO_SPKRAMP
=PP12V_AGP=PP12V_RUN_CPU=PP12V_DISK
PP3V3_AUDIO
=PP3V3_PATA
=PP3V3_DISK
PP2V5_GPU
=PP2V5_RUN_CPU=PP2V5_RUN_RAM
=PPVCORE_PULSAR
=PPVCORE_CPUMAKE_BASE=TRUEPPVCORE_CPU
=PP3V3_PWRON_SB
=PPPCI32_PWRON_SB
GND_AUDIO
SYS_POWER_BUTTON_L
SYS_RESET_BUTTON_L
=PP5V_DISK
VOLTAGE=0MIN_NECK_WIDTH=10MILMIN_LINE_WIDTH=25MIL
GND_CHASSIS_17_INCH_INVERTER
MIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MILVOLTAGE=0
GND_CHASSIS_20_INCH_INVERTER
=PP3V3_PWRON_USB_PP3V3_PWRON_MODEM
=PP5V_PWRON_CPU=PP5V_PWRON_RAM
GND_CHASSIS_LED
GND_CHASSIS_RJ45
VOLTAGE=0MIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=15MIL
=PP5V_ALL_CPU
MAKE_BASE=TRUEVOLTAGE=3.3VMIN_LINE_WIDTH=25MIL
PP3V3_ALL
MIN_NECK_WIDTH=10MIL
=PP3V3_ENETFW=PP3V3_FW=PP3V3_ENETPP3V3_VESTA=PP3V3_ALL_CPU=PP3V3_ALL_SMU
=PPVCORE_PWRON_SB
GND_CHASSIS_AUDIO_EXTERNALMIN_NECK_WIDTH=15MIL
MIN_LINE_WIDTH=25MILMAKE_BASE=TRUEVOLTAGE=0
GND_CHASSIS_USBGND_CHASSIS_VGA
GND_CHASSIS_FIREWIRE
MIN_NECK_WIDTH=15MILVOLTAGE=0MIN_LINE_WIDTH=25MILGND_CHASSIS_TMDS
MAKE_BASE=TRUEGND_CHASSIS_AUDIO_INTERNAL
=PP2V5_PWRON_SB
=PP2V5_ENET
PPVCORE_GPU
=PP1V2_PULSAR
=PP1V2_HT
=PP1V5_AGP
=PP1V2_EI_CPU=PP1V2_EI_NB
=PP3V3_PCI
MIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE
=PPVIO_PCI_USB2
MIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MILVOLTAGE=5V
MAKE_BASE=TRUE
PP5V_ALL
MIN_LINE_WIDTH=12MILMAKE_BASE=TRUEMIN_NECK_WIDTH=8MIL
PP3V3_RUN
MAKE_BASE=TRUE
VOLTAGE=24VMIN_NECK_WIDTH=10MILMIN_LINE_WIDTH=25MIL
VOLTAGE=12VMIN_LINE_WIDTH=25MILMAKE_BASE=TRUEMIN_NECK_WIDTH=10MIL
VOLTAGE=1.2VMAKE_BASE=TRUEMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUEVOLTAGE=1.5VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=10MILMAKE_BASE=TRUEMIN_LINE_WIDTH=25MILVOLTAGE=5V
VOLTAGE=2.5V
MIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUEMIN_NECK_WIDTH=10MILVOLTAGE=1.2V
MAKE_BASE=TRUEMIN_LINE_WIDTH=25MIL
MAKE_BASE=TRUEMIN_NECK_WIDTH=10MILVOLTAGE=2.5VMIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MILMIN_LINE_WIDTH=25MIL
MAKE_BASE=TRUEVOLTAGE=1.5V
VOLTAGE=3.3VMIN_NECK_WIDTH=10MILMAKE_BASE=TRUEMIN_LINE_WIDTH=25MIL
VOLTAGE=5VPP5V_RUN
MIN_NECK_WIDTH=10MILVOLTAGE=0V
MIN_LINE_WIDTH=25MIL
50 59
35
34 58
33
31
77
22
60
31
56
46
13
102
55
36 35
88
30
76
18
18
48
8
50
13
40
11
59
101
54
32 34
74
13
59 13
23
74
51
50
29
28
75
11
11
8
37
89
59
6
49
7
37
64
10
11
102
59
83
100
52
45
31 33
25
7
83
11
90
87
8
6
102
59
25
50
60
49
18
18
74
11
10
10
92
76
36
83
12
28
23
6
6
28
22
26
86
12 10
101
50
3
48
33
6
6
8
25
13
62
80
74
62
26
60
6
7
100
59
102
100
50
33
6
95
83
83
50
31
44
26
29 6
23
23
102
6
13
6
59
59
91
94
36
46
21
87
36
7
89
89
86
12
36
6
3
101
92
59
90
6
101
23
87
22
26
24
48
14
14
25
77
6
6
6
Prelim
inary
-
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
125
125
125
ALIAS
G
D
S
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
MC33465N_30ATR
RESETDELAY
VCC
GND
VOLTAGE DETECTOR
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
VESTA JTAG PULL DOWNSHASTA JTAG
THESE PINS HAVE INTERNAL PULLUPS
CONNECTION
SIGNAL FROM POWER SUPPLY(SMU_BOOT_EPM)
CONNECTOR
SIGNAL ALIAS
518S0104
PLL LOCK LED
SMU ANALOG VREF
CHKSTOP LED
DIAG LED
2.2V FOR CPU VRM10.
CPU VID
NOTE:PULL UP CPU_VIDTO
VID CONTROLLED BY SMU
SMU
PCI CLOCKS
DIFFERENTIAL_PAIRNET_SPACING_TYPEELECTRICAL_CONSTRAINT_SET
PULSAR ERROR_L LEDBACKUP SMU RESET CIRCUIT
DOWNLOAD
518-0158
J802 & R826 CAN MOVE TO DEVELOPMENT BOM POST RAMP
POWER_GOOD IS A 5V DRIVEN
2K PULLUP INSIDE P/S
POWER_FAIL_L
SDF700 IS ALSOUSED FOR HEATSINKMOUNTING
CPU HEATSINK SMT NUTS
1/16W10KMF-LF402
5%
2
1R825
DEVELOPMENT
402MF-LF1/16W5%
1002 1
R826
5%
0
1/16WMF-LF402
21
R802
10K
402MF-LF
5%1/16W
2
1R803NOSTUFF10K5%1/16WMF-LF4022
1R8075%
4021/16W10KMF-LF
2
1R806
402
1/16W
05%
NOSTUFF
MF-LF
21
R828
TSSOP
74LCX1256
14
47
5
U700
TSSOP
74LCX1258
14
107
9
U700
74LCX125
TSSOP
1114
137
12
U700
402MF-LF1/16W5%4.7K
2
1R870
PP2V5_PWRON
402MF-LF1/16W5%10K
2
1R8141/16W10K5%
MF-LF4022
1R8165%1/16WMF-LF
10K
4022
1R817
402
10K
MF-LF1/16W5%
2
1R80810K
402
5%1/16WMF-LF
2
1R809
NOSTUFF
5%1/16WMF-LF
1K
4022
1R8271/16W
NOSTUFF
1K5%
MF-LF4022
1R8291/16W
NOSTUFF
1K5%
MF-LF4022
1R830NOSTUFF
1K5%1/16WMF-LF4022
1R831
PP3V3_RUN
MF-LF1/16W5%10K
4022
1R804
MF-LF1/16W5%20K
4022
1R811
THHSK-NUT-6.5MM
NOSTUFF
1
SDF800NOSTUFF
THHSK-NUT-6.5MM
1
SDF801
NOSTUFF
THHSK-NUT-6.5MM
1
SDF803
NOSTUFF
THHSK-NUT-6.5MM
1
SDF802
SMRED
DEVELOPMENT
2
1D810
6P15R5P4
OMIT
1
ZH804
402
0.01UF20%16VCERM2
1 C880
402
0.01UF20%16VCERM2
1 C881
402
0.01UF20%
CERM16V2
1 C882
402
0.01UF20%16VCERM2
1 C883
CERM16V20%0.01UF
4022
1 C884
402MF-LF1/16W5%180
DEVELOPMENT
2
1R833
REDSM
DEVELOPMENT
2
1LED801
2N7002SOT23-LF
DEVELOPMENT
Q800_D
2
1
3
Q800
1801/16WMF-LF402
5%
DEVELOPMENT
2
1R834
2N3904LFSOT23
DEVELOPMENT
Q801_B2
3
1 Q801
SM
DEVELOPMENT
2N3906 2
3
1
Q802
402
DEVELOPMENT
5%1801/16WMF-LF
2
1R835
180
1/16WMF-LF402
DEVELOPMENT
5%
21
R836GREEN2.0X1.25A
DEVELOPMENT
2
1
LED802
180
MF-LF402
5%1/16W
DEVELOPMENT
2
1R837
402MF-LF1/16W1K5%
DEVELOPMENT
2
1R838
2N3904LFSOT23
DEVELOPMENT
2
3
1 Q8031801/16WMF-LF402
5%
DEVELOPMENT
21
R839
1K
NOSTUFF
5%1/16WMF-LF4022
1R832
I246
I247
REDSM
2
1LED850
2N3904LFSOT23
2
3
1 Q8501K1/16W402
MF-LF
5%
21
R851
PP5V_ALL
402
5%180
MF-LF1/16W
2
1R850
402
1/16W4305%
MF-LF2
1R813
MF-LF402
5%4.7K1/16W
2
1R860
402
5%MF-LF
1K
NOSTUFF
1/16W
2
1R890
402
6.3V10%1uF
CERM
NOSTUFF
2
1 C891
NOSTUFFSM
2
1
3
5
U890
CERM16V10%
402
NOSTUFF
0.01UF2
1C890
05%
1/16WMF-LF402
21
R810
0.1uF10V20%
CERM402
NOSTUFF
2
1C800
DEVELOPMENT
M-ST-THHC17051
9
87
65
43
2
10
1
J802
1/16W10KMF-LF402
5%
2
1R840
01/16W
402MF-LF
5%
NOSTUFF
2
1R805
PP3V3_ALL
F-ST-SM
DEVELOPMENT
U.FL-R_SMT
1
2
3
J800
PP3V3_ALL
1/16W10KMF-LF402
5%
NOSTUFF
2
1R812
NOSTUFF
SSOT-23
2.5V
31
2
VR801
1%
402MF-LF1/16W200
NOSTUFF
2
1R818
805CERM10V20%
2.2UF
NOSTUFF
2
1C801
603
0.47UF20%10VCERM
NOSTUFF
2
1 C802
NOSTUFF
F-ST-SM
BM12B-SRSS-TB
98765432 12
11
10
1 13
14
J803
402MF-LF
0
5%1/16W
21
R819
1/16W5%
0
402MF-LF
21
R820
402
5%
MF-LF
0
1/16W
21
R821
0
5%1/16WMF-LF402
21
R822
402
5%
MF-LF1/16W
021
R823
402
5%
MF-LF1/16W
021
R824
1/16WMF-LF
402
5%
DEVELOPMENT
4.7K
2
1R8015%1/16W402
330
MF-LF
DEVELOPMENT
2
1R800
PP3V3_RUN
04
8 102
051-6772
RAM_CS_L_R
PPVREF_SMUMAKE_BASE=TRUE
SMU_BOOT_SCLK
SMU_BOOT_CNVSS SMU_BOOT_TXD
CPU_VID_R
CPU_VID_R
CPU_VID_R
SMU_BOOT_CESMU_MANUAL_RESET_L
J802_6
J802_2SMU_BOOT_RXD
NB_SUSPEND_ACK_L
ALS1_OUT
SMU_MANUAL_RESET_L
=PP3V3_ALL_SMU
=PCI_ROM_RESET_L=PCI_USB2_RESET_L
CPU_VID_R
10 MIL SPACINGSMU_RESET SYS_WARM_RESET_LSMU_RESET SYS_COLD_RESET_L10 MIL SPACING
CPU_VID_R
FAN_PWM8
RAM_CKE_R
TP_ALS1_OUTMAKE_BASE=TRUE
TP_ALS0_OUTMAKE_BASE=TRUE
PCI_RESET_LMAKE_BASE=TRUE
SYS_SLOT_PWR
RAM_CKE_R
NB_THMONB_THMI
MAKE_BASE=TRUETP_NB_THMI
MAKE_BASE=TRUETP_RAM_CKE_R
MAKE_BASE=TRUETP_RAM_MUXEN4
RAM_MUXEN0
PCI_CLK_P4RAM_CKE_R
GPU_RESET_L
SMU_WARM_RESET_LMAKE_BASE=TRUE
PCI_AIRPORT_RESET_L
MAKE_BASE=TRUEPCI_CLK33M_AIRPORT
MAKE_BASE=TRUETP_RAM_CS_L_R RAM_CS_L_R
MAKE_BASE=TRUETP_RAM_CS_L_R RAM_CS_L_R
MAKE_BASE=TRUETP_RAM_CS_L_R
MAKE_BASE=TRUETP_RAM_CS_L_R RAM_CS_L_R
TP_RAM_MUXEN0MAKE_BASE=TRUE
RAM_MUXEN4
TP_RAM_CKE_RMAKE_BASE=TRUE
MAKE_BASE=TRUETP_RAM_CKE_R
TP_RAM_CKE_RMAKE_BASE=TRUE
RAM_CKE_RMAKE_BASE=TRUE
TP_THMO
NB_WARM_RESET_L
MAKE_BASE=TRUETP_FAN_PWM8
TP_SYS_DRIVE_BAY_INT_LMAKE_BASE=TRUE
SYS_DRIVE_BAY_INT_L
TP_SYS_DOOR_AJAR_LMAKE_BASE=TRUE
SYS_DOOR_AJAR_L
MAKE_BASE=TRUETP_SYS_SLOT_PWR
MAKE_BASE=TRUETP_SMU_PWRSEQ_P1_3 SMU_PWRSEQ_P1_3
TP_SMU_ONEWIREMAKE_BASE=TRUE
SMU_ONEWIREMAKE_BASE=TRUE
TP_ALS_GAIN_BOOST ALS_GAIN_BOOST
ALS0_OUT
MAKE_BASE=TRUETP_PCI_CLK_P4
MAKE_BASE=TRUEPCI_CLK33M_SB_EXT PCI_CLK_P1
MAKE_BASE=TRUETP_PCI_CLK_GP1 PCI_CLK_GP1
_PCI_CLK33M_AIRPORTPCI_CLK_P3
=PCI_CLK33M_USB2PCI_CLK_GP0
MAKE_BASE=TRUEPCI_CLK33M_USB2
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
MAKE_BASE=TRUEDIAG_LED DIAG_LED_R
CPU_VID_R
LED850P2
LED850P1
=PP5V_RUN_CPU
NB_SUSPENDACK_L
SYS_SLEEP
SMU_WARM_RESET_L SYS_WARM_RESET_L
=PPVREF_SMU
PP3V3_ALL_SMU_AVCC
Q802_E
HS_SDF803
HS_SDF800 HS_SDF801 HS_SDF802
GND_SMU_AVSS
Q803_B
Q803_CLED802_1 Q800_G
LED801_1
NB_PMR_OBSV
GND_SMU_AVSS_DAGND
PPVREF_SMU_ADC_REF
SMU_SLEEP
SMU_BOOT_BUSY
Q802_B
PLLLOCK
HS_SDF804
=PP5V_RUN_CPU
POWER_GOOD
SYS_POWERFAIL_L
CHKSTOP_L
MAKE_BASE=TRUETP_JTAG_SB_TCK
MAKE_BASE=TRUETP_JTAG_SB_TMSMAKE_BASE=TRUETP_JTAG_SB_TDOMAKE_BASE=TRUETP_JTAG_SB_TDI
JTAG_SB_TCK
JTAG_SB_TMSJTAG_SB_TDOJTAG_SB_TDI
JTAG_SB_TRST_L
TP_JTAG_VESTA_TDIMAKE_BASE=TRUE
TP_JTAG_VESTA_TMSMAKE_BASE=TRUE
TP_JTAG_VESTA_TCKMAKE_BASE=TRUE
=JTAG_VESTA_TDITP_JTAG_VESTA_TDO
MAKE_BASE=TRUE
SMU_RESET_L
=JTAG_VESTA_TMS=JTAG_VESTA_TDO
=JTAG_VESTA_TCK
ERROR_LED
CLOCK_ERROR_L
=JTAG_VESTA_TRST_LMAKE_BASE=TRUE
JTAG_VESTA_TRST_L
46
31
22
31
77
8
11
77
8
8
8
13
74
74
7
10
74
36
7
29
33
33
33
7
7
7
33
25
24
33
56
13
74
33
6
9
13 25
33
6
13
14
13
37
13
13 13
6
6
6
13
6
13
24
13
6
6
75
77
6
8
13
6
13
37
6
13
37
24
24
6
6
37
27 37
49
8
76
6
6 37
6 37
6
6 37
6
37
6
6
6 37
24
13
13
13
13
13
13
27 27
27
76
27
77
27
13
13
13
13
13
13
13
6
3
13
6
8 8
13
13
13
24
36
36
13
13
29
3
7
6
6
25
25
25
25
25
12
6
12
12
12
27
12
Prelim
inary
-
FB
LD
HD
GND
COMP
SS
VCC VC
G
D
S
G
D
S
G
D
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
2.5V VREG
U900_FEEDBACK
2.5V VOLTAGE REGULATOR
IRU3037CS VREF=1.25VDCVOUT=VREF*(R903+R905)/R905=2.588VDC
SET OUTPUT=2.588V FOR FRAMEBUFFER. NOTE:
PEAK CURRENT OF TOTAL RAILS
9.24A WITHOUT DIMM TERMINATION12.68A WITH DIMM TERMINATION
HIGH TO ENABLE
805
1/8W5%
MF-LF
021
R902
1%
MF-LF402
1/16W10K
2
1R905
5%
NOSTUFF
MF-LF1206
1/4W1.1K
2
1R904
20%6.3VELECTH-KZJ
1800UF2
1 C908
CERM
10UF6.3V20%
12062
1 C901
TH-KZJ
20%ELEC6.3V
1800UF2
1 C909
PP5V_PWRON
805CERM
1UF20%25V2
1 C904
PP5V_PWRON
SOD-123MBR0520LXXG
2 1D900
SOD-123MBR0520LXXG
2 1D901
MBR0520LXXGSOD-123
2
1D902
603CERM10V20%1UF
2
1 C917
603
5%2200PF50VCERM2
1 C905
805CERM25V20%1UF
2
1 C916PP2V5_PWRON
PP2V5_RUN
220PF25V5%CERM402
2
1 C906
1.6UH
CRITICAL
TH
21
L901IRU3037CS
SOI
2 6
8
3
5
4
1
7
U900
10.7K
MF-LF1/16W1%
4022
1R903
603CERM
0.47UF20%10V2
1 C915MF-LF
27.4K1/16W1%
4022
1R901
56PF50VCERM402
5%2
1 C913
3300PF
603
10%CERM50V
NOSTUFF
2
1 C907
603
3900PF5%CERM50V2
1 C914
4.7
805
1/8WMF-LF
5%
2
1R900
402
240
DEVELOPMENT
MF-LF1/16W5%
2
1R950
GREEN
DEVELOPMENT
2.0X1.25A
2
1
LED900
SO-8IRF7413
321
4
8765
Q903
PP12V_RUN
2N7002SOT23-LF
2
1
3
Q940
MF-LF402
5%1/16W470K
2
1R940NOSTUFF
1UF20%CERM25V
12062
1 C912
NTD60N02RCASE369
3
1
4Q901
NTD60N02RCASE369
3
1
4Q902
20%6.3VELECTH-KZJ
1800UF2
1 C9021800UF
TH-KZJELEC6.3V20%
2
1 C9031800UF
TH-KZJELEC6.3V20%
2
1 C910
1206
20%6.3V
10UF
CERM2
1 C911
0.001UF20%50VCERM402
NOSTUFF
2
1 C940
051-6772 04
9 102
Q903_GATE
U900_VC
U900_VC_R
U900_FEEDBACK
Q901_GATE
U900_GATE_LQ902_DRAINMIN_NECK_WIDTH=10MILMIN_LINE_WIDTH=25MIL
SYS_SLEEP
U900_SS
LED_PP2V5_RUN
R901_P2
U900_VC_D
R904_P2
U900_COMP
U900_GATE_H
MIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MILVOLTAGE=2.5V
46 22 11 10 8
6
6
Prelim
inary
-
FB
LD
HD
GND
COMP
SS
VCC VC
G
D
S G
D
S
G
D
S
G
D
S
G
D
S
LM339AV+
GND
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PLACE LED1000 NEAR VREG
PP1V2_ALL VOLTAGE REGULATOR
PP1V2_RUN FET SWITCHPEAK CURRENT ??A
RDSON=?? OHM@ VGS=?? V
PEAK CURRENT ??A
RDSON=0.06 OHM@ VGS=2.5 V
PP1V2_PWRON FET SWITCH
U1000_FEEDBACK
SET OUTPUT=1.2V IRU3037ACS VREF=0.8VDC
-
DG
S
LM339AV+
GND
LM339AV+
GND
TAB
VOUTVPWRVCTRL VOUT
ADJ
SENSE
D
G
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
FET ON IN RUN
5V & 3.3V VREGS
FET ON IN RUN
PP5V_PWRON
Vpwr >= Vout+0.35V
Vctrl >= Vout+1.25V
R2
R1
Iadj=50uA typ
3.30V - 3.45V
Vref=1.250V typ
Vout=Vref(1+R2/R1)+Iadj(R2)
PROCESS SWING
SHUTDOWN -> FLOAT SLEEP -> FLOAT RUN -> LOW
FET ON IN SLEEP
FET ON IN SLEEP
SHUTDOWN -> FLOAT SLEEP -> LOW RUN -> FLOAT
20%10VELEC
100UF
SM2
1 C1100
SI4467DYSM-1
CRITICAL
3
2
1
4
8
7
6
5
Q1100
402MF-LF1/16W5%
100K21
R1100
SOI
CRITICAL3
13
11
10
12
U1100
SOI
3
2
5
4
12
U1100
603MF-LF1/10W
1%47.0K
2
1R1102
CS5253SM
CRITICAL
5
6
3
4
1
2
VR1100
1/16W
100K
MF-LF
5%
402
21
R1103100K
5%
MF-LF1/16W402
21
R1104
603MF-LF1/10W1%124
2
1R1105
603MF-LF1/10W1%210
2
1R1106
603CERM16VN20P80%0.1UF
2
1 C1101
SM-1SI4467DY
3
2
1
4
8
7
6
5
Q1102
20%
ELEC10V
47UF
SM2
1 C1102
MF-LF1/16W1%1K
4022
1R1107
402
1K1%1/16WMF-LF
2
1R1101
SI3443DVTSOP
CRITICAL
4
3 6
5
2
1
Q1103
CRITICAL
TSOPSI3443DV
4
3 6
5
2
1
Q1101
051-6772 04
11 102
MIN_NECK_WIDTH=10MILMIN_LINE_WIDTH=25MILVOLTAGE=5VPP5V_PWRON
RAIL_SLEEP_FETMIN_LINE_WIDTH=20MILMIN_NECK_WIDTH=10MIL
PP5V_ALL
PP3V3_PWRONVOLTAGE=3.3VMIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MIL
PP3V3_ALLVOLTAGE=3.3VMIN_LINE_WIDTH=25MILMIN_NECK_WIDTH=10MIL
PP5V_ALL
RAIL_RUN_FETMIN_LINE_WIDTH=20MILMIN_NECK_WIDTH=10MIL
SYS_SLEEP
SYS_POWERUP_L
PP5V_RUN
MIN_NECK_WIDTH=10MIL
3_3V_ALL_ADJMIN_LINE_WIDTH=20MIL
PP3V3_RUN
PP3V3_ALL
RAIL_CTL_POS
RAIL_CTL_NEG
50
46
34
22
33
22
58
10
13
18
18
11
27
59
11
9
10
10
10
59
18
7
18
11
7
8
7
7
7
11
6
6
6
7
6
6
6
6
6
7
3
Prelim
inary
-
GD
S
VESTA MISC
1 OF 3
PVDDDVDD AVDDL AVDD
GNDAGNDOVDD
REGSUP1REGSEN1REGCTL1
REGSUP2REGSEN2REGCTL2
2.5V_EN
NC
DNCDNCDNC
NC
TDOTCKTMSTRST*
TDI
RESET*
GND
VOUTVIN
NOISECONT
ALIAS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Ethernet LowPwrETHERNET PORTION IN LOW POWER MODEWHEN NOT IN RUN MODE.
Vout = 2.5V @ 150 mA
2.5V LDO
Page NotesPower aliases required by this page:
NC
BOM options provided by this page:
Controls operating mode of Vesta 1.2V
regulator will be in continuous mode.
N9/N10
Signal aliases required by this page:
- VESTA1V2_BURST / VESTA1V2_PULSE
regulator. If both options are off the
NC
N5/N6
Schmitt trigger
L6/M6
(NONE)
L9/M9
Vesta Core / MiscReset RC values per
To keep Vesta from being held
Broadcom recommendation
in reset when system is off
R1252 to enable wirespeed feature
NOTE: Reset GPIO is active HIGH
20%10VCERM402
0.1uF2
1 C12100.1uF
402CERM10V20%
2
1 C1211
402CERM10V20%0.1uF
2
1 C121220%10VCERM402
0.1uF2
1 C1213
0.1uF
CERM402
10V20%
2
1 C12030.1uF
402CERM10V20%
2
1 C12020.1uF
402CERM
20%10V2
1 C120120%10VCERM402
0.1uF2
1 C120020%10V
CERM402
0.1uF2
1C122210V20%
CERM402
0.1uF2
1C122520%10V
CERM402
0.1uF2
1C12210.1uF
20%10V
CERM402
2
1C1224
0.1uF
402CERM10V20%
2
1C123120%10V
CERM402
0.1uF2
1C1230
20%10V
CERM402
0.1uF2
1C12200.1uF
20%10V
CERM402
2
1C1223
0.1uF
402CERM10V20%
2
1C124320%10V
CERM402
0.1uF2
1C124210V
0.1uF
402CERM
20%2
1C12410.1uF
402CERM10V20%
2
1C1240
603
20%1uF10VCERM2
1 C1250SOT23-LF2N7002
2
1
3
Q1250
OMIT
BCM5462FBGA-200
D8E8
E10D7
E7
H4
E2
E1
F2
F1
G4
G5
N4
A15
K1F15A7
A1
M13C3
K2J2
F14
C14
B7B2A2
J1
C15
B15
B1
E9C9B9
N10
N9N6N5M9M6L9L6
R12
R3
P11
P10
P5P4
N8N7M8M7
L8L7
J12
J11
P9P8P7P6
H12
H11
M3U8600
402MF-LF
5%82K1/16W
2
1R1251
10%
X5R
10UF6.3V
8052
1 C1208
FERR-EMI-600-OHM
SM
21
L1200
16VCERM402
0.01uF20%
2
1C1281
402
6.3V10%1uF
CERM 2
1C12806.3VX5R805
10UF10%
2
1 C1282
MM1572FNSOT-25A
CRITICAL
51
4
2
3
U1280
402
4.7K5%
1/16WMF-LF
2
1R1252
100K1/16W402MF-LF
5%
2
1R1262
5%
MF-LF1/16W2.0K
4022
1R1260
402
6.3V10%1uF
CERM2
1 C1260
2N3904LFSOT23
2
3
1 Q1260
1/16WMF-LF
5%1K
4022
1R1261
CERM10V20%0.1UF
402
NOSTUFF
2
1 C1261
1021204051-6772
=JTAG_VESTA_TRST_L
PP3V3_VESTA
TP_VESTA_DNC_B9
ENETFW_RESET
VESTA_RESET_LPP3V3_VESTA
PP3V3_VESTA
PP2V5_VESTA
TP_VESTA_REGSEN2TP_VESTA_REGSUP2
TP_VESTA_REGSEN1TP_VESTA_REGSUP1
TP_VESTA_REGCTL1
TP_VESTA_2_5V_EN
TP_VESTA_DNC_E9
PP1V2_VESTA_AVDDL
MIN_LINE_WIDTH=0.5 mmVOLTAGE=1.2VMIN_NECK_WIDTH=0.25 mm
=JTAG_VESTA_TMS=JTAG_VESTA_TCK=JTAG_VESTA_TDO
TP_VESTA_REGCTL2
=JTAG_VESTA_TDI
PP1V2_VESTA
TP_VESTA_DNC_C9
MAKE_BASE=TRUE
VOLTAGE=2.5VPP2V5_VESTA
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
PP3V3_VESTA =PP2V5_ENETFW
MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
VESTA2V5_NOISE
PP3V3_VESTA
=PP3V3_PWRON_VESTA
VESTA_ENET_LOWPWR
VESTA_ENET_HIGHPWR
12
12
12
12 89
12
8
7
25
7
7
12
8
8
8
8
7
12
7 86
7
7
86
Prelim
inary
-
P9[7]P9[6]P9[5]
P8[7]P8[6]P8[5]
P3[7]P3[6]P3[5]P3[4]
P2[6]P2[7]
P2[4]P2[5]
P1[4]P1[3]P1[2]P1[1]P1[0]
P0[4]
P0[0]
P0[2]P0[3]
P0[1]
P0[7]P0[6]P0[5]
P3[3]P3[2]P3[1]P3[0]
P2[3]P2[2]P2[1]P2[0]
P1[5]P1[6]P1[7]
PCNVSSRESET*XOUT
VREFXIN
P7[7]P7[6]P7[5]P7[4]P7[3]P7[2]P7[1]P7[0]
P6[7]P6[6]P6[5]P6[4]P6[3]P6[2]P6[1]P6[0]
P10[0]P10[1]
P9[3]P9[2]P9[1]P9[0]
P8[4]P8[3]P8[2]P8[1]P8[0]
P10[6]P10[7]
P10[2]P10[3]P10[4]P10[5]
VCC
AVSSVSS
AVCC
SQW/OUT
VBAT
SDA
SCL
X1X2
GND
VCC
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
MASTER: SEEDY
System Management Unit
3.62.7
100K/10uF RC filter at SMU pins.
SMU_VREF should be same signal or
circuit, but be aware that this will
7.6
1.51.61.7
0.60.5
Port0.4
Portable
Alternate Functions
2.6
Port2.5
ConsumerPort
6.16.2
6.0
7.27.4
Tower & Server
Y
Y
IOC2IOC3
SSY
Y
YY
Y
Y
YY
IOC5
INT3*
AN22
YYY
Y
Y
Y
YY
Y
YY
Y
YY
Y
YY
Y
N
NN
(see aliases below)
SS
YY
Y
Y
Y
SYY
S
Y
Y
Y
Y
YY
YY
S
YYY
S SAN26
Y
YYY
Y
Y
YY
Y
Y
Y
YY
SINT0*
S
Y
Y
Y
Y
Y
Y
YY
Y
YSY
Y
Y
Y
YY
NN
SS
Y
Y
Y
Y
Y
YY
YY
Y
Y
Y
YYY
Y
Y
Y
Y
Y
YY
Entry Desktop
Entry Desktop
Desktop
S
Y
Y
YY
Y
Y
YY
S
YY
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
NY
Y
Y
Y
Y
Y
YY
Y
Y
Y
Y
YY
Portable
Y
YY
Y Y
Y
YY
YY
S
Y
Y
Y
SY
Y
Y
S
Y
Y
Y
Y
Y
SY
SY
Y
S
Y
Y
Y
Y
Y
SY
Y
Y
Y
Y
Y
S
Y
Y
Y
Y
Y Y
Y
Y
N
Y
Y
SS
Y
Y
Y
SSY
Y
N
S SNN
N
Consumer
N
N
N
Server
S
YY
Y
Y
Y
Y Y
Y
SY
Y
YY
S
YY
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
YY
Y
YY
Y
S
NSSYY
Y
Y
YY
Y
YY
S
YY
Y
YY
Y
Y YS
N Y
Y
Y YYYY
S SSS
SS
Consumer
Y
SS
Y
S
YY
Y
YY
N
N
YY
Y
YY
Y
YY
Y
Y
S
YY
NN
YY
Y
YY
Y
Portable
Desktop
Y
Server
SMU Pull-ups / pull-down
NET_SPACING_TYPE
System Management Unit
DIFFERENTIAL_PAIR
TA1out
SS
NOTE: Some primary and alternate functions
AC adapter ID. affect other analog inputs such as
those capacitors are provided on
Caps should connect to GND_SMU_AVSS.
(CPU_SENSE_I/CPU_SENSE_V) requires
TA3out
TA4in
IOC6
Power aliases required by this page:
review the latest SMU specification to ensure missing pull-ups are
TB2in
this page.
SCL
Y
IOC4
YY
KI2*
KI0*AN3AN2AN1
Sout3
Y
Y
Y
Y
Y
Y
Y
Y
SCLmm
AN25
INT1*
NMI*
TB1in
AN24
TA1in
TA4out
SDA
AN05
AN07RXD1
CLK0RXD0
RTS1*
CLK1
TXD1
RTS0*/
reuire pull-ups that are not. provided on this page. Please.
NC
Real Time Clock
NOTE: CPU current/voltage monitoring
BOM options provided by this page:
ELECTRICAL_CONSTRAINT_SET
- _PP3V3_ALL_SMU- _PP3V3_ALL_RTC- _PP3V3_PWRON_SMU
(NONE)
(NONE)
reference used by monitoring
provided on another page.
Sin3TB0in
(BUSY)
AN0
TA3in
AN21
AN23
AN27
Y
CE*
INT2*
AN04
TA2in
IOC7
CTS0*
AN06
AN20
Y INT4*INT5*
SDAmm
Y
YSS
Keep crystal subcircuit close to SMU.
S
KI3*
TXD0
AN01
AN03AN02
AN00
TA2out
CLK3
N = Alternate functionY = Primary function
S = Spare
Page Notes
- _PPVREF_SMU (SMU AVCC or 2.5V reference)Signal aliases required by this page:
signal (GND_SMU_AVSS). None of a 100pF capacitor to the SMU AVSSNOTE: All analog inputs to SMU should have
NOTE: Pinout matches SMU pinout v1.51.
KI1*
Y
CRITICAL
10.000M
11.4X4.7X4.2-SM
21
Y1300
OMIT
M30280F8QFP-80
1012
11
77
13
9
798012345
78141516171819
2021222324252627
2829303140414243
3233343536373839
4445464748495051
52535455565758
6869707172737476
59
6061626364656667
6
75
78
U1300
DS1338U-33MSOP
21
8
37
5
6
4
U1301
PP3V3_PWRON
PP3V3_RUN
PP2V5_PWRON
0
NO_SMU_I2C_D
402MF-LF1/16W5%
21
R1399
MMBD914XXGSOT23
3
1
D1310
402
6.3V10%CERM
1uF2
1 C1325
402
1/16WMF-LF
5%10K
2
1R1325
5%1/16WMF-LF402
150K
2
1R1322
CERM6.3V
402
0.22uF20%
2
1C1310
50V5%
402CERM
18pF2
1C130450V5%
CERM
18pF
4022
1C1305
05%
MF-LF1/16W
4022
1R1317
NO STUFF
402
1/16WMF-LF
5%
10M21
R131610K5%
MF-LF1/16W4022
1R1327
402MF-LF1/16W5%
2.0K21
R1312
5%1/16WMF-LF402
2.0K
NO STUFF
21
R1311
402MF-LF1/16W5%
100K21
R1313
100K
5%1/16WMF-LF402
21
R1310
402MF-LF1/16W5%
10K21
R1302
10K
402MF-LF1/16W5%
21
R1300
5%1/16WMF-LF
10K
402
12
R1304
402
0.1uFCERM
20%10V2
1 C1309
402CERM
0.1uF20%10V 2
1C1308
CERM
0.1uF20%10V
4022
1C1302
402CERM
0.1uF20%10V 2
1C1301
805CERM
20%10uF6.3V 2
1C13006.3V10%1uF
CERM402
2
1 C1303
4.7
5%1/16WMF-LF402
21
R1315
SM21
XW1300
CRITICAL
SM-132.768K
4
1Y1301
402MF-LF1/16W5%
10K21
R1303
04
13 102051-6772
SYS_SLOT_PWR
TP_SMU_SPARE_P10_0
SYS_RESET_BUTTON_L
SB_SUSPENDACK_LNB_SUSPENDACK_LSMU_WARM_RESET_L
SMU_PWRSEQ_P9_6
SB_STOPXTALS_L
I2C_SMU_CPU_SDA_OUT_L
FAN_PWM8
I2C_SMU_B_SCL
SMU_PWRSEQ_P9_5
SYS_COLD_RESET_L
SYS_POWER_BUTTON_LSMU_SUSPENDREQ_L
SB_TO_SMU_INT_L
CLOCK_RESET_L
SMU_SLEEP
SYS_SLEWING_L
I2C_SMU_CPU_SCL_OUT_L
CPU_HRESET
FAN_RPM1
SYS_LED
FAN_RPM2
SYS_PME_LSMU_QREQ
I2C_SMU_CPU_SCL_INFAN_RPM0
I2C_SMU_B_SDA
SMU_BOOT_TXDSMU_BOOT_RXD
MAKE_BASE=TRUESYS_POWERUP_L
CPU_VID
RTC_CLK32K_X2
RTC_CLK32K_X1
=PP3V3_ALL_RTC=PP3V3_ALL_SMU
GND_SMU_AVSS
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=15 milVOLTAGE=0V
PP3V3_ALL_SMU_AVCC
MIN_NECK_WIDTH=10 milMIN_LINE_WIDTH=15 milVOLTAGE=3.3V
=PP3V3_ALL_SMU
GND_SMU_AVSS
SYS_POWER_BUTTON_L
SMU_RESET_L
=PP3V3_ALL_SMU
SMU_BOOT_CNVSS
SYS_POWERFAIL_L
FAN_TACH1
15 MIL SPACING SMU_CLK10M_XOUT
RTC_CLK32K_X1RTC_CLK32K_XTAL 15 MIL SPACING
I2C_RTC_SCL
I2C_RTC_SDA
15 MIL SPACING RTC_CLK32K_X2
SMU_CLK10M_XINSMU_CLK10M_XTAL 15 MIL SPACING
I2C_SMU_A_SCL_OUT_LI2C_SMU_A_SCL_IN
I2C_SMU_D_SCL
SMU_PWRSEQ_P1_2
FAN_RPM4
CPU_BYPASS
SMU_PWRSEQ_P1_1SMU_PWRSEQ_P1_0
SYS_DRIVE_BAY_INT_L
CPU_SENSE_VCPU_SENSE_I
I2C_SMU_D_SDA
FAN_RPM5SMU_ONEWIRE
SMU_PWRSEQ_P1_4SMU_PWRSEQ_P1_3
I2C_SMU_E_SDAI2C_SMU_E_SCLFAN_TACH0
SYS_DOOR_AJAR_L
FAN_TACH2FAN_TACH3
FAN_TACH5
SMU_TO_SB_INT_L
CPU_TEMP
SMU_CLK10M_XOUT_R15 MIL SPACING
FAN_RPM3
FAN_TACH4
I2C_SMU_A_SDA_OUT_LI2C_SMU_A_SDA_IN
FAN_TACH6CPU_VID
FAN_TACH8CPU_VIDFAN_TACH7CPU_VID
FAN_PWM7I2C_SMU_CPU_SCL_INFAN_PWM6I2C_SMU_CPU_SDA_IN
SYS_LED_REDFAN_TACH3SYS_LED_GREENFAN_TACH4
ALS0_OUTFAN_RPM3ALS1_OUTFAN_RPM4ALS_GAIN_BOOSTFAN_RPM5SMU_ACINSYS_POWERFAIL_LSMU_BATT_DET_LSYS_DRIVE_BAY_INT_LSYS_LID_OPENSYS_DOOR_AJAR_LSYS_KBDLEDFAN_PWM8
FAN_TACH5 SYS_LED_BLUEDIAG_LEDSMU_CHARGE_BATT
SYS_PME_L
SYS_SLEWING_L
SMU_SUSPENDREQ_L
SYS_COLD_RESET_L
SMU_SLEEP
SYS_POWERUP_L
SYS_RESET_BUTTON_L
=PP3V3_ALL_SMU
CPU_VIDCPU_VIDCPU_VIDCPU_VID
SMU_BOOT_CESMU_BOOT_SCLKSMU_BOOT_BUSY
CPU_VID
I2C_SMU_CPU_SDA_IN
SMU_CLK10M_XOUT
SMU_CLK10M_XINSMU_CLK10M_XOUT_R
=PPVREF_SMU
SYS_OVERTEMP_LSMU_CHARGE_BATT
33
33
13
13
28
33
11
13
36
13
36
13
33
28
11
13
24
13
25
27
77
10
8
33
8
33
13
8
13
18
18
13
77
27
25
24
10
8
27
13
13
13
7
24
13
25
25
18
7
7
13
7
13
7
8
7
8
14
13
13
14
13
13
13
18
18 8
13
13
13
25
25
24
13
13
7
13
7
13
13
13
18
25
8
7
25
8
8
3
25
18
8
18
3
8
6
13
25
27
8
13
18
30
16
21
17
13
28
13
16
18
8
8
6
8
13
13
7
6
8
8 6
8
6
6
6
8
6
16
13
13
18
18
13
13
6
18
18
3
13
30
3
3
8
33
33
18
13
8
3
8
18
18
16
8
17
13
13
25
36
13
13
13
6
18
8
8
8
13
13
21 13
21 13
8 13
8 13
8 13
6
8
8
8
13 21
8 13
13
13
13
8
8
6
7
6
8
8
8
8
8
8
8
8
13
13
13
13
8
16
13
Prelim
inary
-
A30B30A29B29A28B28A27B27A26B26
B25B24B23B22B21
A25A24A23A22A21
C30D30C29D29C28D28C27D27C26D26C25D25
D22D23D24
D21
C24C23C22C21
E30F30E29F29E28F28E27F27E26F26E25F25
F24F23F22F21
E24E23E22E21
G30H30G29H29G28H28G27H27G26H26
H25 G25
G22G23G24
H21H22H23H24
G21H20H19H18H17H16H15H14H13H12H11H10H9H8H7H6H5H4H3H2H1
G20G19G18G17G16G15G14G13G12G11G10G9G8G7G6G5G4G3G2G1
F20F19F18F17F16F15F14F13F12F11F10F9F8F7F6F5F4F3F2F1
E10
E20E19E18E17E16E15E14E13E12E11
E9E8E7E6E5E4E3E2E1
D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1
C20C19C18C17C16C15C14C13C12C11C10C9C8C7C6C5C4C3C2C1 B1 A1
A2A3A4A5A6A7A8A9
A10A11A12A13A14A15A16A17A18A19A20
B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16B17B18B19B20
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NC
NC
CPU LOGIC ANALYZER
NC
402MF-LF1/16W5%
0
DEVELOPMENT
21
R1400
402MF-LF1/16W5%
0DEVELOPMENT
21
R1401
5% 402
0DEVELOPMENT
21R1402
0
4025%
DEVELOPMENT21
R1403
NOSTUFF
YFS-30-03-H-08-SBF-ST-BGA
H9
H8
H7
H6
H5
H4
H30
H3
H29
H28
H27
H26
H25
H24
H23
H22
H21
H20
H2
H19
H18
H17
H16
H15
H14
H13
H12
H11
H10
H1
G9
G8
G7
G6
G5
G4
G30
G3
G29
G28
G27
G26
G25
G24
G23
G22
G21
G20
G2
G19
G18
G17
G16
G15
G14
G13
G12
G11
G10
G1
F9
F8
F7
F6
F5
F4
F30
F3
F29
F28
F27
F26
F25
F24
F23
F22
F21
F20
F2
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F1
E9
E8
E7
E6
E5
E4
E30
E3
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E2
E19
E18
E17
E16
E15
E14
E13
E12
E11
E10
E1
D9
D8
D7
D6
D5
D4
D30
D3
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D2
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D1
C9
C8
C7
C6
C5
C4
C30
C3
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C2
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C1
B9
B8
B7
B6
B5
B4
B30
B3
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B1
A9
A8
A7
A6
A5
A4
A30
A3
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
J1400
10214
04051-6772
EI_CPU_TO_NB_SR_N
EI_CPU1_CLK_P_R
EI_CPU1_CLK_N
EI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_AD EI_CPU_TO_NB_AD
EI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_AD
EI_CPU_TO_NB_ADEI_CPU_TO_NB_AD
CPU1_HTBENCPU_HRESET_L
EI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_SR_PEI_CPU_TO_NB_SR_NEI_CPU_TO_NB_AD
EI_CPU_TO_NB_AD
EI_CPU_TO_NB_AD
CPU_INT_L
EI_CPU_TO_NB_AD
=PP1V2_EI_CPU
EI_CPU_TO_NB_ADEI_CPU_TO_NB_AD
EI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_AD
EI_CPU1_CLK_N
EI_NB_TO_CPU_AD
EI_CPU1_CLK_P
EI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_AD
EI_CPU_TO_NB_ADEI_CPU_TO_NB_CLK_NEI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_SR_P
EI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_CPU_TO_NB_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_AD
EI_CPU1_SYNCCHKSTOP_L
EI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_AD
EI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_AD
EI_NB_TO_CPU_ADEI_NB_TO_CPU_AD
EI_NB_TO_CPU_ADEI_NB_TO_CPU_AD
EI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_AD EI_NB_TO_CPU_SR_NRI_L EI_NB_TO_CPU_SR_PEI_QREQ_L I2C_SMU_A_SCL_OUT_L
EI_NB_TO_CPU_AD
EI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_AD
EI_NB_TO_CPU_AD SYNCENABLEEI_NB_TO_CPU_SR_N TP_PROC_TRIGGER_OUTEI_NB_TO_CPU_SR_P
EI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_AD EI_SEEI_QACK_L
EI_NB_TO_CPU_AD
=PP1V2_EI_NB
EI_NB_TO_CPU_AD
EI_NB_TO_CPU_ADEI_NB_TO_CPU_ADEI_NB_TO_CPU_CLK_NEI_NB_TO_CPU_CLK_PMCP_LI2C_SMU_A_SDA_OUT_L
=PP1V2_EI_NB
EI_CPU_TO_NB_AD
EI_CPU_TO_NB_AD
EI_NB_TO_CPU_AD
EI_CPU1_CLK_P
EI_CPU1_CLK_N_R
EI_CPU1_SYNCEI_CPU1_SYNC_R
CPU1_HTBENCPU1_HTBEN_R
35 31
30
30
30 30
28
28
29
27
29
29 29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
30
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
27
29
27
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
27
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29 29
30 29
29 18
29
29
29
29
29
29 29 30
29
29
29
29
29 29 29
29
29
18
29
29
29
29
29
18
18
29
29
29
27
27
28
14
28
28
28 28
28
28
28
28
28
28
28
28
28
28
28
28
28
14
29
28
28
28
28
28
28
28
28
28
28
25
28
18
28
28
28
28
28
28
28
28
28
28
28
28
28
28
14
28
14
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
14
8
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28 28
29 28
28 13
28
28
28
28
28
28
28 29
28 29
28
28
28
28
28 28
28
28
14
28
28
28
28
28
29
13
14
28
28
28
14
14
14
6
27
6
6
6
6 6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6 6
6 6
6 6
6
6
6
6
6
6
6 6
6 6
6
6
6
6
6 6
6
6
7
6
6
6
6
6
6
6
7
6
6
6
6
27
6 27
6 27
Prelim
inary
-
SDA
SCLGND
OS
VS+
A2A1A0
G
D
S
G
D
S
G
D
S
G
D
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE