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10Qsys System Design Components

2014.06.30

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You can use Qsys IP components to create Qsys systems. Qsys interfaces include components appropriatefor streaming high-speed data, reading and writing registers and memory, controlling off-chip devices, andtransporting data between components.

Qsys supports Avalon®, AMBA® AXI3™ (version 1.0), AMBA AXI4™ (version 2.0), AMBA AXI4-Lite™

(version 2.0), AMBA AXI4-Stream (version 1.0), and AMBA APB™ 3 (version 1.0) interface specifications.

Related Information

• Avalon Interface Specifications

• AMBA Protocol Specifications

• Creating a System with Qsys

• Qsys Interconnect

• Embedded Peripherals IP User Guide

BridgesBridges affect the way Qsys transports data between components. You can insert bridges between mastersand slave interfaces to control the topology of a Qsys system, which affects the interconnect that Qsysgenerates. You can also use bridges to separate components into different clock domains to isolate clockdomain crossing logic.

A bridge has one slave interface and one master interface. In Qsys, one or more master interfaces from othercomponents connect to the bridge slave. The bridgemaster connects to one ormore slave interfaces on othercomponents.

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http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

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http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf

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Figure 10-1: Using a Bridge in a Qsys System

In this example, three masters have logical connections to three slaves, although physically each masterconnects only to the bridge. Transfers initiated to the slave propagate to the master in the same order inwhich they are initiated on the slave.

Bridge

M

S

M1

M

M2

M M

M3

S2

S

S1

S

S

M Master

Slave

S3

S

Arbiter & Write Data ControlSignal Multiplexing

ChipSelect & Read DataMultiplexing

Clock BridgeThe Clock Bridge allows you to connect a clock source to multiple clock input interfaces. You can use theclock bridge to connect a clock source that is outside the Qsys system. You create the connection throughan exported interface, and then connect to multiple clock input interfaces.

Clock outputs have the ability to fan-out without the use of a bridge. You require a bridge only when youwant a clock from an exported source to connect internally to more than one source.

Figure 10-2: Clock Bridge

PIO

S

DMA

M MS

Qsys System

Clock Bridge

External Clock from PCB

CIn

Export

COut

CIn CIn

Qsys System Design ComponentsAltera Corporation

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Avalon-MM Clock Crossing BridgeThe Avalon-MM Clock Crossing Bridge transfers Avalon-MM commands and responses between differentclock domains. You can also use the Avalon-MM Clock Crossing Bridge between AXI masters and slavesof different clock domains.

The Avalon-MM Clock Crossing Bridge uses asynchronous FIFOs to implement clock crossing logic. Thebridge parameters control the depth of the command and response FIFOs in both the master and slave clockdomains. If the number of active reads exceeds the depth of the response FIFO, the Clock Crossing Bridgestops sending reads.

To maintain throughput for high-performance applications, increase the response FIFO depth from thedefault minimum depth, which is twice the maximum burst size.

Related InformationCreating a System with Qsys

Avalon-MM Clock Crossing Bridge Example

In this example, the Avalon-MM Clock Crossing bridges separate slave components into two groups. Low-performance slave components are placed behind a single bridge and are clocked at a low speed. Highperformance components are placed behind a second bridge and are clocked at a higher speed.

By inserting clock-crossing bridges, you optimize the Qsys interconnect and allow the Quartus® II Fitter tooptimize paths that require minimal propagation delay.

Altera CorporationQsys System Design Components

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10-3Avalon-MM Clock Crossing BridgeQII510252014.06.30



Figure 10-3: Avalon-MM Clock Crossing Bridge

S

M Avalon-MM Master Port

Avalon-MM Slave Port

Avalon-MMClock-Crossing

Bridge

S

M


Bridge

S

M

S

DDRSDRAM

S

FlashMemory

S

ExternalSRAM

JTAG DebugModule

S

UART

S S

System ID

S

Seven SegmentPIO

S

LCDDisplay

CPU

M


Bridge

S

M

AvalonTristateBridge

S

M

AvalonTristateBridge

S

M

Avalon-MM Clock Crossing Bridge Parameters

Table 10-1: Avalon-MM Clock Crossing Bridge Parameters

DescriptionValuesParameters

Determines the data width of theinterfaces on the bridge, and affects thesize of both FIFOs. For the highestbandwidth, set Data width to be aswide as thewidestmaster that connectsto the bridge.

8, 16, 32, 64,128, 256,512,1024 (bits)

Data width


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Number of bits per symbol. Forexample, byte-oriented interfaces have8-bit symbols.

1, 2, 4, 8, 16, 32,64 (bits)

Symbol width

The address bits needed to address thedownstream slaves.

1-32 (bits)Address width

The minimum bridge address widththat is required to address thedownstream slaves.

-Use automatically-determined address width

Determines the maximum length ofbursts that the bridge supports.

1, 2, 4, 8, 16, 32,64, 128, 256,512, 1024 (bits)

Maximum burst size

Command (master-to-slave) FIFOdepth.

2, 4, 8, 16, 32,64, 128, 256,512, 1024 2048,4096, 8192,16384 (bits)

Command FIFO depth

Response (slave-to-master) FIFOdepth.

2, 4, 8,16, 32,64, 128, 256,512, 1024 2048,4096,8192,16384(bits)

Respond FIFO depth

The number of pipeline stages in theclock crossing logic in the issuingmaster to target slave direction.Increasing this value leads to a largermeantime between failures (MTBF).You can determine the MTBF for adesign by running a TimeQuest timinganalysis.

2, 3, 4, 5 (bits)Master clock domain synchronizer depth

The number of pipeline stages in theclock crossing logic in the target slaveto master direction. Increasing thisvalue leads to a larger meantimebetween failures (MTBF). You candetermine the MTBF for a design byrunning a TimeQuest timing analysis.

2, 3, 4, 5 (bits)Slave clock domain synchronizer depth

Avalon-MM Pipeline BridgeThe Avalon-MM Pipeline Bridge inserts a register stage in the Avalon-MM command and response paths.It accepts commands on its Avalon-MM slave port and propagates the commands to its Avalon-MM master


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10-5Avalon-MM Pipeline BridgeQII510252014.06.30


port. The pipeline bridge provides separate parameters to turn on pipelining in the command and responsenetworks.

You can use the Avalon-MM bridge to export a single Avalon-MM slave interface to use to control multipleAvalon-MM slave devices. The pipelining feature is optional. You can optionally turn off the pipeliningfeature of this bridge.

Figure 10-4: Avalon-MM Pipeline Bridge in a XAUI PHY Transceiver IP Core

In this example, the bridge transfers commands received on its slave interface to its master port.

Interconnect

Exported to EmbeddedProcessor on PCB

Interleave

PCSS

Alt_PMA

SS

Low LatencyController

S

TransceiverReconfiguration

Controller

XcvrXAUI PHY

M

Avalon-MMPipeline

Bridge (Qsys)

S

PMAChCntl

Because the slave interface is exported to the pins of the device, having a single slave port, rather than separateports for each slave device, reduces the pin count of the FPGA.

Avalon-MM Unaligned Burst Expansion BridgeThe Avalon-MM Unaligned Burst Expansion Bridge aligns read burst transactions from masters connectedto its slave interface, to the address space of slaves connected to its master interface. This alignment ensuresthat all read burst transactions are delivered to the slave as a single transaction.

Figure 10-5: Avalon-MM Unaligned Burst Expansion Bridge

Slave Master

32 bit Avalon-MMMaster

Slave

Master

SlaveUnaligned BurstExpansion Bridge

64 bit Avalon-MMSlave

64 bit Avalon-MMSlave


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QII51025Avalon-MM Unaligned Burst Expansion Bridge10-6 2014.06.30


You can use the Avalon Unaligned Burst Expansion Bridge to align read burst transactions from mastersthat have narrower data widths than the target slaves. Using the bridge for this purpose improves bandwidthutilization for the master-slave pair, and ensures that un-aligned bursts are processed as single transactionsrather than multiple transactions.

Do not use the Avalon-MM Unaligned Burst Expansion Bridge if any connected slave has read sideeffects from reading addresses that are exposed to any connected master's address map. This bridgecan cause read side effects due to alignment modification to read burst transaction addresses.

Note:

ForQsys 14.0, theAvalon-MMUnalignedBurst ExpansionBridge does not supportVHDL simulation.Note:

Related InformationQsys Interconnect

Using the Avalon-MM Unaligned Burst Expansion BridgeWhen a master sends a read burst transaction to a slave, the Avalon-MM Unaligned Burst Expansion Bridgeinitially determines whether the start address of the read burst transaction is aligned to the slave's memoryaddress space. If the base address is aligned, the bridge does not change the base address. If the base addressis not aligned, the bridge aligns the base address to the nearest aligned address that is less than the requestedbase address.

The Avalon-MM Unaligned Burst Expansion Bridge then determines whether the final word requested bythe master is the last word at the slave read burst address. If a single slave address contains multiple words,all of those words must be requested in order for a single read burst transaction to occur.

• If the final word requested by the master is the last word at the slave read burst address, the bridge doesnot modify the burst length of the read burst command to the slave.

• If the final word requested by the master is not the last word at the slave read burst address, the bridgeincreases the burst length of the read burst command to the slave. The final word requested by themodified read burst command is then the last word at the slave read burst address.

The bridge stores information about each aligned read burst command that it sends to slaves connected toa master interface. When a read response is received on the master interface, the bridge determines if thebase address or burst length of the issued read burst command was altered.

If the bridge alters either the base address or the burst length of the issued read burst command, it receivesresponse words that the master did not request. The bridge suppresses words that it receives from the alignedburst response that are not part of the original read burst command from the master.


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Avalon-MM Unaligned Burst Expansion Bridge Parameters

Figure 10-6: Avalon-MM Unaligned Burst Expansion Bridge Parameter Editor

Table 10-2: Avalon-MM Unaligned Burst Expansion Bridge Parameters

DescriptionParameter

Data width of the master connected to the bridge.Data width

The address width of the master connected to the bridge.Address width (in WORDS)

The burstcount signal width of the master connected to thebridge.

Burstcount width

The maximum pending read transactions interface propertyof the bridge.

Maximum pending read transactions

The data width of the connected slave. Supported values are:16, 32, 64, 128, 256, 512, 1024, 2048, and 4096 bits.

If you connect multiple slaves, all slaves must havethe same data width.

Note:

Width of slave to optimize for


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When turned on, the command path is pipelined,minimizingthe bridge's critical path at the expense of increased logic usageand latency.

Pipeline command signals

Avalon-MM Unaligned Burst Expansion Bridge Example

Figure 10-7: Unaligned Burst Expansion Bridge

The example below shows an unaligned read burst command from a master that the Avalon-MM UnalignedBurst Expansion Bridge converts to an aligned request for a connected slave, and the suppression of wordsdue to the aligned read burst command. In this example, a 32-bit master requests an 8-beat burst of 32-bitwords from a 64-bit slave with a start address that is not 64-bit aligned.

XXXXXXXX

123456789ABC

0XXXX

2, 34, 56, 78, 9A, BC, DE, F

0, 1 XXXX

Transaction 1Transaction 2Transaction 3Transaction 4Transaction 5

Transaction 1

XXXXXXXX

123456789ABC

0XXXX

2, 34, 56, 78, 9A, BC, DE, F

0, 1 XXXX

Transaction 1

With Avalon-MM Unaligned Burst Expansion Bridge

BridgeAlignment

X*

X*

Note: the bridge suppressesX* response words

Transaction 1

Without Avalon-MM Unaligned Burst Expansion Bridge

Because the target slave has a 64-bit data width, address 1 is unaligned in the slave's address space. As aresult, several smaller burst transactions are needed to request the data associated with the master's readburst command.

With anAvalon-MMUnalignedBurst ExpansionBridge in place, the bridge issues a new read burst commandto the target slave beginning at address 0 with burst length 10, which requests data up to the word stored ataddress 9.

When the bridge receives the word corresponding to address 0, it suppresses it from the master, and thendelivers the words corresponding to addresses 1 through 8 to the master. When the bridge receives the wordcorresponding to address 9, it suppresses that word from the master.

Bridges Between Avalon and AXI InterfacesWhen designing a Qsys system, you can make connections between AXI and Avalon interfaces without theuse of explicitly-instantiated bridges; the interconnect provides all necessary bridging logic. However, thisdoes not prevent the use of explicit bridges to separate the AXI and Avalon domains.


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Figure 10-8: Avalon-MM Pipeline Bridge Between Avalon-MM and AXI Domains

Using an explicit Avalon-MMbridge to separate theAXI andAvalon domains reduces the amount of bridginglogic in the interconnect at the expense of concurrency.

Network

Avalon-MM

Avalon-MMAXI

AXI

AXIAvalon-MM

Shared Avalon & AXI Domain

Network

Avalon-MMPipeline Bridge

Avalon-MM

AXI

AXIAXI

Network

Avalon-MM

Avalon-MMAvalon-MMAXI

Shared Avalon & AXI Domains

AXI BridgeWith an AXI bridge, you can influence the placement of resource-intensive components, such as the widthand burst adapters. Depending on its use, an AXI bridge may reduce throughput and concurrency, in returnfor higher fMax and less logic.

You can use an AXI bridge to group different parts of your Qsys system. Then, other parts of the systemconnect to the bridge interface instead of to multiple separate master or slave interfaces. You can also usean AXI bridge to export AXI interfaces from Qsys systems.

The example below shows a system with a single AXI master and three AXI slaves. It also has variousinterconnect components, such as routers, demuxes, and muxes. Two of the slaves have a narrower datawidth than the master; 16-bit slaves versus a 32-bit master. In this system, Qsys interconnect creates fourwidth adapters and four burst adapters to access the two slaves. In this case, you could improve resourceusage by adding an AXI bridge. This would result in Qsys having to add only two width adapters and twoburst adapters, one pair for the read channels, and another pair for the write channel.


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Figure 10-9: AXI Example Without a Bridge: Adding a Bridge Can Reduce the Number of Adapters

AXI Master AXI MasterAgent

Router_0 CommandDemux_0


CommandMux_2

CommandMux_0

CommandMux_4

CommandMux_5

CommandMux_1

CommandMux_3

WidthAdapter_1

WidthAdapter_0

WidthAdapter_2

BurstAdapter_1

BurstAdapter_0

BurstAdapter_2

AXI SlaveAgent_0

AXISlave_0

WidthAdapter_3

BurstAdapter_3

AXI SlaveAgent_2

AXISlave_2

AXI SlaveAgent_1

AXISlave_1

Four width adapters (0 - 3) and four burst adapters(0 - 3) are inserted between the master and slavesfor transaction adaptations for the example system.

The example below shows the same system with an AXI bridge component, and the decrease in the numberof width and burst adapters. Qsys creates only two width adapters, and two burst adapters, as compared tothe four width adapters and four burst adapters in the previous example. The system includes morecomponents, but the overall system performance improves because there are fewer resource-intensive widthand burst adapters.


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Figure 10-10: Width and Burst Adapters Added to a System With a Bridge

AXI Master AXI MasterAgent



CommandMux_0

CommandMux_2

CommandMux_1

CommandMux_3

WidthAdapter_0

AXI SlaveAgent_1

BurstAdapter_0

AXISlave_2

WidthAdapter_3

BurstAdapter_3

AXI SlaveAgent_0

AXIBridge

By inserting an AXI bridge, theinterconnect Is divided into twodomains (interconnect_0 andinterconnect_1). Notice thereduction in the number of widthadapters from 4 to 2 after thebridge insertion. The sameprocess applies for burst adapters.

Interconnect_0

AXIBridge

AXI MasterAgent

Router_0 Limiter_0

Router_1 Limiter_1

CommandMux_0

CommandMux_2

CommandMux_1

CommandMux_3

AXI SlaveAgent_0

AXISlave_0

Width and burst adaptersare not required inInterconnect_1 because theadaptations are performedin Interconnect_0.

Interconnect_1

CommandDemux_0

CommandDemux_1

AXI SlaveAgent_1

AXISlave_1

AXI Bridge Signal Types

Based on parameter selections that you make for the AXI Bridge component, Qsys instantiates either theAXI3 or AXI4 master and slave interfaces into the component.

In AXI3, aw/aruser accommodates sideband signal usage by hard processor systems (HPS).Note:


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Table 10-3: Sets of Signals for the AXI Bridge Based on the Protocol

AXI4AXI3Signal Name

yesyesawid / arid

yesyesawaddr /araddr

yes (8-bit)yes (4-bit)awlen / arlen

yesyesawsize/ arsize

yesyesawburst /arburst

yes (1-bit optional)yesawlock /arlock

yes (optional)yes (2-bit)awcache / arcache

yesyesawprot / arprot

yesyesawuser /aruser

yesyesawvalid / arvalid

yesyesawready /arready

yesnoawqos /arqos

yesnoawregion /arregion

no (optional)yeswid

yesyeswdata / rdata

yesyeswstrb

yesyeswlast /rvalid

yesyeswvalid /rlast

yesyeswready /rready

yesnowuser / ruser

yesyesbid / rid

yes (optional)yesbresp / rresp

yesyesbvalid

yesyesbready

AXI Bridge Parameters

In the parameter editor, you can customize the parameters for the AXI bridge according to the requirementsof your design.


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10-13AXI Bridge ParametersQII510252014.06.30


Figure 10-11: AXI Bridge Parameter Editor

Table 10-4: AXI Bridge Parameters

DescriptionRangeTypeParameter

Specifies the AXI version and signals thatQsys generates for the slave and masterinterfaces of the bridge.

AXI3/AXI4

stringAXI Version

Controls the width of the data for themaster and slave interfaces.

8:1024intData Width

Controls the width of the address for themaster and slave interfaces.

1-64 bitsintAddress Width


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DescriptionRangeTypeParameter

Controls the multithreading feature andout-of-order responses.

If a master issues different thread IDs todifferent slaves, in order for a slave to viewthe different thread IDs, you must set theRead Data Reordering Depth to 1.

1-16intRead Data Reordering Depth

Controls the width of the write addresschannel sideband signals of the masterand slave interfaces.

1-64 bitsintAWUSER Width

Controls the width of the read addresschannel sideband signals of the masterand slave interfaces.

1-64 bitsintARUSER Width

Controls the width of the write datachannel sideband signals of the masterand slave interfaces.

1-64 bitsintWUSER Width

Controls the width of the read datachannel sideband signals of the masterand slave interfaces.

1-16 bitsintRUSER Width

Controls the width of the write responsechannel sideband signals of the masterand slave interfaces.

1-16 bitsintBUSER Width

AXI Bridge Slave and Master Interface Parameters

Table 10-5: AXI Bridge Slave and Master Interface Parameters


Controls the width of the thread ID of the master andslave interfaces.

ID Width

Controls the depth of the FIFO that Qsys needs in theinterconnect agents based on the maximum pendingcommands that the slave interface accepts.

Write/Read/Combined Acceptance Capability

Controls the depth of the FIFO that Qsys needs in theinterconnect agents based on the maximum pendingcommands that the master interface issues. Issuingcapability must follow acceptance capability to avoidunnecessary creation of FIFOs in the bridge.

Write/Read/Combined Issuing Capability


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Maximumacceptance/issuing capability is amodel-only parameter and does not influence the bridgeHDL. The bridge does not backpressure when this limit is reached. Downstream components and/orthe interconnect must apply backpreasure.

Note:

Address Span ExtenderThe Address Span Extender creates a windowed bridge and allows memory-mapped master interfaces toaccess a larger or smaller address map than the width of their address signals allow. With an address spanextender, a restricted master can access a broader address range. The address span extender splits theaddressable space into multiple separate windows so that the master can access the appropriate part of thememory through the window.

The address span extender does not limit master and slave widths to a 32-bit and 64-bit configuration. Youcan use the address span extender for other width configurations. The address span extender supports 1-64bit address windows.

If a processor can address only 2GB of an address span, and your system contains 4GB of memory, theaddress span extender can provide two 2GBwindows in the 4GBmemory address space. This issue sometimesoccurs with Altera SoC devices. For example, an HPS subsystem in an SoC device can address only 1GB ofan address span within the FPGA using the HPS-to-FPGA bridge. The address span extender enables theSoC device to address all of the address space in the FPGA using multiple 1GB windows.

CTRL Register Layout

The control registers consist of a 64-bit register for each window. You write the base address that you wantfor each window to its corresponding control register. For example, if CTRL_BASE is the base address of theaddress span extender's control register, and there are two windows (0 and 1), then window 0’s controlregister starts at CTRL_BASE, and window 1’s control register starts at CTRL_BASE + 8 (using byte addresses).

Calculating the Address Span Extender Slave Address

The diagrambelowdescribes howQsys calculates the slave address. In this example the address, span extenderis configured with a 28-bit address space for slaves. The lower 26 bits (bits 0 to 25 or [25:0]) is the offsetinto a particular window and originate from the address span extender's data port. The upper 2 bits [27:26]originate from the control registers.


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Figure 10-12: Address Span Extender

0x00000000_04000000

0x00000000_08000000

0x00000000_0C000000

0x00000000_00000000

0

1

2

3

Extended addr_regs[63:0]addr[27:6]

Mapping Table (Sub-Windows)

(”Extended addr regs”[27:2] | “Slave addr”[25:0]) 00

[37:2] [1:0]

[27:26] [25:0]

28 bit SlaveWord Address

38 bit MasterByte Address

ControlPort

Using the Address Span ExtenderWhen you implement the address span extender in Qsys, you must know the amount of address space themaster uses (the size of the window), the total size of the addressable space (the number of windows), andhow much address space (the size of the window) you want a particular slave to occupy in a master’s addressmap.

This component supports 1 to 64 address windows. Qsys requires an assigned number of registers to holdthe upper address bits for each window. In the parameter editor, you must select the number of bits in theexpanded address map you want to access (ExpandedMaster Byte AddressWidth), the number of bits youwant the master to see (Slave Word Address Width), and the number of sub-windows.

Each sub-window has a 64-bit register set that defines the sub window's upper address, and use only the bitsgreater than the slave byte address.

• window 0—expanded address [63:0]• window 1—expanded address [63:0]

Qsys uses the upper bits of the slave address to pick which window to use. For example, if you specify 4windows, then Qsys uses the top 2 bits of the slave address to specify window [0,1,2,3]. Therefore havingmore windows does require the windows to be smaller, for example having 4 windows requires the windowsthemselves to be 1/4 the size of the slave address space. The total windowed address space is still equal tothe original slave address space, but the windows allow access to memory regions in a larger overall addressspace.

In the parameter editor for the address span extender, you can click Documentation to obtain moreinformation about the component.


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Figure 10-13: Address Span Extender Parameter Editor

Alternate Options for the Address Span ExtenderYou can set parameters for the address span extender with an initial fixed address value. Enter an addressfor theResetDefault forMasterWindow option, and selectTrue for theDisable SlaveControl Port option.This allows the address span extender to function as a fixed, non-programmable component.

Each sub-window is equal in size and stacks sequentially in the windowed slave interface's address space.To control the fixed address bits of a particular sub-window, you can write to the sub-window’s register inthe register control slave interface. Qsys structures the logic so that Qsys can optimize and remove bits thatare not needed.

If Burstcount Width is greater than 1, Qsys processes the read burst in a single cycle, and assumes allbyteenables are asserted on every cycle.

NIOS II SupportIf the address span extender window is fixed, for example, the Disable Slave Control Port option is turnedon, then the address span extender performs as a bridge. Components on the slave side of the address spanextender that are within the window are visible to the NIOS II processor. Components partially within awindow appear to NIOS II as if they have a reduced span. For example, a memory partially within a windowappears as having a smaller size.


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QII51025Alternate Options for the Address Span Extender10-18 2014.06.30


You can also use the address span extender to provide a window for the Nios II processor so that the HPSmemory map is visible to NIOS II. In this way it is possible for the Nios II to communicate with HPSperipherals.

In the example below, a NIOS II processor has an address span extender from address 0x40000 to 0x80000.There is a window within the address span extender starting at 0x100000. Within the address span extender'saddress space there is a slave at base address 0x1100000. The slave appears to NIOS II as being at address:

0x110000 - 0x100000 + 0x40000 = 0x050000

Figure 10-14: NIOS II Support and the Address Span Extender

0x80000

0x40000

Nios IIAddress Span

ExtenderAvalon-MM

Slave

0x140000

0x120000

0x110000

0x100000

Effective Slave Base Address =0x110000 - 0x100000 + 0x040000= 0x050000

If the address span extender window is dynamic. For example, when the Disable Slave Control Port optionis turned off, theNIOS II processor is unable to see components on the slave side of the address span extender.

AXI Default SlaveAnAXIDefault Slave provides a predictable error response service formaster interfaces that send transactionsthat attempt to access an undefined memory region. This service guarantees an error response, should amaster access a memory region that is not decoded to an instantiated slave. The error response service alsohelps to avoid unpredictable behavior in your system.

The default slave is an AXI3 component and displays in the IP Catalog as either AXIDefault Slave or ErrorResponse Slave.

AXI protocol requires that if the interconnect cannot successfully decode slave access, it must return theDECERR error response. Therefore, the default slave is required in AXI systems where the address space isnot fully decoded to slave interfaces.

The default slave behaves like any other component in the system and is bound by translation and adaptationinterconnect logic. An increase in resource usage may occur when a default slave connects to masters ofdifferent data widths, including Avalon or AXI-Lite masters.

You can connect clock, reset, and IRQ signals to a default slave, as well as AXI3 and AXI4 master interfaceswithout also instantiating a bridge. When you connect a default slave to a master, the default slave acceptscycles sent from the master, and returns the DECERR error response. On the AXI interface, the default slavesupports only a read and write acceptance of 1, and does not support write data interleaving. The read andwrite channels are independent, and responses are returned when simultaneously targeted by a read andwrite cycle.


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10-19AXI Default SlaveQII510252014.06.30


There is an optional interface on the default slave that supports CSR accesses for debug. CSR registers logthe required information when returning an error response. When turned on, this channel acts as an Avaloninterface with read and write channels with a fixed latency of 1.

To enable a slave interface as a default slave for a master interface in your system, you must connect theslave to the master in your Qsys system. You specify a default slave for a master it by turning on the DefaultSlave column option in the System Contents tab. A system can contain more than one default slave. Alterarecommends instantiating a separate default slave for each AXI master in your system.

For information about creating secure systems and accessing undefined memory regions, refer to Creatinga System with Qsys in volume 1 of the Quartus II Handbook.

Related InformationCreating a System with Qsys

AXI Default Slave ParametersFigure 10-15: AXI Default Slave Parameter Editor

Table 10-6: AXI Default Slave Parameters

DescriptionValueParameter

Determines themaster IDwidth for error logging.1-8 bitsAXI master ID width


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QII51025AXI Default Slave Parameters10-20 2014.06.30



DescriptionValueParameter

Determines the address width for error logging.

This value also affects the overall address width ofthe system, and should not exceed the maximumaddress width required in the system.

8-64 bitsAXI address width

Determines the data width for error logging.32, 64,or128 bits

AXI data width

When turned on, instantiates an Avalon CSRinterface for error logging.

On or OffEnable CSR Support (for error logging)

Depth of the transaction log, for example, thenumber of transactions the CSR logs for cycleswith errors.

1-16 bitsCSR Error Log Depth

When turned on, controls debug access to theCSRinterface.

On or OffRegister Avalon CSR inputs

CSR RegistersWhen an access violation occurs, and the CSR port is enabled, the AXI Default Slave generates an interruptand transfers the transaction information into the error log FIFO.

The error log count continues until the nth log, where n is the log depth. When Qsys responds to the interruptbit, it reads the register until the interrupt bit is no longer valid. The interrupt bit is valid as long as there isa valid bit in FIFO. A cleared interrupt bit is not affected by the FIFO status. When Qsys finishes readingthe register, the access violation service is ready to receive new access violation requests. If an access violationoccurs when FIFO is full, then an overflow bit is set, indicating more than n access violations have occurred,and some are not logged.

Qsys exits the access violation service after either the interrupt bit is no longer set, or when it determinesthat the access violation service has continued for too long.

CSR Interrupt Status Registers

Table 10-7: CSR Interrupt Status Registers

For CSR register maps: Address = Memory Address Base + Offset.DescriptonDefaultAttributeBitOffset

Reserved.0R031:40x00

Read Access Violation Interrupt Overflow register

Asserted when a read access causes the Interconnect toreturn a DECERR response, and the buffer log depth is full.Indicates that there is a logging error lost due to anexceeded buffer log depth. Cleared by setting the bit to1.

0RW1C3


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10-21CSR RegistersQII510252014.06.30


DescriptonDefaultAttributeBitOffset

Write Access Violation Interrupt Overflow register

Asserted when a write access causes the Interconnect toreturn a DECERR response, and the buffer log depth is full.Indicates that there is a logging error lost due to anexceeded buffer log depth. Cleared by setting the bit to1.

0RW1C2

Read Access Violation Interrupt register

Asserted when a read access causes the Interconnect toreturn a DECERR response. Cleared by setting the bit to1.

Access violation are logged until the bit iscleared.

Note:

0RW1C1

Write Access Violation Interrupt register

Asserted when a write access causes the Interconnect toreturn a DECERR response. Cleared by setting the bit to1.

Access violation are logged until the bit iscleared.

Note:

0RW1C0

CSR Read Access Violation LogThe CSR read access violation log settings are valid only when an associated read interrupt register is set.This set of registers should be read until the valid bit is cleared.

Table 10-8: CSR Read Access Violation Log

DescriptionDefaultAttributeBitOffset


Indicates the burst type of the initiating cycle that causesthe access violation.

0R012:11

Indicates the burst length of the initiating cycle thatcauses the access violation.

0R010:7

Indicates the burst size of the initiating cycle that causesthe access violation.

0R06:4

Indicates the PROT of the initiating cycle that causes theaccess violation.

0R03:1


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QII51025CSR Read Access Violation Log10-22 2014.06.30



Read access violation log for the transaction is valid onlywhen this bit is set. This bit is cleared when the interruptregister is cleared.

0R00

Master ID for the cycle that causes the access violation.0R031:00x104

Read cycle target address for the cycle that causes theaccess violation (lower 32-bit).

0R031:00x108

Read cycle target address for the cycle that causes theaccess violation (upper 32-bit). Valid only if widestaddress in system is larger than 32-bits.

When this register is read, the current readaccess violation log is recovered from FIFO.

Note:

0R031:00x10C

CSR Write Access Violation LogThe CSR write access violation log settings are valid only when an associated read interrupt register is set.This set of registers should be read until the valid bit is cleared.

Table 10-9: CSR Write Access Violation Log



Indicates the burst type of the initiating cycle that causesthe access violation.

0R012:11

Indicates the burst length of the initiating cycle thatcauses the access violation.

0R010:7

Indicates the burst size of the initiating cycle that causesthe access violation.

0R06:4

Indicates the PROT of the initiating cycle that causes theaccess violation.

0R03:1

Write access violation log for the transaction is valid onlywhen this bit is set. This bit is cleared when the interruptregister is cleared.

0R00

Master ID for the cycle that causes the access violation.0R031:00x194

Write target address for the cycle that causes the accessviolation (lower 32-bit).

0R031:00x198

Write target address for the cycle that causes the accessviolation (upper 32-bit). Valid only if widest address insystem is larger than 32-bits.

0R031:00x19C


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10-23CSR Write Access Violation LogQII510252014.06.30



First 32-bits of the write data for the write cycle thatcauses the access violation.

When this register is read, the current writeaccess violation log is recovered from FIFO,when the data width is 32-bits.

Note:

0R031:00x1A0

Bits [63:32] of the write data for the write cycle thatcauses the access violation. Valid only if the data widthis greater than 32 -bits.

0R031:00x1A4

Bits [95:64] of the write data for the write cycle thatcauses the access violation. Valid only if the data widthis greater than 64 -bits.

0R031:00x1A8

The first bits (127:96) of the write data for the write cyclethat causes the access violation. Valid only if the datawidth is greater than 64 -bits.

When this register is read, the current writeaccess violation log is recovered from FIFO.

Note:

0R031:00x1AC

Designating a Default Slave in the System Contents TabYou can designate any slave in your Qsys system as the error response default slave. The designated defaultslave provides an error response service for masters that attempt access to an undefined memory region.

1. In your Qsys system, in the SystemContents tab, right-click the header and turn on ShowDefault SlaveColumn.

2. Select the slave that you want to designate as the default slave, and then click the checkbox for the slavein the Default Slave column.

3. In the System Contents tab, in the Connections column, connect the designated default slave to one ormore masters.

Tri-State ComponentsThe tri-state interface type allows you to design Qsys subsystems that connect to tri-state devices on yourPCB. You can use tri-state components to implement pin sharing, convert between unidirectional andbidirectional signals, and create tri-state controllers for devices whose interfaces can be described using thetri-state signal types.


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QII51025Designating a Default Slave in the System Contents Tab10-24 2014.06.30


Figure 10-16: Tri-State Conduit System to Control Off-Chip SRAM and Flash Devices

In this example, there are two generic Tri-State Conduit Controllers. The first is customized to control aflash memory. The second is customized to control an off-chip SSRAM. The Tri-State Conduit Pin Sharermultiplexes between these two controllers, and the Tri-State Conduit Bridge converts between an on-chipencoding of tri-state signals and true bidirectional signals. By default, the Tri-State Conduit Pin Sharer andTri-State Conduit Bridge present byte addresses. Typically, each address location contains more than onebyte of data.

Altera FPGA

Printed Circuit Board

M

M

M

Nios IIProcessor

Cn SSRAM

Cn FlashTCM

S TCM

Generic Tri-stateController

Parameterizedfor 2 MBytex32 SSRAM

TCM

TCS Tri-stateConduitPin

Sharer

Avalon-MM Master

Avalon-MM Slave

CnTCSTri-stateConduitBridge

Generic Tri-stateController

Parameterizedfor 8 MBytex16 FlashS

S

TCS

TCM Avalon-TC Master

Avalon-TC Slave

ConduitCn

TCS


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10-25Tri-State ComponentsQII510252014.06.30


Figure 10-17: Address Connections from Qsys System to PCB

The flash device operates on 16-bit words andmust ignore the least-significant bit of theAvalon-MMaddress,and shows addr[0]as not connected. The SSRAM memory operates on 32-bit words and must ignore thetwo, low-order memory bits. Because neither device requires a byte address, addr[0] is not routed on thePCB.

The flash device responds to address range 0 MBytes to 8 MBytes-1. The SSRAM responds to address range8 MBytes to 10 MBytes-1. The PCB schematic for the PCB connects addr [21:0] to addr [18:0] of theSSRAM device because the SSRAM responds to 32-bit word address. The 8 MByte flash device accesses 16-bit words; consequently, the schematic does not connect addr[0]. The chipselect signals select betweenthe two devices.

PCB_Addr[21:0]

2 MByte SSRAM(32-bit word)

2 MByte SSRAM(32-bit word)

0

8 MBytes

16 MBytes

10 MBytes

PCB_Addr[19:1]

A[21:0]

8 MByte Flash(16-bit word)

8 MByte Flash(16-bit word)

UnusedA[18:0]

Tristate ConduitBridge

PCB

Qsys Address Map

Addr[22:1] PCB_Addr[21:0]

Addr[0]

Addr[23] x

x

If you create a custom tri-state conduit master with word aligned addresses, the Tri-state ConduitPin Sharer does not change or align the address signals.

Note:


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QII51025Tri-State Components10-26 2014.06.30


Figure 10-18: Tri-State Conduit System in Qsys

Related Information


• Avalon Tri-State Conduit Components User Guide

Generic Tri-State ControllerThe Generic Tri-State Controller provides a template for a controller. You can customize the tri-statecontroller with various parameters to reflect the behavior of an off-chip device. The following types ofparameters are available for the tri-state controller:

• Width of the address and data signals• Read and write wait times• Bus-turnaround time• Data hold time


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10-27Generic Tri-State ControllerQII510252014.06.30


http://www.altera.com/literature/ug/ug_avalon_tc.pdf?GSA_pos=1&WT.oss_r=1&WT.oss=Tristate


In calculating delays, the Generic Tri-State Controller chooses the larger of the bus-turnaround timeand read latency. Turnaround time is measured from the time that a command is accepted, not fromthe time that the previous read returned data.

Note:

The Generic Tri-State Controller includes the following interfaces:

• Memory-mapped slave interface—This interface connects to an memory-mapped master, such as aprocessor.

• Tristate Conduit Master interface—Tri-state master interface usually connects to the tri-state conduitslave interface of the tri-state conduit pin sharer.

• Clock sink—The component’s clock reference. You must connect this interface to a clock source.• Reset sink—This interface connects to a reset source interface.

Tri-State Conduit Pin SharerThe Tri-state Conduit Pin Sharer multiplexes between the signals of the connected tri-state controllers. Youconnect all signals from the tri-state controllers to the Tri-state Conduit Pin Sharer and use the parametereditor to specify the signals that are shared.


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QII51025Tri-State Conduit Pin Sharer10-28 2014.06.30


Figure 10-19: Tri-State Conduit Pin Sharer Parameter Editor

The parameter editor includes a Shared Signal Name column. If the widths of shared signals differ, thesignals are aligned on their 0th bit and the higher-order pins are driven to 0 whenever the smaller signal hascontrol of the bus. Unshared signals always propagate through the pin sharer. The tri-state conduit pinsharer uses the round-robin arbiter to select between tri-state conduit controllers.

All tri-state conduit components are connected to a pin sharer must be in the same clock domain.Note:

Related InformationAvalon-ST Round Robin Scheduler on page 10-57

Tri-State Conduit BridgeThe Tri-State Conduit Bridge instantiates bidirectional signals for each tri-state signal while passing all othersignals straight through the component. The Tri-State Conduit Bridge registers all outgoing and incomingsignals, which adds two cycles of latency for a read request. You must account for this additional pipeliningwhen designing a custom controller. During reset, all outputs are placed in a high-impedance state. Outputsare enabled in the first clock cycle after reset is deasserted, and the output signals are then bidirectional.


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Test Pattern Generator and Checker CoresThe data generation and monitoring solution for Avalon-ST consists of two components: a test patterngenerator core that generates data, and sends it out on an Avalon-ST data interface, and a test pattern checkercore that receives the same data and verifies it. Optionally, the data can be formatted as packets, withaccompanying start_of_packet and end_of_packet signals.

The test pattern generator inserts different error conditions, and the test pattern checker reports these errorconditions to the control interface, each via an Avalon Memory-Mapped (Avalon-MM) slave. The ThrottleSeed is the starting value for the throttle control random number generator. Altera recommends a uniquevalue for each instance of the test pattern generator and checker cores in a system.

Test Pattern GeneratorFigure 10-20: Test Pattern Generator Core

The test pattern generator core accepts commands to generate data via an Avalon-MM command interface,and drives the generated data to an Avalon-ST data interface. You can parameterize most aspects of theAvalon-ST data interface, such as the number of error bits and data signal width, thus allowing you to testcomponents with different interfaces.

Avalon-MMSlave Port

Avalo

n-MM

SlaveP

ort

Avalon-STSourceTEST PATTERN

GENERATORcommand data_out

control & status

The data pattern is calculated as: Symbol Value = Symbol Position in Packet XOR Data ErrorMask. Data thatis not organized in packets is a single stream with no beginning or end. The test pattern generator has athrottle register that is set via the Avalon-MM control interface. The test pattern generator uses the value ofthe throttle register in conjunction with a pseudo-random number generator to throttle the data generationrate.

Test Pattern Generator Command InterfaceThe command interface for the Test Pattern Generator is a 32-bit Avalon-MM write slave that accepts datageneration commands. It is connected to a 16-element deep FIFO, thus allowing a master peripheral to drivea number of commands into the test pattern generator.

The command interface maps to the following registers: cmd_lo and cmd_hi. The command is pushed intothe FIFO when the register cmd_lo (address 0) is addressed. When the FIFO is full, the command interfaceasserts the waitrequest signal. You can create errors by writing to the register cmd_hi (address 1). Theerrors are cleared when 0 is written to this register, or its respective fields.


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QII51025Test Pattern Generator and Checker Cores10-30 2014.06.30


Test Pattern Generator Control and Status Interface

The control and status interface of the Test Pattern Generator is a 32-bit Avalon-MM slave that allows youto enable or disable the data generation, as well as set the throttle. This interface also provides generation-time information, such as the number of channels and whether or not data packets are supported.

Test Pattern Generator Output InterfaceThe output interface of the Test Pattern Generator is an Avalon-ST interface that optionally supports datapackets. You can configure the output interface to align with your system requirements. Depending on theincoming stream of commands, the output data may contain interleaved packet fragments for differentchannels. To keep track of the current symbol’s position within each packet, the test pattern generatormaintains an internal state for each channel.

You can configure the output interface of the test pattern generator with the following parameters:

• Number of Channels—Number of channels that the test pattern generator supports. Valid values are 1to 256.

• DataBits Per Symbol—Bits per symbol is related to the width of readdata and writedata signals, whichmust be a multiple of the bits per symbol.

• Data Symbols Per Beat—Number of symbols (words) that are transferred per beat. Valid values are 1to 256.

• Include Packet Support—Indicates whether or not packet transfers are supported. Packet supportincludes the startofpacket, endofpacket, and empty signals.

• Error Signal Width (bits)—Width of the error signal on the output interface. Valid values are 0 to 31.A value of 0 indicates that the error signal is not in use.

If you change only bits per symbol, and do not change the data width, errors are generated.Note:

Test Pattern Generator Functional Parameter

The Test Pattern Generator functional parameter allows you to configure the test pattern generator as awhole system.


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Test Pattern CheckerFigure 10-21: Test Pattern Checker

The test pattern checker core accepts data via an Avalon-ST interface and verifies it against the samepredetermined pattern that the test pattern generator uses to produce the data. The test pattern checker corereports any exceptions to the control interface. You can parameterizemost aspects of the test pattern checker'sAvalon-ST interface such as the number of error bits and the data signal width. This enables the ability totest components with different interfaces. The test pattern checker has a throttle register that is set via theAvalon-MM control interface. The value of the throttle register controls the rate at which data is accepted.

Avalon-MMSlave Port

Avalo

n-ST

Sink

TEST PATTERNCHECKER

data_in

control & status

The test pattern checker detects exceptions and reports them to the control interface via a 32-element deepinternal FIFO. Possible exceptions are data error, missing start-of-packet (SOP), missing end-of-packet(EOP), and signaled error.

As each exception occurs, an exception descriptor is pushed into the FIFO. If the same exception occursmore than once consecutively, only one exception descriptor is pushed into the FIFO. All exceptions areignored when the FIFO is full. Exception descriptors are deleted from the FIFO after they are read by thecontrol and status interface.

Test Pattern Checker Input InterfaceThe Test Pattern Checker input interface is an Avalon-ST interface that optionally supports data packets.You can configure the input interface to align with your system requirements. Incoming data may containinterleaved packet fragments. To keep track of the current symbol’s position, the test pattern checkermaintainsan internal state for each channel.

Test Pattern Checker Control and Status InterfaceThe Test Pattern Checker control and status interface is a 32-bit Avalon-MM slave that allows you to enableor disable data acceptance, as well as set the throttle. This interface provides generation-time information,such as the number of channels and whether the test pattern checker supports data packets. The control andstatus interface also provides information on the exceptions detected by the test pattern checker. The interfaceobtains this information by reading from the exception FIFO.

Test Pattern Checker Functional ParameterThe Test Pattern Checker functional parameter allows you to configure the test pattern checker as a wholesystem.


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Test Pattern Checker Input Parameters

You can configure the input interface of the test pattern checker using the following parameters:

• Data Bits Per Symbol—Bits per symbol is related to the width of readdata and writedata signals,which must be a multiple of the bits per symbol.

• Data Symbols Per Beat—Number of symbols (words) that are transferred per beat. Valid values are 1to 32.

• Include Packet Support—Indicates whether or not data packet transfers are supported. Packet supportincludes the startofpacket, endofpacket, and empty signals.

• Number of Channels—Number of channels that the test pattern checker supports. Valid values are 1 to256.

• Error Signal Width (bits)—Width of the error signal on the input interface. Valid values are 0 to 31.A value of 0 indicates that the error signal in not in use.


Software Programming Model for the Test Pattern Generator and Checker CoresThe HAL system library support, software files, and register maps describe the software programming modelfor the test pattern generator and checker cores.

HAL System Library SupportForNios II processor users, Altera providesHAL system library drivers that allow you to initialize and accessthe test pattern generator and checker cores. Altera recommends you to use the provided drivers to accessthe cores instead of accessing the registers directly.

For Nios II IDE users, copy the provided drivers from the following installation folders to your softwareapplication directory:

• <IP installation directory>/ip/sopc_builder_ip/altera_avalon_data_source/HAL

• <IP installation directory>/ip/sopc_builder_ip/altera_avalon_data_sink/HAL

This instruction does not apply if you use the Nios II command-line tools.Note:

Test Pattern Generator and Test Pattern Checker Core FilesThe following files define the low-level access to the hardware, and provide the routines for the HAL devicedrivers.

Do not modify the test pattern generator or test pattern checker core files.Note:

• Test pattern generator core files:

• data_source_regs.h—Header file that defines the test pattern generator's register maps.• data_source_util.h , data_source_util.c—Header and source code for the functions and variables

required to integrate the driver into the HAL system library.

• Test pattern checker core files:

• data_sink_regs.h—Header file that defines the core’s register maps.• data_sink_util.h , data_sink_util.c—Header and source code for the functions and variables required

to integrate the driver into the HAL system library.


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Register Maps for the Test Pattern Generator and Test Pattern Checker Cores

Test Pattern Generator Control and Status Registers

Table 10-10: Test Pattern Generator Control and Status Register Map

Shows the offset for the test pattern generator control and status registers. Each register is 32-bits wide.Register NameOffset

statusbase + 0

controlbase + 1

fillbase + 2

Table 10-11: Test Pattern Generator Status Register Bits

DescriptionAccessNameBit(s)

A constant value of 0x64.ROID[15:0]

The configured number of channels.RONUMCHANNELS[23:16]

The configured number of symbols per beat.RONUMSYMBOLS[30:24]

A value of 1 indicates data packet support.ROSUPPORTPACKETS[31]

Table 10-12: Test Pattern Generator Control Register Bits


Setting this bit to 1 enables the test pattern generator core.RWENABLE[0]

Reserved[7:1]

Specifies the throttle value which can be between 0–256, inclusively.The test pattern generator uses this value in conjunction with apseudo-random number generator to throttle the data generationrate.

Setting THROTTLE to 0 stops the test pattern generator core. Settingit to 256 causes the test pattern generator core to run at full throttle.Values between 0–256 result in a data rate proportional to the throttlevalue.

RWTHROTTLE[16:8]

When this bit is set to 1, all internal counters and statistics are reset.Write 0 to this bit to exit reset.

RWSOFT RESET[17]

Reserved[31:18]


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QII51025Register Maps for the Test Pattern Generator and Test Pattern Checker Cores10-34 2014.06.30


Table 10-13: Test Pattern Generator Fill Register Bits


A value of 1 indicates that data transmission is in progress, or thatthere is at least one command in the command queue.

ROBUSY[0]

Reserved[6:1]

The number of commands currently in the command FIFO.ROFILL[15:7]

Reserved[31:16]

Test Pattern Generator Command Registers

Table 10-14: Test Pattern Generator Command Register Map

Shows the offset for the command registers. Each register is 32-bits wide.Register NameOffset

cmd_lobase + 0

cmd_hibase + 1

The cmd_lo is pushed into the FIFO only when the cmd_lo register is addressed.

Table 10-15: cmd_lo Register Bits


The segment size in symbols. Except for the last segment in a packet,the size of all segments must be a multiple of the configured numberof symbols per beat. If this condition is not met, the test patterngenerator core inserts additional symbols to the segment to ensurethe condition is fulfilled.

RWSIZE[15:0]

The channel to send the segment on. If the channel signal is lessthan 14 bits wide, the test pattern generator uses the low order bitsof this register to drive the signal.

RWCHANNEL[29:16]

Set this bit to 1 when sending the first segment in a packet. This bitis ignored when data packets are not supported.

RWSOP[30]

Set this bit to 1 when sending the last segment in a packet. This bitis ignored when data packets are not supported.

RWEOP[31]


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10-35Test Pattern Generator Command RegistersQII510252014.06.30


Table 10-16: cmd_hi Register Bits


Specifies the value to drive the error signal. A non-zero value createsa signalled error.

RWSIGNALED

ERROR

[15:0]

The output data is XORed with the contents of this register to createdata errors. To stop creating data errors, set this register to 0.

RWDATA ERROR[23:16]

Set this bit to 1 to suppress the assertion of the startofpacket signalwhen the first segment in a packet is sent.

RWSUPPRESS

SOP

[24]

Set this bit to 1 to suppress the assertion of the endofpacket signalwhen the last segment in a packet is sent.

RWSUPRESS

EOP

[25]

Test Pattern Checker Control and Status Registers

Table 10-17: Test Pattern Checker Control and Status Register Map

Shows the offset for the control and status registers. Each register is 32 bits wide.Register NameOffset

statusbase + 0

controlbase + 1

Reserved

base + 2

base + 3

base + 4

exception_descriptorbase + 5

indirect_selectbase + 6

indirect_countbase + 7

Table 10-18: Test Pattern Checker Status Register Bits


Contains a constant value of 0x65.ROID[15:0]

The configured number of channels.RONUMCHANNELS[23:16]

The configured number of symbols per beat.RONUMSYMBOLS[30:24]

A value of 1 indicates packet support.ROSUPPORTPACKETS[31]


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QII51025Test Pattern Checker Control and Status Registers10-36 2014.06.30


Table 10-19: Test Pattern Checker Control Register Bits


Setting this bit to 1 enables the test pattern checker.RWENABLE[0]

Reserved[7:1]

Specifies the throttle value which can be between 0–256, inclusively.Qsys uses this value in conjunction with a pseudo-random numbergenerator to throttle the data generation rate.

Setting THROTTLE to 0 stops the test pattern generator core. Settingit to 256 causes the test pattern generator core to run at full throttle.Values between 0–256 result in a data rate proportional to the throttlevalue.

RWTHROTTLE[16:8]

When this bit is set to 1, all internal counters and statistics are reset.Write 0 to this bit to exit reset.

RWSOFT RESET[17]

Reserved[31:18]

If there is no exception, reading the exception_descriptor register bit register returns 0.

Table 10-20: exception_descriptor Register Bits


A value of 1 indicates that an error is detected in the incoming data.RODATA ERROR[0]

A value of 1 indicates missing start-of-packet.ROMISSINGSOP[1]

A value of 1 indicates missing end-of-packet.ROMISSINGEOP[2]

Reserved[7:3]

The value of the error signal.ROSIGNALLED

ERROR

[15:8]

Reserved[23:16]

The channel on which the exception was detected.ROCHANNEL[31:24]

Table 10-21: indirect_select Register Bits

DescriptionAccessBits NameBit

Specifies the channel number that applies to the INDIRECT PACKETCOUNT, INDIRECT SYMBOL COUNT, and INDIRECT ERROR COUNT

registers.

RWINDIRECT

CHANNEL

[7:0]

Reserved[15:8]


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The number of data errors that occurred on the channel specifiedby INDIRECT CHANNEL.

ROINDIRECT

ERROR

[31:16]

Table 10-22: indirect_count Register Bits


The number of data packets received on the channel specified byINDIRECT CHANNEL.

ROINDIRECT

PACKET

COUNT

[15:0]

The number of symbols received on the channel specified byINDIRECT CHANNEL.

ROINDIRECT

SYMBOL

COUNT

[31:16]

.

Test Pattern Generator APIThe following subsections describe application programming interface (API) for the test pattern generator.

API functions are currently not available from the interrupt service routine (ISR).Note:

data_source_reset() on page 10-39

data_source_init() on page 10-39

data_source_get_id() on page 10-39

data_source_get_supports_packets() on page 10-40

data_source_get_num_channels() on page 10-40

data_source_get_symbols_per_cycle() on page 10-41

data_source_get_enable() on page 10-41

data_source_set_enable() on page 10-41

data_source_get_throttle() on page 10-42

data_source_set_throttle() on page 10-42

data_source_is_busy() on page 10-43

data_source_fill_level() on page 10-43

data_source_send_data() on page 10-43


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data_source_reset()

Table 10-23: data_source_reset()

DescriptionInformation Type

void data_source_reset(alt_u32 base);Prototype

NoThread-safe

<data_source_util.h >Include

base—Base address of the control and status slave.Parameters

voidReturns

Resets the test pattern generator core including all internal counters andFIFOs. The control and status registers are not reset by this function.

Description

data_source_init()

Table 10-24: data_source_init()


int data_source_init(alt_u32 base, alt_u32 command_base);Prototype

NoThread-safe


base—Base address of the control and status slave.

command_base—Base address of the command slave.

Parameters

1—Initialization is successful.

0—Initialization is unsuccessful.

Returns

Performs the following operations to initialize the test pattern generatorcore:

• Resets and disables the test pattern generator core.• Sets the maximum throttle.• Clears all inserted errors.

Description

data_source_get_id()

Table 10-25: data_source_get_id()


int data_source_get_id(alt_u32 base);Prototype


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YesThread-safe



Test pattern generator core identifier.Returns

Retrieves the test pattern generator core’s identifier.Description

data_source_get_supports_packets()

Table 10-26: data_source_get_supports_packets()


int data_source_init(alt_u32 base);Prototype

YesThread-safe



1—Data packets are supported.

0—Data packets are not supported.

Returns

Checks if the test pattern generator core supports data packets.Description

data_source_get_num_channels()

Table 10-27: data_source_get_num_channels()

DescriptionDescription

int data_source_get_num_channels(alt_u32 base);Prototype

YesThread-safe



Number of channels supported.Returns

Retrieves the number of channels supported by the test pattern generatorcore.

Description


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data_source_get_symbols_per_cycle()

Table 10-28: data_source_get_symbols_per_cycle()

DescriptionDescription

int data_source_get_symbols(alt_u32 base);Prototype

YesThread-safe



Number of symbols transferred in a beat.Returns

Retrieves the number of symbols transferred by the test pattern generatorcore in each beat.

Description

data_source_get_enable()

Table 10-29: data_source_get_enable()


int data_source_get_enable(alt_u32 base);Prototype

YesThread-safe



Value of the ENABLE bit.Returns

Retrieves the value of the ENABLE bit.Description

data_source_set_enable()

Table 10-30: data_source_set_enable()


void data_source_set_enable(alt_u32 base, alt_u32 value);Prototype

NoThread-safe



value— ENABLE bit set to the value of this parameter.

Parameters


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voidReturns

Enables or disables the test pattern generator core. When disabled, thetest pattern generator core stops data transmission but continues to acceptcommands and stores them in the FIFO

Description

data_source_get_throttle()

Table 10-31: data_source_get_throttle()


int data_source_get_throttle(alt_u32 base);Prototype

YesThread-safe



Throttle value.Returns

Retrieves the current throttle value.Description

data_source_set_throttle()

Table 10-32: data_source_set_throttle()


void data_source_set_throttle(alt_u32 base, alt_u32 value)

;

Prototype

NoThread-safe



value—Throttle value.

Parameters

voidReturns

Sets the throttle value, which can be between 0–256 inclusively. Thethrottle value, when divided by 256 yields the rate at which the test patterngenerator sends data.

Description


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data_source_is_busy()

Table 10-33: data_source_is_busy()


int data_source_is_busy(alt_u32 base);Prototype

YesThread-safe



1—Test pattern generator core is busy.

0—Test pattern generator core is not busy.

Returns

Checks if the test pattern generator is busy. The test pattern generatorcore is busy when it is sending data or has data in the command FIFO tobe sent.

Description

data_source_fill_level()

Table 10-34: data_source_fill_level()


int data_source_fill_level(alt_u32 base);Prototype

YesThread-safe



Number of commands in the command FIFO.Returns

Retrieves the number of commands currently in the command FIFO.Description

data_source_send_data()

Table 10-35: data_source_send_data()


int data_source_send_data(alt_u32 cmd_base, alt_u16 channel,

alt_u16 size, alt_u32 flags, alt_u16 error, alt_u8 data_

error_mask);

Prototype

NoThread-safe



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cmd_base—Base address of the command slave.

channel—Channel to send the data.

size—Data size.

flags —Specifies whether to send or suppress SOP and EOP signals.Valid values are DATA_SOURCE_SEND_SOP, DATA_SOURCE_SEND_EOP, DATA_SOURCE_SEND_SUPRESS_SOP and DATA_SOURCE_SEND_SUPRESS_EOP.

error—Value asserted on the error signal on the output interface.

data_error_mask—Parameter and the data are XORed together to produceerroneous data.

Parameters

Returns 1.Returns

Sends a data fragment to the specified channel. If data packets aresupported, applications must ensure consistent usage of SOP and EOPin each channel. Except for the last segment in a packet, the length ofeach segment is a multiple of the data width.

If data packets are not supported, applications must ensure that there areno SOP and EOP indicators in the data. The length of each segment in apacket is a multiple of the data width.

Description

Test Pattern Checker APIThe following subsections describe API for the test pattern checker core. The API functions are currentlynot available from the ISR.

data_sink_reset() on page 10-45

data_sink_init() on page 10-45

data_sink_get_id() on page 10-46

data_sink_get_supports_packets() on page 10-46

data_sink_get_num_channels() on page 10-46

data_sink_get_symbols_per_cycle() on page 10-47

data_sink_get_enable() on page 10-47

data_sink_set enable() on page 10-47

data_sink_get_throttle() on page 10-48

data_sink_set_throttle() on page 10-48

data_sink_get_packet_count() on page 10-49

data_sink_get_error_count() on page 10-49

data_sink_get_symbol_count() on page 10-49

data_sink_get_exception() on page 10-50


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data_sink_exception_is_exception() on page 10-50

data_sink_exception_has_data_error() on page 10-51

data_sink_exception_has_missing_sop() on page 10-51

data_sink_exception_has_missing_eop() on page 10-51

data_sink_exception_signalled_error() on page 10-52

data_sink_exception_channel() on page 10-52

data_sink_reset()

Table 10-36: data_sink_reset()


void data_sink_reset(alt_u32 base);Prototype

NoThread-safe

<data_sink_util.h >Include


voidReturns

Resets the test pattern checker core including all internal counters.Description

data_sink_init()

Table 10-37: data_sink_init()


int data_source_init(alt_u32 base);Prototype

NoThread-safe



1—Initialization is successful.

0—Initialization is unsuccessful.

Returns

Performs the following operations to initialize the test pattern checkercore:

• Resets and disables the test pattern checker core.• Sets the throttle to the maximum value.

Description


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data_sink_get_id()

Table 10-38: data_sink_get_id()


int data_sink_get_id(alt_u32 base);Prototype

YesThread-safe



Test pattern checker core identifier.Returns

Retrieves the test pattern checker core’s identifier.Description

data_sink_get_supports_packets()

Table 10-39: data_sink_get_supports_packets()


int data_sink_init(alt_u32 base);Prototype

YesThread-safe



1—Data packets are supported.

0—Data packets are not supported.

Returns

Checks if the test pattern checker core supports data packets.Description

data_sink_get_num_channels()

Table 10-40: data_sink_get_num_channels()


int data_sink_get_num_channels(alt_u32 base);Prototype

YesThread-safe



Number of channels supported.Returns


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Retrieves the number of channels supported by the test pattern checkercore.

Description

data_sink_get_symbols_per_cycle()

Table 10-41: data_sink_get_symbols_per_cycle()


int data_sink_get_symbols(alt_u32 base);Prototype

YesThread-safe



Number of symbols received in a beat.Returns

Retrieves the number of symbols received by the test pattern checker corein each beat.

Description

data_sink_get_enable()

Table 10-42: data_sink_get_enable()


int data_sink_get_enable(alt_u32 base);Prototype

YesThread-safe



Value of the ENABLE bit.Returns

Retrieves the value of the ENABLE bit.Description

data_sink_set enable()

Table 10-43: data_sink_set enable()


void data_sink_set_enable(alt_u32 base, alt_u32 value);Prototype

NoThread-safe


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value—ENABLE bit is set to the value of the parameter.

Parameters

voidReturns

Enables the test pattern checker core.Description

data_sink_get_throttle()

Table 10-44: data_sink_get_throttle()


int data_sink_get_throttle(alt_u32 base);Prototype

YesThread-safe



Throttle value.Returns

Retrieves the throttle value.Description

data_sink_set_throttle()

Table 10-45: data_sink_set_throttle()


void data_sink_set_throttle(alt_u32 base, alt_u32 value);Prototype

NoThread-safe

<data_sink_util.h >Include:


value—Throttle value.

Parameters

voidReturns

Sets the throttle value, which can be between 0–256 inclusively. Thethrottle value, when divided by 256 yields the rate at which the test patternchecker receives data.

Description


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data_sink_get_packet_count()

Table 10-46: data_sink_get_packet_count()


int data_sink_get_packet_count(alt_u32 base, alt_u32 channel)

;

Prototype

NoThread-safe



channel—Channel number.

Parameters

Number of data packets received on the channel.Returns

Retrieves the number of data packets received on a channel.Description

data_sink_get_error_count()

Table 10-47: data_sink_get_error_count()


int data_sink_get_error_count(alt_u32 base, alt_u32 channel)

;

Prototype

NoThread-safe




Parameters

Number of errors received on the channel.Returns

Retrieves the number of errors received on a channel.Description

data_sink_get_symbol_count()

Table 10-48: data_sink_get_symbol_count()


int data_sink_get_symbol_count(alt_u32 base, alt_u32 channel)

;

Prototype

NoThread-safe



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Parameters

Number of symbols received on the channel.Returns

Retrieves the number of symbols received on a channel.Description

data_sink_get_exception()

Table 10-49: data_sink_get_exception()


int data_sink_get_exception(alt_u32 base);Prototype

YesThread-safe



First exception descriptor in the exception FIFO.

0—No exception descriptor found in the exception FIFO.

Returns

Retrieves the first exception descriptor in the exception FIFO and popsit off the FIFO.

Description

data_sink_exception_is_exception()

Table 10-50: data_sink_exception_is_exception()


int data_sink_exception_is_exception(int exception);Prototype

YesThread-safe


exception—Exception descriptorParameters

1—Indicates an exception.

0—No exception.

Returns

Checks if an exception descriptor describes a valid exception.Description


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data_sink_exception_has_data_error()

Table 10-51: data_sink_exception_has_data_error()


int data_sink_exception_has_data_error(int exception);Prototype

YesThread-safe


exception—Exception descriptor.Parameters

1—Data has errors.

0—No errors.

Returns

Checks if an exception indicates erroneous data.Description

data_sink_exception_has_missing_sop()

Table 10-52: data_sink_exception_has_missing_sop()


int data_sink_exception_has_missing_sop(int exception);Prototype

YesThread-safe



1—Missing SOP.

0—Other exception types.

Returns

Checks if an exception descriptor indicates missing SOP.Description

data_sink_exception_has_missing_eop()

Table 10-53: data_sink_exception_has_missing_eop()


int data_sink_exception_has_missing_eop(int exception);Prototype

YesThread-safe




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1—Missing EOP.

0—Other exception types.

Returns

Checks if an exception descriptor indicates missing EOP.Description

data_sink_exception_signalled_error()

Table 10-54: data_sink_exception_signalled_error()


int data_sink_exception_signalled_error(int exception);Prototype

YesThread-safe



Signal error value.Returns

Retrieves the value of the signaled error from the exception.Description

data_sink_exception_channel()

Table 10-55: data_sink_exception_channel()


int data_sink_exception_channel(int exception);Prototype

YesThread-safe



Channel number on which an exception occurred.Returns

Retrieves the channel number on which an exception occurred.Description


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Avalon-ST Splitter CoreFigure 10-22: Avalon-ST Splitter Core

The Avalon-ST Splitter Core allows you to replicate transactions from an Avalon-ST source interface tomultiple Avalon-ST sink interfaces. This core supports from 1 to 16 outputs.

Output 0

In_Data

Out_Data

Avalo

n-ST

Sink

Avalon-STSplitter Core

Output NAvalon-STSource0

Clock

Avalon-STSourceN

The Avalon-ST Splitter core copies input signals from the input interface to the corresponding output signalsof each output interface without altering the size or functionality. This includes all signals except for theready signal. The core includes a clock signal to determine the Avalon-ST interface and clock domain wherethe core resides. Because the splitter core does nor use the clock signal internally, latency is not introducedwhen using this core.

Splitter Core BackpressureThe Avalon-ST Splitter core integrates with backpressure by AND-ing the ready signals from the outputinterfaces and sending the result to the input interface. As a result, if an output interface deasserts the readysignal, the input interface receives the deasserted ready signal, as well. This functionality ensures thatbackpressure on the output interfaces is propagated to the input interface.

When the Qualify Valid Out parameter is set to 1, the out_valid signals on all other output interfaces aregated when backpressure is applied from one output interface. In this case, when any output interfacedeasserts its ready signal, the out_valid signals on the other output interfaces are also deasserted.

When the Qualify Valid Out parameter is set to 0, the output interfaces have a non-gated out_valid signalwhen backpressure is applied. In this case, when an output interface deasserts its ready signal, the out_validsignals on the other output interfaces are not affected.

Because the logic is combinational, the core introduces no latency.

Splitter Core InterfacesThe Avalon-ST Splitter core supports streaming data, with optional packet, channel, and error signals. Thecore propagates backpressure from any output interface to the input interface.

Table 10-56: Avalon-ST Splitter Core Support

SupportFeature

Ready latency = 0.Backpressure

Configurable.Data Width


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SupportFeature

Supported (optional).Channel

Supported (optional).Error

Supported (optional).Packet

Splitter Core Parameters

Table 10-57: Avalon-ST Splitter Core Parameters

DescriptionDefault ValueLegal ValuesParameter

The number of output interfaces. Qsyssupports 1 for some systems where noduplicated output is required.

21 to 16Number Of Outputs

Determines whether the out_valid signal isgated or non-gated when backpressure isapplied.

10 or 1Qualify Valid Out

The width of the data on the Avalon-ST datainterfaces.

81–512Data Width

The number of bits per symbol for the inputand output interfaces. For example, byte-oriented interfaces have 8-bit symbols.

81–512Bits Per Symbol

Indicates whether or not data packet transfersare supported. Packet support includes thestartofpacket, endofpacket, and empty

signals.

00 or 1Use Packets

The option to enable or disable the channelsignal.

00 or 1Use Channel

The width of the channel signal on the datainterfaces. This parameter is disabled whenUse Channel is set to 0.

10-8Channel Width

The maximum number of channels that adata interface can support. This parameter isdisabled when Use Channel is set to 0.

10-255Max Channels

The option to enable or disable the errorsignal.

00 or 1Use Error


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The width of the error signal on the outputinterfaces. A value of 0 indicates that thesplitter core is not using the error signal.This parameter is disabled when Use Erroris set to 0.

10–31Error Width

Avalon-ST Delay CoreFigure 10-23: Avalon-ST Delay Core

The Avalon-ST Delay Core provides a solution to delay Avalon-ST transactions by a constant number ofclock cycles. This core supports up to 16 clock cycle delays.

Out_DataIn_Data

Clock

Avalo

n-ST

Sink

Avalon-STSourceAvalon-ST

Delay Core

TheDelay core adds a delay between the input and output interfaces. The core accepts transactions presentedon the input interface and reproduces them on the output interface N cycles later without changing thetransaction.

The input interface delays the input signals by a constant N number of clock cycles to the correspondingoutput signals of the output interface. The Number Of Delay Clocks parameter defines the constant N,which must be between 0 and 16. The change of the in_valid signal is reflected on the out_valid signalexactly N cycles later.

Delay Core Reset SignalThe Avalon-ST Delay core has a reset signal that is synchronous to the clk signal. When the core assertsthe reset signal, the output signals are held at 0. After the reset signal is deasserted, the output signals areheld at 0 for N clock cycles. The delayed values of the input signals are then reflected at the output signalsafter N clock cycles.

Delay Core InterfacesThe Delay core supports streaming data, with optional packet, channel, and error signals. The delay coredoes not support backpressure.

Table 10-58: Avalon-ST Delay Core Support

SupportFeature

Not supported.Backpressure



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SupportFeature

Supported (optional).Channel

Supported (optional).Error

Supported (optional).Packet

Delay Core Parameters

Table 10-59: Avalon-ST Delay Core Parameters


Specifies the delay the core introduces, inclock cycles. Qsys supports 0 for somesystems where no delay is required.

10 to 16Number Of Delay Clocks

The width of the data on the Avalon-ST datainterfaces.

81–512Data Width

The number of bits per symbol for the inputand output interfaces. For example, byte-oriented interfaces have 8-bit symbols.

81–512Bits Per Symbol

Indicates whether or not data packet transfersare supported. Packet support includes thestartofpacket, endofpacket, and empty

signals.

00 or 1Use Packets

The option to enable or disable the channelsignal.

00 or 1Use Channel

The width of the channel signal on the datainterfaces. This parameter is disabled whenUse Channel is set to 0.

10-8Channel Width

The maximum number of channels that adata interface can support. This parameter isdisabled when Use Channel is set to 0.

10-255Max Channels

The option to enable or disable the errorsignal.

00 or 1Use Error

The width of the error signal on the outputinterfaces. A value of 0 indicates that the errorsignal is not in use. This parameter is disabledwhen Use Error is set to 0.

10–31Error Width


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Avalon-ST Round Robin SchedulerFigure 10-24: Avalon-ST Round Robin Scheduler

The Avalon-ST Round Robin Scheduler core controls the read operations from a multi-channel Avalon-STcomponent that buffers data by channels. It reads the almost-full threshold values from themultiple channelsin the multi-channel component and issues the read request to the Avalon-ST source according to around-robin scheduling algorithm.

Request(Channel_select) Almost Full StatusAvalon-ST

Round-RobinSchedulerAv

alon-MM

Write

Maste

r

Avalon-STSink

In a multi-channel component, the component can store data either in the sequence that it comes in (FIFO),or in segments according to the channel. When data is stored in segments according to channels, a scheduleris needed to schedule the read operations.

Almost-Full Status Interface (Round Robin Scheduler)The Almost-Full Status interface is an Avalon-ST sink interface that collects the almost-full status from thesink components for the channels in the sequence provided.

Table 10-60: Avalon-ST Interface Feature Support

PropertyFeature

Not supportedBackpressure

Data width = 1; Bits per symbol = 1Data Width

Maximum channel = 32; Channel width = 5Channel

Not supportedError

Not supportedPacket

Request Interface (Round Robin Scheduler)The Request Interface is an Avalon-MM write master interface that requests data from a specific channel.The Avalon-ST Round Robin Scheduler cycles through the channels it supports and schedules data to beread.

Round Robin Scheduler OperationIf a particular channel is almost full, the Avalon-ST Round Robin Scheduler does not schedule data to beread from that channel in the source component.


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The scheduler only requests 1 beat of data from a channel at each transaction. To request 1 beat of data fromchannel n, the scheduler writes the value 1 to address (4 ×n). For example, if the scheduler is requesting datafrom channel 3, the scheduler writes 1 to address 0xC. At every clock cycle, the scheduler requests data fromthe next channel. Therefore, if the scheduler starts requesting from channel 1, at the next clock cycle, itrequests from channel 2. The scheduler does not request data from a particular channel if the almost-fullstatus for the channel is asserted. In this case, the scheduler uses one clock cycle without a request transaction.

The Avalon-ST Round Robin Scheduler cannot determine if the requested component is able to service therequest transaction. The component asserts waitrequest when it cannot accept new requests.

Table 10-61: Avalon-ST Round Robin Scheduler Ports

DescriptionDirectionSignal

Clock and Reset

Clock reference.Inclk

Asynchronous active low reset.Inreset_n

Avalon-MM Request Interface

The write address that indicates which channel hasthe request.

Outrequest_address (log2 Max_

Channels–1:0)

Write enable signal.Outrequest_write

The amount of data requested from the particularchannel.

This value is always fixed at 1.

Outrequest_writedata

Wait request signal that pauses the scheduler whenthe slave cannot accept a new request.

Inrequest_waitrequest

Avalon-ST Almost-Full Status Interface

Indicates that almost_full_channel and almost_

full_data are valid.Inalmost_full_valid

Indicates the channel for the current status indication.Inalmost_full_channel (Channel_

Width–1:0)

A 1-bit signal that is asserted high to indicate that thechannel indicated by almost_full_channel is almostfull.

Inalmost_full_data (log2 Max_

Channels–1:0)


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Round Robin Scheduler Parameters

Table 10-62: Avalon-ST Round Robin Scheduler Parameters


Specifies the number of channels the Avalon-ST RoundRobin Scheduler supports.

2–32Number of channels

Specifies whether the scheduler uses the almost-full interface.If not, the core requests data from the next channel at thenext clock cycle.

0–1Use almost-full status

Avalon Packets to Transactions ConverterFigure 10-25: Avalon Packets to Transactions Converter Core

The Avalon Packets to Transactions Converter core receives streaming data from upstream componentsand initiates Avalon-MM transactions. The core then returns Avalon-MM transaction responses to therequesting components.

Avalo

n-ST

Sink

AvalonPackets toTransactionsConverter

data_out

Avalo

n-MM

Maste

rdata_in

Avalo

n-ST

Source

Avalon-MMSlave

Component

The SPI Slave to Avalon Master Bridge and JTAG to Avalon Master Bridge are examples of thePackets to Transactions Converter core. For more information, refer to the Avalon Interface Specifi-cations.

Note:

Related InformationAvalon Interface Specifications

Packets to Transactions Converter Interfaces

Table 10-63: Properties of Avalon-ST Interfaces

PropertyFeature


Data width = 8 bits; Bits per symbol = 8.Data Width


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PropertyFeature

Not supported.Channel

Not used.Error

Supported.Packet

The Avalon-MM master interface supports read and write transactions. The data width is set to 32 bits, andburst transactions are not supported.

Packets to Transactions Converter OperationThe Packets to Transactions Converter core receives streams of packets on its Avalon-ST sink interface andinitiates Avalon-MM transactions. Upon receiving transaction responses from Avalon-MM slaves, the coretransforms the responses to packets and returns them to the requesting components via its Avalon-ST sourceinterface. The core does not report Avalon-ST errors.

Packets to Transactions Converter Data Packet FormatsA response packet is returned for every write transaction. The core also returns a response packet if a notransaction (0x7f) is received. An invalid transaction code is regarded as a no transaction. For readtransactions, the core returns the data read.

The Packets to Transactions Converter core expects incoming data streams to be in the formats shown thetable below.

Table 10-64: Data Packet Formats

DescriptionFieldByte

Transaction Packet Format

Type of transaction.Transaction code0

Reserved for future use.Reserved1

Transaction size in bytes. For write transactions, the sizeindicates the size of the data field. For read transactions,the size indicates the total number of bytes to read.

Size[3:2]

32-bit address for the transaction.Address[7:4]

Transaction data; data to be written for write transactions.Data[n:8]

Response Packet Format

The transaction code with the most significant bit inversed.Transaction code0

Reserved for future use.Reserved1

Total number of bytes read/written successfully.Size[4:2]


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Related InformationPackets to Transactions Converter Interfaces on page 10-59

Packets to Transactions Converter Supported Transactions

Table 10-65: Packets to Transactions Converter Supported Transactions

Avalon-MM transactions supported by the Packets to Transactions Converter core.DescriptionAvalon-MM TransactionTransaction

Code

Writes data to the address until the total number of byteswritten to the sameword address equals to the value specifiedin the size field.

Write, non-incrementing address.0x00

Writes transaction data starting at the current address.Write, incrementing address.0x04

Reads 32 bits of data from the address until the total numberof bytes read from the same address equals to the valuespecified in the size field.

Read, non-incrementing address.0x10

Reads the number of bytes specified in the size parameterstarting from the current address.

Read, incrementing address.0x14

No transaction is initiated. You can use this transaction typefor testing purposes. Although no transaction is initiated onthe Avalon-MM interface, the core still returns a responsepacket for this transaction code.

No transaction.0x7f

The Packets to Transactions Converter core can process only a single transaction at a time. The ready signalon the core's Avalon-ST sink interface is asserted only when the current transaction is completely processed.

No internal buffer is implemented on the data paths. Data received on the Avalon-ST interface is forwardeddirectly to the Avalon-MM interface and vice-versa. Asserting the waitrequest signal on the Avalon-MMinterface backpressures the Avalon-ST sink interface. In the opposite direction, if the Avalon-ST sourceinterface is backpressured, the read signal on the Avalon-MM interface is not asserted until the backpressureis alleviated. Backpressuring the Avalon-ST source in the middle of a read could result in data loss. In thiscases, the core returns the data that is successfully received.

A transaction is considered complete when the core receives an EOP. For write transactions, the actual datasize is expected to be the same as the value of the size property. Whether or not both values agree, the corealways uses the end of packet (EOP) to determine the end of data.

Packets to Transactions Converter Malformed Packets

The following are examples of malformed packets:

• Consecutive start of packet (SOP)—An SOP marks the beginning of a transaction. If an SOP is receivedin the middle of a transaction, the core drops the current transaction without returning a response packetfor the transaction, and initiates a new transaction. This effectively precesses packets without an end ofpacket (EOP).

• Unsupported transaction codes—The core processes unsupported transactions as a no transaction.


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Avalon-ST Streaming Pipeline StageThe Avalon-ST pipeline stage receives data from an Avalon-ST source interface, and outputs the data to anAvalon-ST sink interface. In the absence of back pressure, the Avalon-ST pipeline stage source interfaceoutputs data one cycle after receiving the data on its sink interface.

If the pipeline stage receives back pressure on its source interface, it continues to assert its source interface'scurrent data output. While the pipeline stage is receiving back pressure on its source interface and it receivesnew data on its sink interface, the pipeline stage internally buffers the new data. It then asserts back pressureon its sink interface.

Once the backpressure is deasserted, the pipeline stage's source interface is de-asserted and the pipeline stageasserts internally buffered data (if present). Additionally, the pipeline stage de-asserts back pressure on itssink interface.

Figure 10-26: Pipeline Stage Simple Register

If the ready signal is not pipelined, the pipeline stage becomes a simple register.

Sink Sourcedata_in data_outRegister 0

Figure 10-27: Pipeline Stage Holding Register

If the ready signal is pipelined, the pipeline stage must also include a second "holding" register.

Sink Sourcedata_in data_outRegister 1

Register 0

Full?

Full?

Streaming Channel Multiplexer and Demultiplexer CoresThe Avalon-ST channel multiplexer core receives data from various input interfaces and multiplexes thedata into a single output interface, using the optional channel signal to indicate the origin of the data. TheAvalon-ST channel demultiplexer core receives data from a channelized input interface and drives that datato multiple output interfaces, where the output interface is selected by the input channel signal.

The multiplexer and demultiplexer cores can transfer data between interfaces on cores that supportunidirectional flow of data. The multiplexer and demultiplexer allow you to create multiplexed or demulti-plexed data paths without having to write custom HDL code. The multiplexer includes an Avalon-ST RoundRobin Scheduler.


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Related InformationAvalon-ST Round Robin Scheduler on page 10-57

Software Programming Model For the Multiplexer and Demultiplexer ComponentsThe multiplexer and demultiplexer components do not have any user-visible control or status registers.Therefore, Qsys cannot control or configure any aspect of the multiplexer or demultiplexer at run-time. Thecomponents cannot generate interrupts.

Avalon-ST MultiplexerFigure 10-28: Avalon-ST Multiplexer

The Avalon-ST multiplexer takes data from a variety of input data interfaces, and multiplexes the data ontoa single output interface. The multiplexer includes a round-robin scheduler that selects from the next inputinterface that has data. Each input interface has the same width as the output interface, so that the otherinput interfaces are backpressured when the multiplexer is carrying data from a different input interface.

srcsink

data _ in _n

sink

data _ in 0

data _out...

Round Robin , BurstAware Scheduler

(optional )

sink

sink..

.

channel

The multiplexer includes an optional channel signal that enables each input interface to carry channelizeddata. The output interface channel width is equal to:

(log2 (n-1)) + 1 + w

where n is the number of input interfaces, and w is the channel width of each input interface. All inputinterfaces must have the same channel width. These bits are appended to either the most or least significantbits of the output channel signal.

The scheduler processes one input interface at a time, selecting it for transfer. Once an input interface hasbeen selected, data from that input interface is sent until one of the following scenarios occurs:

• The specified number of cycles have elapsed.• The input interface has no more data to send and the valid signal is deasserted on a ready cycle.• When packets are supported, endofpacket is asserted.

Multiplexer Input InterfacesEach input interface is an Avalon-ST data interface that optionally supports packets. The input interfacesare identical; they have the same symbol and data widths, error widths, and channel widths.

Multiplexer Output InterfaceThe output interface carries the multiplexed data stream with data from the inputs. The symbol, data, anderror widths are the same as the input interfaces.


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10-63Software Programming Model For the Multiplexer and Demultiplexer ComponentsQII510252014.06.30


The width of the channel signal is the same as the input interfaces, with the addition of the bits needed toindicate the origin of the data.

You can configure the following parameters for the output interface:

• Data Bits Per Symbol—The bits per symbol is related to the width of readdata and writedata signals,which must be a multiple of the bits per symbol.

• Data Symbols Per Beat—The number of symbols (words) that are transferred per beat (transfer). Validvalues are 1 to 32.

• Include Packet Support—Indicates whether or not packet transfers are supported. Packet supportincludes the startofpacket, endofpacket, and empty signals.

• Channel SignalWidth (bits)—The number of bits Qsys uses for the channel signal for output interfaces.For example, set this parameter to 1 if you have two input interfaces with no channel, or set this parameterto 2 if you have two input interfaces with a channel width of 1 bit. The input channel can have a widthbetween 0-31 bits.

• Error Signal Width (bits)—The width of the error signal for input and output interfaces. A value of 0means the error signal is not in use.


Multiplexer Parameters

You can configure the following parameters for the multiplexer:

• Number of Input Ports—The number of input interfaces that the multiplexer supports. Valid values are2 to 16.

• Scheduling Size (Cycles)—The number of cycles that are sent from a single channel before changing tothe next channel.

• Use Packet Scheduling—When this parameter is turned on, the multiplexer only switches the selectedinput interface on packet boundaries. Therefore, packets on the output interface are not interleaved.

• Use high bits to indicate source port—When this parameter is turned on, the multiplexer uses the highbits of the output channel signal to indicate the origin of the input interface of the data. For example, ifthe input interfaces have 4-bit channel signals, and the multiplexer has 4 input interfaces, the outputinterface has a 6-bit channel signal. If this parameter is turned on, bits [5:4] of the output channel signalindicate origin of the input interface of the data, and bits [3:0] are the channel bits that were presentedat the input interface.


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Avalon-ST DemultiplexerFigure 10-29: Avalon-ST Demultiplexer

That Avalon-ST demultiplexer takes data from a channelized input data interface and provides that data tomultiple output interfaces, where the output interface selected for a particular transfer is specified by theinput channel signal.

sinkdata _out _n

data _out 0

sinksinkdata _ in

src

src

...

...

channel

The data is delivered to the output interfaces in the same order it is received at the input interface, regardlessof the value of channel, packet, frame, or any other signal. Each of the output interfaces has the same widthas the input interface; each output interface is idle when the demultiplexer is driving data to a differentoutput interface. The demultiplexer uses log2 (num_output_interfaces) bits of the channel signal to selectthe output for the data; the remainder of the channel bits are forwarded to the appropriate output interfaceunchanged.

Demultiplexer Input InterfaceEach input interface is an Avalon-ST data interface that optionally supports packets. You can configure thefollowing parameters for the input interface:

• Data Bits Per Symbol—The bits per symbol is related to the width of readdata and writedata signals,which must be a multiple of the bits per symbol.

• Data Symbols Per Beat—The number of symbols (words) that are transferred per beat (transfer). Validvalues are 1 to 32.

• Include Packet Support—Indicates whether or not data packet transfers are supported. Packet supportincludes the startofpacket, endofpacket, and empty signals.

• Channel Signal Width (bits)—The number of bits for the channel signal for output interfaces. A valueof 0 means that output interfaces do not use the optional channel signal.

• Error Signal Width (bits)—The width of the error signal for input and output interfaces. A value of 0means the error signal is in use.


Demultiplexer Output InterfaceEach output interface carries data from a subset of channels from the input interface. Each output interfaceis identical; all have the same symbol and data widths, error widths, and channel widths. The symbol, data,and error widths are the same as the input interface. The width of the channel signal is the same as the inputinterface, without the bits that the demultiplexer uses to select the output interface.


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10-65Avalon-ST DemultiplexerQII510252014.06.30


Demultiplexer Parameters

You can configure the following parameters for the demultiplexer:

• Number of Output Ports—The number of output interfaces that the multiplexer supports Valid valuesare 2 to 16.

• High channel bits select output—When this option is turned on, the demultiplexing function uses thehigh bits of the input channel signal, and the low order bits are passed to the output. When this optionis turned off, the demultiplexing function uses the low order bits, and the high order bits are passed tothe output.

Where you place the signals in our design affects the functionality; for example, there is one input interfaceand two output interfaces. If the low-order bits of the channel signal select the output interfaces, the evenchannels goes to channel 0, and the odd channels goes to channel 1. If the high-order bits of the channelsignal select the output interface, channels 0 to 7 goes to channel 0 and channels 8 to 15 goes to channel 1.

Figure 10-30: Select Bits for the Demultiplexer

sink

data _out _n

data _out 0

sinksinkdata _ in

src

src

channel <4 ..0>

channel <3 ..0>

channel <3..0>

Single-Clock and Dual-Clock FIFO CoresThe Avalon-ST Single-Clock and Avalon-ST Dual-Clock FIFO cores are FIFO buffers which operate witha common clock and independent clocks for input and output ports respectively.

Figure 10-31: Avalon-ST Single Clock FIFO Core

Avalon-STSingle-Clock

FIFO

Avalon-MMSlave

almost_full almost_empty

csr

Avalon-STStatusSource

Avalon-STStatusSource

outin Avalon-STDataSink

Avalon-STDataSource


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Figure 10-32: Avalon-ST Dual Clock FIFO Core

Avalon-MMSlave

in_csr out_csr

Avalon-MMSlave

outin

Clock A Clock B

Avalon-STDual-Clock

FIFO

Avalon-STDataSink

Avalon-STDataSource

Interfaces Implemented in FIFO CoresThe following interfaces are implemented in FIFO cores:

Avalon-ST Data Interface on page 10-67

Avalon-MM Control and Status Register Interface on page 10-67

Avalon-ST Status Interface on page 10-68

Avalon-ST Data Interface

Each FIFO core has an Avalon-ST data sink and source interfaces. The data sink and source interfaces inthe dual-clock FIFO core are driven by different clocks.

Table 10-66: Avalon-ST Interfaces Properties

PropertyFeature



Supported, up to 255 channels.Channel

Configurable.Error

Configurable.Packet

Avalon-MM Control and Status Register Interface

You can configure the single-clock FIFO core to include an optional Avalon-MM interface, and the dual-clock FIFO core to include an Avalon-MM interface in each clock domain. The Avalon-MM interfaceprovides access to 32-bit registers, which allows you to retrieve the FIFO buffer fill level and configure the


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almost-empty and almost-full thresholds. In the single-clock FIFO core, you can also configure the packetand error handling modes.

Avalon-ST Status Interface

The single-clock FIFO core has two optional Avalon-ST status source interfaces from which you can obtainthe FIFO buffer almost-full and almost empty statuses.

FIFO Operating Modes• Default mode—The core accepts incoming data on the in interface (Avalon-ST data sink) and forwards

it to the out interface (Avalon-ST data source). The core asserts the valid signal on the Avalon-ST sourceinterface to indicate that data is available at the interface.

• Store and forward mode—This mode applies only to the single-clock FIFO core. The core asserts thevalid signal on the out interface only when a full packet of data is available at the interface. In this mode,you can also enable the drop-on-error feature by setting the drop_on_error register to 1. When thisfeature is enabled, the core drops all packets received with the in_error signal asserted.

• Cut-through mode—This mode applies only to the single-clock FIFO core. The core asserts the validsignal on the out interface to indicate that data is available for consumption when the number of entriesspecified in the cut_through_threshold register are available in the FIFO buffer.

To use the store and forward or cut-through mode, turn on the Use store and forward parameter to includethe csr interface (Avalon-MM slave). Set the cut_through_threshold register to 0 to enable the store andforward mode, and then set the register to any value greater than 0 to enable the cut-through mode. Thenon-zero value specifies theminimumnumber of FIFO entries thatmust be available before the data is readyfor consumption. Setting the register to 1 provides you with the default mode.

Fill Level of the FIFO BufferYou can obtain the fill level of the FIFO buffer via the optional Avalon-MM control and status interface.Turn on the Use fill level parameter (Use sink fill level and Use source fill level in the dual-clock FIFOcore) and read the fill_level register.

The dual-clock FIFO core has two fill levels. one in each clock domain. Due to the latency of the clockcrossing logic, the fill levels reported in the input and output clock domains may be different for any instance.In both cases, the fill level may report badly for the clock domain; that is, the fill level is reported high in theinput clock domain, and low in the output clock domain.

The dual-clock FIFO has an output pipeline stage to improve fMAX. This output stage is accounted for whencalculating the output fill level, but not when calculating the input fill level. Therefore, the best measure ofthe amount of data in the FIFO is by the fill level in the output clock domain. The fill level in the input clockdomain represents the amount of space available in the FIFO (available space = FIFOdepth – input fill level).

Almost-Full and Almost-Empty Thresholds to Prevent Overflow and UnderflowYou can use almost-full and almost-empty thresholds as a mechanism to prevent FIFO overflow andunderflow. This feature is available only in the single-clock FIFO core. To use the thresholds, turn on theUse fill level, Use almost-full status, and Use almost-empty status parameters. You can access thealmost_full_threshold and almost_full_threshold registers via the csr interface and set the registersto an optimal value for your application.

You can obtain the almost-full and almost-empty statuses from almost_full and almost_empty interfaces(Avalon-ST status source). The core asserts the almost_full signal when the fill level is equal to or higher


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than the almost-full threshold. Likewise, the core asserts the almost_empty signal when the fill level is equalto or lower than the almost-empty threshold.

Single-Clock and Dual-Clock FIFO Core Parameters

Table 10-67: Single-Clock and Dual-Clock FIFO Core Parameters

DescriptionLegalValues

Parameter

These parameters determine the width of the FIFO.

FIFO width = Bits per symbol * Symbols per beat, where:Bits per symbol is the number of bits in a symbol, andSymbols per beat is the number of symbols transferred ina beat.

1–32Bits per symbol

1–32Symbols per beat

The width of the error signal.0–32Error width

The FIFO depth. An output pipeline stage is added to theFIFO to increase performance, which increases the FIFOdepth by one. <n> = n=1,2,3,4...

2 nFIFO depth

Turn on this parameter to enable data packet support onthe Avalon-ST data interfaces.

—Use packets

The width of the channel signal.1–32Channel width

Avalon-ST Single Clock FIFO Only

Turn on this parameter to include the Avalon-MM controland status register interface.

—Use fill level

Avalon-ST Dual Clock FIFO Only

Turn on this parameter to include the Avalon-MM controland status register interface in the input clock domain.

—Use sink fill level

Turn on this parameter to include the Avalon-MM controland status register interface in the output clock domain.

—Use source fill level

The length of the write pointer synchronizer chain. Settingthis parameter to a higher value leads to better metastabilitywhile increasing the latency of the core.

2–8Write pointer synchronizerlength

The length of the read pointer synchronizer chain. Settingthis parameter to a higher value leads to better metastability.

2–8Readpointer synchronizer length

Turn on this parameter to specify the maximum channelnumber.

—Use Max Channel

Maximum channel number.1–255Max Channel


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For more information on metastability in Altera devices, refer to Understanding Metastability inFPGAs. For more information on metastability analysis and synchronization register chains, referto the Managing Metastability.

Note:

Related Information

• Understanding Metastability in FPGAs

• Managing Metastability

Avalon-ST Single-Clock FIFO Registers

Table 10-68: Avalon-ST Single-Clock FIFO Registers

The csr interface in the Avalon-ST Single Clock FIFO core provides access to registers.DescriptionResetAccessName32-Bit Word

Offset

24-bit FIFO fill level. Bits 24 to 31 are not used.0Rfill_

level

0

Reserved for future use.——Reserved1

Set this register to a value that indicates the FIFO buffer isgetting full.

FIFOdepth–1

RWalmost_

full_

threshold

2

Set this register to a value that indicates the FIFO buffer isgetting empty.

0RWalmost_

empty_

threshold

3

0—Enables store and forward mode.

Greater than 0—Enables cut-through mode and specifiesthe minimum of entries in the FIFO buffer before the validsignal on the Avalon-ST source interface is asserted. Oncethe FIFO core starts sending the data to the downstreamcomponent, it continues to do so until the end of the packet.

This register applies only when the Use store and forwardparameter is turned on.

0RWcut_

through_

threshold

4

0—Disables drop-on error.

1—Enables drop-on error.

This register applies onlywhen theUsepacket andUse storeand forward parameters are turned on.

0RWdrop_on_

error

5


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http://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf

http://www.altera.com/literature/hb/qts/qts_qii51018.pdf


Table 10-69: Register Description for Avalon-ST Dual-Clock FIFO

The in_csr and out_csr interfaces in the Avalon-ST Dual Clock FIFO core reports the FIFO fill level.DescriptionReset ValueAccessName32-Bit Word Offset

24-bit FIFO filllevel. Bits 24 to 31are not used.

0Rfill_level0

Related Information


• Avalon Memory-Mapped Design Optimizations

Document Revision History

Table 10-70: Document Revision History

The table below indicates edits made to the Qsys System Design Components content since its creation.ChangesVersionDate

• AXI Bridge support.• Address Span Extender

updates.• Avalon-MM Unaligned Burst

Expansion Bridge support.

14.0.0June 2014

• Address Span Extender13.1.0November 2013

• Added Streaming PipelineStage support.

• Added AMBA APB support.

13.0.0May 2013

• Moved relevant content fromthe Embedded Peripherals IPUser Guide.

12.1.0November 2012

Related InformationQuartus II Handbook Archive


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http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf

http://www.altera.com/literature/lit-qts_archive.jsp


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