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RADIO FREQUENCY CIRCUITS FOR WIRELESS RECEIVER FRONT-ENDS
A Dissertation
by
CHUNYU XIN
Submitted to the Office of Graduate Studies ofTexas A&M University
in partial fulfillment of the requirements for the degree of
DOCTOR OF PHILOSOPHY
August 2004
Major Subject: Electrical Engineering
RADIO FREQUENCY CIRCUITS FOR WIRELESS RECEIVER FRONT-ENDS
A Dissertation
by
CHUNYU XIN
Submitted to Texas A&M Universityin partial fulfillment of the requirements
for the degree of
DOCTOR OF PHILOSOPHY
Approved as to style and content by:
Edgar Sanchez-Sinencio(Chair of Committee)
Jose Silva-Martınez(Member)
Aydin Ilker Karsilayan(Member)
Don R. Halverson(Member)
Eva Sevick-Muraca(Member)
Chanan Singh(Head of Department)
August 2004
Major Subject: Electrical Engineering
iii
ABSTRACT
Radio Frequency Circuits for Wireless Receiver Front-ends. (August 2004)
Chunyu Xin, B.S., Nankai University, China;
M.S., Nankai University, China
Chair of Advisory Committee: Dr. Edgar Sanchez-Sinencio
The beginning of the 21st century sees great development and demands on wireless
communication technologies. Wireless technologies, either based on a cable replace-
ment or on a networked environment, penetrate our daily life more rapidly than ever.
Low operational power, low cost, small form factor, and function diversity are the cru-
cial requirements for a successful wireless product. The receiver’s front-end circuits
play an important role in faithfully recovering the information transmitted through
the wireless channel.
Bluetooth is a short-range cable replacement wireless technology. A Bluetooth
receiver architecture was proposed and designed using a pure CMOS process. The
front-end of the receiver consists of a low noise amplifier (LNA) and mixer. The
intermediate frequency was chosen to be 2MHz to save battery power and alleviate
the low frequency noise problem. A conventional LNA architecture was used for
reliability. The mixer is a modified Gilbert-cell using the current bleeding technique
to further reduce the low frequency noise. The front-end draws 10 mA current from a
3 V power supply, has a 8.5 dB noise figure, and a voltage gain of 25 dB and -9 dBm
IIP3.
A front-end for dual-mode receiver is also designed to explore the capability of
a multi-standard application. The two standards are IEEE 802.11b and Bluetooth.
They work together making the wireless experience more exciting. The front-end is
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designed using BiCMOS technology and incorporating a direct conversion receiver
architecture. A number of circuit techniques are used in the front-end design to
achieve optimal results. It consumes 13.6 mA from a 2.5 V power supply with a
5.5 dB noise figure, 33 dB voltage gain and -13 dBm IIP3.
Besides the system level contributions, intensive studies were carried out on the
development of quality LNA circuits. Based on the multi-gated LNA structure, a
CMOS LNA structure using bipolar transistors to provide linearization is proposed.
This LNA configuration can achieve comparable linearity to its CMOS multi-gated
counterpart and work at a higher frequency with less power consumption. A LNA us-
ing an on-chip transformer source degeneration is proposed to realize input impedance
matching. The possibility of a dual-band cellular application is studied. Finally, a
study on ultra-wide band (UWB) LNA implementation is performed to explore the
possibility and capability of CMOS technology on the latest UWB standard for multi-
media applications.
v
To my parents, my beloved wife Jinding · · ·
vi
ACKNOWLEDGMENTS
Upon finishing my graduate study at Texas A&M University, I would like first to
give Dr. Edgar Sanchez-Sinencio my most sincere appreciation. As my advisor, he
has been the sole support for my research and study in the past several years. I
have benefited from his academic foresight and technical insight in research. His
great personality made my research experience more joyful and encouraging. I am
particularly grateful to him for his advice in the academic realm and also for my
professional career.
I would like to thank Dr. Jose Silva-Martınez for his advice on my course of study
and project questions. He was always available for questions and comments. I am
also grateful to Dr. Sherif Embabi. I was his teaching assistant for one semester and
really learned much from helping him with the class. His attitude toward work and
study gave me great encouragement. I also give thanks to Dr. Aydin Ilker Karsilayan.
He not only gave advice on my studies, but also supported me and the whole analog
and mixed signal center group by maintaining a great UNIX computing environment.
Some of the simple yet effective scripts he developed really made life a lot easier.
Most of my research time was spent on two major research projects, the Bluetooth
and Chameleon projects. The contribution and cooperation of the team members
made the learning and research study a great experience. Here I would like to thank
all of the team members, including Wenjun Sheng, Ahmed Emira, Bo Xia, Sung Tae
Moon, Ari Yakov Valero-Lopez, Alberto Valdes-Garcia, Ahmed Mohieldin and David
Hernandez-Garduno for the great team environment we created together. In these
two big projects, we learned from each other, tackled problems together and cheered
on each other. I felt the power of team work. I think this valuable experience will
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benefit my future professional career greatly.
Thanks should also be given to my committee members, Dr. Don R. Halverson
and Dr. Eva Sevick-Muraca, for their time and valuable comments on my research.
I would like to thank the secretary of our group, Ella Gallagher. Her enthusiasm,
warm sense of humor and positive attitude is a valuable asset for the group. I am
also indebted to all the other professors and students in the analog and mixed signal
center for their kind help and technical discussions.
Special thanks go to my parents for their love. Finally, I want to thank my dear
wife, Jingding Dou. I would not have been able to achieve this goal without her love
and support.
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TABLE OF CONTENTS
CHAPTER Page
I INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . 1
A. Research Motivation . . . . . . . . . . . . . . . . . . . . . 3
B. Dissertation Overview . . . . . . . . . . . . . . . . . . . . 3
II LOW NOISE AMPLIFIER DESIGN OVERVIEW . . . . . . . . 5
A. Basics on S-parameters . . . . . . . . . . . . . . . . . . . . 5
B. Amplifier’s Gain and Stability . . . . . . . . . . . . . . . . 9
C. Noise Performance . . . . . . . . . . . . . . . . . . . . . . 14
1. Two-Port Network Noise Model . . . . . . . . . . . . . 15
2. MOS Transistor Two-Port Noise Parameters . . . . . 21
3. Impact of LNA Gain and Noise Factor on System
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . 24
D. Large Signal Behavior . . . . . . . . . . . . . . . . . . . . 25
1. 1-dB Compression Point . . . . . . . . . . . . . . . . . 27
2. Intercept Point . . . . . . . . . . . . . . . . . . . . . . 28
3. Dynamic Range . . . . . . . . . . . . . . . . . . . . . 29
4. Wide-Band Non-Linearity . . . . . . . . . . . . . . . . 32
E. LNA Topologies in CMOS Technology . . . . . . . . . . . 36
F. Design Procedure of a Source Degenerated CMOS LNA . . 40
III MIXER DESIGN OVERVIEW AND AN IMPLEMENTA-
TION FOR LOW-IF BLUETOOTH RECEIVER . . . . . . . . 53
A. Mixer Mathematical Model . . . . . . . . . . . . . . . . . . 53
B. Mixer Metrics . . . . . . . . . . . . . . . . . . . . . . . . . 55
1. Conversion Gain or Loss . . . . . . . . . . . . . . . . . 56
2. Noise Figure . . . . . . . . . . . . . . . . . . . . . . . 56
3. Port-to-Port Isolation . . . . . . . . . . . . . . . . . . 59
4. Linearity Measurement . . . . . . . . . . . . . . . . . 60
C. Circuit Topologies of Mixers . . . . . . . . . . . . . . . . . 60
1. Diode Mixers . . . . . . . . . . . . . . . . . . . . . . . 61
2. Passive Mixer in CMOS Technology . . . . . . . . . . 62
3. Gilbert-cell Mixer . . . . . . . . . . . . . . . . . . . . 64
4. Sub-Sampling Mixer . . . . . . . . . . . . . . . . . . . 65
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CHAPTER Page
5. Harmonic Mixer . . . . . . . . . . . . . . . . . . . . . 66
D. Mixer Design for a Low-IF Bluetooth Receiver . . . . . . . 67
1. Low-IF Bluetooth Receiver Architecture . . . . . . . . 69
2. Implementation of the Down-Conversion Mixer . . . . 69
3. Layout Considerations and Simulation Results . . . . 74
4. Experimental Results of the Mixer Within the Receiver 77
IV BLUETOOTH/WI-FI DUAL-STANDARD RECEIVER RF
FRONT-END . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
A. Direct Conversion Bluetooth/Wi-Fi Dual-Standard Receiver 81
B. RF Front-End Design Considerations . . . . . . . . . . . . 83
C. Circuits Implementations . . . . . . . . . . . . . . . . . . . 86
1. LNA Implementation . . . . . . . . . . . . . . . . . . 87
2. Mixer Implementation . . . . . . . . . . . . . . . . . . 97
3. PTAT Biasing Circuit . . . . . . . . . . . . . . . . . . 100
D. Layout and Experimental Results . . . . . . . . . . . . . . 103
V LNA LINEARIZATION TECHNIQUES . . . . . . . . . . . . . 111
A. Non-Linearity Analysis . . . . . . . . . . . . . . . . . . . . 112
1. Non-Linear System Representations . . . . . . . . . . 112
2. Non-Linearity of Fully Differential Circuits . . . . . . 115
3. IM3 Due to 5th-Order and 2nd-Order Non-Linearity . 116
4. Non-Linearity Due to Output Impedance . . . . . . . 118
5. Third-Order Distortion of Inductive Source-Degenerated
LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
B. Theoretical Analysis of Multi-Gated Linearization Technique 126
C. Proposed Linearization Scheme Using BJTs in CMOS
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
1. Hybrid LNA: BJT as Auxiliary Transistor . . . . . . . 133
2. Volterra Analysis of Resistive-Degenerated BJT . . . . 135
3. Input Matching and Noise Contributions . . . . . . . . 138
4. Sensitivity to Bias Condition, Process Corners and
Temperature . . . . . . . . . . . . . . . . . . . . . . . 141
5. The Differential Configuration . . . . . . . . . . . . . 145
D. Measurement Results and Comparisons . . . . . . . . . . . 149
VI A MUTUAL-COUPLED DEGENERATED LNA AND ITS
EXTENSION TO CONCURRENT DUAL-BAND OPERATION 155
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CHAPTER Page
A. Principle of Impedance Match Using Mutual Inductance . 156
1. Input Impedance . . . . . . . . . . . . . . . . . . . . . 157
2. Interstage Impedance . . . . . . . . . . . . . . . . . . 160
3. Effective Transconductance . . . . . . . . . . . . . . . 162
4. Noise Analysis . . . . . . . . . . . . . . . . . . . . . . 163
B. Chip Measurement Results of the Mutual-Coupled De-
generated LNA . . . . . . . . . . . . . . . . . . . . . . . . 167
C. A Dual-Band Inductive Coupled LNA . . . . . . . . . . . . 168
D. Simulation Results of the Dual-band LNA . . . . . . . . . 171
VII FRONT-END CIRCUITS FOR WIDE-BAND APPLICATION . 175
A. Introduction to Ultra-Wide Band System . . . . . . . . . . 175
B. Distributed RF Front-End Circuits . . . . . . . . . . . . . 178
1. Transmission Line Properties and Characterization . . 178
2. Transmission Lines on Silicon Substrate . . . . . . . . 183
3. Distributed Amplifier as LNA . . . . . . . . . . . . . . 187
4. Analysis of Distributed Mixer . . . . . . . . . . . . . . 198
C. Wide-Band Impedance Match Using Lumped Components 201
1. Impedance Matching Procedure Using Lumped Com-
ponents . . . . . . . . . . . . . . . . . . . . . . . . . . 202
2. Wide-Band LNA with Lumped-Matched Network . . . 205
VIII SUMMARY AND CONCLUSION . . . . . . . . . . . . . . . . . 207
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
APPENDIX A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
APPENDIX B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
VITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
xi
LIST OF TABLES
TABLE Page
I Important equations for RF amplifier’s gain, stability and noise . . . 26
II Equations related to non-linearity . . . . . . . . . . . . . . . . . . . 35
III Popular CMOS LNA architectures . . . . . . . . . . . . . . . . . . . 41
IV Calculated and simulated design parameters . . . . . . . . . . . . . . 51
V Targeted specifications and simulated performance . . . . . . . . . . 51
VI Mixer specifications for low-IF Bluetooth receiver . . . . . . . . . . . 69
VII Bluetooth mixer simulation results . . . . . . . . . . . . . . . . . . . 77
VIII Bluetooth and Wi-Fi standards key features . . . . . . . . . . . . . . 81
IX Block specifications for the BT/Wi-Fi RF front-end . . . . . . . . . . 87
X Chameleon LNA simulation results . . . . . . . . . . . . . . . . . . . 96
XI Chameleon Mixer simulation results . . . . . . . . . . . . . . . . . . 99
XII RF front-end nominal biasing condition . . . . . . . . . . . . . . . . 102
XIII RF front-end measurement results . . . . . . . . . . . . . . . . . . . 110
XIV Device noise contribution ratios of single-ended hybrid LNA (†signal generator’s internal resistance) . . . . . . . . . . . . . . . . . . 141
XV fT of a 2× 2 NPN transistor . . . . . . . . . . . . . . . . . . . . . . 142
XVI Noise contribution ratios of differential configuration († signal gen-erator’s internal resistance) . . . . . . . . . . . . . . . . . . . . . . . 149
XVII Comparison of the proposed linearization implementation with
the state-of-the-art linear LNA’s in the literature . . . . . . . . . . . 153
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TABLE Page
XVIII Reported LNA performance for GSM applications . . . . . . . . . . 169
XIX Reported LNA performance in for cellular applications († indi-
cates the value is for the whole front-end) . . . . . . . . . . . . . . . 172
XX Basic properties of lossless and low loss T-line . . . . . . . . . . . . 182
XXI Simulation results of lumped-matched wide-band LNA . . . . . . . . 206
XXII Volterra series versus Taylor series . . . . . . . . . . . . . . . . . . . 231
XXIII Volterra kernels of degenerated BJT . . . . . . . . . . . . . . . . . . 235
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LIST OF FIGURES
FIGURE Page
1 A receiver RF front-end . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Two-port network showing incident waves (a1, a2) and reflected
waves (b1, b2) used in S-parameter definiations . . . . . . . . . . . . . 7
3 Single-stage RF amplifier block diagram . . . . . . . . . . . . . . . . 9
4 Noisy two-port network representations: (a) z-parameters, (b) y-
parameters and (c) ABCD-parameters . . . . . . . . . . . . . . . . . 15
5 Noise factor calculation . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 MOS transistor thermal noise model (a) gate and drain noise
sources (b) input-referred noise sources . . . . . . . . . . . . . . . . 21
7 (a) In-band blockers generate in-channel intermodulation term (b)
The two-tone test spectrum . . . . . . . . . . . . . . . . . . . . . . . 28
8 1-dB compression point . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Meaning of IP2 and IP3 . . . . . . . . . . . . . . . . . . . . . . . . . 30
10 (a) SFDR defination (b) Relationship between SFDR and IIP3 . . . 31
11 Compression-free dynamic range . . . . . . . . . . . . . . . . . . . . 32
12 Triple-order beats . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
13 Popular single-ended CMOS LNA topologies (a) Resistive termi-
nation (b) Common gate (c) Shunt-series feedback (d) Inductive
source-degeneration (e) Current-reuse (f) Cgd neutralization . . . . . 37
14 Inductive source degenerated LNA . . . . . . . . . . . . . . . . . . . 42
15 Flow chart of LNA design procedure . . . . . . . . . . . . . . . . . . 43
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FIGURE Page
16 α, Vgs − Vth, gm/W , and gdo/W versus drain current density . . . . . 44
17 Cgs/W and fT versus gate over drive voltage Vgs − Vth . . . . . . . . 45
18 Noise factor scaling coefficient versus quality and current density
for 0.18µm NMOS device (a) 3-D plot (b) 2-D plot . . . . . . . . . . 47
19 IIP3 versus gate overdrive and device size . . . . . . . . . . . . . . . 48
20 Simulation plots of the designed LNA (a) Voltage gain, S11 and
noise figure (b) IIP3 and P1dB . . . . . . . . . . . . . . . . . . . . . . 52
21 Mixers perform frequency translation in communication system . . . 54
22 Mixer mathematical model . . . . . . . . . . . . . . . . . . . . . . . 54
23 Mixing process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
24 Double-side band conversion . . . . . . . . . . . . . . . . . . . . . . . 57
25 Single-side band conversion . . . . . . . . . . . . . . . . . . . . . . . 58
26 Single-side band conversion with image rejection . . . . . . . . . . . 58
27 LO-to-RF leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
28 Single-diode mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
29 Single-balanced diode mixer . . . . . . . . . . . . . . . . . . . . . . . 62
30 Double-balanced diode mixer . . . . . . . . . . . . . . . . . . . . . . 62
31 CMOS passive double-balanced mixer . . . . . . . . . . . . . . . . . 63
32 Gilbert-cell mixer (a) transistor implementation (b) working prin-
ciple and (c) single-ended version . . . . . . . . . . . . . . . . . . . . 64
33 Sub-sampling mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
34 Harmonic mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
35 The proposed low-IF Bluetooth receiver . . . . . . . . . . . . . . . . 70
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FIGURE Page
36 Bluetooth receiver down-conversion mixer . . . . . . . . . . . . . . . 71
37 Mixer design flow chart . . . . . . . . . . . . . . . . . . . . . . . . . 75
38 Layout of the down-conversion mixers . . . . . . . . . . . . . . . . . 76
39 Die photo of Bluetooth receiver . . . . . . . . . . . . . . . . . . . . . 78
40 Input return loss of the Bluetooth front-end . . . . . . . . . . . . . . 79
41 Measured IIP3 of the Bluetooth receiver . . . . . . . . . . . . . . . . 79
42 Bluetooth/Wi-Fi receiver . . . . . . . . . . . . . . . . . . . . . . . . 83
43 Differential LNA common mode stability . . . . . . . . . . . . . . . . 85
44 RF front-end block diagram of BT/Wi-Fi Receiver . . . . . . . . . . 86
45 LNA for BT/Wi-Fi receiver . . . . . . . . . . . . . . . . . . . . . . . 88
46 Noise optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
47 LNA layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
48 Coupling factor between two shifted spirals . . . . . . . . . . . . . . 95
49 Mixer for BT/Wi-Fi receiver . . . . . . . . . . . . . . . . . . . . . . 97
50 Waveforms at switching pair common emitters . . . . . . . . . . . . 98
51 Mixer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
52 Bias circuit for the RF front-end . . . . . . . . . . . . . . . . . . . . 101
53 Die photo of the front-end . . . . . . . . . . . . . . . . . . . . . . . . 103
54 Substrate noise isolation by deep trenches and guard rings . . . . . . 103
55 RF front-end test board . . . . . . . . . . . . . . . . . . . . . . . . . 104
56 Testing setup for input match . . . . . . . . . . . . . . . . . . . . . . 105
57 Input matching for high gain mode . . . . . . . . . . . . . . . . . . . 105
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FIGURE Page
58 Input matching for low gain mode . . . . . . . . . . . . . . . . . . . 106
59 Testing setup for IIP3 and IIP2 measurement . . . . . . . . . . . . . 107
60 IIP3 plot for 2-tone test at 12MHz and 25MHz offset . . . . . . . . . 107
61 IIP2 plot for 2-tone test at 12.2MHz and 12.8MHz offset . . . . . . . 108
62 I/Q mismatch measurement . . . . . . . . . . . . . . . . . . . . . . . 108
63 I-Q mismatch performance . . . . . . . . . . . . . . . . . . . . . . . 109
64 Testing setup for noise figure and conversion gain . . . . . . . . . . . 110
65 Frequency components in two-tone test . . . . . . . . . . . . . . . . . 114
66 Second-order distortion contributing to IM3 terms . . . . . . . . . . 118
67 Load non-linearity large signal model . . . . . . . . . . . . . . . . . . 120
68 Inductive degenerated CMOS LNA . . . . . . . . . . . . . . . . . . . 123
69 MOS transistor 2nd-order and 3rd-order distortion terms . . . . . . . 129
70 Multi-gated linearization using two NMOS transistors . . . . . . . . 130
71 NMOS multi-gated transistor linearity v.s. auxiliary bias voltage . . 130
72 Multi-gated linearization using NMOS and PMOS . . . . . . . . . . 131
73 Complementary multi-gated transistor linearity plot . . . . . . . . . 131
74 Bipolar as auxiliary transistor for 3rd-order linearization . . . . . . . 134
75 Emitter-degenerated BJT large signal model . . . . . . . . . . . . . . 135
76 Resistive-degenerated BJT 3rd-order coefficient at DC and 3GHz . . 138
77 3rd-order terms of the BJT, NMOS and their combination . . . . . . 139
78 Small signal circuit for input impedance calculation . . . . . . . . . . 140
79 Effect of bipolar transistor on input matching . . . . . . . . . . . . . 140
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FIGURE Page
80 IIP3 of NMOS-NPN combination vs. bias conditions . . . . . . . . . 143
81 IIP3 against process corners . . . . . . . . . . . . . . . . . . . . . . . 143
82 IIP3 temperature behavior . . . . . . . . . . . . . . . . . . . . . . . . 144
83 NPN transistor optimal biasing profile . . . . . . . . . . . . . . . . . 144
84 Mixer design flow chart . . . . . . . . . . . . . . . . . . . . . . . . . 146
85 Linearized differential LNA using bipolar differential pair . . . . . . . 147
86 (a) 2nd-order input range expansion and (b) 3rd-order cancella-
tion of the proposed differential LNA . . . . . . . . . . . . . . . . . . 148
87 Die photomicrographs of hybrid linearized LNA’s (a) single-ended
(b) differential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
88 IIP3 of the single-ended bipolar linearized LNA . . . . . . . . . . . . 151
89 Linearized single-ended LNA S-parameters . . . . . . . . . . . . . . . 151
90 IIP3 of differential LNA with and without bipolar cancellation
pair activated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
91 Linearized differential LNA S-parameters . . . . . . . . . . . . . . . . 152
92 Mobile station receiver band . . . . . . . . . . . . . . . . . . . . . . . 156
93 Matching utilizing mutual inductance . . . . . . . . . . . . . . . . . . 157
94 Input impedance small signal circuit . . . . . . . . . . . . . . . . . . 158
95 Inter-stage impedance . . . . . . . . . . . . . . . . . . . . . . . . . . 160
96 Overall transconductance . . . . . . . . . . . . . . . . . . . . . . . . 162
97 Equivalent input noise sources of the inductive coupled LNA . . . . . 163
98 The proposed mutual-coupled degenerated LNA . . . . . . . . . . . . 165
99 Design flow of the mutual-coupled LNA . . . . . . . . . . . . . . . . 166
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FIGURE Page
100 Die microphotograph of the mutual-coupled degenerated LNA . . . . 167
101 Measured small signal performance of the mutual-coupled degen-
erated LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
102 Measured IIP3 of the mutual-coupled degenerated LNA . . . . . . . 169
103 Dual-band inductive coupled LNA (bias not shown) . . . . . . . . . . 171
104 Simulated small signal performance of the dual-band LNA (a) S11
and S21 (b) noise figure and minimum noise figure . . . . . . . . . . 173
105 Simulated IIP3 of the dual-band LNA (a) GSM-900 (b) DCS-1800 . . 174
106 UWB signal spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . 176
107 Direct conversion UWB receiver . . . . . . . . . . . . . . . . . . . . 177
108 Distributed model of transmission line . . . . . . . . . . . . . . . . . 179
109 Coplanar stripline formed by metal 6 (dimensional drawing) . . . . . 184
110 Coplanar stripline rendered by HFSS . . . . . . . . . . . . . . . . . . 185
111 Coplanar stripline operation mode (a) Even mode (b) Odd mode . . 185
112 Micro-stripline HFSS render . . . . . . . . . . . . . . . . . . . . . . . 186
113 Field distribution of micro-stripline . . . . . . . . . . . . . . . . . . . 187
114 Zc of (a) coplanar stripline and (b) micro-stripline at 30 GHz . . . . 188
115 Schematic representation of a distributed LNA . . . . . . . . . . . . 189
116 Unit section of a distributed LNA . . . . . . . . . . . . . . . . . . . . 190
117 Layout of the five-section distributed LNA . . . . . . . . . . . . . . 192
118 S-parameters of the five-section distributed LNA . . . . . . . . . . . 192
119 Noise figure of the five-section distributed LNA . . . . . . . . . . . . 193
120 Noise model of a distributed LNA unit section . . . . . . . . . . . . 194
xix
FIGURE Page
121 A distributed mixer block diagram . . . . . . . . . . . . . . . . . . . 199
122 Wide band matching procedure using lumped components . . . . . . 203
123 Wide-band LNA with lumped-matched network . . . . . . . . . . . 205
124 Wide-band LNA S-parameters and noise figure . . . . . . . . . . . . 206
125 Circuit model of a non-linear time-invariant system . . . . . . . . . . 225
126 Second and third order response block diagrams . . . . . . . . . . . . 226
127 A MOS differential pair for Volterra analysis . . . . . . . . . . . . . . 227
1
CHAPTER I
INTRODUCTION
It is generally known that a typical receiver consists of two major parts: i) the RF
front-end, which performs small signal amplification and frequency down conversion,
and ii) a base-band portion, which performs demodulation and generates the required
digital control to the system. Although there is no specific definition for the RF front-
end, it usually includes a low noise amplifier (LNA), image rejection filter (IRF), down
conversion mixer, local oscillator (LO), frequency synthesizer, intermediate frequency
(IF) filter, and other IF amplifiers. Another understanding of the RF front-end is
that it only ends at the mixer. Fig. 1 is the block diagram of a super-heterodyne
receiver RF front-end. The functions of each block is elaborated below.
BPF LNA IRF FrequencySynthesizer
Mixer
LPF
DSPADC
VGA
Fig. 1. A receiver RF front-end
The LNA is a very important block of the whole receiver. It interfaces directly
with the antenna (usually there is a passive RF band-pass filter between the antenna
and the LNA, the function of this filter is to provide band selection). The LNA
must be able to provide enough power amplification and introduce small additional
The style and format follow IEEE Journal of Solid-State Circuits.
2
amounts of noise to the system. It also should be linear enough to tolerate high power
level interferences coming from the wireless channel.
For a heterodyne receiver, the image rejection filter follows the LNA to remove
the image frequency component from the band. The image of the signal resides on the
other side of the local oscillator frequency, if not removed or attenuated somehow,
it will fold into the IF band with the signal, and degrade the signal to noise and
distortion ratio. For a zero-IF receiver architecture, there is no image problem, so
the image rejection filter is not needed. For a low-IF receiver, which usually has a
relatively low intermediate frequency (several MHz), the image is rejected after the
mixer by using complex filtering.
It is usually difficult and uneconomical to process the received signal directly
at RF frequencies (several hundred MHz to several GHz), so the mixer is another
important block in the receiver. It converts the signal from a high frequency to a low
frequency to make the signal process easier and more effective. Because the mixer
operates among three frequencies (RF, LO and IF), it must be able to provide enough
isolation between them, deliver enough conversion gain, and keep reasonable dynamic
range.
The local oscillator and frequency synthesizer provide a stable and clean pro-
grammable LO signal to the mixer for channel selection. The IF filters and amplifiers
are used to further filter out the unwanted signal, and provide the proper signal level
to the base-band analog-to-digital converter (ADC). The IF amplifier is usually a
variable gain amplifier (VGA), adjusting its gain according to the received signal
strength such that the ADC always sees the optimum input signal level.
3
A. Research Motivation
The rapid development in the wireless technology introduces new design issues and
challenges, such as the low power consumption, high speed, low cost, small form factor
and multi-standard programmability. This work is focused on the design of front-end
circuits: LNA and mixer for both narrow band and broad band applications. The
LNA and mixer are the two blocks in the signal path operating at the highest signal
frequency. They see all the interferences and noise coming from the wireless channel.
The quality of the front-end circuits directly affect the performance of the whole
system. The challenge of LNA design is to implement it by meeting the voltage gain,
noise, linearity, silicon area and power consumption at the same time. The mixer
design in low-IF and direction conversion architecture requires mainly low noise and
high linearity. Also the non-linear switching behavior of mixer’s current commutating
pair make the design of mixer more difficult. The emphasis will be put on the system
integration of the LNA and mixer in Bluetooth and IEEE 802.11b receivers, LNA
linearization technique using bipolar transistor, LNA input matching network design
using on-chip transformer and possible wide-band LNA implementations. The next
section gives a more detailed overview of the organization of the dissertation.
B. Dissertation Overview
The whole dissertation is organized as follows. Chapter I discusses the research mo-
tivations, and the outline skeleton of the work. In Chapter II and Chapter III, an
overview of the LNA and mixer design issues and techniques will be given. Based on
the current bleeding/injection technique, the later sections of Chapter III introduces
a mixer implementation for a low-IF Bluetooth receiver. Chapter IV is dedicated to
the RF front-end implementation of a direct conversion Bluetooth/WiFi dual-mode
4
receiver. The LNA and mixer design trade-offs and considerations are elaborated
in this chapter. Chapter V and Chapter VI give novel LNA design techniques for
linearity and multi-band operation respectively. Ultra-wide band implementations of
front-end blocks is tackled in Chapter VII. Chapter VIII concludes the work of this
dissertation.
5
CHAPTER II
LOW NOISE AMPLIFIER DESIGN OVERVIEW
Low noise amplifier (LNA) is the first gain stage encountered in a receiver environ-
ment either wired or wireless. It must meet several specifications at the same time,
which make its design really challenging. Signal coming from the receiver antenna
is very small, usually from -100 dBm (3.2 µV ) to -70 dBm (0.1 mV )1, therefore sig-
nal amplification is needed for the following stage (mixer) to handle. This sets the
requirement of a certain gain to the LNA. The received signal should have a certain
signal-to-noise ratio (SNR) in order to be reliably detected, therefore, noise added by
the circuit should be reduced as much as possible, which will set the noise requirement
of the LNA. Large signal or blocker can occur at the input of LNA. The circuits should
be sufficiently linear in order to have a reasonable signal reception. For portable and
mobile applications, reasonable power consumption is another constraint.
A. Basics on S-parameters
In design and analysis, scattering parameters, which are commonly referred to as
S-parameters, are widely used in microwave and RF circuits. S-parameters use a
parameter set that relates to the traveling waves that are scattered or reflected when
an n-port network is inserted into a transmission line. S-parameter analysis is basi-
1The unit dBm is a power unit referred to 1 mW in dB scale. If a signal’s poweris P Watt, then in dBm, it is 10 log (P/1mV) dBm. When related to a voltage, thereis a reference impedance R involved. This impedance is usually 50Ω. When we say0.1 mV is corresponding to -70 dBm, what we mean is that the power dissipated intoa 50Ω resistor by a sinusoidal voltage signal which has a peak value of 0.1 mV is 10−7
mW, and corresponds to -70 dBm.
6
cally a modeling method to characterize an n-port linear network. There are other
methods to characterize the network, such as H-parameters, Y-parameters and Z-
parameters. All of them fall into the same modeling category for a network together
with S-parameters. They are behavioral modeling methods. The network or device is
treated as a black box, only the interaction between the ports and outer environment
is modeled.
For low frequencies, H-, Y-, or Z-parameters are more widely used. They use port
voltage and current as variables. But when the frequency moves higher and higher,
some problems arise. A bottleneck requirement for H, Y or Z measurement is to apply
short and/or open circuit condition at each port. This can be hard to do, especially at
RF frequencies where lead inductance and capacitance make short and open circuits
difficult to obtain. Active devices, such as transistors and tunnel diode, very often
can not be connected in stable short or open circuit conditions. S-parameters, on the
other hand, are usually measured with the device imbedded between a 50Ω load and
source, and there is very little chance for oscillations to occur. Another important
advantage of S-parameters stems from the fact that traveling waves, unlike terminal
voltages and currents, do not vary in magnitude at points along a lossless transmission
line. This means that scattering parameters can be measured on a device located at
some distance from the measurement transducers, provided that the measuring device
and the transducers are connected by low-loss transmission lines.
The linear equations describing the behavior of the two-port network in Fig. 2
using S-parameters are
b1 = s11a1 + s12a2 (2.1)
b2 = s21a1 + s22a2 (2.2)
where b1, b2, a1 and a2 are traveling waves and have dimensions of√Watts. The
7
LinearTwo-PortNetwork
ZS
VS ZLV1
I1
V2
I2+
-
+
-a1b1
a2b2
Fig. 2. Two-port network showing incident waves (a1, a2) and reflected waves (b1, b2)
used in S-parameter definiations
S-parameters s11, s22, s21 and s12 are defined by:
s11 =b1a1
∣
∣
∣
∣
a2=0
(2.3)
s22 =b2a2
∣
∣
∣
∣
a1=0
(2.4)
s21 =b2a1
∣
∣
∣
∣
a2=0
(2.5)
s12 =b1a2
∣
∣
∣
∣
a1=0
(2.6)
For most measurements and calculations, it is convenient to assume the port
reference impedances are positive and real. The two ports can have different reference
impedances, but the same reference impedance Z0 will the used for all the ports here.
The independent variables a1 and a2 can be related to port voltages (V1, V2) and
currents (I1, I2) as follows:
a1 =V1 + I1Z0
2√Z0
=Vi1√Z0
(2.7)
a2 =V2 + I2Z0
2√Z0
=Vi2√Z0
(2.8)
where Vi1 =V1+I1Z0
2and Vi2 =
V2+I2Z0
2are the voltage waves incident on port 1 and
port 2 respectively. Therefore, |a1|2 is the power incident on the input of the network,
8
and is also the power available from a source impedance Z0. |a2|2 is the power incident
on the output of the network, and is also the power reflected from the load.
Similarly, the dependent variables b1 and b2 can be related to port voltages and
currents as follows:
b1 =V1 − I1Z02√Z0
=Vr1√Z0
(2.9)
b2 =V2 − I2Z02√Z0
=Vr2√Z0
(2.10)
where Vr1 = V1−I1Z0
2and Vr2 = V2−I2Z0
2are the voltage waves reflected from port 1
and port 2 respectively. Therefore, |b1|2 is the power reflected from the input port
of the network, or the power available from a Z0 source minus the power delivered
to the input of the network. |b2|2 is the power reflected from the output port of the
network, or the power incident on the load, which is also the power that would be
delivered to a Z0 load.
From the above explanation of a1, a2 and b1, b2, the four S-parameters are simply
related to power gain and mismatch loss:
|s11|2 =Power reflected from the network input
Power incident on the network input(2.11)
|s22|2 =Power reflected from the network output
Power incident on the network output(2.12)
|s21|2 = Power delivered to Z0 loadPower available from Z0 source
= Transducer power gain with Z0 load and source(2.13)
|s12|2 = Reverse transducer power gain with Z0 load and source (2.14)
It needs to be noticed that all of these two-port parameters are equivalent, be-
cause they describe the same network property. However, for all the practical pur-
poses, S-parameters are easier for the LNA design and characterization, while under
certain scenarios, Y-, H-, or Z-parameters maybe more straightforward. Observe that
9
not all the networks (e.g. ideal transformer, a serials impedance or a shunt admit-
tance) have Y- or Z-parameters, but they will have S-parameter characterization.
B. Amplifier’s Gain and Stability
Gain performance for a RF amplifier is determined by the RF transistor itself and the
input/output matching network. Fig. 3 shows a single-stage amplifier block diagram.
The amplifier is characterized by its S-parameters and terminated by arbitrary source
and load impedance Zs and ZL. s11 and s22 are the input and output reflection coeffi-
cients with Z0 source and load termination. For an arbitrary impedance termination,
the input and output reflection coefficient Γin and Γout for a two-port network [1] can
be found to be
Γin =b1a1
= s11 +s12s21ΓL1− s22ΓL
(2.15)
Γout =b2a2
= s22 +s12s21Γs1− s11Γs
(2.16)
where Γs = Zs−Z0
Zs+Z0and ΓL = ZL−Z0
ZL+Z0are the source and load reflection coefficient
respectively.
ZC InputMatchand
FilteringNetwork
ZinRF Amplifier
[S]
Γs ΓoutΓin Γ L
OutputMatchand
FilteringNetwork
Load or2ndStage
PL
Zout
a1b1
a2b2
Vs
Vo
V1
+_ V2
+_
Fig. 3. Single-stage RF amplifier block diagram
If the input and output are simultaneously complex conjugate matched, i.e. Γin =
10
Γ∗s and Γout = Γ∗
L, the amplifier has maximum power transfer. Usually it is not easy
to achieve the simultaneous complex conjugate matching condition. A special case is
for an unilateral device, s12 is practically zero, then Γin = s11 and Γout = s22. The
input and output are decoupled from each other, matching can be done at the input
and output separately.
Several gain definitions exist for an amplifier. Power gain (G) characterizes the
actual power amplification of an amplifier. It is defined as the power delivered to the
load divided by the power input to the network. Available power gain (GA) shows
the maximum possible power amplification of the amplifier. For IC implementations,
LNA input is interfaced off-chip and usually matched to specific impedance (50Ω or
75Ω). Its output is not necessarily matched if directly driving on-chip blocks such as
mixers. This situation is usually characterized by voltage gain or transducer power
gain by knowing the load impedance level.
The voltage gain (AV ) is defined as the voltage at the output port divided by
the voltage at the input port of the amplifier. Relating to the s-parameters of the
amplifier
AV =V2V1
=s21 (1 + ΓL)
(1− s22ΓL) (1 + Γin)(2.17)
The transducer power (GT ) [1] is defined as the power delivered to the load
divided by the power available from the source:
GT =PLPAV S
(2.18)
where PL equals the power incident on load minus the power reflected from load:
PL = |b2|2(
1− |ΓL|2)
(2.19)
11
and PAV S is
PAV S =|bs|2
1− |Γs|2(2.20)
where bs =Vs
√Z0
ZS+Z0. Therefore
GT =
∣
∣
∣
∣
b2bs
∣
∣
∣
∣
2(
1− |Γs|2) (
1− |ΓL|2)
(2.21)
Using the signal flow chart, the ratio b2bs
can be found to be
b2bs
=s21
(1− s11Γs) (1− s22ΓL)− s12s21ΓsΓL(2.22)
Finally, the transducer power gain expression is
GT =|s21|2
(
1− |Γs|2) (
1− |ΓL|2)
|(1− s11Γs) (1− s22ΓL)− s12s21ΓsΓL|2(2.23)
By using cascode or neutralization technique, a network can be treated as uni-
lateral, i.e., s12 is small and effectively zero, (2.23) will be reduced to
GTu = GT |s12=0 = 1−|Γs|2|1−s11Γs|2
|s21|2 1−|ΓL|2|1−s22ΓL|2
= GS |s21|2GL
(2.24)
where GS and GL are the source and load mismatch factor respectively:
GS =1− |Γs|2
|1− s11Γs|2(2.25)
GL =1− |ΓL|2
|1− s22ΓL|2(2.26)
Once the device and its bias condition is established, s21 remains unchanged. GS is
only related to the input parameters s11 and Γs. GS shows the degree of mismatch
between the source impedance and the input impedance. Similarly,ML is only related
to the output parameters s22 and ΓL and shows the matching condition at the output.
When Γs equals s11’s complex conjugate s∗11, GS reaches its maximum value of
12
GS,max = 11−|s11|2
. This can be verified by writing s11 = a + jb and Γs = x + jy,
substituting them into (2.25) and solve equations ∂GS∂x
= 0 and ∂GS∂y
= 0 for x and y.
The same result can be obtain for ΓL: when ΓL = s∗22, GL reaches its maximum value
of GL,max = 11−|s22|2
.
It is also easy to see that when |Γs| = 1, GS has a minimum value of zero and
when|ΓL| = 1, GL has a minimum value of zero. For other values of GS or GL, the
corresponding Γs or ΓL lie on a circle in the Smith Chart. Different values of GS or
GL have different circles. These circles are usually referred to as constant gain circles.
They have their centers located on the line drawn from the center of the Smith Chart
to the point of s∗11 or s∗22. Specifically, the center of the circles resides at
ci =gis
∗ii
1− |sii|2 (1− gi)(2.27)
and the radius of the circles is
ri =
√1− gi
(
1− |sii|2)
1− |sii|2 (1− gi)(2.28)
where gi = Gi
(
1− |sii|2)
= GiGi,max
is the normalized gain value for the gain circle
Gi. The subscript i represents S for input and L for output, ii represents 11 for
input and 22 for output. The detailed proof of the constant gain circle is given in
Appendix A.
The stability of RF amplifiers is also a very important metric. Only when the
amplifier is stable, the other metrics such as gain, noise figure are meaningful. Suppose
the input impedance at the input port of the amplifier is Zi = Ri + jXi, then the
input reflection coefficient module is
|Γin| =∣
∣
∣
∣
Zi − Z0Zi + Z0
∣
∣
∣
∣
=
√
(Ri − Z0)2 +X2i
(Ri + Z0)2 +X2
i
(2.29)
From (2.29) it is easy to see that if the real part of the input impedance is negative,
13
i.e. if Ri < 0, then |Γin| > 1. If this negative impedance compensates the loss
coming from the input termination network, oscillation can occur. The amplifier is
potentially unstable. The same argument holds for the output. If for all the passive
terminations at the input and output, the following conditions hold, then the amplifier
is unconditionally stable. Otherwise, it is potentially unstable or conditionally stable.
|Γin| < 1; |Γout| < 1 (2.30)
A meaning for (2.30) is that the real parts of input and output impedance of the
amplifier are resistive, or, in Smith Chart, Γin and Γout will never go out of the unity
circle.
It can be shown that the conditions for unconditionally stable [1] in term of
s-parameters are
|s11| < 1
|s22| < 1
K > 1
(2.31)
where K is the stability factor given by
K =1− |s11|2 − |s22|2 + |s11s22 − s12s21|2
2 |s12s21|(2.32)
For example, an amplifier has the following S-parameters at 1250 MHz:
s11 = 0.38∠− 115, s12 = 0.06∠14, s21 = 6.0∠104, s22 = 0.50∠− 52 (2.33)
It can be calculated from the above data that |s11| = 0.38 < 1, |s22| = 0.5 < 1, and
K = 1.02 > 1. So the amplifier is unconditionally stable. While at 750 MHz, the
same amplifier has the following S-parameter:
s11 = 0.56∠− 78, s12 = 0.05∠33, s21 = 8.6∠122, s22 = 0.66∠− 42 (2.34)
14
In this case, |s11| = 0.56 < 1, |s22| = 0.66 < 1, but K = 0.60 < 1, So it is potentially
unstable.
In order to stabilize an active device, one simple way is to add a series resistance
or a shunt conductance to the unstable port. For example, the input port of the
amplifier at 750 MHz mentioned above can be stabilized by series a 16.5Ω resistor or
shunt a 17.8Ω resistor. Its output port can be stabilized with a 40Ω series resistor or
a 161Ω shunt resistor. In practise, due to the coupling between the input and output
ports of the amplifier, it is usually sufficient to just stabilize one of the ports, and
one should avoid resistive loading of the input port, because it will cause additional
noise to be amplified. Therefore, one will generally try to stabilize the output port.
The prices paid for stabilizing using resistive loading are poor impedance matching,
reduced power gain, and larger noise figure.
C. Noise Performance
The noise performance of a RF amplifier is represented by its noise factor or noise
figure. Noise factor shows the degradation of signal’s signal-to-noise-ratio (SNR) due
to the amplifier, it is defined as the SNR at the input of the network divided by the
SNR at the output of the network:
F =SNRin
SNRout
(2.35)
where SNRin and SNRout are the SNR at the input and output of the amplifier
respectively. The represent the signal’s quality in terms of noise before and after the
network. Noise figure is just the logarithm form of noise factor, its unit is dB:
NF (dB) = 10 logF (2.36)
15
1. Two-Port Network Noise Model
It will be pretty involved if one tries to use a transistor’s equivalent noise circuit to
analysis the whole amplifier or network. Using a two-port network noise model can
simplify the calculation of its noise factor and also gain insight on minimize noise
figure [2].
An effective way to analyze noise in a given circuit is to assume that the circuit
is noiseless and model its internal noise by external noise sources at the input and
output ports. These noise sources must have the same noise power appearing at the
circuit’s terminals as the original noisy circuit.
The noiseless network can be represented by its Z-, Y- or ABCD-parameters as
shown in Fig. 4. In the following discussions, it is assumed that port 1 is the input
port and port 2 is the output port.
NoiselessNetworkV1
i1 Vn1
V2
i2Vn2
(a)
NoiselessNetworkV1
i1
in1 V2
i2
in2
(b)
NoiselessNetworkV1
i1
V2
i2
(c)
in
Vn
Fig. 4. Noisy two-port network representations: (a) z-parameters, (b) y-parameters
and (c) ABCD-parameters
16
Using the Z-parameters in Fig. 4(a), the voltage-current relationship among ports
can be written as
v1 = z11i1 + z12i2 + vn1 (2.37)
v2 = z21i1 + z22i2 + vn2 (2.38)
The equivalent noise source vn1 and vn2 can be measured from the open-circuited
(o.c) measurements as
vn1 = v1 |i1=i2=0 (2.39)
vn2 = v2 |i1=i2=0 (2.40)
Using the Y-parameters in Fig. 4(b), the voltage-current relationship among ports
can be written as
i1 = y11v1 + y12v2 + in1 (2.41)
i2 = y21v1 + y22v2 + in2 (2.42)
The equivalent noise source in1 and in2 can be obtained from the short-circuited (s.c.)
measurements as
in1 = i1 |v1=v2=0 (2.43)
in2 = i2 |v1=v2=0 (2.44)
Referring the noise sources to the input port is convenient for noise analysis.
This leads to the ABCD-parameter representation in Fig. 4(c),
v1 = Av2 +B (−i2) + vn (2.45)
i1 = Cv2 +D (−i2) + in (2.46)
The noise vn and in cannot be measured using the o.c. or s.c. measurement technique,
but they can be found as function of vn1 and vn2 or as function of in1 and in2 through
17
the following expressions:
vn = vn1 − vn2(
z11z21
)
(2.47)
in = −vn2z21
(2.48)
or
vn = − in2y21
(2.49)
in = in1 − in2(
y11y21
)
(2.50)
Therefore, the noise factor of a two-port network can be calculated using the
noise representation in Fig. 4(c). Consider a general network with a noise current
source connected to its input port as shown in Fig. 5. It is assumed that the noise of
the source is and the noise of the network, in and vn, are uncorrelated but vn and in
may be correlated.
NoiselessNetwork
+
-
i2
v2
vn
inis Ys
Fig. 5. Noise factor calculation
The total output noise power is proportional to the mean square value of the
short-circuited current (i2s.c.) at the input port of the noiseless network. The noise
due to the source is only proportional to the mean square value of the current i2s. The
noise factor is thus given by:
F =i2s.c.i2s
= 1 +(in + vnYs)
2
i2s(2.51)
where i2s.c. = i2s + (in + vnYs)2 and Ys = Gs + jBs is the source admittance.
18
Typically there is correlation between vn and in. The gate and drain noise in
MOS transistor is a good example. In this case, in can be expressed as
in = inu + inc (2.52)
where inu is the part of in which is uncorrelated with vn, and inc is the part of in which
is correlated with vn. inc can be related to vn through the correlation admittance Yc,
and
inc = Ycvn (2.53)
Note that Yc is not a physical admittance, it is called admittance only because it has
the admittance dimension.
The noise factor can be rewritten using the above established equations as:
F = 1 +[inu + (Yc + Ys) vn]
2
i2s= 1 +
i2nu + |Yc + Ys|2 v2ni2s
(2.54)
The noise source is can be expressed in terms of the source conductance Gs,
i2s = 4kTGs∆f (2.55)
The noise voltage vn can be expressed in terms of an equivalent (fictitious) noise
resistance Rn,
v2n = 4kTRn∆f (2.56)
The uncorrelated noise current inu can be expressed in terms of an equivalent (ficti-
tious) noise conductance Gu,
i2nu = 4kTGu∆f (2.57)
Now the noise factor can be written in terms of noise parameters Rn, Gs and Gu,
F = 1 +Gu
Gs
+Rn
Gs
[
(Gs +Gc)2 + (Bs +Bc)
2] (2.58)
19
where Gc and Bc are the real and imaginary part of Yc respectively.
Note that Gs and Bs can be changed independently. So the noise factor can be
first minimized by choosing
Bs = −Bc ≡ Bopt (2.59)
Now, the second square term in the square brackets of (2.58) becomes zero, and F is
reduced to
F = 1 +Gu
Gs
+Rn
Gs
(Gs +Gc)2 (2.60)
It can be further minimized by using a proper value for Gs, which can be found by
differentiating the expression of F in respect to Gs and equating the result to zero:
d
dGs
[
1 +Gu
Gs
+Rn
Gs
(Gs +Gc)2
]
= 0
Solving it for Gs, one can obtain,
Gs =
√
G2c +Gu
Rn
≡ Gopt (2.61)
The above Gs and Bs describe the optimum source admittance which would
minimize the noise factor, and will be referred to as Gopt and Bopt respectively.
The minimum noise factor can be written as
Fmin = F |Ys=Yopt= 1 + 2Rn (Gopt +Gc) (2.62)
The noise factor now can be written as
F = Fmin +Rn
Gs
|Ys − Yopt|2 (2.63)
By using normalized impedance and admittance, the noise factor can be ex-
pressed as
F = Fmin +rngs|ys − yopt|2 (2.64)
20
where rn = RnZo
, gs = GsZo, ys = YsZo and yopt = YoptZo.
From the definition of reflection coefficient, we have
ys =1− Γs1 + Γs
yopt =1− Γopt1 + Γopt
and
gs =1
2(ys + y∗s) =
1− |Γs|2
1 + |Γs|2 + (Γs + Γ∗s)
=1− |Γs|2
|1 + Γs|2
So the noise factor can be expressed in terms of reflection coefficients Γs and Γopt,
F = Fmin +4rn |Γs − Γopt|2
(
1− |Γs|2)
|1 + Γopt|2(2.65)
Now the concept of the constant noise circle will be introduced. For this purpose,
rewrite (2.65) as
|Γs − Γopt|2
1− |Γs|2= N (2.66)
where N = F−Fmin4rn
|1 + Γopt|2. Since F ≥ Fmin, then N ≥ 0. For constant F , N is
also constant. It can be shown that the source reflection coefficient Γs for constant
noise factor F is a circle in the Smith Chart Γs-plane (see Appendix A). Its radius
and center location are given by
rF =N
1 +N
√
1 +1
N
(
1− |Γopt|2)
(2.67)
and
cF =Γopt1 +N
(2.68)
respectively.
If F = Fmin, then N = 0 and cF = Γopt, rF = 0, then circle reduces to a point
which corresponds to the minimum noise factor. When F increases, N also increases,
21
moving the center cF toward the origin of the Γs-plane, and enlarge the radius of the
circle. If F → ∞, then N → ∞, cF → 0 and rF → 1, this corresponds to the unit
circle. It can be concluded that the outer circles have a larger noise factor than the
inner ones.
2. MOS Transistor Two-Port Noise Parameters
The most popular CMOS LNA usually consists of just one stage utilizing one MOS
transistor. Design insight can be gained by studying the two-port noise parameters
Rn, Gu, Gc and Bc of a MOS transistor. From (2.62) and (2.63) , it is observed that
the noise factor can be calculated by knowing these four noise parameters.
For the first order approximation, the drain and induced gate current noise dom-
inate the noise performance of a MOS transistor. Fig. 6(a) shows the physical origin
of a MOS transistor’s noise sources.
i
"!$# %'&)( &*%+%-,/. "!$# %'&)( &*%+%-,/.
Fig. 6. MOS transistor thermal noise model (a) gate and drain noise sources (b) in-
put-referred noise sources
The mean square value of the drain current noise is
i2nd = 4kTγgdo∆f (2.69)
22
where gdo is the drain source conductance at zero drain-source biasing. γ is about
2/3 for long channel devices in the saturation region. For short channel devices, γ is
typically 2-3 or even larger [3]. This increased value of γ is due to carrier heating by
large electric fields developed across drain and source. Thus keeping the drain-source
bias voltage as low as possible will reduce the value of γ.
The gate noise current mean square value is
i2ng = 4kTδgg∆f (2.70)
where δ is the gate noise coefficient and is about twice the value of γ for long channel
devices and the parameter gg is
gg =ω2C2gs5gdo
(2.71)
Both drain and gate noise are originated from the thermal agitation of channel
charge, so they are correlated. The correlation coefficient [3] is defined by
c =ing · i∗nd√
i2ng · i2nd(2.72)
For long channel devices its value is j0.395. The pure imaginary value implies that
the correlation is due to capacitive coupling from channel to gate. So the gate noise
current can be expressed as the sum of component ingc which is fully correlated with
drain current noise and component ingu which is completely uncorrelated with drain
current noise.
Using the method described in the previous section, refer all the noise sources
in Fig. 6(a) to the input port (gate-source) of the MOS device as in Fig. 6(b). The
noise voltage is
v2n =4kTγgdo∆f
g2m(2.73)
23
and the noise current is
in = (inc1 + ingc) + ingu (2.74)
where inc1 = jωCgsvn, Cgs is the gate-source capacitance. inc1 is completely correlated
with noise voltage vn. It is easy to see that
inc = inc1 + ingc (2.75)
and
inu = ingu (2.76)
Whereby if the gate noise is ignored, noise voltage and noise current will be fully
correlated.
The four noise parameters [3] can be found to be
Rn =γgdog2m
=γ
α
1
gm(2.77)
Yc = Gc + jBc = jωCgs
(
1 + α |c|√
δ
5γ
)
(2.78)
Gu =δω2C2gs
(
1− |c|2)
5gdo(2.79)
where α = gmgdo
. It is seen that Gc, the real part of Yc, is essentially zero. Thus the
real and imaginary part of the optimum source admittance are
Gopt =
√
Gu
Rn
= αωCgs
√
δ
5γ
(
1− |c|2)
(2.80)
and
Bopt = −Bc = −ωCgs
(
1 + α |c|√
δ
5γ
)
(2.81)
respectively. The minimum noise factor is
Fmin = 1 + 2RnGu = 1 +2√5
ω
ωT
√
γδ(
1− |c|2)
(2.82)
24
where ωT = gmCgs
.
In order to achieve as small of a noise factor as possible, one can design an input
matching network to make Ys as close to Yopt as possible, which makes F approach
Fmin. At the same time, in the IC design, one has the freedom to choose the size
and biasing condition of transistors. By making Fmin small will also reduce the
overall noise figure. From (2.82), one can conclude that increasing ωT and/or the
correlation coefficient c will reduce the minimum noise factor. For a chosen process,
the correlation coefficient is fixed by the technology. The choice left for the circuit
designer to reduce Fmin is to have large ωTω. For example, suppose that γ = 2 and
δ = 4, and c is assumed to be 0.395. If ωTω
= 5, then Fmin = 1.7 dB, while if ωTω
= 15,
Fmin will be reduce to 0.6 dB.
3. Impact of LNA Gain and Noise Factor on System Sensitivity
The importance of gain and noise factor specifications on LNA can be discussed
further from the receiver’s system sensitivity aspect. The sensitivity Ps represents
the smallest input signal power that can be reliably detected by the system [4]
Ps = −174dBm+ 10 logBW + SNR + 10 logFtot (2.83)
The first two terms in (2.83) are usually referred to as noise floor. BW is the system
bandwidth and is determined by a specific application. System SNR is determined by
the bit-error-rate (BER2) requirement of the system. For example, for a Bluetooth
2BER is directly related with EbN0
of the received signal in an additive white Gaus-
sian noise (AWGN) channel. Eb is the energy per bit. N0 is the thermal noise density.If the date rate is R bits per second and the signal bandwidth is B, then the signal’sSNR can be related to Eb
N0as: SNR = R
BEbN0
. So for a certain BER specification, lower-ing data rate or increasing signal bandwidth can reduce required SNR, thus improvesensitivity.
25
receiver, simulation shows that a 12.3 dB SNR is needed for a BER lower than 10−3,
and for an 802.11b receiver, an 11.4 dB SNR is required to achieve better than 10−5
BER. Ftot is the system total noise factor and is directly affected by the LNA’s gain
and noise factor. Ftot can be calculated by
Ftot = FLNA +FafterLNA − 1
GLNA
(2.84)
The above equation shows that the LNA’s noise factor FLNA appears directly in
the system’s noise factor. For high sensitivity, low system noise factor is required,
therefore FLNA should be made as small as possible. The second term of (2.84)
shows that noise coming from the stages following the LNA will be suppressed by the
LNA’s gain, hence a high gain LNA is desirable for high sensitivity. For example, if
the LNA’s noise figure is 1.5 dB, its available power gain GLNA is 10 dB, and the
overall noise figure of the circuits following the LNA is 18 dB, then the system’s total
noise figure can be found using (2.84) to be 8.8 dB. If the LNA’s gain is increased
to 15 dB, the total noise figure will be reduce to 5.3 dB. System sensitivity will be
improved by 3.5 dB. If 8.8 dB noise figure is a fixed system specification, the noise
figure requirement on the circuits after the LNA can be relaxed to 22 dB.
On the other hand, a high gain of the first stage, which is the LNA in this case,
will put a more stringent linearity requirement on the following stages. Therefore
a trade-off must be made between gain, noise, and linearity. Table I summaries
important results obtained in the previous sections.
D. Large Signal Behavior
The RF amplifier is a non-linear system in nature. If the input signal is small enough,
the circuit can be modeled using a linear model around its operating point. But if the
26
Table I. Important equations for RF amplifier’s gain, stability and noise
Input and output
reflection coefficient
Γin = s11 +s12s21ΓL1−s22ΓL
Γout = s22 +s12s21Γs1−s11Γs
Unilateral transducer
power gainGTu = 1−|Γs|2
|1−s11Γs|2|s21|2 1−|ΓL|2
|1−s22ΓL|2
Voltage gain AV = s21(1+ΓL)(1−s22ΓL)(1+Γin)
Constant gain circle
center and radius
ci =gis
∗
ii
1−|sii|2(1−gi)
ri =√1−gi(1−|sii|2)1−|sii|2(1−gi)
Unconditional stable
for passive source and
load termination
|s11| < 1
|s22| < 1
K > 1
K = 1−|s11|2−|s22|2+|s11s22−s12s21|22|s12s21|
Two-port network
noise factor
F = Fmin +RnGs|Ys − Yopt|2
Fmin = 1 + 2Rn (Gopt +Gc)
Yopt = Gopt + jBopt =√
G2c +GuRn
+ j (−Bc)
MOS transistor
four noise parameters
Rn = γα1gm
Gc ≈ 0
Bc = ωCgs
(
1 + α |c|√
δ5γ
)
Gu =δω2C2
gs(1−|c|2)5gdo
MOS transistor
minimum noise factorFmin = 1 + 2√
5ωωT
√
γδ(
1− |c|2)
27
signal level is relatively high, due to non-linearity, the amplifier’s dynamic operation
point will be changed and become a function of the signal level. The LNA’s proper
operation must be checked by using a large signal input. On the other hand, although
the signal itself is small, large interferers may come together with the signal. This
situation is shown in Fig. 7(a). The interferers can be coming from the adjacent chan-
nel or generated by intentionally jammer. The interference specifications are usually
provided by the system standards. The non-linearity performance is characterized by
the two-tone test (f1, f2) as depicted in Fig. 7(b). Usually distortion term 2f1 − f2
and 2f2 − f1 fall in-band, they are characterized by the 3rd order non-linearity. For
example, the desired signal channel in Fig. 7(a) has a bandwidth of 1 MHz and is
centered at 1000 MHz. Two large blockers are located 1 MHz away from the center of
the channel and separated by 1 MHz, i.e. f1 = 1001 MHz and f2 = 1002 MHz. Thus
the lower side IM3 component will be at 2f1 − f2 = 1000 MHz, which is right upon
the center of the channel, degrading the signal’s SNR. Detailed non-linear distortion
analysis can be found in Chapter V. A large in-band blocker tends to desensitize the
circuit, it is measured by the 1-dB compression point. Dynamic range measures the
signal handling capacity of a circuit, which is bounded by the IIP3 and system noise
floor.
1. 1-dB Compression Point
The 1-dB compression point (P1dB) is the point (input or output) where the funda-
mental gain reduced by 1 dB from the ideal small signal gain at a certain frequency
(see Fig. 8). Assume a non-linear system can be approximated by Taylor series
y (t) = α1x (t) + α2x2 (t) + α3x
3 (t) + · · · (2.85)
28
010101010010101010010101010010101010010101010010101010010101010010101010010101010010101010
Desired signal-102dBm
IM3f=2f1-f2
Unwantedin-band blocker
-23dBm
f1 f2(a)
fa fb
fa<2f1-f2<fb
f1 f2f1 f2
f2-f1 2f2-f12f1-f2 f1+f22f1 2f2
(b)
Fig. 7. (a) In-band blockers generate in-channel intermodulation term (b) The two–
tone test spectrum
The input-referred 1-dB compression point [4] can be calculated as
P1dB =
√
0.145
∣
∣
∣
∣
α1α3
∣
∣
∣
∣
(2.86)
where α1 and α3 are the 1st-order and 3rd-order coefficients of the Taylor series
expansion of the system’d input/output characteristics as in (2.85).
2. Intercept Point
The two tone test is usually used to mimic the real-world scenario in which both
a desired signal and a potential interferer feed the input of the amplifier. Due to
29
23547678:9 ;<=+>
2+? @5AB8DCE=+>F<=+> GH*I
2+J K$L HMIONQP
2SR7TVUOL HMIENWP
Fig. 8. 1-dB compression point
the non-linearity of the circuit, the 2nd and 3rd order inter-modulation products will
appear at the output and they may lie within the pass band thus, degrading the
desired output signal.
We usually plot the desired output (fundamental), 2nd order intermodulation
output (IM2) and 3rd order intermodulation output (IM3) as a function of the input
signal level. The 2nd order intercept point (IP2) is the extrapolated intersection of
the fundamental curve and the IM2 curve. The 3rd order intercept point (IP3) is the
extrapolated intersection of the fundamental and IM3 curve (Fig. 9).
For the system described by (2.85), the input-referred IP3 (IIP3) [4] is given by
IIP3 =
√
4
3
∣
∣
∣
∣
α1α3
∣
∣
∣
∣
(2.87)
From (2.86) and (2.87), it is easy to show that IIP3 is about 10 dB higher than P1dB
for the same system if the third-order non-linearity dominates the linearity behavior.
3. Dynamic Range
Dynamic range (DR) is generally defined as the ratio of the maximum input level that
the circuit can tolerate without appreciable distortion to the minimum input level at
30
XZY\[Z]5^_E` [ a ^ b
cFdfe cFdhgcic1jg
k c1jgk c1je
cic1jle
m7n7o\p+q1rstvu
m*w x q1rsOtyu
Fig. 9. Meaning of IP2 and IP3
which the circuit provides a reasonable signal quality. Two different definitions are
usually used: spurious-free dynamic range (SFDR) and compression-free dynamic
range (CFDR).
Fig. 10(a) shows the definition of SFDR. The upper bound of SFDR is based on
intermodulation behavior and is defined as the maximum input level in a two-tone
test for which the third order intermodulation (IM3) products do not exceed the
noise floor. From Fig. 10(b), it can be shown that the input level for which the IM3
products become equal to the noise floor is given by
Pin,max =2× IIP3 +Nfloor
3(2.88)
where Nfloor = −174 dBm + NF + 10 logBW , is the noise floor. All the quantities
are expressed in dBm.
The lower bound of SFDR is limited by the system’s sensitivity. If for a certain
required signal quality, the minimum SNR is SNRmin, then the minimum detectable
31
zSF|FB~f | ~
IIP3
OIP3
Pin (dBm)P in,maxP in,min
SNRmin
SFDR
N floorf1
2f2-f12f1-f2f2 3f2-2f13f1-2f2
IM3HIM3LIM5HIM5LNoise floor
Minimumdetectablesignal level
Testing tones
SNRmin
SFDR
(a) (b)
Pout (dBm)
Fig. 10. (a) SFDR defination (b) Relationship between SFDR and IIP3
signal level in dBm at the input is
Pin,min = SNRmin +Nfloor (2.89)
This is also shown in Fig. 10(b). The SFDR is then calculated by the difference
between Pin,max and Pin,min:
SFDR =2
3(IIP3−NF − 10 logB + 174 dBm)− SNRmin (2.90)
Compression-free dynamic range (CFDR) is the difference, in dB, between the
input-referred 1-dB compression point and the noise floor as in Fig. 11:
CFDR = P1dB −Nfloor (2.91)
Here is a numerical example. Suppose an 802.11b receiver has the following
system specifications:
32
P1dB
1dB
Pin (dBm)N
CFDRfloor
Pout (dBm)
Fig. 11. Compression-free dynamic range
Parameter Value Unit
SNRmin 11.4 dB
BW 6.0 MHz
IIP3 -13 dBm
NF 12.9 dB
The noise floor Nfloor calculated from the above data is -93 dBm. From (2.88) and
(2.89), Pin,max and Pin,min are -40 dBm and -82 dBm, respectively. Thus SFDR is
42 dB. The 1dB compression point can be estimated from the IIP3 which is usually
10 dB larger than P1dB, therefore CFDR is about 90 dB.
4. Wide-Band Non-Linearity
The non-linearities of the wide-band circuits are also measured by their third-order
and second-order linearity behavior. But different from narrow-band system, wide-
band signal occupies a large amount of bandwidth and the two-tone test for narrow-
band system is not sufficient. For example, the cable TV (CATV) system has many
equally spaced carries, the linearities are measured by the composite triple-order beat
33
(CTB) and composite second-order distortion (CSO) [5].
For three equally spaced carries/tones (x1, x2, x3) in a wide-band system, the
distortion terms generated by the third order non-linearity are:
(x1 + x2 + x3)3 = H3 + IM3 + TB (2.92)
where
H3 = x31 + x32 + x33 (2.93)
IM3 = 3x21x2 + 3x21x3 + 3x22x1 + 3x23x1 + 3x22x3 + 3x23x2 (2.94)
TB = 6x1x2x3 (2.95)
The third order harmonic products in H3 are at three times of frequency. There are
N of them for N tones or carriers. These products are 15.6 dB weaker than the triple-
beat term in (2.95) and do not fall near a carrier, thus they usually are ignored. The
third order intermodulation products in (2.94) are half of the magnitude of the triple-
beats and they are fewer in number. In a system with 20 channels, the contribution
of the IM3 terms is less than 0.1 dB and their contribution decreases with increasing
number of channels.
The triple-beat (TB) term creates spurious frequencies at f1± f2± f3(f1 < f2 <
f3) and those spurs are 6 dB stronger than the third order intermodulation products
in (2.94). Fig. 12 illustrates the triple-order beats generation. The beats are drawn
offset from the carriers for showing purpose, they are actually reside on the carriers.
In the case of N tones/carriers, the total number of composite distortion products can
be approximated by N2
4at the edge of the band and 3
8N2at the middle of the band. So
triple-beats dominate the third-order distortion performance in a wide-band system.
The triple-beat power in dBm can be related to the intercept point power PIP3
34
f1 f2 f3
x1 x2 x3
f3+f2-f1f1-f3+f2f0 f4
f1+f3-f2
Fig. 12. Triple-order beats
and signal power Ps as:
TB = PIP3 − 3 (PIP3 − Ps) + 6 (2.96)
The CTB is usually measured by how many dB the triple-beat down from the
signal power. Because the mid-band has the maximum number of beats, so
CTB = 2 (PIP3 − Ps)− 10 log
(
3
8N2
)
− 6 (2.97)
Composite second order distortion (CSO) is a result of one or two carries expe-
riencing a second order non-linearity. Comparing to a narrow band system, multiple
second-order beats exist for a wide-band system having N carriers. For a CATV sys-
tem having fLas its lowest channel, fHas its highest channel and d is the frequency
offset from a multiple of 6 MHz (1.25 MHz), then the number of second-order beats
above any given carrier f is calculated by
NB = (N − 1)f − 2fL + d
2 (fH − fL)(2.98)
and the number of second-order beats below a given carrier f is
NB = (N − 1)
(
1− f − dfH − fL
)
(2.99)
35
Each of the above second-order beats is an IP2 tone, so its power can be expressed
in dBm as
SO = PIP2 − 2 (PIP2 − Ps) (2.100)
The CSO is specified as how many dBs the beats power down from the signal power
and will be given by
CSO = PIP2 − Ps − 10 logNB (2.101)
Note that all the quantities are measured at the output of the system. A typical value
of CTB and CSO for a CATV system would be -97 dBc and -89 dBc.
Table II summaries the equations obtain in this section.
Table II. Equations related to non-linearity
Non-linear system
characteristicsy (t) = α1x (t) + α2x
2 (t) + α3x3 (t) + · · ·
Non-linear circuit
1dB compression pointP1dB =
√
0.145∣
∣
∣
α1
α3
∣
∣
∣
Non-linear circuit
3rd order intercept pointIIP3 =
√
43
∣
∣
∣
α1
α3
∣
∣
∣
System dynamic rangeSFDR = 2
3(IIP3−NF − 10 logB + 174dBm)
−SNRmin
Wide-band system
triple-beat distortionCTB = 2 (PIP3 − Ps)− 10 log
(
38N2)
− 6
Wide-band system
second order distortionCSO = PIP2 − Ps − 10 logNB
36
E. LNA Topologies in CMOS Technology
Before continuing the discussion of LNA topologies, we will review the LNA speci-
fications in some wireless standards. For an LNA used in a GSM mobile receiver,
it will typically require about 20 dB gain, less than 2 dB noise figure, better than
-10 dBm IIP3. Its power consumption should be minimized and return loss should
no less than -8 dB. For the LNA used in a Bluetooth low-IF receiver, it will need to
have a voltage gain of 18 dB, noise figure of 3.5 dB and IIP3 of -3.5 dBm. The power
consumption also needs to be minimized and input return loss should be better than
10 dB. The challenge of LNA design is to fulfill all the specifications with limited
power consumption and silicon area.
LNA’s performance is more dependent on process technology than on circuit
topology. Indeed, LNA usually only involves one or two transistors in its signal path,
and there is not much degree of freedom to form different architectures. Still, for a
fixed technology, different circuit structures will produce a different performance and
design trade-off. Fig. 13 shows several popular LNA structures implementable in a
CMOS integrated circuit [3] [6]. Because an LNA’s input will directly interface with a
RF filter which generally requires certain impedance termination, so input impedance
matching is a must requirement for all the LNA’s listed in Figs. 13. The LNA struc-
tures are distinguished from each other by how the input impedance matching is
achieved.
Fig. 13(a) achieves input matching by directly placing a 50 Ω resistor in parallel
with the gate of transistorM1. This is the most straightforward method but the noise
figure is exceptionally high. A lower bound of its noise factor is
F ≥ 2 +4γ
α
1
gmRs
(2.102)
37
INM1
Rs
IN
(a) (b)
IN
M2VBB
ZLOUT
VDD
OUTM1
VBBRL
VDD
IN
Cgs
Lg
Ls
(d)
M1
VBB
ZL
OUT
VDD
M2
(e)
M1
RF
RL
OUT
VDD
R1
(c)
(f)
VDD
OUTIN
M1
M2
M3 VBB_+
M1
LFRL
OUT
VDD
CgdCF
Ls
IN
Fig. 13. Popular single-ended CMOS LNA topologies (a) Resistive termination (b)
Common gate (c) Shunt-series feedback (d) Inductive source-degeneration (e)
Current-reuse (f) Cgd neutralization
38
So the noise figure is readily larger than 6dB. The primary contribution of noise comes
from the termination resistor and transistor drain noise. Only in very rare cases, is
this LNA structure employed and usually not referred to as an LNA anymore.
The difficulty of input impedance match comes from the high input impedance if
a common source configuration is used. Common gate configuration avoids the high
gate input impedance as in Fig. 13(b). For the first order approximation, the real part
of input impedance is just 1gm
. By carefully choosing the size of the transistor and
biasing condition, 50 Ω impedance match is readily obtained. Ignoring gate current
noise, a lower bound of noise factor for this topology is represented by
F ≥ 1 +γ
α(2.103)
This bound is about 2.2 dB and 4.8 dB for a long and short channel device respectively.
The induced gate noise will make the noise factor larger, but the drain noise is still
the dominant factor.
Fig. 13(c) utilizes negative shunt feedback to modify the input impedance of a
common source stage. Its input impedance can be calculated approximately by
Zin =RF
1 + A(2.104)
where A is the voltage gain from input to output and is approximately in the order of
RLR1
, assuming M1’s gm is large enough. The noise figure of this structure is far better
than that of 13(a) but it is still too high to use in some applications. A noise factor
expression for this LNA without the source resistor R1 is given as [7]
F = 1 +Rsδgg +
(
Gs +GF
gm −GF
)2
Rs (GL + γgdo) +
(
Gs + gmgm −GF
)2
RsGF (2.105)
where Gs is the conductance of the signal generator, GF = R−1F and GL = R−1
L . For
lower power consumption, drain noise is the major noise contribution, but for high
39
power consumption, gate noise and the noise due to RF also become significant.
All of the three architectures introduced above have another similarity. Their
input impedance matching can cover a wide frequency band. Proper input impedance
is required by the RF filter preceding the LNA and the maximum power transfer. The
variations of Fig. 13(a), (b) and (c), are also widely used in wide-band systems [8] [9].
Fig. 13(d) is a very popular narrow-band LNA. It is narrow-band because impedance
matching is only established within a very narrow frequency range due to the res-
onant nature of the reactive matching network. Impedance matching is established
by inductive degeneration. Around operation frequency ωo =1√
Cgs(Lg+Ls), the input
impedance only presents a real part Zin = gmCgs
Ls. Detailed analysis can be found
in [10]. The noise figure of this inductive degenerated LNA can be readily made
below 2 dB or even lower [11] [12].
A closed form noise factor expression can be found to be [7]
F = 1+
(
ωoωT
)2
Rsγgdo+
[
(
ωTωogmRs
)2
+ 1
]
Rsδgg+0.79Rs
(
ωoωT
)
√
γgdoδgg (2.106)
In the above equation, the second term represents the contribution of the drain noise,
the third term is the gate noise contribution, and the last term shows the noise con-
tribution due to the correlation between the gate and drain noise. When considering
the series resistance of the inductors used in the LNA, an additional termRLgRs
should
be added to (2.106). The noise from series resistance of the degeneration inductor
is negligible. Among all the noise contributors, gate noise is the largest one. This
is because the gate noise current sees a high impedance due to the resonance of the
input matching network. Therefore, in order to reduce the noise factor, the Q value
of the input matching network should be limited.
The basic problem with using CMOS transistor for LNAs is its inherently low
transconductance and hence low gain. However, [6] uses a current-reuse technique
40
to almost double a single stage transconductance without increasing bias current.
Fig. 13(e) shows a simplified schematic of this design. The key point is that given
the same bias current, the effective transconductance is gm1 + gm2, while it is simply
gm1 in the case of no M2 presented. A major drawback of this design is its high input
and output impedances, thus requiring external impedance matching networks. This
prevents the use of this LNA in fully integrated applications Due to the high gain
property, strong Miller effect reduces the reverse isolation of this LNA. In the actual
design, two identical stages are cascaded to improve the reverse isolation.
In order to improve the reverse isolation of the LNA, Cgd neutralization technique
can be used as shown in Fig. 13(f). The LNA’s reverse isolation is limited by the
drain-source parasitic capacitor Cgd. An inductor LF is added in parallel with this
capacitor to provide a different feedback polarity to cancel the effect of Cgd. Care
must be taken to ensure that the inductive feedback does not incur any potential
stability issues.
Table III summarizes the performance of the five LNA circuits discussed in this
section.
F. Design Procedure of a Source Degenerated CMOS LNA
In this section, an inductive source degenerated LNA will be designed using a 0.18µm
CMOS technology to show the LNA design procedure and trade-offs. The simplified
LNA schematic is redrawn in Fig 14. We want to have an LNA working at 2.4 GHz
ISM band with less than 1.6 dB noise figure (noise factor: 1.45), -8 dBm IIP3, 20 dB
(10 V/V) voltage gain and drawing no more than 10 mA current from a 1.8 V power
supply.
The step by step design details from hand calculations to simulation verifications
41
Table III. Popular CMOS LNA architectures
Highlight Drawback Noise figure
Resistive
termination
Effortless input
match
Excessive
large NF> 6 dB
Common
gate
Easy input match
moderate NF
Large NF
and power2.2 ∼ 4.8 dB
Series/shunt
feedback
Broadband input
and output match
Stability issue
and isolation1.8 ∼ 5 dB
Inductive
degeneration
Good narrowband
match, small NFLarge area ∼ 2 dB
Current
reuse
High gain,
Low power
External matching
network required∼ 2.2 dB
Inductor
neutralization
Good reverse
isloation
Increased area,
stablility concern∼ 2 dB
are provided below. A flow chart is given in Fig. 15 to further visualize the design
flow.
Step 1: Important Design Equations
Because low-noise is the most important requirement for a LNA, the design consider-
ation will start from the LNA’s noise factor equation. The major noise contribution
comes from M1. Under input impedance match conditions:
ωTLs = Rs (2.107)
42
VIN
VB
Cgs
Lg
VDD
Ls
M1
M2
Rs
RL
Vo
CDLD
Fig. 14. Inductive source degenerated LNA
and
1√
Cgs (Lg + Ls)= ωo (2.108)
where Cgs and ωT areM1’s gate-source capacitance and cut-off frequency respectively.
ωo is the operation frequency. The noise factor of the LNA can be shown to be
F = 1 + κnf
(
ωoωT
)
(2.109)
where
κnf =γ
α
1
2Q
[
1− 2 |c|χd + 4(
Q2 + 1)
χ2d]
(2.110)
Q =1
2RsωoCgs
(2.111)
χd = α
√
δ
5γ(2.112)
κnf is called noise factor scaling coefficient. Rs is the source impedance and usually
is 50Ω or 75Ω. Q is the input quality factor and also controls the voltage gain from
input to gate-source port.
43
Estimate fT andcalculate κnf
Determine Iden, Q andCalculate Device Size
Calculate Lg, LS andRequired Load
Design Specs- Noise figure- IIP3- Voltage gain- Power consumption
- gm, gdo, α, Vgs-Vth v.s. Iden- fT and Cgs v.s. Vgs-Vth- κnf v.s. input Q and Iden- IIP3 v.s. Vgs-Vth and W
DesignParameter
Plots
SimulationVerification
Meet theSpecs ?
YES
↑−↑→ thgs VVIIP3
↓↑↑↓→ deno
T IQF ,,
ω
ω
↓↓−↓→ denthgsD IVVP ,
Trade between designSpecs and fine tunecircuit parameters
NO Layout and postlayout simulation
Meet theSpecs ?
NO
Tape-out YES
nHRLT
ss 2.0≈=ω
nHLC
L sgso
g 2612 ≈−=ω
Ω≈= 30sVT
oL RARω
ω
mfFWCgs µ/3.1=fFQRC
osgs 166~
21ω
=
mmfFfFW µµ
128/3.1
166==
denDS IWI ×=
( ) 5.71 =−=
T
onf f
fFκ
Fig. 15. Flow chart of LNA design procedure
44
Step 2: Know the Process and Obtain Design Guide Plots
To start, it is necessary to know the behavior of MOS transistor’s parameters related
with the above equations. The data can be collected through measurement or simu-
lation. The first parameter we want to investigate is α. It is defined as the ratio of gm
to gdo and changes with biasing condition. Fig. 16 plots the value of α and Vgs − Vthversus drain current density Ids/W . gm and gdo are also shown on the graph in the
form of gm/W and gdo/W .
E E E
'E + EO O E E * OEM M M M M
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Ç ÈÉ Ê¸Å¾Ç Ë ÌÉ Ê ÍÎÉ ÏÍÄ
Fig. 16. α, Vgs − Vth, gm/W , and gdo/W versus drain current density
Here minimum length of transistor is used. When bias current is low, MOS
transistor can be modeled using long channel approximation, thus α is near unity.
With the increasing of bias current, short channel effect becomes significant rapidly.
α deviates from unity. It is also observed that after current density is greater than
70µA/µm, making it larger does not help to increase gm much. γ is treated as a
constant and assumed to be about 3. δ/γ is also assumed to be constant and equal
45
to 2.
The next two parameters are the gate-source capacitance normalized to gate
width, i.e. Cgs/W , and device cut off frequency fT when transistor is biased in
saturation region. Fig. 17 shows the curves of Cgs/W and fT versus gate over drive
voltage Vgs − Vth.
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ì íî\ïðñññ òóô íóõö ÷ø ù úûü
ì ýþýöÿ î ýõöó óõÿ î ÷øñ ü
Fig. 17. Cgs/W and fT versus gate over drive voltage Vgs − Vth
Some insights can be gained from these plots. fT increases with Vgs − Vth when
Vgs−Vth is small. When Vgs−Vth becomes larger than 0.3 V, short channel effects such
as mobility reduction and velocity saturation make gm increasing slowly with Vgs−Vthand finally reaching a saturation value. Therefore the speed of fT increment with Vgs−
Vth is also reduce. When gate overdrive is small, transistor is biased at weak inversion
region, the charge controlled by the gate is sparse thus gate-source capacitance is
small. Channel charge increases rapidly with gate overdrive and so does the gate-
source capacitance. After Vgs−Vth becomes larger than 0.2 V, Cgs/W increases with
gate overdrive very slowly. At high gate overdrive, gm is almost constant and Cgs
46
increases slowly, so fT begins to degrade gradually after Vgs−Vth is larger than 0.8 V.
Now the noise factor scaling coefficient can be plotted againstQ and drain current
density Ids/W as illustrated in Fig. 18, where (a) is the 3-D plot for visual inspection
and (b) is the 2-D plot for design lookup purpose. Generally, the larger the current
density, the smaller the scaling coefficient; and the larger the Q, the larger the larger
the scaling coefficient. For a really large current density there is an optimal value of
Q which minimize the scaling coefficient. But the current density maybe too large
for practical applications. It is also worth to notice that for a fixed current density,
choosing large Q will reduce the total current consumption.
The last plot is not related directly to noise factor but to the linearity perfor-
mance. Fig. 19 is the IIP3 versus gate overdrive at 2 GHz for different size of devices.
Note that IIP3 is more dependent on gate over-drive voltage than device size.
Step 3: Estimate fT and Calculate κnf
Because we have a small current budget, the gate over drive can not be very large.
It will probably some where between 0.2 V to 0.4 V. Here we do not intend to fix
the gate overdrive voltage but rather have a rough idea of what value of fT we can
use. From Fig. 17, fT is estimated to be about 40 GHz. For 1.6 dB noise figure, from
(2.109) we need κnf to be no larger than 7.5:
κnf = (F − 1)fTfo
= 7.5 (2.113)
Step 4: Determine Current Density, Q factor and Calculate Device Size
For 0.2 V to 0.4 V gate overdrive, from plots in Fig. 16, the current density is some-
where between 60µA/µm and 140µA/µm. From Fig. 19, the device raw IIP3 is from
7 dBm to 14 dBm, so if Q is chosen to be 4, IIP3 will have good change meet the
47
2 4 6 8100200300400500600
4
6
8
10
12
14
16
18
Quality factorCurrent density (µA/µm)
Noi
se fa
ctor
sca
ling
coef
ficie
nt
(a)
! "
## ! "$&%' ! "$(#*) +"%,, "
-/.102 3 4+576+018*4 9:
; <= >?@ ABC < D>BAE= FGB<?@@= B= ?FC
HI.:J: KL4NMKL1O3 4+5
(b)
Fig. 18. Noise factor scaling coefficient versus quality and current density for 0.18µm
NMOS device (a) 3-D plot (b) 2-D plot
48
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S S!YJW S!Y Q SZY [ S!Y T S\Y ]
^`_a^Zb cedNf gh_a^Zb chd`f iN_a^!b chdNf
jlkXmonqprnhsut`swv rnxrp`y mRkzen|JZ~
Fig. 19. IIP3 versus gate overdrive and device size
specification. From Fig. 18(b), for Q of 4, the current density is chosen to be about
70µA/µm. The required gate-source capacitance is calculated to be
Cgs =1
2QRsωo≈ 166 fF (2.114)
From Fig. 17, the gate-source capacitance density is about 1.3 fF/µm, so the required
device width will be
W =166 fF
1.3 fF/µm≈ 128µm (2.115)
The device current can be estimated by
Ids = W × 70µA/µm ≈ 8.9mA (2.116)
Under the above conditions, the transistor’s gate overdrive voltage is about 0.23 V
and its transconductance gm is about 50mA/V . Before continuing to calculate the
49
required gate and source inductance, ωT is re-calculated by :
ωT =gmCgs
≈ 2π × 48GHz (2.117)
Considering the effect of gate-drain capacitance Cgd, the ωT is pretty near the value
being estimated before.
Step 5: Calculate Ls, Lg and Required Load
The source degeneration inductance is obtained by
Ls =Rs
ωT≈ 0.2nH (2.118)
And the gate inductance is
Lg =1
ω2oCgs
− Ls ≈ 26nH (2.119)
The cascoded transistor M2 will use the same size as the main driving transistor and
its size can be optimized through simulation if required. The gate bias voltage of M2
is tied to power supply in this example, its value can also be optimized. Generally,
it is chosen just large enough to bias M1 in saturation region for all possible input
levels. The use of M2 reduces the Miller effect and improves reverse isolation of the
LNA.
In order to obtain a desired voltage gain, the load impedance has to be set
correctly. Assuming the load is LC tuned and its equivalent impedance around ωo is
dominated by load resistor RL. The voltage gain of the LNA can be shown to be
Av = jQgmRL = j
(
ωTωo
)
RL
Rs
(2.120)
50
So the value of load resistor should be
RL =
(
ωoωT
)
|Av|Rs ≈ 30Ω (2.121)
Step 6: Simulation Verification
Now the design calculation is finished. But most of the design parameters need to be
fine tuned through circuit simulation. The above procedure shows the design trade-
offs between all the design parameters and can be used to guide circuit adjustment in
simulation. The initially calculated and simulated final device parameters are listed in
Table IV. Table V compares the targeted specifications and simulation results. The
hand calculations match the simulation results well except that the gate inductance
is much more over estimated by hand calculations. Fig. 20 shows the simulation plots
of various parameters of this LNA. Note that it is assumed that high quality on-chip
inductors are available in our design, their Q values can be as large as 20 at the
working frequency.
A differential LNA can be designed using the same procedure provide above. A
MOS differential pair should be investigated in order to obtain the required design
plots. Detailed discussion of differential LNA design issues will be given in Chapter IV.
51
Table IV. Calculated and simulated design parameters
Device parameter Calculation Simulation
W 128 µm 127.5 µm
Ids 8.9 mA 8 mA
gm 50 mA/V 50.7 mA/V
Cgs 166 fF 151fF
Ls 0.2 nH 0.2 nH
Lg 26 nH 16 nH
RL 30 Ω 40 Ω
Table V. Targeted specifications and simulated performance
Design parameter Target Simulated
Noise figure 1.6 dB 0.8 dB
Current drain <10 mA 8.0 mA
Voltage gain 20 dB 21 dB
IIP3 -8 dBm -6.4 dBm
P1dB – -20 dBm
S11 – -17 dB
S12 – -25 dB
Power Supply 1.8 V 1.8 V
52
-100
-80
-60
-40
-20
0
20
-40 -35 -30 -25 -20 -15 -10 -5 0
Input Power (dBm)
Outpu
t Volt
age (
dBV)
P1dB=-20 dBm
IIP3=-6.4 dBm
-20.0
-15.0
-10.0
-5.0
0.0
5.0
10.0
15.0
20.0
25.0
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.600.78
0.80
0.82
0.84
0.86
0.88
Input Frequency (GHz)
Noise
Figu
re (dB
)
S11 a
nd AV
(dB)
S11
AV
NF
(a)
(b)
Fig. 20. Simulation plots of the designed LNA (a) Voltage gain, S11 and noise figure
(b) IIP3 and P1dB
53
CHAPTER III
MIXER DESIGN OVERVIEW AND AN IMPLEMENTATION FOR LOW-IF
BLUETOOTH RECEIVER
In the receiving path (Rx) of a communication system, one of the goals is to pick
up the useful signal from the presence of noise and interferer, i.e. select interested
channel band. While it is hard to design a filter with a 1 MHz band centered at
2.4 GHz (Q∼2400), it is relatively easier to select a 1 MHz band centered at 4 MHz
(Q∼4). The down-conversion mixer is the key block that transfers the spectrum from
a high frequency band to a low frequency band.
At the same time, in the transmitting path (Tx) of the system, in order to make
the transmission of the baseband signal efficient and practical, the low frequency band
usually needs to be transferred to a much higher frequency band. Thus, the signal
can be radiated out by a compact enough antenna. Up-conversion mixer does this
job. It translates the low frequency baseband spectrum to the RF spectrum, then the
power amplifier amplifies this high frequency signal to a sufficient amount of power
and radiates out by the antenna. Fig. 21 is the simplified block diagram of a low-
IF/zero-IF transceiver. It shows the position and roles of the up- and down-conversion
mixers.
A. Mixer Mathematical Model
Most mixer implementations use some kind of multiplication of two signals, the signal
to be up- or down-converted (IF or RF) and the signal whose frequency determines
the output frequency (LO). So mathematically, an ideal mixer can be treated as a
54
LNA
PA
Rx/TxSwitch
Rx Baseband
Tx Baseband
LO
Up-ConversionMixer
Down-ConversionMixer
RF Portion IF PortionFrequencyConversion
Fig. 21. Mixers perform frequency translation in communication system
multiplier as shown in Fig. 22.
vRF
vLO
Mixer Output
Fig. 22. Mixer mathematical model
Assume the RF input signal is vRF (t) = ARF cos (ωRF t) and the LO signal is
vLO = ALO cos (ωLOt), then the output of an ideal multiplier is
vIF = vRF (t)× vLO (t) =ARFALO
2[cos (ωRF − ωLO) + cos (ωRF + ωLO)]
For an up-conversion mixer, component ωRF − ωLO is filtered out. For a down-
conversion mixer, component ωRF +ωLO is filtered out. If the input signal occupies a
frequency band, that band of frequency will be moved to a lower frequency for down-
conversion or a higher frequency for up-conversion. More insights can be obtained by
55
considering this mixing model in frequency domain. Usually the ideal LO signal is a
single tone, vLO = cos (ωLOt). Here the amplitude of the LO is normalized to unity.
The Fourier transform of the LO signal is
VLO (ω) = πδ (ω − ωLO) + πδ (ω + ωLO) (3.1)
The RF signal resides within a certain band around its center ωRF . The ampli-
fication in time domain will become convolution in frequency domain, i.e., the RF
signal will convolve with two δ-functions in frequency domain. Fig. 23 demonstrates
this process. It can be seen that the RF frequency band is translated into side-band,
the lower side-band centered around ωRF − ωLO and the upper side-band centered
around ωRF + ωLO.
0ω
VLO( )ω
0ω
VRF( )ω
0 ω
VIF( )ω
ωLO−ωLO ωRF−ωRF
ωRF + ωLOωRF − ωLOωLO − ωRFωRF − ωLO
Fig. 23. Mixing process
B. Mixer Metrics
In order to evaluate the performance of mixers, several metrics are defined, they are:
conversion gain or loss, noise figure, port isolations, linearity and power consumption,
etc.
56
1. Conversion Gain or Loss
Conversion gain or loss is a measure of mixer efficiency, it is defined as the ratio of the
desired IF output (voltage or power) to the RF input signal value (voltage or power).
More specifically:
Voltage conversion gain =r.m.s. voltage of the IF signal
r.m.s. voltage of theRF signal
Power conversion gain =IF power deliverd to the load
Power availabe from theRF source
The power gain definition here is actually transducer power gain. Usually for a dis-
crete implementation of mixer, power gain is specified. For on-chip implementations,
people usually specify its voltage conversion gain.
Mixers can be active or passive. Active mixers are capable of providing voltage
gain and power gain. At most a passive mixer can only provide voltage or current
gain but not power gain. The parametric converter, which is a special kind of passive
mixer, can provide power gain.
2. Noise Figure
A mixer’s noise figure (NF) is the signal-to-noise ratio (SNR) at the input (RF)
port divided by the SNR at the output (IF) port. Although the mixer’s noise figure
definition looks similar to the LNA’s noise figure definition, there are some subtle
differences between them.
The signal-to-noise ratios at the input and output are referred to different op-
eration frequencies. Mixers perform frequency translation, so there are two different
types of noise figures according to two different types of frequency conversion schemes,
single-side band (SSB) noise figure and double-side band(DSB) noise figure.
For the DSB noise figure, the desired signal appears at the both sides of the LO
57
frequency. Fig. 24 gives the situation of the double-side band conversion. Assume
the RF signal power for each side is Si, the noise power for each side presented at the
RF input is Ni, the conversion power gain is G, the mixer internal noise referred to
its output is Nno, the noise factor of the double-side band mixer can be calculated as
FDSB =SiNi
× 2NiG+Nno
2SiG= 1 +
Nno
2NiG(3.2)
For the SSB noise figure, the desired signal only appears at one side of the LO
f LOf RF1 f RF2
Ni
Desired Signal
2N iG
N noRF IF
LO
Si Si
f IF
2S iG
Fig. 24. Double-side band conversion
frequency. Suppose the noise at image frequency has not been removed, Fig. 25
shows this scenario. Using the same notation as the calculation of DSB noise factor,
the SSB noise factor can be expressed as
FSSB =SiNi
× 2NiG+Nno
SiG= 2 +
Nno
NiG(3.3)
From (3.2) and (3.3),
FSSB = 2FDSB (3.4)
It shows that the SSB noise figure is 3 dB higher than the DSB noise figure. When
designing a mixer, it should be made clear which noise figure is targeted at. The
simulator like SpectreRF gives the SSB noise figure. So if the DSB noise figure is
required, a 3-dB difference should be subtracted manually.
In practical system, the image noise in a SSB case is filtered using an image
58
f LOf RF1 f RF2
Ni
Desired Signal
2N iG
N noRF IF
LO
Si
f IF
S iG
Fig. 25. Single-side band conversion
rejection filter (IRF) before the mixer or a complex filter after the mixer (see Fig. 26).
So, the image noise experiences different gain with the noise within the signal band.
Suppose the gain of the IRF or complex filter at image frequency is Gim, the noise
factor is
FSSB,IRF =SiNi
× NiG+NiGimG+Nno
SiG= 1 +Gim +
Nno
NiG
With related to SSB or DSB noise factor,
FSSB,IRF = FSSB − (1−Gim)
2FDSB − (1−Gim)(3.5)
&o Xwul
o* \e
/ X
¡e¢1£&¤ ¥ ¢¦¨§X¤ ©ª¬«X
® ¯
Fig. 26. Single-side band conversion with image rejection
59
3. Port-to-Port Isolation
In reality, signals always leak through different mechanisms from one port to another.
The port-to-port isolation figure accounts for this unwanted transmission, it is defined
as the ratio of the signal power available into one port of the mixer to the measured
power level of that signal at one of the other mixer ports in a 50 Ω system.
The mixer has three ports. The desired transmission is from RF port at RF
frequency to IF port at IF frequency. The leakage can occur among all the other
ports. The most interested ones are discussed in detail as follows.
The signal leaked from the LO port to the RF port at a RF frequency (LO-to-RF
leakage) will mix with the LO signal again, causing the so called self-mixing problem
in direct conversion. Due to the non-zero reverse gain (s12) of the LNA, the LO
leakage may even reach the antenna through the LNA, then reflected back by the
antenna/LNA interface (see Fig. 27).
LNA
LO
RF IF
Fig. 27. LO-to-RF leakage
The LO-to-IF feed-through may cause desensitization of the block following the
mixer which is usually a low pass filter. In order to guarantee a good mixing per-
formance, the LO power is usually greater than the IF power. Although the LO
frequency will be in the stop-band of the filter, the large LO signal will drive the
60
filter out of its desired operation region. Whereby it is desirable to have some passive
filtering at the output of the mixer.
The RF-to-LO feed-through will allow the interferer and spurs present in the RF
signal to interact with the LO. The RF-to-IF feed-through at the IF frequency may
cause problems in direct conversion architecture due to the low-frequency even-order
intermodulation product.
4. Linearity Measurement
When a real mixer operates, not only do the desired tones mix (multiply) each other,
their harmonics also experience the mixing process due to the non-linear characteristic
of the mixing device. These unwanted products may fall into the spectrum band of
the signal and degrade the desired signal. The non-linear behavior of the system is
frequency dependent. We are interested in the dynamic linearity of the system, not
just the DC non-linear characteristics.
In communication systems we usually use the following metrics to measure the
mixer’s linearity: 1-dB compression point (P1dB), second and third order intercept
point (IP2 and IP3), spurious free dynamic range (SFDR) and compression free dy-
namic range (CFDR). The meanings of these terms for mixer are similar as for RF
amplifiers, just be aware of the frequency conversion in the mixer.
C. Circuit Topologies of Mixers
Down-converter and up-converter mixers are used in RF front-end to transform signal
spectrum from one location to another. Linear, time-invariant systems can not gener-
ate spectral components not presented in the input. The mixer must be a non-linear
or time-variant system. Virtually any nonlinear elements can be used as mixers. Some
61
nonlinearities just work better and more practical than others. The mixer can be pas-
sive or active depending on whether the mixer can provide conversion loss or gain.
The mixer can also be unbalanced, single-balanced or double-balanced, depending
on the signal operation symmetrical properties. Depending how the signal spectrum
is transferred, mixers can be implemented to work in real signal domain or complex
signal domain.
1. Diode Mixers
Diode mixers use the non-linearity of the diode to implement the frequency conversion.
Fig. 28 shows the single-diode mixer.The single-diode mixer is the simplest and oldest
passive mixer. The output LC tank is tuned to the desired IF, and the input is the
sum of RF, LO and DC bias. This mixer can not provide any isolation between
ports, neither can it achieve conversion gain. However, at very high frequencies (e.g.
millimeter-wave band) this kind of mixer is extremely useful.
VIN VOUT
RCL
Fig. 28. Single-diode mixer
A single-diode mixer belongs to the unbalanced configuration. The single-balanced
diode mixer uses two diodes as shown in Fig. 29. LO is large enough to make the
diodes work as switches, regardless of the level of the RF signal. When the diodes
are on, RF and IF are connected together, so the RF-IF isolation is poor. But the
RF signal is common-mode for the transformer, so the RF-LO isolation is excellent.
62
LO IF RF
Fig. 29. Single-balanced diode mixer
A double-balanced diode mixer uses four diodes. Due to the symmetry of the
circuit, isolations between each pair of ports are excellent, mainly limited by the
device matching. The diode mixer is almost completely linear and the upper limit of
the dynamic range is constrained by diode break-down. Typically, double-balanced
mixers can achieve conversion loss of around 6 dB, and port isolations of at least
30 dB. Fig. 30 shows the typical configuration of this type of mixer.
LO
IF
RF
Fig. 30. Double-balanced diode mixer
2. Passive Mixer in CMOS Technology
This kind of mixer is more like the double-balanced diode mixer. The diodes are re-
placed by MOS transistors working as switches as shown in Fig. 31. MOS transistors
63
M1-M4 are working as switches and are driven by a large LO signal in the anti-phase.
Thus, only one diagonal pair of transistors are turned on at any given time. More
specifically, when the LO is high, M1 and M4 are on, VIF equals to VRF , and when
the LO is low, M2 and M3 are on, VIF equals to −VRF . So it is equivalent to treat
the mixing behavior as multiplication: the RF signal is multiplied by a square wave
whose amplitude is either +1 or -1 and whose frequency is that of the LO signal.
L 3
L 4
RG
CL
M1 M2
M3 M4
LO
LO
V IF°²±R³´µ¶
´µ¶ LO
LO
C 2 L 2
C1 L1
C3
Fig. 31. CMOS passive double-balanced mixer
In Fig. 31, the input LC network provides matching and filtering. And due to
the reactive matching network, the voltage conversion gain can be greater than 1,
but this mixer can not provide power conversion gain. The noise figure and IIP3 are
strong functions of the LO signal strength and depend on how the MOS transistors
are switched. The implementation of a passive mixer is usually simple and there are
no stability issues involved [13].
64
3. Gilbert-cell Mixer
Gilbert cell mixers are the most popular types of integrated mixers. They can be
implemented either in BJT or CMOS technology. They are usually double-balanced
mixers. Fig. 32(a) shows one possible implementation using MOS transistors. Good
port isolation (40∼60 dB) can be achieved as a result of circuit symmetry. If the
input signals (RF and LO) are small enough such that all the transistors in Fig. 32(a)
are working in their linear region, then the Gilbert-cell will behave like an analog
multiplier. But this is not an efficient way to perform the RF frequency conversion
using a Gilbert-cell, it will generate a prohibitive high noise figure and has a strong
LO dependence of conversion gain.
GmVRF
IF
LO LO LO
-GmVRF
RF
IF
M1 M2
M3 M4 M5 M6LO
RF
IF
M1
M3 M2LO LO
(a) (b) (c)
Fig. 32. Gilbert-cell mixer (a) transistor implementation (b) working principle and (c)
single-ended version
In principle, the Gilbert-cell mixer works as shown in Fig. 32(b). M1 and M2
work as a voltage to current (V-I) converter or transconductance stage, and M3∼M6
are driven by a large enough LO signal such that they work as current commuting
65
switches. The linearity of the mixer is limited by the linearity of the V-I converter.
Additional linearization techniques are usually applied to the V-I converter to improve
the linearity of the mixer. For direct conversion and low IF, the noise figure is limited
by the flicker noise of the current switches and for higher IF, the noise figure is
limited by the thermal noise of the circuit. The transconductance conversion gain
can be expressed as
Gc = α2
πgm (3.6)
where gm is the transconductance of the V-I converter. Factor α is referred to as
switching efficiency. Because the practical mixer’s switches are usually not ideal,
loss is introduced due to non-ideal switching and is modeled by α, which is usually
smaller than its ideal value one. In some cases, single-balanced mixer can fulfill the
requirement, then half of the Gilbert-cell can be used as shown in Fig. 32(c). This
mixer consumes half of the power, has single-ended input and differential output. It
is easy to interface with single-ended LNA.
4. Sub-Sampling Mixer
A properly designed track-and-hold circuit can work as a sub-sampling mixer. Fig. 33
shows a general structure of this kind of mixer. One big advantage of this circuit is
that the LO signal is clocked at a relative low frequency, which eases the design of LO
circuitry. But the sampler still must have a good time resolution which means the
clock absolute time jitter must be a tiny fraction of the carrier period. Due to the sub-
sampling, the noise folding effect makes the mixer present a large noise figure. The
linearity of the sub-sampling mixer is usually very high, but due to jitter noise and
thermal noise folding, its dynamic range may be inferior to other carefully designed
mixers. Finally, the sub-sampling performance will be limited by the performance
66
of the operational amplifier (Opamp) used in the sampler. The limited achievable
gain-bandwidth (GBW) of the Opamp will limit the RF input signal to a certain
range.
RF
VCM
VCM
φ 1_b
φ 1_b
φ1
φ3
φ3
φ2
φ2
M1
M2
M3
M4
M5
M7
M6
Fig. 33. Sub-sampling mixer
5. Harmonic Mixer
Unlike conventional mixers, harmonic mixers mix RF signals with the second or higher
order harmonic of the LO signal. For standard mixers, the mixing product of interest
is LO ± RF . For harmonic mixers the nLO ± RF signal is desired. Usually n = 2
and the mixer is called sub-harmonic mixer.
The idea of harmonic mixing is to use the even harmonics of LO for its conversion
product. The odd harmonics including its fundamental will be rejected either due to
the odd symmetry of the system or by filtering or both.
One direct benefit of this idea is that the LO can run at half rate, which makes
67
VCO design easier. But because of the harmonic mixing, the conversion gain is usually
small (several dB) and the noise figure is high. Harmonic mixers are attractive for
the direct conversion applications due to the fact that they have low self-mixing DC
offset.
Fig. 34 is one possible implementation of the harmonic mixer [14]. Two emitter-
coupled BJT pairs work as two limiters. The odd symmetry of their transfer function
suppress even order distortion including LO self-mixing. The small RF signal will
modulate the zero crossing point of the relatively large LO signal. The output of
the mixer is a rectangular wave in pulse width modulation fashion, a low pass filter
will demodulate the signal. The leaked LO signal will generate a position modulated
signal which can not be demodulated by the low pass filter. So ideally this mixer will
not have DC offset.
LORF RF
VCC
RL RLIF
Fig. 34. Harmonic mixer
D. Mixer Design for a Low-IF Bluetooth Receiver
Bluetooth is a wireless technology for small form-factor, low-cost, short-range radio
links between mobile PCs, mobile phones, PDAs and other portable devices. It oper-
68
ates at the 2.4 GHz Industrial Scientific Medicine(ISM) band. Its modulation format
is Gaussian frequency shift keying (GFSK) with an index of 0.28∼0.35. The data rate
is 1 Mb/s and the channel spacing is 1 MHz. Low cost and possible system-on-chip
(SoC) solutions are the most attractive features of Bluetooth technology. The digi-
tal system is an important part of the system and digital technology benefits most
by using CMOS process. So the CMOS process is a must for SoC implementation.
Comparing to the BiCMOS technology, CMOS process is preferred in the Bluetooth
system design because it provides inexpensive implementation at a high integration
level. Thanks to the recent development in the silicon fabrication technique, the
current CMOS technology is able to accommodate the high speed RF circuit design
in the GHz frequency band and hence can be applied in the Bluetooth receiver de-
sign. Therefore, TSMC 0.35 µm CMOS technology is chosen to realize the Bluetooth
receiver system.
For a fully integrated CMOS implementation, there are two architecture can-
didates, direct conversion and low-IF. Direct conversion has the most possible high
level integration and does not require image rejection. It needs less components and
can achieve low power consumption. The difficulties faced by direct conversion are
DC offset and flicker noise [15]. While DC offset can be removed by some dedicated
circuitry, the flick noise presented in the mixer prevents one from adopting this archi-
tecture. The process, TSMC 0.35 µm CMOS, used in this implementation has flicker
noise corner frequency around 1∼2 MHz. It is not possible to make the mixer’s noise
figure meet the specification for direct conversion. A low-IF receiver can also achieve
a high level integration and has a possible low power requirement with careful system
level and circuit level design [16]. For low-IF, flicker noise is less significant in the
signal band. The DC offset can be easily removed with relatively simple circuitry.
But one needs to consider the image rejection and folded-back interference problem.
69
So low-IF architecture is a better choice for this implementation. The IF frequency
is decided to be 2 MHz due to the high flicker noise corner frequency. The image and
fold back interferer is rejected by a complex filter following the mixer.
1. Low-IF Bluetooth Receiver Architecture
Fig. 35 shows the low-IF Bluetooth receiver block diagram. It has two identical mixers
for the I and Q branches. The mixers in this receiver convert the 2.4 GHz frequency
band RF signal to a 2 MHz band IF signal, then the down-converted I and Q signals
are fed to a complex filter to make image/interferer rejection and channel selection.
The specifications for the mixer required in this receiver are listed in Table VI.
Table VI. Mixer specifications for low-IF Bluetooth receiver
Parameters min. typ. max. Unit
RF input frequency range 2400 2480 MHz
LO input frequency range 2400 2482 MHz
IF output frequency range - 2 - MHz
Voltage conversion gain - 12 - dB
LO drive level (internal) - 0 - dBm
Input 1dB compression point - 0.1 - dBm
IIP3 (Vrms) - 5.6 - dBm
Input referred noise - - 7.5 nV/√Hz
2. Implementation of the Down-Conversion Mixer
For the front-end of the Bluetooth receiver, the LNA is designed by designer Wenjun
Sheng using the conventional source inductive degeneration technique [17]. The down-
70
RFFilter
ComplexFilter
GFS
KD
emod
ulat
or
Q Mixer
Limiter &RSSILNA
I Mixer
BinaryStream
Synthesizer& VCO
DC
Offs
etC
ance
llatio
n
090
Fig. 35. The proposed low-IF Bluetooth receiver
conversion mixer is a modified Gilbert-Cell mixer [18], as shown in Fig. 36. In order to
improve the output dynamic range, the tail current in the conventional Gilbert-cell is
removed, this also allows low voltage operation and has higher linearity. It is obvious
that without the tail current, the voltage headroom will be improved by a Vdsat of a
MOS transistor if a simple current source was used. The improved linearity without
current source can be explained as below.
For a source coupled differential pair, in order to operate both of the two tran-
sistors in the saturation region, the input differential voltage should be within [19]
|Vid| <√2Vod (3.7)
where Vod is the gate over-drive voltage when Vid = 0, i.e. at quiescent DC biasing
point. But if there is no tail current source, for the same DC biasing current, the
differential input range for active operation will be expanded to
|Vid| < 2Vod (3.8)
The differential pair has less linear input range due to the existence of the tail
current source. The current source makes the two transistors in the differential pair
71
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½¿¾Ä»À7ŬÆÀÇÅ(È
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½Å(È ½lÅ(È
½Å¬Æ ½lŬÆÒxÆ ÒºÈ
ÒºÓ ÒºÔ ÒÂÕ ÒºÖ
½l× ½×Ø × Ø ×ÀÂÁ¿Á
ز٠زÙ
à Šà Å
Fig. 36. Bluetooth receiver down-conversion mixer
interact with each other so the their active input region is limited more than two single
transistors without such interaction. However, without tail current source, the circuit
is not a truly differential structure any more which may have a poor common-mode
rejection performance. Fortunately, if the LNA’s output signals are well balanced
and/or additional loop is used to suppress the common-mode signal, this architecture
can be used.
The injected current IB, called bleeding current, allows separate control of current
72
flowing through the drive stage (M1 and M2) from the current switches (M3∼M6).
For the same drive bias current, bleeding reduces the current flowing through the
current switches and load resistance. Since flicker noise can be expressed as [20]
i2nf = KfIAfD
CoxWeffLefff∆f (3.9)
Reducing the bias current will significantly reduce flicker noise contributed by the
switches and allow large load resistors which increases the conversion gain. Fur-
thermore, with current bleeding, the switches can work with smaller gate to source
voltage, so for a given LO signal level, smaller charges are necessary to turn on or off
the switches and conversion efficiency is improved.
On the other hand, bleeding can degrade the high frequency performance of the
RF drive stage, because bleeding reduces the bias current of the switches therefore
increasing the load impedance seen by the driving transistors. Ideally, the RF drive
stage works as a voltage-current converter, it should see as small impedance at its
output as possible, increased load impedance reduces voltage-current conversion effi-
ciency. Due to Miller effect, increased voltage gain from the input of the RF stage to
its load makes reverse isolation larger than without bleeding.
Current bleeding also adds additional noise sources due to the bleeding circuit,
which is usually implemented using active devices. In this implementation, the bleed-
ing current source is formed by a PMOS current source with a large device size. This
arrangement makes the flicker noise contribution from the bleeding source smaller.
Care must be taken to make the matching between the two bleeding current sources
as good as possible. Otherwise, a large mismatch will drive the injection node to-
wards the positive or negative power supply, if the switch current is too small to set
the drain voltage of M1 or M2. Although additional common mode feedback circuits
can be used to prevent this problem [21], it will require an additional tail current
73
source which is removed for the limited voltage headroom reason. Since the load of
the mixer is resistive, the need of a common mode feedback circuit at the mixer’s
output is avoided.
The voltage conversion gain can be written as
Avc =2
πgm,RFRL (3.10)
where gm,RF is the differential transconductance of M1 and M2. IF M1 and M2are
perfectly matched, then gm,RF = gm,M1= gm,M2
, otherwise for the first order approx-
imation, assume ∆gm = |gm,M1− gm,M2
| ¿ gm,RF ,
gm,RF ≈gm,M1
+ gM,M2
2(3.11)
IIP3 of the mixer is approximately given by [22]
VIIP3 ≈ 2
√
4
3
gm,RFKθ
≈ 4
√
2
3
Vodθ
(3.12)
where K = 12µeffCox
WL, θ = 1
EsatLand Vod = VGS − Vth. It is assumed that θVod ¿ 1.
For a regular differential pair with tail current source, and using the same transistor
size and bias condition, its IIP3 can be found to be [22]
VIIP3 ≈ 4
√
2
3Vod (3.13)
which is by a factor of 1√θVod
smaller than the one used here without a tail cur-
rent source. It is obvious from (3.10) and (3.12) that an increase in the drive stage
transconductance will increase the conversion gain and linearity at the same time.
But increasing gm will result in a larger power consumption. The noise analysis of
the mixer is quite involved and can be found in [23].
The mixer’s design flow is shown in Fig. 37. Because the signal reaches the mixer’s
input after being amplified by the LNA, we start with the linearity specification for
74
the RF driving stage. From (3.12), the required gate over-drive voltage Vod,RF can
be calculated, then from (3.10), the device size WRF , bias current IRF and load
resistor RL can be determined. The bleeding current is chosen by considering the
output voltage headroom. In order to allow the current switches working efficiently,
the LO swing should be larger than the switch differential pair’s linear operation
voltage range, which is√2Vod, SW . Therefore, the gate over-drive of the current
switches Vod, SW , and their size WSW can be calculated. After the hand calculations,
simulation verification is carried out. Usually the design parameters needs to be
adjusted intensively through simulation and several iterations are required to achieve
the targeted specifications.
3. Layout Considerations and Simulation Results
When doing the layout of the mixer, special care should be taken to ensure the I and
Q mixers are symmetrical and the gate resistance is minimized. Matching techniques
such as common centroid and inter-digitized pattern are applied. The length of the
poly gate is kept short enough to reduce the gate resistance (large gate resistance
will degrade the noise performance). For the layout of a poly-poly capacitor, if the
bottom plate is floating, the parasitic capacitance from the bottom plate to the sub-
strate should be considered. It is about 40% of the nominal capacitance. Decoupling
capacitors may be needed to prevent the circuits from oscillation. Metal should be
wide enough to carry large current. The current density allowed through metal is
about 1 mA/µm. Guarding rings are place around the circuits to improve isolations
from other blocks on the same die. The mixer uses resistors as load, guidelines for
reducing resistor mismatch are: 1) Use dummy poly lines when possible. 2) Maximize
the number of contacts per width of the device. 3) Avoid partial coverage of resistors
by any layer of metal. 4) Local symmetry is important for matching, in a bank of
75
Design Specs- Noise figure- IIP3- Voltage gain- Power consumption
SimulationVerification
Meet theSpecs ?
YESNO Layout and postlayout simulation
Meet theSpecs ?
NO
Tape-out YES
Current Switches
SWodSWodpeakpeakLO VVV,,,
2 →>>−
SWSWSWod WIV →,,
RF Driving Stage:
RFodRFod
IIP VV
V ,,
3 324 →=θ
LRFRFLRFmVC RIWRgA ,,2,
→=π
Bleeding CurrentSWBRFL IIIR ,, →
Fig. 37. Mixer design flow chart
76
identical resistors, resistors at the edge showed about 2% difference in value from
their nearest neighbors. 5) Gradient effects are present and do effect matching, keep
critically matched pairs as close as possible.
Fig. 38 is the layout of the mixer, it includes both I and Q branches. The
circuit is simulated using Cadence SpectreRF environment. Because the mixer will
be interfaced with LNA directly, its input impedance is first obtained around its
operation frequency. And is given to the LNA designer. The LNA and mixer co-
simulation is done to make sure they are compatible. Mixer’s separate performance
is than re-simulated and listed in Table VII.
RF drive stageCurrent switches
Bleed
ing cu
rrent
source
Bias
I Mixer Q Mixer
Fig. 38. Layout of the down-conversion mixers
77
Table VII. Bluetooth mixer simulation results
Parameter Value Unit
Voltage conversion gain 12.4 dB
RF Input resistance 214 Ω
RF Input capacitance 166 fF
Input referred noise 6.8 nV/√Hz
RF-LO isolation 30 dB
LO swing 0 dBm
Supply Voltage 3 V
Current consumption 5 mA
4. Experimental Results of the Mixer Within the Receiver
The Bluetooth receiver IC is fabricated using the TSMC 0.35 µm standard CMOS
process through MOSIS service and packaged in a 48-pin TQFP plastic package. The
die microphotograph is shown in Fig. 39, and it occupies 2.5 mm × 2.5 mm silicon
area.
As an integrated part of the Bluetooth receiver, the mixer is tested together
with the LNA. In order to guarantee the performance, no access to the internal high
frequency nodes within the LNA and mixer is granted. Therefore, the LNA and mixer
have been tested as a single block. Together they consume 10 mA current from a 3 V
power supply.
The measured cascaded NF and voltage gain are 8.5 dB and 25 dB, respectively.
Fig. 40 shows the input S11 measurement plot of the front-end. The S11 is less than
-10 dB in the 2.4GHz band. The system IIP3 is about -10 dBm. Fig. 41 is the IIP3
78
Fig. 39. Die photo of Bluetooth receiver
plot of the receiver system. The IIP3 was tested using two tones 3 MHz and 6 MHz
away from the desired signal. The 3rd order intermodulation product was observed
at the output of the complex filter and referred back to the receiver input to calculate
IIP3. The achieved sensitivity is -82 dBm for the whole receiver.
79
Fig. 40. Input return loss of the Bluetooth front-end
Ú!ÛÜÝ/Þ!ßáà Ü\â ÞIã
äåælç å æèåXé*ê
ëëIìîí
Fig. 41. Measured IIP3 of the Bluetooth receiver
80
CHAPTER IV
BLUETOOTH/WI-FI DUAL-STANDARD RECEIVER RF FRONT-END
With the rapid development of wireless access technique, more and more devices
are Bluetooth enabled. At the same time, the wireless LAN (IEEE 802.11b, Wi-Fi)
standard comes into our everyday life. While Bluetooth targets on short range cable-
replacement and point-to-point communication applications [24], Wi-Fi is focused on
wireless local network connection capabilities for portable devices such as laptops and
PDAs [25]. These two standards do not compete with each other, but rather comple-
ment each other [26]. They do different things and tasks. There are circumstances
where Bluetooth is preferable to Wi-Fi, for example, short range point to point or
multi-point data transfer with low power consumption, data self-synchronization and
updating. But for more complicated network functionalities and high speed data
transfer, Wi-Fi will take over. One big application is wireless Internet access. All
those functions are needed in high-end laptop and PDAs. So there are practical
needs to require both standards within one application. Combining these two stan-
dards together into one single chip will reduce the fabrication cost and add more
functionalities to the product.
Both Bluetooth and IEEE 802.11b standards work at the 2.4 GHz ISM band.
Although the base band will be quite different between these two standards, the
co-band operation makes the RF front-end having maximum compatibility. And it
is reasonable to integrate the two standards in a single-chip with maximum circuit
building block sharing. Table VIII lists the key features of both standards.
This chapter focused on the development of a dual-mode receiver RF front-end.
In the following sections, the direct conversion Bluetooth/Wi-Fi dual-standard re-
81
Table VIII. Bluetooth and Wi-Fi standards key features
Bluetooth Wi-Fi
Frequency band 2.4-2.48 GHz 2.4-2.48 GHz
Available speed 720 Kbps 5.5 Mbps
Operation range 10 cm-10 m 100 m
Security risk Low High
Targeted application Wireless PAN Wireless LAN
Form factor Small Large
Power requirement Low High
ceiver architecture is discussed, the design considerations and circuits implementa-
tions of the RF front-end is presented as well as the measurement results.
A. Direct Conversion Bluetooth/Wi-Fi Dual-Standard Receiver
As stated above, Wi-Fi belongs to the wireless local area network standard family.
It operates at the same frequency band as Bluetooth, and there is a demand to
combine these two standards together to make the product more competitive. In this
design, direct-conversion architecture was explored for both standards to avoid the
image rejection problem in IF architecture, maximizing block sharing between two
standards to save power and silicon area. A major concern in the low-IF architecture
is the selection of the intermediate frequency (IF). In order to benefit the most from
the low-IF architecture, the IF frequency is usually optimized to suite the modulation
format and signal bandwidth defined in a particular standard. Therefore, the IF will
vary as the receiver switches between the standards to avoid significant degradation
82
of receiver performance. As a consequence, the channel select filter, whose center
frequency is located at the IF, becomes difficult to design. In the direct conversion
receiver architecture, the channel select filter will be just a low pass filter. It does not
have a center frequency to adjust when the receiving mode changes. Furthermore, the
signal bandwidth is also different from one standard to the other. The implementation
of a bandwidth variable filter is more straightforward for low pass than that for band
pass.
Although the direct conversion receiver enjoys the high level integration and
potential of low power consumption, it suffers from some inherent implementation
difficulties, such as DC offset and low frequency noise. The large DC offset and low
frequency flick noise make it difficult to design a direct conversion receiver in current
CMOS technologies for narrow band systems. Additional circuits and techniques,
such as a digital calibration circuit, have to be used to alleviate the performance
degradation due to the large DC offset. While there is no obvious way to solve the
flick noise problem in CMOS technology for narrow band systems like Bluetooth.
BiCMOS technology, on the other hand, has much lower intrinsic DC offset and
flicker noise. Simple measures, like a 2nd or 3rd order high pass filter, can provide
enough suppression to the DC offset and flick noise. Therefore, BiCMOS process is
chosen for this dual-standard direct conversion receiver to relax design complexity for
a reasonable increase of cost.
Fig. 42 is the block diagram of the Bluetooth/Wi-Fi dual-standard receiver. In
this receiver, the front-end blocks, LNA and mixer, are completely shared between
Bluetooth and Wi-Fi standards. The received signal in the Wi-Fi standard can be
10 dBm stronger than the Bluetooth signal. To accommodate the larger dynamic
range of the 802.11b received signal, the LNA has two gain modes. It switches
between a 15 dB gain or a 15 dB attenuation according to the received signal power.
83
An integer-N frequency synthesizer is used to generate two times the desired local
oscillation (LO) frequency to avoid the LO pull-in problem in a transceiver due to
the coupling from the power amplifier to the VCO. The output of VCO is then passed
through a divided-by-two circuit to generate quadrature LO signals for the I and Q
channels. The received signal is converted to DC by the down-conversion IQ mixer.
A Gm−C low-pass channel selection filter with programmable bandwidth is used
to accommodate both standards. Then the signal is conditioned by the variable-
gain amplifier and sent to analog-to-digital converter (ADC). The ADC is a parallel
pipelined structure. For Bluetooth, its sampling rate is 10 MHz, and has an 11-bit
resolution. For Wi-Fi mode, the sampling rate is 44 MHz, and its resolution reduces
to 8-bit. DC offsets cancelation technique is used to remove both static and dynamic
offsets [27].
15dB
Attenuator(-15dB)
RFFilter
Q Mixer
LNA
I Mixer
Synthesizer& VCO
090
φ
LPF
LPF
ADC
ADC
18dB
φ
Signal LevelMeasurement
GainControlφ
φ
Fig. 42. Bluetooth/Wi-Fi receiver
B. RF Front-End Design Considerations
For this design, a fully-differential structure is used to reject the common-mode noise
coming from the digital parts and other sources as much as possible. The differential
structure can also isolate the influence of bond-wire. For a single-ended circuit, bond-
84
wire for signal grounds directly becomes part of the circuit and must be modeled well
in order to have an accurate prediction in simulation. In a differential structure,
bond-wire is in series with the tail current and is in both DC and common-mode
path, so it does not or has little effect on the circuit differential operation. Thus its
performance is more reliable and predictable. The differential structure consumes as
twice of the power as single-ended one for the same performance, but the improved
isolation and reliability justifies the power increase.
For a differential LNA, the desired operation mode is the differential mode. But
the common mode operation also presents. An important issue or consideration is
the common mode stability. Fig. 43 shows the source degenerated differential LNA
input stage, its differential half-circuit and its common mode equivalent half-circuit.
In the figure, Lg is the gate inductor, Ls is the source degeneration inductor, they
together resonate with gate capacitor C1. C1 is the total capacitance between the
gate and source, it is composed of gate-source overlapping capacitance Cov, gate-
source channel capacitance and additional capacitance added externally. 2C2 is the
parasitic capacitor of the current source. For the differential operation, this capacitor
does not appear in the half circuit. For the common mode, half of this capacitor will
present in series with the inductor Ls. The resistance of the current source is assumed
to be sufficiently large.
For the differential half-circuit, the input impedance [10] can be expressed as
Zin,diff = jω (Lg + Ls) +1
jωC1+gmC1Ls (4.1)
At the resonate frequency ω = 1√(Lg+Ls)C1
, it is a pure positive resistance gmC1Ls, where
gm is the small signal transconductance of transistor M1. So there is no obvious
stability problem for the differential operation.
85
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ñòXó
òôòôõoö õoö
õo÷õo÷
ø ù&ú1ûü ý ý þ*ÿ þ ü ùwõ7ü ù(þ
ø oú ò þwù ý&ü ÿ (ü ø Rú1ûü ý ý þ*ÿ þ ü ùwù ý&ü ÿ (ü
ïhð1ð
òXóòôõoö
õo÷
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! % & &
ïhð1ð
òôõoö
Fig. 43. Differential LNA common mode stability
For the common mode half-circuit, the input impedance is given by
Zin,com = jω (Lg + Ls) +C1 + C2jωC1C2
+gmC1Ls −
gmω2C1C2
(4.2)
The real part of Zin,comis
Rin,com =gmC1
(
Ls −1
ω2C2
)
(4.3)
It can be seen that if this real part goes negative, then there exists potential instability.
One may want to increase the capacitance of C2 in order to keep Rin,com greater than
zero. This is not the right way. A large common-mode capacitance will disturb the
differential operation and even worse, increase the common-mode gain. We should
keep this capacitance as small as possible. For an ideal tail current source of the
differential pair, the common-mode gain is infinity, so the oscillation will not be
able to sustain. Of course one should check the sign of (4.3) and further evaluate if
this negative resistance will cancel the source impedance’s real part thus causing a
problem.
86
Another concern is the interface between the LNA and mixer. We have a direct
conversion receiver. There is no image rejection filter between the LNA and mixer,
so the LNA does not need to drive 50Ω impedance and the mixer does not have
to provide 50Ω input matching. This is another degree of freedom for the direct
conversion front-end design. The design strategy is that the mixer will be designed
first. Then the mixer input impedance becomes known and will be driven by the
LNA. Another way is to have a rough estimate of the impedance level of the mixer
input and then the LNA and mixer can be designed at the same time by different
designers. The LNA and mixer must be brought together to verify their interface
behavior. For off-chip interconnection, the effect of bond wires on the circuit must
be modeled and considered with the circuit design.
BIASING CIRCUIT
I+I-
Q+Q-
3GHz1:1 BALUN
BuffersQuadratureLO
LNARF_IN
Fig. 44. RF front-end block diagram of BT/Wi-Fi Receiver
C. Circuits Implementations
The dual-mode RF front-end includes the LNA, mixer, buffers and their biasing
circuit. Fig. 44 gives the block diagram of the RF front-end. This is a direct conversion
front-end, so no image rejection filter (IRF) is required between the LNA and mixer.
This improves the aspect of integration of this architecture.
87
Table IX lists the specifications of the LNA and mixer for the Bluetooth and
Wi-Fi operation. Notice that Wi-Fi has the most stringent requirement. So the RF
front-end is shared by both the Bluetooth and Wi-Fi modes and targeted at the most
stringent specifications in the table.
Table IX. Block specifications for the BT/Wi-Fi RF front-end
Parameters LNA Mixer Unit
Voltage Gain 15/15 18/18 dB
Noise figure 2/2 25/15 dB
IIP3 -8/-8 0/0 dBm
IIP2 20/20 40/30 dBm
1. LNA Implementation
The SiGe BiCMOS technology is used to implement the front-end. The LNA is given
in Fig. 45. It is an inductive degenerated differential structure and can provide two
gain steps of 15dB and -15dB. Gain control is implemented by a differential attenuator
built around the LNA as indicated in the dashed box in Fig. 45. The attenuator
is formed using NMOS transistor M5 ∼ M9. For high gain mode, all the NMOS
transistors will be turned off by connecting their gates to ground. Thus the normal
operation of the LNA will not be affected. For low gain operation, these transistors are
driven into their triode region and the LNA’s bias current Itail will be cut off. Under
this mode, the LNA itself will not consume current and is by-passed. The resistor
divider formed by the NMOS transistors is used to provide further attenuation (-
15 dB). A capacitor Cm is inserted into the attenuator to improve impedance matching
for the low gain mode.
88
LNA_cas_bias
Vo+
Vo-
VDD
LNA_bypass
Ls Ls
LdLdLNA bypass switches and attenuator
LNA_rf_biasi_tail
CmVin+
Vin- M1 M2
M5
M6
M7
M8
M9
M3 M4
Q1 Q2
Rb Rb
Bond wire
Cd Cd
Vbb
Rb Rb
Cm
Fig. 45. LNA for BT/Wi-Fi receiver
All the matching conditions are established on-chip using the inductive source
degeneration technique [10]. The only required off-chip components are a 1:1 RF
BALUN to convert the single-ended signal to differential and two additional chip-
inductors to provide matching.
The RF drive stage was chosen to be NMOS transistors due to the fact that MOS
transistors are more linear than bipolar transistors for the same current consump-
tion [28]. The cascoded bipolar transistors Q1 and Q2 provide stable and matched
bias voltage to the drain of NMOS M1 and M2. Here bipolar is preferred because the
base-emitter voltage change is much smaller than the gate-source voltage change for
the same bias current variation. The transconductance available from NPN bipolar is
much larger than the one from NMOS for the same current. Thus voltage at the drain
of M1 and M2 does not change significantly which minimizes the voltage gain from
89
the gate to the drain of M1 or M2, therefore the Miller effect is reduced and reverse
isolation is improved. This can be seen more clearly through the input impedance of
the cascoded stage, which can be expressed as
Zcas,in = re +α0RL
gm,bjtrce(4.4)
where re =α0
gm,bjt≈ 1
gm,bjt. α0 is the emitter to collector current ratio and is very near
unity for a modern NPN bipolar process. RL is the equivalent output load impedance.
rce is the bipolar transistor output impedance.
If the cascoded transistor is replaced by its MOS counterpart, its input impedance
will be
Z′
cas,in =1
gm,mos + gmb,mos+
RL
(gm,mos + gmb,mos) rds(4.5)
where gm,mos and gmb,mos are the transconductance of a MOS transistor from gate
and bulk terminal to drain terminal respectively. rds is the drain output impedance.
For the same bias current,
re <1
gm,mos + gmb,mos
and
gm,bjtrce > (gm,mos + gb,mos) rds
so
Zcas,in < Z′
cas,in
. The gain from input of M1(M2) to its drain is proportional to the cascoded tran-
sistors input impedance, therefore using bipolar as cascoded transistor this gain is
smaller than that uses a MOS transistor.
Degenerative inductor Ls (1 nH) and load inductor Ld (3 nH) are on-chip planar
spiral inductors. They are formed using the top layer metal (analog metal, AM) and
there is a deep trench lattice pattern beneath them to reduce metal loss and substrate
90
loss respectively. Bond wires at the input are used to form the input biasing network.
The use of bond wire has two benefits. First, its quality factor is much larger than
on-chip inductors and thus, contributes less noise the overall noise factor. Second, it
does not occupy die area and makes the chip more compact.
A systematic design procedure was followed from the beginning and the circuit
was finely tuned through extensive simulations. Under matching conditions, there
are several equations established for the input matching network. The operation
frequency of the LNA relates the inductance and capacitance in the matching network
as
ωo =1
√
(Lg + Ls)Ct
(4.6)
In addition to the MOS transistor’s intrinsic gate-source capacitance Cgs, another
capacitor Cmim is added between the gate and source for noise consideration (not
shown in Fig. 45). Ct is the total capacitance between the gate and source and
Ct = Cgs + Cmim (4.7)
At ωo the LNA is matched to the source impedance Rs and
Rs =gmCt
Ls = 50Ω (4.8)
The input matching network’s Q can be expressed as
Q =1
2ωoCtRs
=1
2ωoLsgm(4.9)
In the above equations, gm is the transconductance of M1and M2, Lg is the required
gate inductance implemented using bonding wire.
Now the proper Q value should be determined and the considerations about
input Q is elaborated as follows. The RF filter before the LNA requires a certain load
91
termination, which is the input impedance of the LNA, for maximum power transfer
and low sensitivity, and its performance is only guaranteed for a given tolerance for
this termination impedance, for example, between 25Ω and 100Ω. The variation in
the reactance part of the matching network can also cause serious variation of the
RF filter gain and pass band ripple. In order to maintain small variations in the
impedance and reactance of the matching network, its Q value can not be too large,
although a large Q is beneficial for low current consumption. Also large Q tends to
degrade the linearity of the input stage, because the Q is also the voltage gain of the
matching network, the input referred IIP3 will be reduced by a factor of Q. So the Q
value is usually chosen to be 2-3 [29].
From (4.9), the required total gate-source capacitance for a specific Q can be
calculated using
Ct =1
2ωoRsQ(4.10)
As stated above, the Ct is composed of gate-source capacitance Cgs of M1 (M2)
and an MiM capacitance Cmim. The addition of Cmim helps to optimize the noise
performance and will be explained in further detail [11].
Fig. 46 shows the differential half circuit schematic (a) and small signal noise
equivalent circuit (b) of the LNA. Here the cascoded bipolar transistors have minor
influence on the noise behavior of the LNA, therefore its contribution to the total
noise is discarded in the small signal circuit.
The capacitance Ct affects the output noise current through the gate induced
noise current in,g. Gate induced noise power can be expressed as
i2n,g = 4kTβ(ωCgs)
2
gdo∆f (4.11)
where gdo is the transistor M1’s output conductance for zero drain-source voltage, β
92
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D EGF H B -JI;1B
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D EKF H9
D EKF A 2 AGBO P
D EGF 9Q I
=SR?
Fig. 46. Noise optimization
is the gate induced current noise factor and is about 415
for long channel devices.
From the above discussions about the choice of the input quality factor, it is
established that Q should be relatively small. However, in order to keep Q small,
from (4.9), it is necessary to have large Ct. If all the capacitance is provided by the
transistor’s gate-source capacitance Cgs, the gate induced noise current will be quite
large, since the gate induced noise grows with the square of Cgs, which can be easily
seen from (4.11). Splitting Ct into Cgs and Cmim decouples Q from Cgs which allows
for an adjustable reduction of Q for any given value of Cgs.
The effect of adding Cmim can be further explained as follows. The output noise
current due to gate induced noise current in,g is
in,o,g =gm
jωoCt
jRsωoCt − 1
j2RsωoCt
in,g (4.12)
93
From (4.12) and (4.11) , one can obtain
i2n,o,g∆f
≈ kTβ
gdo
(
ω
ωo
)2g2m
R2s (ωoCt)2
(
Cgs
Cgs + Cmim
)2
∝ P 2 (4.13)
where P has been defined as
P ≡ Cgs
Ct
=Cgs
Cgs + Cmim
(4.14)
The total capacitance Ct is determined by Q through (4.9). Thus, by adding Cmim
and keeping Ct fixed, the output noise current originated from the gate induced noise
current is reduced by a factor of 1P.
The noise factor of Fig. 46(b) is [11]
F = 1 + aQ2W3
2 +a
4W
3
2 + bQ−2W− 1
2 (4.15)
where a and b are constant determined by the length of the transistor M1, process
parameters such as µeffCox and bias current.
For a fixed Q, there exists an optimal value for W , which can be obtained by
taking the first order derivative of (4.15) in respect to W and equating it to zero.
Wopt =Ab
2Q2
√
5
6
143ωoRsCoxL
(4.16)
where Ab is the bulk charge factor [30].
Now that the size of the transistor is known from (4.16), Cgs can be calculated
from
Cgs =2
3CoxWoptL (4.17)
Ct has already been fixed by Q, so the required additional capacitance, Cmim, can
be found through (4.7). The gm of M1 can be fixed from the gain specification of
the LNA, then the degeneration inductance Ls will be obtained by (4.8). Finally the
94
biasing condition and current consumption can be determined.
After fine tuning through simulation, the width of M1 and M2 was fixed to be
96µm which was laid out by 24 fingers. The additional capacitance Cmim is 277 fF and
Cgs is 140 fF for the size of the transistor mentioned above. The transconductance
at the operating frequency of 2.4 GHz band is about 11 mA/V. The degeneration
inductance Ls is 1 nH and the required gate inductance Lg is about 10 nH, which will
be implemented by the bonding wire and off-chip surface mount inductors. It can be
verified that the input impedance is about 26Ω for the half-circuit shown in Fig. 46.
So the differential input impedance is about 50Ω as required.
M T ,M UQ T ,Q U
Gain S.W.
L V L V
L WL W
G G GSS
Fig. 47. LNA layout
Fig. 47 is the layout. Its area is 570 × 580µm2. In the layout, interdigitate
95
and common-centroid techniques are used for transistor M1 and M2 to achieve good
matching [31]. The differential input pads are formed into a G-S-G-S-G pattern to
provide decoupling between each other.
-0.2
0
0.2
0.4
0.6
0.8
1
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4Normalized spacing (µm)
Coup
ling f
actor
Fig. 48. Coupling factor between two shifted spirals
One can follow the LNA design flow given in Fig. 15, Chapter II. A single-ended
LNA is designed first then transformed to the differential form by duplicating it and
adding a tail current source.
It is worth mention that, for the differential structure, the two source degenera-
tion inductors and two load inductors should be placed apart enough to avoid mutual
coupling. In order to obtain a quantitative knowledge about the coupling effect, the
mutual coupling factor k between two inductors in adjacent metal layers is simulated
using ASITIC [32]. The studied inductors are octagon spirals with a radius of 100µm,
metal spacing of 2µm and metal width of 8µm. One of the inductors is laid out using
metal layer 4, the other using metal layer 3. These two inductors are first put one on
top of the other, then they are shifted apart. Mutual coupling factors (k = M√L1L2
,
96
M is the mutual inductance between L1 and L2) are calculated for different shifting
and are plotted in Fig. 48. The x-axis is the normalized spacing and is defined by the
spacing from center to center of the two spirals divided by the diameter of the spiral.
When the two spirals are completely overlapped, k is greater than 0.9 showing strong
coupling. Coupling is reduced with the increment of normalized spacing. There exists
a specific point where k equals to zero. After this point, k will increase with opposite
polarity and will reach an extremum. When the normalized spacing is 1, the two
spirals are shifted apart without any overlapping. The absolute value of the coupling
factor k for this configuration is about 0.03, which is already small enough. With the
two spirals shifting further apart, the coupling factor becomes gradually smaller.
It can be seen from the above study that as long as the two spirals are put apart
greater than 1.2 times of their diameter, the coupling can be reduced to a negligible
value. In Fig. 47, the minimum normalized spacing among the four inductors is 2.6.
Table X summarizes the simulation results of the LNA.
Table X. Chameleon LNA simulation results
Parameter Value Unit
S21 15/-15 dB
NF 1.6 dB
IIP3 -3 dBm
S11 <-20 dB
Pd 16 mW
97
2. Mixer Implementation
The mixer shown in Fig. 49 is a fully differential Gilbert-cell based structure with I
and Q branches sharing the same RF drive stage, therefore eliminating the RF drive
stage mismatch compared to the conventional two separated I/Q mixers. The cur-
rent commutating switches are NPN bipolar transistors which require less LO power
than NMOS transistor switch pairs. This relaxes the required LO cross-coupling and
isolation performance. Bipolar switching pair also has lower flicker noise than their
NMOS counterpart. In addition, the bipolar transistors provide a higher fT , which is
required in order to achieve symmetrical on-off switching. This helps to minimize the
second-order distortion caused by a non-ideal LO signal duty circle [33]. The RF driv-
ing stage uses NMOS transistors for high linearity. A further detailed discussion [34]
of the LO leakage mechanism of the I/Q mixer is given as follows.
X YZX [ \]^ _ `Ga
X YZb[ \ b
cdd
eY ]_ f gih gkj
b h b j blbm bonbp bqrbs
et
eu ueu u
et et et
[ \ X
_ v_ wx]^ _ `Gaeu ueu u
eu ueu u
g l
Fig. 49. Mixer for BT/Wi-Fi receiver
When there is no RF signal, due to the large LO signal, the voltage waveform
98
at the drain of M1 or M2 has a significant swing and it changes four times faster
than that of the LO signal. Comparing with the case of using two separate mixers,
the voltage swing at the drain of M1 or M2 is also much smaller. This is shown
in Fig. 50. Therefore, a signal with four times the LO frequency will leak into the
mixer’s RF input port through capacitive coupling (Cgd, Cgs). Because this leakage
is at high frequency and its amplitude is about 10 times smaller than that of the two
separate mixer configuration, it will not cause problem. Due to device mismatch,
this high frequency signal will also appear at IF port but will be filtered out by the
load capacitance. Fig. 51 is the mixer layout view. Table XI summarizes the mixer’s
simulation results.
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z y ~ z
Z Z
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» ¡¢¼£¢¤¥
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Fig. 50. Waveforms at switching pair common emitters
99
Fig. 51. Mixer layout
Table XI. Chameleon Mixer simulation results
Parameter Value Unit
Conversion Gain 19 dB
DSB. NF 10.6 dB
IIP3 +2 dBm
LO drive -10 dBm
Pd 8.8 mW
100
The design flow of the mixer can be generally followed as shown in Fig. 37,
Chapter III. The differences are 1) the current switching pairs are formed by bipolar
transistors here, their sizes are chosen just large enough to accommodate the current
following through them, which helps to reduce the parasitics at the drain of the RF
drive MOS transistors; 2) There is no bleeding current source in this implementation.
3. PTAT Biasing Circuit
The RF driving stage of the LNA and mixer are all NMOS transistors. The threshold
voltage of a MOS device tends to have a temperature coefficient in the magnitude
around −2mV/oC, like the bipolar transistor base-emitter voltage VBE. The carrier
mobility is also temperature dependent and it tends to dominate the temperature
behavior of a MOS transistor due to its exponential nature as shown in (4.18).
µ (T ) ≈ µ0
(
T
T0
)− 3
2
(4.18)
where µ0 is the mobility at reference temperature T0. The transconductance gm of a
MOS transistor is proportional to µ (T ). With the increment of temperature, carrier
mobility decreases, so does the gm. This can be seen more easily by considering
the MOS gm expression in the first order I-V approximation, i.e. the square law
ID = Kn (VGS − Vth)2 asgm = 2Kn (VGS − Vth)
= 2√KnID
(4.19)
where Kn = 12µ (T )Cox
WLeff
. So It can be derived from (4.19) and (4.18) that
gm ∝√
IDT 3/2
(4.20)
In order to combat the temperature-induced gm reduction, the bias current
IDshould be increased with temperature. It is not easy to implement the 32expo-
101
nential increment of ID, while a linear increment is implemented using PTAT (Pro-
portional To Absolute Temperature) current source [35]. Fig. 52 is the simplified
schematic of the biasing scheme for the proposed RF front-end.
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æèçKé æêçGë ÄìíîæêçGë ÄìïÄðæêçGë Äìñ òóôõZõ
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Ê<ø
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Ê ÂÂ
Á ÌÁ ÎÁ Í
úúû ×
úúû × üý úû ×úþû ×ÿ ý û ×
Fig. 52. Bias circuit for the RF front-end
Q1 (Q1A and Q1B in parallel), Q2, M1 ∼ M4 and REE form the PTAT current
source. Q1A, Q1B and Q2 have the same emitter area AE. The current mirror formed
by M1 ∼ M4 forces the current flowing through transistor Q1 to be the same as the
current flowing through Q2. This current is noted as IPTAT and assumes the satura-
tion current density of Q1 and Q2 is Jo, then the base-emitter voltage of transistor
Q1 and Q2 can be written as
VBE1 =kT
qlnIPTAT2AEJo
(4.21)
VBE2 =kT
qlnIPTATAEJo
(4.22)
The voltage developed across resistor REE can be obtained by subtracting (4.21)
102
from (4.22)
∆VBE = VBE2 − VBE1 =kT
qln 2 (4.23)
This voltage is proportional to absolute temperature. If the temperature coefficient
of resistor REE can be neglected, then the PTAT current IPTAT is given by
IPTAT =VtREE
ln 2 (4.24)
where Vt =kTq. For the REE value shown in Fig. 52, the nominal current at 298K
ambient temperature is about 52µA. All the other currents and voltages are derived
from this source. VLNA bypass is the control terminal to turn off LNA and put it into
attenuation mode.
From the above discussions, the biasing circuit can be designed as following.
First the current mirroring ratios are chosen. These ratios are usually less than 10.
Too small value will increase the power consumption of the biasing circuit, while too
large value will degrade the current mirroring accuracy. For the LNA, this ratio is
4 and for mixer, this ratio is 8. Secondly, the PTAT current IPTAT is known from
the current of the LNA and mixer, and the mirroring ratios. The required emitter
resistor REE, can be calculated from (4.24). The third step is to chose proper value of
resistors to generate all the required bias voltage. Finally, a start-up circuit is added
to ensure the correct operation status of the PTAT current source and a control circuit
is also inserted to turn on and off the LNA bias current. Table XII shows the nominal
biasing voltages and currents for the RF front-end.
Table XII. RF front-end nominal biasing condition
Bias point Ibuffer Imixer ILNA VLO VLNA RF VLNA CAS
Value 12.8µA 410µA 2mA 1.6V 1.4V 2.2V
103
D. Layout and Experimental Results
The RF front-end was fabricated using IBM 0.25µm SiGe BiCMOS technology through
MOSIS. A die photo is shown in Fig. 53. The area of RF front-end is 740 × 770µm2,
not including bond pads. Deep trench and substrate contact rings are placed around
the front-end as indicated in Fig. 54. There are two layers of deep trench. The
substrate contact ring is connect to a quiet ground. This arrangement improves the
substrate noise isolation from the other part of the die.
Fig. 53. Die photo of the front-end
Substratecontact ring
2 layers of deep trench
Fig. 54. Substrate noise isolation by deep trenches and guard rings
104
The testing board photo is shown in Fig. 55. This is the board for the whole
dual-mode Bluetooth/Wi-Fi receiver with accessible mixer output. The LNA input
SMA connector is put as close to the chip as possible. This is why there is a cut-in at
the left edge of the board. The PCB is fabricated using FR4 material with a thickness
of 0.031”. This FR4 material is relatively less costly than dedicated high frequency
lamination materials, and the thin thickness of the board makes the 50Ωand 25Ω
transmission line width manageable.
LNA input
Mixer I and Qbranch output
Differential to single-ended buffers
Powe
r sup
plies f
or LN
A,mi
xer a
nd bi
as cir
cuit
Fig. 55. RF front-end test board
The input impedance matching condition was checked using a network S-parameter
analyzer HP8719ES. The testing setup is presented in Fig. 56, and the testing results
are shown in Fig. 57 for high gain mode and Fig. 58 for low gain mode. In both cases
the matching is better than -11 dB.
105
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02135476
Fig. 56. Testing setup for input match
Fig. 57. Input matching for high gain mode
106
Fig. 58. Input matching for low gain mode
The intermodulation performance of the front-end was tested within the whole
receiver using the two-tone test method. Fig. 59 shows the instrumental setup. Two
signal generators SMIQ03 are used to generate the two testing tones. The two tones
are then combined by a power combiner and fed into the LNA’s input. The output
spectrum is observed by the spectrum analyzer FSEB30 from the VGA output with
the VGA gain setting of 12 dB.
The IIP3 curve in Wi-Fi mode is plotted in Fig. 60. The two tones are applied
at 12 MHz and 25 MHz away from same side of the LO frequency respectively when
the LNA is in high gain mode. The measured IIP3 is -13 dBm.
Fig. 61 shows the IIP2 plot. The two tones are applied at 12.2 MHz and 12.8 MHz
away from same side of LO tone and the measured IIP2 is 10 dBm. These values
meet the system specifications and indicate that the front-end performed as designed.
107
89:7;*<=
>?A@ B*CED!F,GIH89:7;*<=
J 8KL=A<M/NOQPR>
SEDATU?GV DWXC,Y ZE?G
Fig. 59. Testing setup for IIP3 and IIP2 measurement
-50 -45 -40 -35 -30 -25 -20 -15 -10-80
-60
-40
-20
0
20
40
60
2-Tone Input Power (dBm)
Out
put (
dBm
)
IIP3=-13dBm
Fig. 60. IIP3 plot for 2-tone test at 12MHz and 25MHz offset
108
-60 -50 -40 -30 -20 -10 0 10 20
-60
-40
-20
0
20
40
60
80
2-Tone Input Power [dBm]
Out
put (
dBm
)
IIP2=10dBm
Fig. 61. IIP2 plot for 2-tone test at 12.2MHz and 12.8MHz offset
The I and Q branch matching performance testing setup is shown in Fig. 62.
The input signal is swept to cover from 1 MHz to 10 MHz IF frequency range. The I
and Q branch’s amplitude and phase difference is observed by putting vector network
analyzer HP89140 into vector mode and looking at the amplitude and phase response.
[\U]7^*_`
abEc,d2e3f _
gh!ijlknm,o,prqs2tvu w,x!yzj
] t&myzjx,yzj
Fig. 62. I/Q mismatch measurement
The measured mismatch between I and Q outputs of the mixer across 10 MHz
109
IF frequency range is shown in Fig. 63. It shows that the amplitude mismatch is less
than 1.2 dB, and phase mismatch is within 3.8 degrees. In the Bluetooth mode (up
to 1 MHz) the phase mismatch is as large as 3.5 degrees and the amplitude mismatch
0.96 dB. For the Wi-Fi mode (up to 6MHz), the phase mismatch is smaller than
3.5 degrees and the amplitude mismatch smaller than 1 dB. The demodulator’s SNR
degradation due to the I/Q mismatch is less than 0.2 dB in both cases.
0.920.940.960.98
11.021.041.061.081.1
1.12
1 2 3 4 5 6 7 8 9 100
0.5
1
1.5
2
2.5
3
3.5
4
Ampli
tude m
ismatc
h (dB
)
Phase
mism
atch (
)o C
IF Frequency (MHz)
Fig. 63. I-Q mismatch performance
The noise figure and conversion gain measurement can be performed by using the
spectrum analyzer FSEB30 from Rohde & Schwarz and noise source NC346B form
Noise/COM. The testing setup is shown in Fig. 64. Before the actual measurement,
the instruments are setup for calibration, then the front-end test board is inserted
into the testing chain. Testing is automated by software supplied with the spectrum
analyzer. The measured conversion gain is about 33 dB and noise figure is 5.5 dB
across 10 MHz IF frequency range. Table XIII summarizes the measurement results.
110
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3A A
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°±z²³´zµn¶n· ¸
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Fig. 64. Testing setup for noise figure and conversion gain
Table XIII. RF front-end measurement results
Parameters Value Unit
Voltage gain 33 dB
IIP3 -13 dBm
Vdd 2.5 V
Current 13.6 mA
IIP2 10 dBm
NF 5.5 dB
S11 < -11 dB
Phase mismatch < 3.8 degree
Amp. mismatch <1.2 dB
111
CHAPTER V
LNA LINEARIZATION TECHNIQUES
Linearity is a key issue in RF systems. A circuit’s non-linearity causes many problems
such as inter-modulation and gain compression. The development of micro-processor
technique makes the CMOS process much cheaper than the others. The system-
on-chip target, also demands CMOS technology. For the same current consumption,
NMOS transistors are more linear than bipolar transistors. Still, the linearity of MOS
transistors can not meet the stringent requirements of state-of-the-art applications
such as CDMA/AMPS. For example [36], in the IS-98 CDMA standard, the IIP3 of
the LNA is set by the single-tone desensitization requirement:
IIP3 ≥ 59.5− LTX−RX + LTX [dBm] (5.1)
where LTX−RX is the duplexer TX-RX isolation in TX band and LTX is the duplexer
TX-antenna insertion loss. Typically, LTX−RX is about 53 dB and LTX is about
2.7 dB, which requires the LNA’s IIP3 to be better than +9.2 dBm.
Linearity based on negative feedback is not suitable for high frequency applica-
tions due to stability issues and gain reduction. Thus, a lot of linearization techniques
that focus on linearizing MOSFET transistors are introduced. The basic idea of lin-
earization here is to use an additional transistor’s non-linearity to compensate or
cancel the nonlinearity of the main operation device using a feed-forward technique.
The conventional way involves MOS transistors working in triode or weak inversion
to provide linearization. With the development of technology, bipolar is available
in CMOS technology. Although its performance is not as good as that in BiCMOS
process, it is sufficient to provide linearization. The proposed linearization technique
112
is derived from multi-gated linearization. A time-invariant memoryless system can be
represented using a Taylor series. Volterra analysis should be applied to non-linear
systems with memory effect. Based on the non-linearity analysis, the techniques for
linearizing the LNA will be introduced, and then the proposed linearization technique
using hybrid transistors, i.e. using both MOS and BJT is discussed in details.
A. Non-Linearity Analysis
1. Non-Linear System Representations
For a memoryless non-linear circuit or system, its transfer function can be represented
by Taylor series:
y =+∞∑
k=0
akxk
= a0 + a1x+ a2x2 + a3x
3 + . . .
(5.2)
The system non-linearity is usually characterized through the two-tone test. Sup-
pose the two testing signals are two sinusoids with the same amplitudes and different
frequencies: x1 = A cos (ω1t) and x2 = A cos (ω2t). Substituting x = x1 + x2 into
(5.2), it is easy to shown that the linear term (x1 + x2) of the two-tone test is
A cosω1t+ A cosω2t (5.3)
the 2nd-order term (x1 + x2)2 can be shown as
A2 + 12A2 cos 2ω1t+
12A2 cos 2ω2t
+ A2 cos (ω1 − ω2) t+ A2 cos (ω1 + ω2) t(5.4)
113
and the 3rd-order term (x1 + x2)3 can be expended into
94cosω1t+
94cosω2t
+ 14cos 3ω1t+
14cos 3ω2t
+ 34cos (2ω1 − ω2) t+ 3
4cos (2ω2 − ω1) t
+ 34cos (2ω1 + ω2) t+
34cos (2ω2 + ω1) t
× A3 (5.5)
The 3rd-order intermodulation (IM3) is one of the most important considerations
in the RF small signal amplifier design. The 3rd order intermodulation component
is contributed by the odd-order nonlinearities. The major contribution comes from
the 3rd-order term (x1 + x2)3 in the Taylor series. But the higher odd-order terms
also have contribution, especially when 3rd order cancellation techniques are used,
the 5th-order contribution may be pronounced. The (x1 + x2)5 term contributes to
the fundamental, 3rd-order and 5th-order intermodulation components as follow:
254cosω1t+
254cosω2t
+ 258cos (2ω1 − ω2) t+ 25
8cos (2ω2 − ω1) t
+ 58cos (3ω1 − 2ω2) t+
58cos (3ω2 − 2ω1) t
× A5 (5.6)
Higher than 5th-order non-linearities usually have less contributions and will generally
be ignored.
Fig. 65 summarizes the frequency components of the two-tone test as mentioned
above. For the 3rd-order and 5th-order terms, only the fundamental and intermodula-
tion components are shown in the figure. Notice that odd-order nonlinearities generate
spurs around the fundamental and compress or expand the fundamental amplitude.
Even-order nonlinearities can generate DC and low frequency components which may
change the DC biasing point of the circuits.
If the system has memory effect, its Taylor expansion should be replaced by
114
1 1
11/2 1/2
DC
1 1
( )211 xxa + Aa1×
22Aa×
( )2212 xxa +
1ω 2ω
12 ωω − 22ω12ω12 ωω +
9/4 9/4
3/4 3/4 33Aa×( )3213 xxa +
3rd-order:Fundamental and
intermod components
1ω 2ω122 ωω −212 ωω −
25/4 25/4
25/8 55Aa×
( )5215 xxa + 5th-order:Fundamental and
intermod components
1ω 2ω
122 ωω −212 ωω −
2nd order
25/8
21 23 ωω − 12 23 ωω −
5/8 5/8
Fig. 65. Frequency components in two-tone test
115
Volterra series (see Appendix B):
y =+∞∑
k=0
Hk (ω1, ω2, · · · , ωk) xk
= H0 +H1 (ω1) x+H2 (ω1, ω2) x2 +H3 (ω1, ω2, ω3) x3 + . . .
(5.7)
where Hk (ω1, ω2, · · · , ωk) is called Volterra kernel. The DC term H0 can be obtained
from Taylor expansion and will be dropped for AC analysis. The operator “” means
that the magnitude and phase of each frequency term in xk is to be changed by
the magnitude and phase of Hk (ω1, ω2, · · · , ωk) [37]. The Taylor series only shows
the low frequency effect (or the amplitude) of circuit non-linearity for a circuit with
memory, while Volterra series contains both amplitude and phase information. For
a general non-linear system, the locations of frequency components are the same as
depicted in Fig. 65, but their amplitudes and phases will be functions of frequency ω1
and ω2. The rest of the text in this section will obverse several non-linearity effects
using Volterra or Taylor notations.
2. Non-Linearity of Fully Differential Circuits
For a fully-differential circuit, assume its two inputs are x1 = x and x2 = −x, then
keeping up to 5th-order non-linearity terms, its two outputs will be
yo1 (x1) = H1 x+H2 x2 +H3 x3 +H4 x4 +H5 x5 (5.8)
and
yo2 (x2) = −H1 x+H2 x2 −H3 x3 +H4 x4 −H5 x5 (5.9)
The differential output will be
yo = yo1 − yo2 = 2(
H1 x+H3 x3 +H5 x5)
(5.10)
116
So a perfect fully-differential circuit does not have even-order terms in its differ-
ential output. But in reality, there will be asymmetry in the circuit. This can be the
mismatch between two signal paths or the input signals itself are not fully-balanced.
This effect can always be modeled by a DC offset ∆ at the input signal as x1 = x+∆
and x2 = −x. Under this condition, the differential output can be shown to be
yo ≈ 2 (H1 x+H3 x3 +H5 x5)
+ H1∆+ (2H2 x+ 3H3 x2 + 4H4 x3 + 5H5 x4)(5.11)
It can be seen that input signal offset or system mismatch will cause the dif-
ferential output not only having DC offset H1∆ but also the even-order terms. The
output DC offset is also a function of frequency because H1 is generally frequency
dependent.
3. IM3 Due to 5th-Order and 2nd-Order Non-Linearity
IM3 is directly generated by 3rd-order non-linearity of the system but higher odd-
order nonlinearities also have contribution to IM3. For example, in Fig. 65 the fifth-
order nonlinearity term can also generate an IM3 term and cause the IM3 curve to
deviate from 3:1 slope.
At small signal amplitude, when 5th-order effects can be ignored, the amplitudes
of the IM3 terms are proportional to the 3rd power of the input amplitude. If the
signal amplitude is significantly large, however, 5th-order distortion will start to affect
the IM3 responses. When some of the 3rd-order non-linearity cancellation techniques
are used to reduce the 3rd-order distortion, the IM3 curve usually deviates from
the 3:1 slope for a moderately large input signal. The curve will compress or expand
determined by the phase of the fifth-order term. If the phases of the 3rd and 5th order
coefficients are coherent, 5th-order distortion will expand the IM3 curve, whereas if
117
the phases are opposite, the IM3 curve will be compressed.
Second-order non-linearity contributes to IM3 indirectly through feedback in the
non-linear system. Specifically, the second-order components 2ω1, 2ω2 and ω1 ± ω2
feedback to the input of the system (through Cgd of MOS transistor, e.g.) and mixed
with the fundamentals again to generate 3rd-order terms. The IM3 term contributed
by the 3rd-order distortion and second-order distortion can be written using Volterra
series coefficients sun as
IM3 (2ω1 − ω2) = 34H3 (ω1, ω1, −ω2)X (ω1)X (ω1)X
∗ (ω2)
+ H2 (ω1, ω1 − ω2)X (ω1)X∗ (ω2 − ω1)
+ H2 (−ω2, 2ω1)X∗ (ω2)X (2ω1)
(5.12)
IM3 (2ω2 − ω1) = 34H3 (ω2, ω2, −ω1)X (ω2)X (ω2)X
∗ (ω1)
+ H2 (ω2, ω2 − ω1)X (ω2)X (ω2 − ω1)
+ H2 (−ω1, 2ω2)X∗ (ω1)X (2ω2)
(5.13)
where Hn is the n-th order Volterra kernel, n = 2, 3. X(ωk) represents the input
two tones in frequency domain, k = 1, 2. X (2ω1), X (2ω2) and X (ω2 − ω1) are the
second-order intermodulation terms feeded back to the input of the system. X∗ (ω) is
the complex conjugate of X (ω). Fig. 66 shows how the envelope terms and harmonics
of the second-order distortion contribute to IM3 terms.
Quite often one may observe that the IM3 response at 2ω1 − ω2 and 2ω2 − ω1
are asymmetric in amplitudes. Suppose equal amplitudes in the two-tone test input
signals at ω1and ω2, non-linear terms caused by 3rd-order distortion H3 in the first
term of (5.12) and (5.13) usually match each other. Asymmetry arises from the facts
that i) the envelop term X (ω2 − ω1) appears in opposite phase in the lower and upper
sidebands, which is clear from the complex conjugate operation in the second term of
(5.12) and (5.13), and ii) the response of fundamental tones may be different. This
118
1ω 2ω122 ωω −212 ωω −
22ω12ω
12 ωω +DC
12 ωω −21 ωω −
1ω 2ω1ω−2ω−
Fig. 66. Second-order distortion contributing to IM3 terms
usually is not the case because a flat pass band is generally desired for fundamentals.
But the 2nd-order harmonics X (2ω1) and X (2ω2) in the third term of (5.12) and
(5.13) are already far away from each other and further away from the pass band, so
their response can be quite different.
4. Non-Linearity Due to Output Impedance
For a MOS transistor, non-linearity is largely introduced by the non-linear behavior
of its transconductance, but its output impedance is also non-linear and contributes
to distortion. At low frequency, the circuit can be assumed to be memoryless and
Taylor analysis can be applied.
To start, write the MOS transistor’s small signal output impedance as
rout =1
λID(5.14)
119
where λ = 1VA, VA is Early voltage. ID is drain current. If the drain current contains
DC term IDQ and AC term io, then
rout =1
λ (IDQ + io)(5.15)
Assume rout dominates the output AC impedance, thus the output voltage due to
this impedance is
vo = iorout =io
λ (IDQ + io)=
1
λ
io/IDQ1 + io/IDQ
(5.16)
It is known for |x| < 1, x1+x
= x−x2+x3−x4+x5+ . . .. Usually∣
∣
∣
ioIDQ
∣
∣
∣< 1, thus
vo ≈ ro
(
io −1
IDQi2o +
1
I2DQi3o
)
= β1io + β2i2o + β3i
3o (5.17)
where ro =1
λIDQ, β1 = ro, β2 = −λr2o, β3 = λ2r3o. The output AC current io can be
related to the input voltage vi by
io = −Gm (vi) ≈ −[
α1vi + α2v2i + α3v
3i
]
(5.18)
where α1 = gm = KVod2+θVod1+θVod
, α2 =K
(1+θVod)3 , α3 =
−θK(1+θVod)
4 .
From (5.17) and (5.18), one can arrive at
vo = −α1β1vi −(
α2β1 + α21β2)
v2i −(
α3β1 + 2α1α2β2 + α31β3)
v3i
or
vo = −Avvi +[
λA2v − α2ro]
v2i +[
2λα2Avro − λ2A3v − α3ro]
v3i (5.19)
where Av = α1β1 = gmro. If the non-linearity induced by output impedance can be
ignored, i.e. λ ∼ 0 then
vo = −AV vi − α2rov2i − α3rov3i (5.20)
120
Compare (5.19) and (5.20) the total nonlinearity term may be improved or de-
graded depending on the sign and relative value of the terms contributed from output
impedance non-linearity. If the output of the transistor is loaded by an additional
impedance ZL which is linear and |ZL| ¿ rout, then the total output impedance
can be approximated by ZLand the input Gm non-linearity dominates the overall
non-linearity behavior.
ÉÊËÌÍÏÎÐÒÑ
Ó Ô Ó ÔÕÕÀÖ×Õ ØÙØÚÛ ÜÝÝÞ ßà
áâ ãä
Fig. 67. Load non-linearity large signal model
At high frequency, the load impedance will be dominated by the load capacitance,
thus memory effect can not be ignored. The output voltage should be expressed using
Volterra series:
vo = H0 +H1 vi +H2 v2i +H3 v3i + · · · (5.21)
Fig. 67 illustrates the large signal model of the circuit under consideration. For
simplicity and clarity, it is assumed that the MOS transistor is a long channel device
and has a large signal transfer function of
io = K (vi + Vod)2 (1 + λvo) (5.22)
where Vod = Vgs0 − Vth, Vth is transistor’s threshold voltage. The output voltage for
121
sinusoid inputs is
vo = −ioZL = −K (vi + Vod)2 (1 + λvo)ZL (5.23)
where ZL represents the impedance of RL and CL in parallel. Keep (5.21) up to
3rd-order term and substitute it into (5.23):
H0 +H1 vi+
H2 v2i +H3 v3i = D0 +D1vi +D2v2i
+ λD0 (Ho +H1 vi +H2 v2i +H3 v3i )
+ λD1 (Ho +H1 vi +H2 v2i +H3 v3i ) vi+ λD2 (Ho +H1 vi +H2 v2i +H3 v3i ) v2i
(5.24)
where
D0 = −KV 2odZL (5.25)
D1 = −2KVodZL (5.26)
D2 = −KZL (5.27)
In order to find the Volterra kernel Hk, equate the same order term of vi in both
sides of (5.24) and use the following relationships:
KV 2odRL ¿1
λ(5.28)
ωCL À1
RL
(5.29)
gm = 2KVod (5.30)
go = KλV 2od (5.31)
(5.28) holds because MOS transistor’s Early voltage is usually much greater than
its output DC voltage. (5.29) means the circuit’s output impedance is dominated
122
by the load capacitance at high frequency and the circuit has strong memory effect.
(5.30) and (5.31) are the linear small signal transconductance and output conductance
respectively. It can be found that
H0 =D0
1 + λD0≈ −KV 2odRL (1− goRL) (5.32)
H1 (ω) =1 + λH01 + λD0
D1 ≈ −gmjωCL
(1− goRL) (5.33)
H2 (ω1, ω2) =D2 + λ (D1H1 +D2H0)
1 + λD0≈ − K (1− goRL)
j (ω1 + ω2)CL
(5.34)
H3 (ω1, ω2, ω3) =λ (D1H2 +D2H1)
1 + λD0≈ −KλgmZ3 (ω1, ω2, ω3)
(ω1 + ω2 + ω3)C2L(5.35)
where Z3 (ω1, ω2, ω3) =13
(
1ω1+ω2
+ 1ω1+ω3
+ 1ω2+ω3
+ 1ω1
+ 1ω2
+ 1ω3
)
.
It can be shown by substituting gm = 2KVod, α2 = K and α3 = 0 into (5.19)
that the low frequency Taylor series of the circuit in Fig. 67 is
vo = −gmrovi + 3Krov2i − 2Kλgmr
2ov3i (5.36)
Here the DC term is dropped and it is assumed RL À ro. Notice that due to the
output capacitive loading, both the amplitude and phase of the non-linear term are
quite different from the case without memory effect.
5. Third-Order Distortion of Inductive Source-Degenerated LNA
Inductive source-degenerated LNA in CMOS technology is a very popular LNA struc-
ture. It handles the trade-off among input impedance matching, noise figure and gain
gracefully. This text will study the 3rd-order non-linearity of this type of LNA.
Figs. 68 are the schematic view (a) and equivalent circuit for non-linearity analy-
sis (b).
It is assumed that the dominant non-linearity comes from the transconductance
123
gL
sLsR
sv
dL dRdC
(a)
gsC
gdC
gsv
( )gsds vfi =
dL dRdC
3Z
2Z
gLsRsv
1Z
(b)
Fig. 68. Inductive degenerated CMOS LNA
gm of the LNA core device, here the MOS transistor. The drain AC current can be
expanded using Taylor series up to 3rd-order term as
ids = f (vgs) = gmvgs + g2v2gs + g3v
3gs (5.37)
The distortion analysis for BJT was studied in [38], [39] using Volterra series. The
equations can be adapted for MOS transistors by noting that MOS transistors have
infinite DC current gain (β → ∞) and no base-emitter diffusion capacitance (τ =
0) [40]. In a two-tone test, the two tones are near each other, ω ≈ ω2 ≈ ω1, such
that their separation, ∆ω = ω2 − ω1, is much smaller than ω. Rs is the signal
source resistance. The IMD3 at drain node and the input referred IP3 power can be
expressed as
IMD3 =3
4· |H (ω)| · |A1 (ω)|3 · |ε (∆ω, 2ω)|A2s (5.38)
and
IIP3 (2ω2 − ω1) =1
6Rs · |H (ω)| · |A1 (ω)|3 · |ε (∆ω, 2ω)|(5.39)
124
where As is the amplitude of the testing tones and
H (ω) =1 + jωCgs [Z1 (ω) + Z2 (ω)] + jωCgdZ1 (ω)
gm − jωCgd [1 + Z2 (ω) (gm + jωCgs)](5.40)
A1 (ω) =1
gm + g (ω)
1 + jωCgdZ3 (ω)
Zx (ω)(5.41)
ε (∆ω, 2ω) = g3 − goB (∆ω, 2ω) (5.42)
goB (∆ω, 2ω) =2
3g22
[
2
gm + g (∆ω)+
1
gm + g (2ω)
]
(5.43)
g (ω) =1 + jωCgd [Z1 (ω) + Z3 (ω)] + jωCgs [Z1 (ω) + Zx (ω)]
Zx (ω)(5.44)
Zx (ω) = Z2 (ω) + jωCgd [Z1 (ω)Z2 (ω) + Z1 (ω)Z3 (ω) + Z2 (ω)Z3 (ω)] (5.45)
In the above equations, H (ω) relates the equivalent input IM3 voltage to the IM3
response of the drain current non-linear terms. A1 (ω) is the linear transfer function
from the input voltage vs to the gate-source voltage vgs. ε (∆ω, 2ω) shows how the
non-linear terms in (5.37) contribute to the 3rd-order distortion. The first term in
(5.42) comes from the 3rd-order non-linearity and the second term comes from the
2nd-order non-linearity as explained in (5.12) and (5.13). The 2nd-order feedback
paths here include the gate-drain capacitor and the degeneration inductor.
|H (ω)| and |A1 (ω)| depend on the in-band source and load impedances which are
usually selected to provide desired gain, noise figure and impedance match. Therefore
lower distortion is achieved by reducing |ε (∆ω, 2ω)|. If g3 dominates non-linearity
which is generally the case, reducing it can significantly improve IIP3. In a bipo-
lar LNA, out-of band termination or matching is usually used to make the term
|ε (∆ω, 2ω)| small thus IMD3 will be reduced. This is possible because g3 and goB
have the same sign for bipolar transistor. |ε (∆ω, 2ω)| is the difference between these
two quantities. By making g3 ≈ goB, |ε (∆ω, 2ω)| can be maintained at a pretty
small value. But for a MOS transistor, it will be shown later that g3 and goB have
125
different signs. More specifically, in the saturation region, since g3 is negative while
goB is positive, the only way to reduce |ε (∆ω, 2ω)| is to make both g3 and goB small
values.
So when g3 has already been reduced by the third-order cancellation technique,
it is also important to reduce goB by keeping g (∆ω) and g (2ω) large. It is assumed in
the above discussions that ∆ω is at a very low frequency. Therefore for the inductive
source-degenerated LNA, Z1 (∆ω) ≈ Rs, Z2 (∆ω) ≈ 0 and Z3∆ω ≈ 0. So g (∆ω) has
a very large value with respect to gm, and goB (∆ω, 2ω) can be approximated by
goB (∆ω, 2ω) ≈ goB (2ω) =2
3
g22gm + g (2ω)
(5.46)
If the load LC tank has a high enough quality factor, then Z3 (2ω) is a small quan-
tity and Z1 (2ω) = Rs + j2ωLg, Z2 (2ω) = j2ωLs. Under input impedance match
condition, ωTLs = gmCgs
Ls = Rs holds. Putting all these considerations together, it
can be shown that |g (2ω)| is proportional to 1ωLs
. So in order to have small goB,
one must select a small Ls, which means less degeneration. This is contrary to the
general belief that degeneration improves linearity. Actually, inductive degeneration
will degrade linearity. An additional out-of-band termination network can be added
at the input to make Z1 (2ω) ≈ 0 [39]. If a termination network is used, |g (2ω)|can be
about 2 ∼ 3 times larger. Therefore, IIP3 can have an improvement by at least 3 dB.
This |g (2ω)| increment assumes that the out-of-band termination network is added
directly at the gate of the MOS transistor, thus it has to be implemented on the chip.
In practice, this termination network can be implemented as a high Q LC parallel
tank resonant at ω, provides a very small impedance path to ground at frequency 2ω.
Its performance will be limited by the quality of inductors available in the process
and it will introduce additional noise, and probably affect the in-band impedance
match. So it is usually not desirable for the LNA design. Off-chip termination using
126
low loss quarter-wave transmission lines is another way, but the improvement will be
relatively small and is not worth the complexity, and added cost. To conclude, in
order to make a linear LNA, the 3rd-order coefficient g3 of the intrinsic transistor’s
Taylor series should be small and if possible, adding an out-of-band termination net-
work and/or using a smaller degeneration inductor will also help. The rest of this
chapter will study the techniques to provide a more linear LNA core circuit.
B. Theoretical Analysis of Multi-Gated Linearization Technique
The low noise amplifier (LNA) has stringent requirements on operation frequency,
noise, and linearity. Therefore, a LNA usually uses a minimum number of transis-
tors. For example, a single-ended LNA usually contains only one or two transistors in
its main signal path. In order to improve the LNA’s linearity, more components have
to be added into the signal path. Resistive degeneration and shunt-series feedback
are traditionally used, but they introduce additional noise and require more power. A
method based on multi-gated transistor (MGT) third-order non-linearity cancellation
is discussed in [41]-[44]. This method directly reduces the 3rd-order coefficient of a
LNA’s core devices. There is no theoretical analysis done on the previously reported
MGT. This section will explore the nature of the multi-gated linearization technique
and the later sections will present a different way to implement the 3rd-order inter-
modulation cancellation by using a hybrid structure, i.e. combining the MOS and
bipolar transistors available in a CMOS technology.
The input-output transfer characteristics of a MOS transistor can be expressed
using the Taylor series (5.2) and is repeated here by dropping DC and terms higher
than 3rd-order:
ids (vgs) = gmvgs + g2v2gs + g3v
3gs (5.47)
127
In order to obtain a large IIP3, gm should be kept almost unchanged or even larger
and try to reduce g3 and g2.
The transfer characteristics of a short channel MOS transistor that is valid in all
operation regions can be expressed as [45]
iDS = Kχ2
1 + θχ(5.48)
where
χ = 2ηφt ln(
1 + eVgs−Vth
2ηφt
)
(5.49)
Vth is the threshold voltage, φt is the thermal voltage kTq, µe is effective mobility
and K = 0.5µeCoxWL. θ approximately models source series resistance, mobility
degradation due to vertical E-field and velocity saturation effect. It is a function of
channel length and is independent of body effect. η is the rate of exponential increase
of drain current with gate-source voltage in the sub-threshold region and the size of
the moderate inversion region, which has values between 1 and 2 [45]. In moderate
or strong inversion, (5.48) reduces to
iDS = K(Vgs0 − Vth + vgs)
2
1 + θ (Vgs0 − Vth + vgs)(5.50)
Here the gate-source voltage is expressed as the sum of the a DC bias voltage Vgs0
and small signal AC voltage vgs, and Vod = Vgs0 − Vth is the gate source over-drive
voltage.
Expanding (5.50) using the Taylor series in terms of vgs and neglecting the DC
component and components higher than 3rd-order, the coefficients in (5.47) are de-
termined by
gm =KVod (2 + θVod)
(1 + θVod)2 , g2 =
K
(1 + θVod)3 , g3 = −
θK
(1 + θVod)4 (5.51)
128
The low frequency 3rd-order intercept point for the transistor in strong inversion is
A2IIP3,strong =4
3
Vodθ
(2 + θVod) (1 + θVod)2 (5.52)
and a lower bound can be found by assuming θVod is sufficiently small to be
A2IIP3,strong >8
3
Vodθ
(5.53)
In weak inversion, (5.48) can be reduced to
iDS = K (2ηφt)2 e
Vgs0−Vth+vgs
ηφt (5.54)
Further expressed in small signal term
ids = Is0evgsηφt (5.55)
where Is0 = K (2ηφt)2 e
Vodηφt . Treated the same way as in the strong inversion case, the
Taylor series coefficients of (5.54) are
gm =Is0ηφt
, g2 =Is0
2 (ηφt)2 , g3 =
Is0
6 (ηφt)3 (5.56)
and the 3rd-order intercept point is
AIIP3,weak = 2√2ηφt (5.57)
Fig. 69 shows the second and third-order terms of a NMOS transistor versus its
gate-source biasing levels. It can be easily seen that between the moderate/strong
and weak inversion, the 2nd-order term has the same sign, and both are positive.
The 3rd-order term has a different sign. In the moderate or strong inversion, it has
negative sign, and in the weak inversion it has a positive sign. In the moderate
inversion region, there is a point where the 3rd order term is zero. Of course, it is
very hard to bias a transistor exactly at this optimal point for minimum 3rd-order
129
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g÷ø ù
ú ûü÷
g
ýø ùú ûüý
g þg ÿ
g
g
ø ùú ûü
V
V
Fig. 69. MOS transistor 2nd-order and 3rd-order distortion terms
non-linearity. The alternative is to use two or more transistors and bias them at
different inversion regions and trim the size of the transistors such that the positive
term will cancel the negative term. This way, the minimum 3rd-order distortion is
achieved. [40]-[44] shows the idea of using multiple NMOS transistors connected in
parallel form and biased at different gate drive levels to achieve an extremely linear
device for RF circuit applications such as LNAs and power amplifiers.
The multi-gated configuration using two NMOS transistors is shown in Fig. 70.
TransistorM1 is the main transistor working in the strong inversion region. Transistor
M2 is the auxiliary device biased in the weak inversion region.
Fig. 71 shows the linearity (IIP3 and IIP2) versus bias voltage VBaux of the
auxiliary transistor. The main transistor is biased at 0.74 V. Notice that when the
bias voltage of the auxiliary transistor is around 0.5 ∼ 0.55V , the combined device
response has the best IIP3. The IIP3 improvement is about 10 dB compared to only
having transistor M1. Note that the linearity measurement here is for multi-gated
130
VBmain
VBauxRB
RB
Cc
Cc
RFIN M1
M2
Fig. 70. Multi-gated linearization using two NMOS transistors
transistors only. The observed output is the combined drain current. The actual
circuit using the multi-gated core will have less IIP3. The current consumption only
increases slightly because M2 is operating in the weak inversion.
6789
10111213141516
0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7678910111213141516
Auxilliary gate bias, VBaux (V)
IIP2IIP3
VBmain=0.74V
IIP3 (
dBm)
IIP2 (
dBm)
Fig. 71. NMOS multi-gated transistor linearity v.s. auxiliary bias voltage
Notice that the IIP2 almost has its worst value as demonstrated in Fig. 71. This
is due to the fact that for different gate biases, although the 3rd-order terms can have
different signs, so they can be canceled out by combining the current, the 2nd-order
131
terms will always have the same signs. By adding the output currents of the main and
auxiliary transistors, the 2nd-order term will be added constructively, deteriorating
the IIP2.
VBmain
VBauxRB
RB
Cc
Cc
RFIN
M3
VDD
VB
M1
M2
ids,n
ids,p
io
Fig. 72. Multi-gated linearization using NMOS and PMOS
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Fig. 73. Complementary multi-gated transistor linearity plot
By using PMOS instead of NMOS for the auxiliary transistor (complementary
multi-gated transistor, CMGT), IIP3 and IIP2 can be improved at the same time.
Fig. 72 illustrates this configuration. When the AC signal of the NMOS transistor
132
(M1) is increasing, the corresponding AC input signal of the PMOS transistor (M2)
will decrease. So if the input for M1 is vgs, the input for M2 will be −vgs. Thus if we
ignore the DC and higher order distortion terms, the output current of NMOS M1
and PMOS M2 can be written as
ids, n = gm,nvgs + g2, nv2gs + g3, nv
3gs (5.58)
ids, p = −gm, pvgs + g2, pv2gs − g3, pv3gs (5.59)
The overall output current of the CMGT is the difference between the currents of
those two transistors:
io = ids, n − ids, p= (gm,n + gm, p) vgs + (g2, n − g2, p) v2gs + (g3, n + g3, p) v
3gs
(5.60)
It is observed that as the total transconductance increases, the IM2 term de-
creases because g2, n and g2, p have the same sign, and the IM3 term decreases because
g3, n and g3, p have different signs as shown in (5.51) and (5.56). Fig. 73 shows the
IIP3 and IIP2 curves of the CMGT configuration. Because PMOS transistors have
an inferior performance compared to NMOS transistors, the IIP3 improvement is not
as significant as the NMOS MGT. It is also clear that the IIP2 and IIP3 do not share
the same optimal bias voltage. This is due to the different non-linear characteristics
of NMOS and PMOS transistors. If the future process can match the non-linear be-
havior and speed of NMOS and PMOS transistors, the linearity improvement will be
more significant.
Instead of making g3 small by using MGT and goB small by out-of-band termi-
nation, [47] proposed a method to change the phase and amplitude of the MGT’s
in-band g3 by tapping the degeneration inductor into the source of the transistor
working in the weak inversion. The consequence is that g3 is modified to match the
133
phase and amplitude of goB, therefore, an improved IIP3 is achieved.
C. Proposed Linearization Scheme Using BJTs in CMOS Process
1. Hybrid LNA: BJT as Auxiliary Transistor
Using a MOS transistor biased at weak inversion may have potential speed limita-
tions [48]. A new implementation method to cancel the IM3 term is proposed. The
goal is to keep the main transistor M1 in the strong or moderate inversion where its
IM3 has a negative sign and another transistor is added to provide a positive signed
IM3. Instead of using the MOS transistor M2 biased in its weak inversion, a bipolar
transistor Q2 is used. Fig. 74 depicts the configuration of the proposed LNA lin-
earization method (Hybrid LNA). This implementation requires both MOS and BJT
available in the process. BiCMOS is a natural choice, but in a specific RF CMOS
process, BJT is sometimes available as a byproduct. Although its performance can
not compete with that in a BiCMOS process, for linearization purposes, it may be
good enough. For example, in the TSMC 0.18µm RF CMOS process, a 2µm × 2µm
bipolar transistor biased at 11µA base current, its cut-off frequency fT is 28 GHz
and its βac is 22. A NMOS RF transistor with dimensions 185µm × 0.18µm biased
at 0.64V gate-source voltage has a cut-off frequency of about 30 GHz.
The current-voltage transfer function of a bipolar transistor can be expressed by
ice = IsoeVBEQ+vbe
φt = IQevbeφt (5.61)
where VBEQis the base-emitter bias voltage, Iso is the saturation current and IQ =
IsoeVBEQφt . Note that (5.61) resembles (5.55), so its 3rd-order term coefficient can be
obtained from (5.56) as
g3, bjt =g3m6I2Q
(5.62)
134
reRB1
RFIN
RB2
VBNPN
VBMOS
VDD
Ld RFOUT
Bond wire
Bipolar replaces NMOSat weak inversion.M1
Q2
Fig. 74. Bipolar as auxiliary transistor for 3rd-order linearization
From (5.51), NMOS transistor’s 3rd-order term coefficient in moderate/strong inver-
sion is
g3,mos = −θK
(1 + θVeff )4 (5.63)
It is observed from (5.62) and (5.63) that g3, bjt and g3,mos have different signs. If
their magnitudes are matched, the overall 3rd-order term can be canceled. Usually
the absolute value of the bipolar’s IM3 coefficient g3, bjt is much larger than that of the
NMOS transistor’s IM3 coefficient g3,mos. Therefore, g3, bjt needs to be scaled down
properly in order to provide maximum cancellation. This is achieved by resistive
emitter degeneration as shown in Fig. 74. Before one can continue, it is important to
show that the memory effect in the degenerated BJT is weak, so it does not change the
phase of the non-linear terms. For this purpose, Volterra analysis of the degenerated
BJT is carried out.
135
2. Volterra Analysis of Resistive-Degenerated BJT
Considering memory effect, the collector current io of an emitter-degenerated bipolar
transistor can be expanded using the Volterra series as:
io = B0 +B1 vi +B2 v2i +B3 v3i + · · · (5.64)
Where all the signal quantities are assumed to be in the sinusoidal form, e.g., io means
Aio cos (ωt+ φ). In order to calculate Volterra kernel Bk, a large signal high frequency
model is shown in Fig. 75. In this model, only the collector current non-linearity is
considered. The base current ib and resistor rb (as shown in the dashed box) are
ignored and all the capacitors are assumed linear. Base-collector capacitor Cµ will be
combined with the MOS transistor’s gate-drain capacitor Cgd, so it is excluded from
the model. The difference between the emitter and collector current is also ignored,
and Re is the degeneration resistor. A more strict analysis can be found in [38].
πCπv
ev
−=
t
eiQo
vvIi φexp
eR
oiiv
br
bi
µC
Fig. 75. Emitter-degenerated BJT large signal model
If the quiescent collector current is IQ then the dynamic collector current is
io = IQevi−veφt ≈ IQ
[
1 +vi − veφt
+1
2
(
vi − veφt
)2
+1
6
(
vi − veφt
)3
+ · · ·]
(5.65)
136
where vi and ve are AC signals. Using KCL at the emitter node:
(vi − ve) jωCπ + io = vege (5.66)
where ge = R−1e . Solving for ve and substituting it into (5.65) and replacing io by its
Volterra expansion (5.64):
B0 +B1 vi +B2 v2i +B3 v3i + · · · =
IQ
1 + 1It[−B0 + (ge −B1) vi −B2 v2i −B3 v3i + · · ·]
+ 12I2t
[−B0 + (ge −B1) vi −B2 v2i −B3 v3i + · · ·]2
+ 16I3t
[−B0 + (ge −B1) vi −B2 v2i −B3 v3i + · · ·]3+ · · ·
(5.67)
where It = φt (ge + jωCπ) = φtge (1 + jωCπRe). Bk can be solved by equating the
same order of vi at both sides of (5.67).
The zero-th order kernel or DC term B0 is
B0 = IQe− B0φtge (5.68)
It shows that B0 is smaller than the quiescent DC current IQ due to non-linearity.
φtge is usually at the magnitude of around 1mA while B0 is at the same magnitude
of IQ which is about several tens of µA. Therefore B0 can be approximated by
B0 ≈ IQ
(
1− IQIt0
)
≈ IQ (5.69)
where It0 = φtge.
The 1st-order or linear kernel B1can be shown to be
B1 (ω) ≈gm
1 + gmRe
(
1− j ωωπ
)
(5.70)
where ωπ = 2πfπ = geCπ
, gm =IQφt. Typically ge ≈ 0.05, Cπ ≈ 16fF , so fπ is at the
order of several hundreds of GHz and for moderate operating frequencies ωωπ
< 0.01
137
holds. Therefore, the phase angle of B1 is very small (no greater than 1 degree) and
for practical purposes, B1 can be treated as frequency independent.
The 2nd-order kernel B2 can be approximated by
B2 (ω1, ω2) ≈1
2IQ
g2m(1 + gmRe)
3
[
1− j 2 (ω1 + ω2)
ωπ
]
(5.71)
and its frequency dependence is also very weak.
The 3rd-order kernel B3 is
B3 (ω1, ω2, ω3) ≈1
6I2Q
g3m(1 + gmRe)
5 (1− 2gmRe)
[
1− j 3 (ω1 + ω2 + ω3)
ωπ
]
(5.72)
For the worst case ω1 = ω2 = ω3, the phase angle of B3 is no greater than 6 degrees.
Thus B3 can also be regarded as frequency independent. It should also be noticed
that if the degeneration resistance is chosen right, B3 can become zero or change
polarity.
The above derivations have justified the memory effect in the resistive-degenerated
BJT is very weak and can be ignored. Resistive degeneration can be used to scale
the magnitude of the 3rd-order coefficient to match that of MOSFET. In this case
(5.62) corresponds to
g3, bjt =1
6I2Q
g3m(1 + gmRe)
5 (1− 2gmRe) (5.73)
Fig. 76 compares the simulated 3rd-order coefficients obtained at DC to the one at
3 GHz. The theoretical curves for DC and 3 GHz actually overlap with each other
due to the extremely weak frequency independence. Because the theoretical analysis
does not consider the BJT’s base and emitter’s extrinsic resistance, so the theoretical
curves are shifted from the simulated ones, and the non-linearity predicted by the
theoretical curves is a little bit larger, but the trend is well predicted. Fig. 77 shows
the 3rd-order cancellation effect of the proposed hybrid configuration. The MOS and
138
BJT are biased separately and then their bias voltages are swept and their output
currents are used to calculate the 3rd-order terms.
-0.15
-0.10-0.05
0.000.05
0.10
0.150.20
0.25
0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00Bias voltage (V)
DC
3 GHz
DC & 3 GHz
Simulated
Theoretical(A/
V )3g 3
,NPN
Fig. 76. Resistive-degenerated BJT 3rd-order coefficient at DC and 3GHz
3. Input Matching and Noise Contributions
The input matching network can be designed using the inductive source-degeneration
technique [10]. The degeneration inductor will be implemented using bond wire.
The gate inductance will be implemented in part from the bond wire and the other
part from off-chip surface mount inductor. The on-chip inductor is usually not used
at input because its size is usually large, so it will consume too much chip area.
Another reason to put the gate inductor off-chip is that the on-chip inductor does not
have a good quality factor, so the loss of the on-chip inductor will degrade the noise
performance of the low noise amplifier.
Fig. 78 is the small signal equivalent circuit for the input impedance calcula-
139
-0.30
-0.22
-0.14
-0.06
0.02
0.10
0.18
0.26
0.34
-0.16 -0.12 -0.08 -0.04 0.00 0.04 0.08 0.12 0.16
g3,NPN
Input voltage (V)
g3,MOS g3
(A/V )3
g 3
Fig. 77. 3rd-order terms of the BJT, NMOS and their combination
tion. Ct accounts for the total capacitance between the gate and source of the MOS
transistor M1 in Fig. 74.
Ct = Cgs1 + Cπ (5.74)
where Cgs1 is the gate-source capacitance of M1, Cπ is the bipolar base-emitter ca-
pacitance. gπ is the conductance introduced by the bipolar transistor and can be
expressed as
gπ =1
rπ=
IQβφt
(5.75)
The bipolar’s emitter degeneration resistor Re is about 20 ∼ 40 Ω. This is a relatively
small value and will be ignored in the following analysis for simplicity.
Assuming ω2C2t À gπ, the input impedance of the configuration can be derived
as
Zin ≈ jω
(
Ls + Lg +gmgπLsω2C2t
)
+1
jωCt
+gmCt
Ls +gπ
ω2C2t(5.76)
It is observed that the bipolar transistor introduces a shunted RC network between
the gate and source of the MOS transistor as shown in Fig. 78. The base-emitter
140
πgtC
gL
inZgsv
gsmvg
sL
Fig. 78. Small signal circuit for input impedance calculation
capacitance Cπ will shift the input matching frequency to a lower frequency. The
resistance rπ in parallel with this additional capacitor is at the magnitude of several
kilo-ohms. This resistance will vertically shift the S11 curve upward. Fig. 79 shows
the simulated S11 plot with and without the bipolar transistor activated. Therefore,
considering the effects of bipolar input impedance on the total input impedance, the
input can still be matched to a specific value using inductive degeneration.
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jDklmXnopq r s
jDkltvu w1opq r s
x1y z6|z~U,QU
Fig. 79. Effect of bipolar transistor on input matching
141
Due to the low bias current, the bipolar contributes a small amount of noise to
the whole circuit. Simulation shows that the bipolar transistor adds less than 2.4%
to the overall noise of the circuit while the MOS transistor contributes about 14%.
Table XIV lists the noise contribution ratios of different devices at 3 GHz. Here the
input matching network is designed to achieve the best impedance match. The noise
figure calculated from the values given in the table is about 2.2 dB.
Table XIV. Device noise contribution ratios of single-ended hybrid LNA († signal gen-erator’s internal resistance)
Components Noise ratio
R †s 60%
MOS transistor 14%
Bipolar transistor 2.4%
Other devices 23.6%
4. Sensitivity to Bias Condition, Process Corners and Temperature
In the proposed linearization technique, an NPN transistor in a CMOS process is
used. It is necessary to verify that the NPN transistor is fast enough to work at the
RF frequency. Table XV lists the simulated fT of the NPN transistor and NMOS
transistor used in Fig. 74 against process corners. It can be seen that the NPN
transistor almost has the same speed as the NMOS transistor in FF and SS corners.
Figs. 80 gives the IIP3 of the NMOS-NPN combination with different bias condi-
tions of the MOS and bipolar device. Two operation frequencies are given: 2.4 GHz
and 3 GHz. The two test tones are placed 2 MHz apart. The two plots in Figs. 80
for different frequencies are almost the same. This means that IIP3 is not sensitive
142
Table XV. fT of a 2× 2 NPN transistor
Corner NMOS NPN
TT 30GHz 28GHz
FF 53GHz 35GHz
SS 21GHz 22GHz
to operational frequency as proved previously.
It is observed from the figures that if the MOS transistor is biased at 0.685 V
and the bipolar transistor is biased at 0.8 V, the configuration has the optimal IIP3
condition. If the MOS transistor gate is biased too low or too high, there will exist
two IIP3 maxima, one for a lower bipolar base bias and the other for a higher bias.
For Vbmos = 0.685V , if due to process variations, its value changes to 0.635 V or
0.700 V, the IIP3 does not vary significantly. If Vbnpn is around 0.8 V, the IIP3 curves
is pretty flat for Vbmos = 0.635V and Vbmos = 0.685V . Notice that for Vbmos = 0.7V ,
the IIP3 at Vbnpn = 0.8V has a local minima, so the variation of Vbnpn within about
±30mV will not degrade the IIP3.
Fig. 81 is the IIP3 versus bipolar base bias voltage against process corners. Here
the MOS transistor is biased at 0.685 V. Process corners will make the optimal bias
condition change, especially for the FF corner. The optimal bias voltage is shifted to
a lower value for the FF corner. An On-chip corner dependent biasing scheme can be
used to modify the biasing point.
Temperature behavior of the proposed configuration is shown in Fig. 82. It shows
how the IIP3 profile changes with different bias voltage of the NPN transistor under
different temperatures. The optimal biasing point of the bipolar transistor shifts with
temperature as shown in Fig. 83. This biasing profile can be realized by deriving the
143
1
1
1
11
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¯°±²³².´².¯².°²±´³
³µ ¶³µ ¶´³µ ¶¯³µ ¶!°³µ ¶±h³µ ±·³1µ ±!´¸³µ ±¯³1µ ±°³µ ±±³1µ ¹
º»O¼½O¾<¿À<Á Â<À<À ºº»O¼½O¾<¿À<Á Â<Ã<Ä ºº»O¼½O¾<¿À<Á Â<Å<Ä ºº»O¼½O¾<¿À<Á ÆOÀ<À ºÇ1µ ³ÈSÉÊ
ËDÌ.Í<Î.ÍKÏ,ËQÐ
ËDÌ.Í<Î.ÍKÏ,ËQÐ
ÑÑÒÓÔÕ Ö×Ø
ÑÑÒÓÔÕ Ö×Ø
Fig. 80. IIP3 of NMOS-NPN combination vs. bias conditions
4
6
8
10
12
14
16
18
0.7 0.74 0.78 0.82 0.86 0.9
SSTTFF
Vbnpn (V)
IIP3(d
Bm)
Fig. 81. IIP3 against process corners
144
base bias voltage from a PTAT current source running through a resistor. The NMOS
transistor should be biased using a constant -gm biasing circuit to keep the gmof the
circuit constant over temperature variations.
4
6
8
10
12
14
16
18
20
22
24
0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88
Temp=-10 Temp=0Temp=10 Temp=30Temp=50 Temp=80Temp=100
Vbnpn (V)
IIP3(
dBm
)
Fig. 82. IIP3 temperature behavior
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ã áÙÙháÙÞÙåäÙæâ1ÙåßÙæÛ1ÙæÝÙà1ÙçÜÙèáÙÙ
éêé ëìíî ïðñòî ðóôõö
÷Qøùûúøü ýþ ÿ ü ø
Fig. 83. NPN transistor optimal biasing profile
This single-ended hybrid LNA’s design flow is depicted in Fig. 84. To begin with,
a single-ended inductive-degenerated LNA is design according to the provided speci-
145
fications. In this stage, the linearity is not considered. Then an emitter-degenerated
BJT is added to the circuit. The BJT and degeneration resistor’s size and bias cur-
rent can be determined from the MOS transistor and BJT’s 3rd order coefficient
simulation plot. After optimal conditions are found, the input impedance matching
inductors Lg and Ls need to be adjusted to accommodate the added devices. Also
the load should be fine-tuned to make gain return to the specification. The overall
simulation verification is then carried out and the design usually needs to iterate to
finally meet the required specifications.
5. The Differential Configuration
The IIP2 shown Fig. 71 almost has its worst value for the best IIP3. This is due to
the fact that for different gate bias, although the 3rd-order terms can have different
signs, so they can be canceled out by combining the current, the 2nd-order terms,
however, will always have the same signs. By adding the output current of the main
and auxiliary transistor, the 2nd-order terms will be added constructively, which will
deteriorate IIP2. The single-ended hybrid LNA configuration also has this problem.
In order to simultaneously keep the 2nd-order performance and provide 3rd-order
compensation, a differential structure is proposed as in Fig. 85.
The 3rd-order Volterra kernel H3 of a differential pair can be expressed as [37]
H3 (ω1, ω2, ω3) ≈ g3
(
1− j ω1 + ω2 + ω33ωp
)
(5.77)
where g3 is the 3rd-order coefficient of the Taylor series at DC. ωp = gmCp
. gm is the
differential pair low frequency transconductance. Cp is the total capacitance of the
common-source or common-emitter node and it is assumed to dominate the memory
effect of a differential pair. Usually Cp is proportional to the size of the tail current
source and thus, to the tail current. gm is also proportional to the tail current.
146
Design a LNA withoutconsidering linearity
specifications
Add an emitter-degenerated BJT,simulation plots are used to
determine the sizes of devices
Adjust Lg, LS and Load
Design Specs- Noise figure- IIP3- Voltage gain- Power consumption
SimulationVerification
Meet theSpecs ?
YESNO Layout and postlayout simulation
Meet theSpecs ?
NO
Tape-out YES
NF, Gain, PD
NF, Gain
IIP3
Fig. 84. Mixer design flow chart
147
Therefore, ωp for MOS is at the same order as that for the BJT. The additional
phase shift in H3 for MOS is almost the same as that of BJT, i.e. for a bipolar
or MOS differential pair, their 3rd-order terms will have the same sign. However, as
mentioned before, for the same current consumption, bipolar’s 3rd-order term is much
larger than that of the MOS transistor. So with reduced bias current and resistive
emitter degeneration, bipolar’s 3rd-order term can be made to match that of the MOS
transistor. By subtracting the output of the MOS and bipolar differential pair, the
3rd-order term can be canceled without significantly reducing the overall gain.
M1 M2
Q1 Q2
re re
VDD
VOUT+
VIN-
LD LD
VIN+
IEE ISS
VOUT-
MB1 MB2 MB3 MB4
Fig. 85. Linearized differential LNA using bipolar differential pair
In the ideal case, where the matching between transistors is perfect, there should
be no 2nd-order non-linearity at the biasing point of the differential pair. But in
148
practise, mismatch exists, and can be modeled as a biasing offset. The proposed
differential method can not make the 2nd-order non-linearity substantially smaller
than a single differential pair, but it can expand the input range for a small 2nd-order
term, thus becoming more tolerant to the bias offset or device mismatch. On the other
hand, if single-ended output is chosen from the differential structure, simulation shows
that IIP2 can be improved by about 10 dB compared to without bipolar differential
pair linearization. Fig. 86 shows the 2nd and 3rd-order non-linear terms of the MOS
and bipolar differential pairs together with overall non-linearity terms. The 3rd-order
cancellation and 2nd-order range expansion are easily identified from the plots.
-1.60
-1.20
-0.80
-0.40
0.00
0.40
0.80
1.20
-300 -200 -100 0 100 200 300
Input voltage (mV)
BJT
BJT+NMOS
NMOS
(b)
-120
-80
-40
0
40
80
120
-300 -220 -140 -60 20 100 180 260
Input voltage (mV)
NMOS
BJT+NMOS
Extended flatnessfor small IM2
BJT
(a)
IM2 (
mA/V
)2
IM3 (
A/V )3
Fig. 86. (a) 2nd-order input range expansion and (b) 3rd-order cancellation of the
proposed differential LNA
The differential structure uses a destructive combination of MOS and bipolar
differential pairs. The output currents coming from the bipolar differential pair is
subtracted from that of the MOS differential pair. While in the single-ended struc-
ture, the output currents generated from the MOS and bipolar transistors are con-
structively combined. This subtle difference makes the input matching of differential
structure using inductive degeneration unfeasible. The degeneration inductor will
149
probably introduce an additional differential phase shift between the MOS and bipo-
lar differential pairs which will deviate the non-linearity cancellation effect. So the
input impedance matching is implemented using an LC network.
Again due to the destructive combine of MOS and bipolar pairs, the bipolar’s
noise contribution is more pronounced compared to the signal-ended structure. It
contributes about 15% to the overall noise of the circuit. Table XVI shows how
the noise contribution ratios break-down into different components. The noise figure
calculated from the values given here is 3.7 dB.
Table XVI. Noise contribution ratios of differential configuration († signal generator’sinternal resistance)
Components Noise ratio
R †s 42%
MOS transistors 10%
Bipolar transistors 15%
Other devices 33%
The differential hybrid LNA’s design procedure is similar to the single-ended one
previously shown in Fig. 84.
D. Measurement Results and Comparisons
The single-ended and differential LNA’s were designed using TSMC 0.18µm RF
CMOS process. Testing chips were fabricated through MOSIS MEP program and
packed in a QFN package. The die photomicrographs of these two circuits are shown
in Figs. 87. The active size is 390µm × 390µm for the single-ended LNA and is
620µm × 490µm for the differential one.
150
(a) (b)
Fig. 87. Die photomicrographs of hybrid linearized LNA’s (a) single-ended (b) differ-
ential
Fig. 88 shows the IIP3 plot of a single-ended linearized LNA using the lineariza-
tion technique depicted in Fig. 74. Out-of-band termination is realized using the
tuned LC tank as the load [49]. The two tones are put at 2700 MHz and 2701 MHz
respectively. The S-parameter measurement plots are shown in Fig. 89. The S11 is
better than -10 dB from 2.6 GHz to 2.9 GHz. Due to the single-ended structure and
lack of cascoded transistor, the reverse isolation (S12) is not very good. The power
gain is about 6.4 dB, noise figure is measured to be 2.1 dB around 2.7 GHz. It draws
6.4 mA from a single 1.2 V power supply.
The differential version (Fig. 85) of the hybrid LNA’s operation frequency is
centered around 2.5 GHz. Fig. 90 is the measured IIP3 plots of the circuit with
and without the cancellation bipolar pair activated. The two testing tones are put
at 2500 MHz and 2501 MHz respectively. When the bipolar pair is enabled, the
fundamental term is reduced by about 2 dB and the IM3 term is reduced by 12.5 dB,
therefore about 5 dB IIP3 improvement can be obtained with the bipolar cancellation
pair. Fig. 91 is the measured S-parameters of the differential LNA. The S11 is better
than -9 dB from 2.4 GHz to 2.6 GHz. The circuit’s reverse isolation measured by S12
151
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Fig. 88. IIP3 of the single-ended bipolar linearized LNA
FG-HFG-IF4JFK
LKJ
IM N IM NN IOM H I M HPN I M Q IM QN IM J IOM JN IM R
S I G
S II
S GGS GI
T-UVWX-V"Y-Z\[^]4_+`Pacb
defg hgijk j hlmn op
Fig. 89. Linearized single-ended LNA S-parameters
152
-100-80-60-40-20
02040
-30 -25 -20 -15 -10 -5 0 5 10 15Input Power (dBm)
Outpu
t Pow
er (dB
m)
IIP3 with BJT enabled: 12.3 dBm
IIP3 with BJT disabled: 7.3 dBm
12.5 dB
Fig. 90. IIP3 of differential LNA with and without bipolar cancellation pair activated
qsrOtq\uvq\utq\wvq\wtqxvqx-tq\vtvx-txv
wOy uzwy uvzwy rwy rOv|w y vwOy vPv~wOy ~wy Pvzw y
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x-w
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Fig. 91. Linearized differential LNA S-parameters
153
is much better than that of the single-ended LNA. The power gain is about 10 dB.
Noise figure is measured to be 3.4 dB around 2.5 GHz. This differential LNA draws
11 mA from a single 1.8 V power supply. Because the differential structure inherently
suppresses the second-order non-linear term, out-of-band termination is not required
as in the single-ended case.
Table XVII compares the proposed technique with reported high linearity LNA’s.
The figure of merit (FOM) [50] is defined as
FOM =PIIP3 ×G(F − 1)PD
(5.78)
where PIIP3, G, F and PD are the input-referred 3rd-order intercept point, power
gain, noise factor and power dissipation respectively.
Table XVII. Comparison of the proposed linearization implementation with the
state-of-the-art linear LNA’s in the literature
Freq.
(GHz)
Gain
(dB)
NF
(dB)
IIP3
(dBm)
Power
(mW)FOM
Single-ended [41] 0.9 10 2.85 15.6 21.1 18.5
Single-ended [proposed] 2.7 6.4 2.1 14.5 8.9 22.8
Differential [49] 0.9 5 2.8 18 45 4.9
Differential [proposed] 2.5 10 3.4 12.3 19.8 7.2
The proposed linearized LNAs can work at a higher frequency and achieve an
improved figure-of-merit. This is due to the fact that the emitter-degenerated BJT
has a better controlled 3rd-order non-linearity by the degeneration resistance, and it
requires less current to compensate the MOST’s non-linearity. Therefore, the circuit
can be designed without the BJTs first, and then adding the BJTs for linearization.
154
Note that the proposed design is implemented in CMOS technology, the bipolar
device has a limited performance. One may wonder what if a true BiCMOS technol-
ogy is used. To this end, a single-ended hybrid LNA is simulated using IBM 0.25µm
BiCMOS technology. Thanks to the superior bipolar transistor available in the BiC-
MOS process, the noise figure of this LNA is less than 1.2 dB at 3.0 GHz with the
power gain of 9.5 dB and IIP3 of 12 dBm. The power dissipation is 6.6 mW. Thus
the BiCMOS design has a figure-of-merit 67, which is much better than its CMOS
counterpart.
155
CHAPTER VI
A MUTUAL-COUPLED DEGENERATED LNA AND ITS EXTENSION TO
CONCURRENT DUAL-BAND OPERATION
Nowadays, wireless technologies are advancing faster then ever. The diverse range
of wireless applications have demands on communication systems for versatility and
flexibility. While different wireless applications are usually operating in different
frequency bands, recently dual-band or even multi-band transceivers gain a lot of
interest. Being the first active block in the receiver chain, the low noise amplifier
(LNA) has to have multi-band capabilities. Most of the current wireless systems are
narrow band. A wide band LNA can be used to cover a wide frequency range, but it
consumes a large amount of power and at the same time amplifies interferences which
are not on the actual reception band. Therefore, one would like the LNA’s transfer
function curve to looks like the superposition of two or more narrow band LNAs. In
order for the front-end LNA to cover more than one frequency band, the matching
network must be able to provide degrees of freedom equal to the number of bands
covered. Methods already reported in the literatures are: (i) device switching [33], (ii)
concurrent matching [51], and (iii) device switching plus concurrent matching [52].
The switched method can provide optimal design for every band while the concurrent
approach can receive more than one band at the same time.
Current wireless mobile terminals provide dual- or multi-band operations mainly
for cellular capacity reasons. While in the future multi-band/multi-mode terminals
will be enabled to access different systems providing various services. Fig. 92 shows
the mobile station receiver band in the spectrum for a clear review of frequency
allocations. The frequency numbers in the figure are shown in MHz. Numbers shown
156
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¶ «¨· ¶ «¨¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¸ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ ¹ º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º ºº º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º ºº º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º ºº º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º ºº º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º º±\¢µ ¯ ±\¢¢µ^±¤²*µ ±¤-£µ»´±±\µ ´±c¼*µ
½¾"«-® ±\¢µµ ©c¾"«-® ±¤-µµ ¿ ¾½P¨§ÀsÁ ÂsÁ ÃÁ ÄÅ ÄÅ
Fig. 92. Mobile station receiver band
in the rectangle representing the band are its bandwidth. A dual-band receiver front-
end typically consists of a dual-band antenna, followed by a monolithic dual-band
filter and dual-band LNA ate provides gain and impedance match at two bands.
An input impedance match method using mutual coupled inductors will be stud-
ied first and measurement results for an LNA working in the 900 MHz GSM band will
be presented. Then the extension of a concurrent dual-band LNA will be proposed.
The advantage of concurrent operation is it does not need any dual-band switch or
duplexer and has maximum front-end circuit sharing which reduces the silicon area.
Concurrent reception is more desired when two bands provide different services such
as voice and data.
A. Principle of Impedance Match Using Mutual Inductance
The inductive source-degenerated LNA is a very popular architecture in the inte-
grated CMOS RF and microwave circuit design [10]. It nicely trade-offs among input
matching, noise figure and gain specifications. A cascoded structure is usually used
in the LNA to reduce Miller effect on input impedance and improve reverse isolation.
An inter-stage inductor is used in [53] and [54] to provide inter-stage matching. In
this section, the mutual coupling between the degeneration and inter-stage inductors
is added to obtain another degree of freedom for the design.
157
ÆÈÇ*ÉÊË Ç
Ë É
ËÌÍ Ê
ÍÏÎÐÒÑ
Ó
ÓÔ
ÕªÖ×
Fig. 93. Matching utilizing mutual inductance
1. Input Impedance
Fig. 93 shows the idea of using mutual inductance in the LNA input matching network.
Its small signal circuit for input impedance calculation is depicted in Fig. 94. It is
easily seen that the input impedance Zin can be written as the sum of inductor LG’s
impedance sLG and the impedance ZX looking into the circuit after inductor LG:
Zin = sLG + ZX (6.1)
Impedance ZX can be calculated by solving the following equations
Vs1 = sLs (Ii + Id1)± Id1sM
VG1 = Vs1 +Ii
sCGS1
Id1 = gm1VGS1 = gm1Ii
sCGS1
ZX = VG1
Ii
(6.2)
where M is the mutual inductance between LS and LM . Its polarity is determined
158
ØÚÙÛ-ÜÝ Ù
Þ
ßÝ Û
Ý à
ááªâsãäªåæçèéêëìíî
ïðñ
ò
òóôõ
ö÷ñ
ø
ùúû
Fig. 94. Input impedance small signal circuit
by how the magnetic coupling is constructed. Coupling coefficient k is defined as
k =M√LSLM
(6.3)
A typical range for the k-factor achievable in silicon designs is 0.6 ≤ k ≤ 0.95. Zin is
given by
Zin = s (LG + LS) +1
sCGS1
+gm1CGS1
(LS ±M) (6.4)
For the mutual coupling polarity shown in Fig. 94 by the asterisk, minus sign
will be assigned to the third term in (6.4). This impedance expression resembles the
one without mutual inductance coupling except that the real part is modified by the
mutual inductance. Under resonant frequency
ωo =1
√
(LG + LS)CGS1
(6.5)
Zin only presents resistance
Rin = ωT (LS ±M) (6.6)
where ωT = gm1
CGS1.
159
For long channel approximation
ωT ∝1
L2µ (VGS1 − Vth1) (6.7)
The device channel length L is usually chosen to be process minimum for high fre-
quency performance. CGS1 is calculated from the optimum input quality factor QI =
1ωoCGS1Rs
. Therefore the device width W is obtained by resolvingCGS1 = 23WLCox.
Gate over drive voltage VGS1 − Vth1 can be fixed by power consumption constraint
ID ∝ WL(VGS1 − Vth1)2or linearity requirement IIP3 ∝ VGS1 − Vth1.
For a conventional inductive degenerated LNA, difficulty may arise from using
high bias level to obtain high input linearity. Input match condition requires Rs =
ωTLS, where RS is usually 50Ω or 75Ω. For high gate bias level, VGS1 − Vth1 is
large, therefore ωT is also large. This situation will probably require a very small
degeneration inductance LS which is hard to design or already comparable to the
bond wire inductance. Of course, bond wire can be used but it is less controllable
by the designer and is affected by the placement of the die in the package which is
unknown at the very beginning of the design stage. Small LS will also require large
LG to provide the same resonant frequency ωo. While a large inductance generally
has a larger series resistance which will degrade the noise figure of the LNA directly,
because LG is series directly with the gate. The presence of the mutual inductance
offers another degree of freedom for input impedance matching. By choosing the
negative sign in (6.4), Rs = ωT (LS −M), larger LS can be used. If the design is
targeting minimum current consumption and if VGS1 − Vth1 is small, a large LS may
be required. In this case, the positive sign in (6.4) can be used to enable smaller
degeneration inductance LS.
160
CGS1
LG
+_
LS
LM
11 GSmVg1GSV
*
*ro1Zo
Zin2Zo1Zin2'
CGS2
2
1mg
sI
1oI
CGD1
Fig. 95. Inter-stage impedance
2. Interstage Impedance
In Fig. 93, cascoded transistor M2 reduces Miller effect and provides output-input
isolation. Adding LM can provide inter-stage impedance transformation and help to
further reduce Miller capacitance of M1 therefore increasing reverse isolation. Fig. 95
shows the small signal equivalent circuit for inter-stage impedance calculation. Zo is
the source impedance. 1gm2
in parallel with CGS2 represents the input impedance of
the cascoded stage.
Intuitively, the common-gate configured transistor M2 has an input resistance of
about 1gm2
(actually it is larger than 1gm2
because the drain of M2 is not shorted to AC
ground. 1gm2
is good approximation for low load impedance though). The M2’s gate-
source capacitance CGS2 together with inductor LM forms a shunt-series impedance
transformation network. This network transforms 1gm2
to a smaller value. Therefore
the voltage gain from the gate of M1 to its drain terminal will be decreased due to a
reduced load impedance, thus reducing the Miller feedback.
It can be shown that M1’s drain current Io1 and source current Ishave the fol-
lowing relationship
Is = F1Io1 (6.8)
161
F1 =sLG ± sM + 1
sCGS1+ Zo
sLG + sLs +1
sCGS1+ Zo
(6.9)
At input matched condition, F1 can be simplified as
F1 = 1− j ωoωT
(6.10)
The impedance looking into the drain of M1 is
Zo1 = 2ro1 +ω2oωT
Ls + jωoωT
Zo (6.11)
Usually ωo is far below ωT and Zo is 50Ω or 75Ω, so the reactive part of (6.11) will
be relatively much smaller than the resistive part. Zo1 will be nearly resistive.
Looking away from the drain of M1, the impedance can be shown to be
Z′
in2 =1
gm2
1
1 +(
ωoωT2
)2 ±(
ωoωT
)2
ωTM + jωo
[
(LM ±M)− 1
gm2
ωT2ω2T2 + ω2o
]
(6.12)
where ωT2 =gm2
CGS2. By choosing a proper ωT2, Z
′
in2 can have only the resistive part
and its value is smaller than 1gm2
. The effect is that there will be more current pumped
into the cascoded stage thus improving efficiency.
It can be shown that the transconductance of the first stage does not get affected
by the mutual coupling
Gm1 = QIgm1 (6.13)
By choosing negative polarity of the inductive coupling, the voltage gain from M1’s
gate to its drain is
AV 1 = Gm1
(
2ro1 +ω2oωT
Ls
)
‖
1
gm2
1
1 +(
ωoωT2
)2 −(
ωoωT
)2
ωTM
(6.14)
This gain can be made smaller than that without mutual inductive coupling therefore
further reducing the Miller effect.
162
üýþÿ ý
þ
ÿ
Fig. 96. Overall transconductance
3. Effective Transconductance
The effective transconductance from the input terminal to the current flowing through
inductor LM can be found by observing the small signal equivalent circuit in Fig. 96.
At around frequency ωo, one can write the following equations
VGS1 = QIVi
Is = Io + Ig
Ig = jωoCGS1VCGS1
Vi − (VGS1 + jωoLGIg) = jωoLsIs ± jωoMIo
(6.15)
The effective transconductance Gm can be shown to be
Gm =IoVi
=1 +QI
(
ω2o
ω2oG
+ ω2o
ω2oS
− 1)
j(
ωoωT
)
Zo(6.16)
where
ωoG =1√
LGCGS1
(6.17)
and
ωoS =1√
LSCGS1
(6.18)
It is easy to shown from (6.5), (6.18) and (6.17) that ω2o
ω2oG
+ ω2o
ω2oS
= 1, so Gm is further
163
CGS1
LG
LS
LM
M1 *
*21ngi
21ndi
CGS1
LS
LM
M1 *
*
2ni
2nv LG
Fig. 97. Equivalent input noise sources of the inductive coupled LNA
simplified into
Gm = −j(
ωTωo
)
1
Zo(6.19)
It is seen that the phase of effective transconductance is -90 degrees. In order to
have large effective transconductance, the cut-off frequency of the RF transistor M1
should be large or equivalently, M1’s gate over-drive voltage need to be raised, which
means larger power consumption.
4. Noise Analysis
Since in an LNA with the cascoded structure, the cascoded MOSFET has a little
effect on the noise performance of the whole circuit [55], its noise contribution will
be ignored in the following noise analysis. M1’s drain noise current i2nd1 and induced
gate noise current i2ng1 will be represented by a noise voltage v2n and noise current i2n
as shown in Fig. 97.
It can be shown that at around operation frequency ωo,
in = ing1 + ind1jωoωT
(6.20)
164
and
vn = − ing1jωoCgs1
(6.21)
Since the mutual inductance does not appear explicitly in the above equations, it
does not make the expression forms of input equivalent noise sources different from a
regular inductive degenerated LNA.
Noise parameters Gu, Rn, Gc and Bc are found to be
Gu =γ
αgm1
(
ωoωT
)2(
1− |c|2)
(6.22)
Rn =αδ
5gm1(6.23)
Gc ≈ 0 (6.24)
and
Bc = −ωoCgs1
(
1 +|c|α
√
5γ
δ
)
(6.25)
The minimum noise figure obtained for this circuit configuration is
Fmim = 1 +2√5
ωoωT
√
γδ(
1− |c|2)
(6.26)
This minimum NF requires
Gs = Gopt = gm1ωoωT
√
5γ
α2δ
(
1− |c|2)
(6.27)
and
Bs = Bopt = ωoCgs1
(
1 +|c|α
√
5γ
δ
)
(6.28)
Under perfect impedance match condition, Gs =1Zo
= 1Rs
and Bs = 0, the noise figure
is
F = 1 +αδ
5
1
gm1Rs
+
(
ωoωT
)2
gm1Rs
(
αδ
5+γ
α+ |c|
√
4
5γδ
)
(6.29)
165
Several observations can be obtained from (6.29). The(
ωoωT
)2
term shows the noise
figure will increase with operation frequency if other parameters keep constant. If
there is no correlation between the gate and drain noise current, i.e. c = 0, the noise
figure could be smaller. There is an optimal value of gm1Rs product which makes the
noise figure under perfect impedance match minimum. For γ = 2, δ = 4, α = 0.85
and |c| = 0.4:
gm1Rs|opt ≈ 0.4
(
ωTωo
)
(6.30)
Fig. 98 is the schematic of the proposed LNA, and Fig. 99 shows a detailed design
flowchart. It is very similar with the design flow in Fig. 15, Chapter II. The major
difference is the input impedance matching involves mutual inductance and the design
trade-offs also include the mutual coupling factor.
CGS1
LS
LM
M1
M2VB
*
*
k
CC1 M3
LD1
LD2
RD
CC2
CC3
RS
VDD
RF IN
RF OUTLG
Output Buffer
Fig. 98. The proposed mutual-coupled degenerated LNA
166
Estimate fT andcalculate κnf
Determine Iden, Q andCalculate Device Size
Calculate Lg, LS, Mand Required Load
Design Specs
- Noise figure- IIP3- Voltage gain- Return loss- Power consumption
- gm, gdo, α, Vgs-Vth v.s. Iden- fT and Cgs v.s. Vgs-Vth- κnf v.s. input Q and Iden- IIP3 v.s. Vgs-Vth and W
DesignParameterPlots
SimulationVerification
Meet theSpecs ?
YES
MLVVIIP Sthgs −↑→−↑→3↓↑↑↓→ den
o
T IQF ,,
ω
ω
MLIVVP SdenthgsD +↓→↓−↓→ ,
Trade between designSpecs and fine tunecircuit parameters
NO Layout and postlayout simulation
Meet theSpecs ?
NO
Tape-out YES
( )T
onf f
fF 1−=κ
T
ss
RMLω=±
sgso
g LC
L −= 21ω
sVT
oL RARω
ω=
osgs QRC
ω21
=
denDS IWI ×=
Fig. 99. Design flow of the mutual-coupled LNA
167
B. Chip Measurement Results of the Mutual-Coupled Degenerated LNA
The proposed mutual-coupled source-degenerated LNA is implemented using TSMC
0.35µm CMOS technology and fabricated through MOSIS service. Its die micro-
photograph is shown in Fig. 100.
Fig. 100. Die microphotograph of the mutual-coupled degenerated LNA
The mutual coupled inductors LM and Ls was implemented on-chip by two in-
terleaved square spirals. The inductor LG was formed by the bond wire and off-chip
surface mount inductor. Multiple bond pads were used for ground connections to
reduce the ground inductance. The LNA occupies 700µm × 500µm active silicon
area.
Fig. 101 shows the measured small signal performance of the proposed LNA. The
gain (S21) is 17 dB at 960 MHz. The noise figure is 3.4 dB which seems a little higher
for GSM application. This is because it includes the output buffer formed by M3,
Rs and LD2. Bonding pads and inferior quality factors of inductors also makes the
NF larger. Simulation shows that the LNA with better inductors and bonding pads
removed can have a noise figure about 1.4 dB. The LNA is tested within a plastic
package and soldered on a PCB board. The S12 is measured for the whole setup,
168
so the reverse isolation for the LNA itself should be better than what is shown in
Fig. 101. The measured IIP3 plot is illustrated in Fig. 102, which is -5.1 dBm. The
LNA draws 5.6 mA from a single 2.3 V power supply.
-50-46-42-38-34-30-26-22-18-14-10-6-226
101418
750 800 850 900 950 1000 1050 1100 11500
1
2
3
4
5
6
7
8
9
10
Frequency (MHz)
S11,
S21 a
nd S1
2 (dB
)
Noise
Figu
re (dB
)
S21
Noise figure
S11
S12
Fig. 101. Measured small signal performance of the mutual-coupled degenerated LNA
Table XVIII summarizes the measurement results together with other reported
GSM LNA’s performance in the literature.
C. A Dual-Band Inductive Coupled LNA
Multi-band operation can be implemented by device switching or concurrent impedance
match or both. The device switching method can provide separate optimization at
different working frequencies [33]. It basically attempts to merge two or more designs
into one compact circuit by sharing components. An issue of this method is that the
169
-90
-75
-60
-45
-30
-15
0
15
-45 -40 -35 -30 -25 -20 -15 -10 -5 0
IIP3= -5.1 dBm
Input power (dBm)
Outpu
t pow
er (dB
m)
Fig. 102. Measured IIP3 of the mutual-coupled degenerated LNA
Table XVIII. Reported LNA performance for GSM applications
GSM LNA TechnologyGain
(dB)
NF
(dB)
IIP3
(dBm)
S11
(dB)
Power
(mW)
[52] 0.18µm CMOS 22.4 0.6 -5.3 <-25 15.3
[56] 0.25µm CMOS 15/-5 1.9 -7 -8 25
[29] 0.25µm CMOS 16.2 1.85 -7.25 -8 27
[57] 0.35µm CMOS 20 1.6 +2 -14 11.25
This Work 0.35µm CMOS 17 1.4 -5.1 -14 13
170
shut-off components may affect the active ones due to the parasitics introduced by
turned-off devices. The concurrent operation LNA can work at two or more modes
at the same time, but usually it is hard to provide optimal working condition for
both [51]. Introducing switches at the output of concurrent matched LNA can pro-
vide additional degrees of freedom for more frequency bands [52]. Because the switch
is at output, it will not affect the input matching condition. But linearity of the
switch and parasitics may offset the linearity and output working condition of the
circuit.
From (6.4) one can find that without disturbing other factors, using a different
LG value can provide input match around different operation frequency ωo. A strait
forward implementation is to switch in or out more inductance using switches. This
approach suffers from the added parasitic capacitance and resistance of the switches
and increased noise due to switch resistance. Without using switches, an LC parallel
network can be put in series with LG as shown in Fig. 103. The parallel LC network
(LB ‖ CB) will present inductive or capacitive impedance below or above its intrinsic
resonant frequency (ωB = 1√LBCB
), thus modify the effective inductance series with
the gate. Mutual coupling between LG and LB can further modify the impedance
and also reduce the required value of inductance thus save area. L′
G represents the
bonding wire inductance or additional required inductance for matching.
The equivalent impedance formed by CB, LB and LG can be found to be
ZBG = jω (LG +MG) + jω(LB +MG)
(
1 + ω2
ω2M
)
1− ω2
ω2B
(6.31)
where ωM = 1√MGCB
and ωB = 1√LBCB
. The first term in (6.31) shows that mutual
inductanceMG enhances the effective inductance of LG, so lower inductance value and
size of LG can be used. The frequency point where the second term of (6.31) changes
171
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Fig. 103. Dual-band inductive coupled LNA (bias not shown)
from inductive to capacitive does not depends on the mutual coupling. Therefore
by changing CB, the impedance property cross-over point can be changed and by
adjusting the coupling strength, proper matching at different frequency points can be
realized. Fig. 99 can be followed as the design procedure of the dual-band LNA by
considering the discussions about input impedance matching.
D. Simulation Results of the Dual-band LNA
The dual-band LNA is design using the TSMC 0.35µm CMOS technology. Fig. 104(a)
is the simulated S11 and S21 plot of the dual-band LNA. The LNA’s input is matched
to 50Ω at 900 MHz GSM band and 1800 MHz DCS-1800 band. The S21 for these
two bands are 14 dB and 19 dB respectively.
Fig. 104(b) shows the noise performance. The noise figure at the two bands
almost equals to the minimum noise figure, which means the input matching network
is also optimized for noise matching. The noise figure is 0.8 dB for 900 MHz band and
172
1.6 dB for 1800 MHz band. Fig. 105 shows the input-referred third-order intercept
point (IIP3) plots for both bands. In the 900 MHz GSM band, the IIP3 is -5.5 dBm.
For DCS-1800, the IIP3 is -2.5 dBm. A Q value of 10 for the inductors is assumed in
the simulation.
Table XIX summaries the performance of some reported dual/multi-band LNAs
and the proposed dual-band LNA. It shows that the inductive-coupled LNA gives
comparable results to the literature.
Table XIX. Reported LNA performance in for cellular applications († indicates the
value is for the whole front-end)
Multi-Band Standard Technology Gain NF IIP3 S11 Power
LNA (dB) (dB) (dBm) (dB) (mW)
[58] GSM900 0.8 µm 20 1.6 -6.97 -17 15.4
DCS1800 BiCMOS 18 1.85 -3.68 -21
[52] GSM900 0.18µm 22.4 0.6 -5.3
GSM1800 CMOS 14.5 1.0 -3.8 <-25 15.3
WCDMA 14.1 1.4 -3.1
[33] GSM900 0.35µm 39.5† 2.3† -19† <-12 11.88
WCDMA BiCMOS 33† 4.3† -14.5† <-18 10.98
This Work GSM900 0.35µm 17 0.8 -5.5 -14 13
DCS1800 CMOS 19 1.6 -2.5 -14 13
173
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IJHHLKHHMEHHMNHHOD$HHHPDD$HHPDGCJHHQD$RHHSDGFJHHPD$THHQDGIJHHPD$KHHQD$EHHPD$NHHUCJHHHVXW Y[Z]\^`_ acb
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v0pcpxwcpcpxycpcpzcp'p|qJpcpcpqcqpcpUq2r0p0pUq"scpcp~q2t0p0pUq"ucpcpq2v0pcpq"wcp'pq"ycpcpq"zcpcpr0p'pcpX[]`60
(b)
Fig. 104. Simulated small signal performance of the dual-band LNA (a) S11 and S21
(b) noise figure and minimum noise figure
174
−40 −35 −30 −25 −20 −15 −10 −5 0−100
−80
−60
−40
−20
0
20
Input power (dBm)
Out
put p
ower
(dB
m)
IIP3=−5.5dBm
(a)
−40 −30 −20 −10 0 10−100
−80
−60
−40
−20
0
20
40
Input power (dBm)
Out
put p
ower
(dB
m)
IIP3=−2.5dBm
(b)
Fig. 105. Simulated IIP3 of the dual-band LNA (a) GSM-900 (b) DCS-1800
175
CHAPTER VII
FRONT-END CIRCUITS FOR WIDE-BAND APPLICATION
Ultra-wide band (UWB) systems are being considered excellent candidates for the
future-generation short-range, high-throughput wireless communications. It is emerg-
ing as a solution for the IEEE 802.15.3a (TG3a) standard [59] and will complement
with Bluetooth and WiFi standards. UWB-based technology is expected to enable
personal devices with integrated wireless connectivity. This requires high data rates
(110, 200, 480 Mbps) and reasonable low power consumption. Therefore, UWB re-
quires CMOS design in order to achieve low power and low cost integration with other
devices, and to fulfill the vision of integrated connectivity [60].
A. Introduction to Ultra-Wide Band System
Ultra-wide band systems transmit signals that demonstrate extremely low power-
spectral-density and occupy very wide bandwidth. The UWB signal bandwidth is
greater than 20% of its center frequency and must have a minimum value of 500 MHz
as required by US Federal Communication Commission (FCC). The ultra-wide nature
of UWB signals in the frequency domain leads to ultra-fine multi-path resolution in
the time domain, which enables a path diversity gain by using a RAKE receiver.
Therefore UWB signals are immune to multi-path fading. According to Shannon
channel capacity theorem, the information a channel can carry [61] (channel capacity,
C) is
C = B log2
(
1 +P
BN0
)
(7.1)
176
where B is the channel bandwidth in hertz (Hz), P is the received signal power in
watt (W), N0 is the noise power spectral density in watt per hertz (W/Hz). In
order to increase the channel capacity, one can increase the transmitted power or
the signal bandwidth. But the channel capacity has a linear increase in bandwidth
while a logarithmic increase in signal power. So it is more beneficial to have a wider
bandwidth than higher signal power. With increased bandwidth, the transmitted
power can be reduced thus reducing the interference to other systems. As an overall
consequence, UWB can provide very high data rates at limited range using very low
signal power. Due to its extremely low power spectral density, UWB can co-exist with
other standards operating in its frequency bands. Fig. 106 shows the UWB spectrum
compared with the 802.11a signal spectrum.
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¨ ¨ ¨ ¨ ¨¨ ¨ ¨ ¨ ¨¨ ¨ ¨ ¨ ¨¨ ¨ ¨ ¨ ¨¨ ¨ ¨ ¨ ¨¨ ¨ ¨ ¨ ¨¨ ¨ ¨ ¨ ¨¨ ¨ ¨ ¨ ¨¨ ¨ ¨ ¨ ¨¨ ¨ ¨ ¨ ¨¨ ¨ ¨ ¨ ¨¨ ¨ ¨ ¨ ¨© ª[« ©`¬=© X« © -¡?£
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Fig. 106. UWB signal spectrum
The bandwidth resources available for UWB can be used two different ways.
Impulse radio was the original approach to UWB realization. It communicates with
baseband pulses of very short durations, typically on the order of a nanosecond,
thereby spreading the energy of the radio signal very thinly from near DC to a few
gigahertz. Data could be modulated using either pulse amplitude modulation (PAM)
or pulse-position modulation (PPM). Multiple-access could be supported by utilizing
177
the time-hopping format [62].
A more recent approach to UWB is a multi-banded system where the UWB fre-
quency band from 3.1 GHz to 10.6 GHz is divided into several smaller bands. Each of
these bands has a bandwidth greater than 500MHz to comply with the FCC definition
of UWB. Several companies like Intel, Texas Instruments and Time Domain support
this approach. The multi-banded approach has a much greater flexibility in coex-
istence with other wireless systems and is based on more conventional technologies.
The official UWB standard is still under development by several companies that have
already provided their proposals to the 802.15.3a task group. As an example, Texas
Instruments proposed a multi-band OFDM system. It divides the UWB spectrum
into several 528 MHz bands. Information is transmitted using OFDM modulation on
each band. The OFDM carries are generated using an 128-point IFFT/FFT.
Due to the wide bandwidth of UWB signal, direct conversion may be the best
receiver architecture. If an IF is to be used, it should be at least higher than 250
MHz. This high IF will increase the complexity, power consumption and cost of the
baseband circuit. The wide band nature of UWB signal makes the DC offset and low
frequency noise less problematic than that in a narrow band system. Fig. 107 depicts
a conceptual UWB receiver block diagram.
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Fig. 107. Direct conversion UWB receiver
178
The wide spread spectrum of UWB signal makes its dynamic range (10-12 dB)
much smaller than that of its narrow band counterpart (50 dB for Bluetooth and 66 dB
for IEEE 802.11b). It may be suitable to employ the so called software-defined radio
architecture where the ADC is put directly after the LNA. But for current technology,
a high sampling rate ADC is still a big challenge, so the frequency conversion scheme
will still be needed in the near future.
B. Distributed RF Front-End Circuits
In conventional circuit design, it is well known that there exists a fundamental limi-
tation of the gain-bandwidth product. The gain-bandwidth product is proportional
to gmC, and is intrinsic to the devices used. In other words, gain will trade with band-
width. Conventional circuit design treats the circuit elements as lumped-elements,
i.e. each element only accounts for one dominant physical or electrical effect. Re-
sistor represents the heat dissipation, inductor represents energy storage of magnetic
field and capacitor represents energy storage of electric field. But in the real world,
especially at high frequency, when the dimensions of a circuit is comparable to the
wavelength, no single lumped-elements can be identified. For example, a 10 mm long
lossy metal line at 30 GHz has all of the effects of heat dissipation, magnetic and
electric energy storage. No single one of the effects overwhelms others. Thus the
circuit will be treated as distributed. Distributed circuits have the potential of large
bandwidth and the gain will not trade with bandwidth but rather with time delay.
1. Transmission Line Properties and Characterization
Transmission line (T-line) is the key element of distributed circuits. Fig. 108 is the
equivalent circuit model of an infinitesimal small segment of a transmission line. The
179
series inductance is due to the magnetic field effects and the shunt capacitance is
due to electric field coupling between the signal and ground lines. The loss in the
transmission media is modeled by series and shunt resistor. The R, L and C constants
are defined as per unit length circuit parameters. Note that this model only applies
to TEM mode transmission lines exactly [2].
L
C
R ∆z∆z
∆zG∆z
I(z,t)
z
V(z,t)
I(z+ ,t)∆z
V(z+ ,t)∆z
Fig. 108. Distributed model of transmission line
Assuming steady state operation, V (z, t) = V (z) ejωt, I (z, t) = I (z) ejωt. V (z)
and I (z) are voltage phasor and current phasor respectively. It can be shown that
the voltage and current along the line fulfill the following equations
dV (z)
dz= (R + jωL) I (z) (7.2)
dI (z)
dz= (G+ jωC)V (z) (7.3)
or
d2V (z)
dz= γ2V (z) (7.4)
d2I (z)
dz= γ2I (z) (7.5)
where γ =√
(R + jωL) (G+ jωC) = α+ jβ. γ is known as propagation constant, α
is known as attenuation constant, β is usually called the wave number, and β = 2πλ.
180
The general solutions for (7.4) and (7.5) are
V = V +0 eγz + V −
0 e−γz (7.6)
I = I+0 eγz + I−0 e
−γz (7.7)
The current phasor can also be written as
I =V +0Zc
eγz − V −0
Zce−γz (7.8)
where Zc =√
R+jωLG+jωC
is the characteristic impedance of the transmission line.
For lossless transmission line, R = 0 and G = 0, the characteristic impedance
becomes
Zc =
√
L
C(7.9)
and the propagation constant is γ = jω√LC, so α = 0 and
β = ω√LC (7.10)
The phase velocity of lossless transmission line is
vp =ω
β=
1√LC
(7.11)
For low loss transmission line, it is generally assumed that R¿ ωL and G¿ ωC,
so Zc is approximately to be
Zc ∼=√
L
C(7.12)
which is the same as the characteristic impedance of a lossless line. The propagation
constant can be written as
γ =√
RG− ω2LC + jω (RC + LG)
Due to the low loss assumption, the RG term can be dropped off from the above equa-
181
tion. Then applying the binomial expansion,(a− b)n = an+nan−1b+n(n−1)2!
an−2b2+· · ·
to the above equation it reads
γ ∼= jω√LC +
1
2
√LC
(
R
L+G
C
)
+j
8ω√LC
(
R
ωL+
G
ωC
)2
+ · · · (7.13)
Based on low loss assumption, only keep the first two terms of (7.13),
γ ∼= α + jβ =1
2
√LC
(
R
L+G
C
)
+ jω√LC (7.14)
The phase constant β is the same as the wave number in the lossless case. But the
attenuation constant is not zero any more:
α =R
2Zc+GZc2
(7.15)
The phase velocity of the signal in the low loss line is
vp =jω
γ∼= jω
jω√LC + 1
2
√LC
(
RL+ G
C
) =1√
LC + 12j
(
RωL
+ GωC
)√LC∼= 1√
LC
(7.16)
which is the same as the lossless line.
Now the formula of the loss per unit length for low loss line will be derived. For
a matched line, there is no reflected signal, the voltage along the line at point z+∆z
can be expressed as
V (z +∆z) = V +0 eγ(z+∆z)
When the voltage propagates to point z, it is
V (z) = V +0 eγz
So the attenuation is
P (z +∆z)
P (z)=
∣
∣
∣
∣
V (z +∆z)
V (z)
∣
∣
∣
∣
2
= e2α∆z
182
Expressed in dB form, it is
∆PdB∆z
= 20α log10 e =10
ln (10)
(
R
Zc+GZc
)
(7.17)
Table XX summarizes the basic properties of lossless and low-loss transmission
lines.
Table XX. Basic properties of lossless and low loss T-line
Lossless T-line Low-loss T-line
Zc
√
LC
√
LC
α 0 R2Zc
+ GZc2
β ω√LC ω
√LC
vp1√LC
1√LC
For a certain length of transmission line, it is characterized by its characteris-
tic impedance Zc and propagation constant γ. A S-parameter-base method can be
used to measure these values [63]. The S-parameter matrix for a lossy unmatched
transmission line with characteristic impedance Zc and propagation constant γ in a
Zo impedance system is [63]
[S] =
s11 s12
s21 s22
=
1
Ds
(Z2c − Z2o ) sinh γl 2ZcZo
2ZcZo (Z2c − Z2o ) sinh γl
(7.18)
where l is the physical length of the line, Ds = 2ZcZo cosh γl + (Z2c + Z2o ) sinh γl. It
can be shown that
Zc = Zo
√
(1 + s11)2 − s221
(1− s11)2 − s221(7.19)
e−γl =
(
1− s211 + s2212s21
±K)−1
(7.20)
183
where K = 12s21
√
(s211 − s221 + 1)2 − 4s211.
After obtaining γ and Zc, the distributed parameters R, G, L and C can be
calculated by
R = <γZc (7.21)
G = <
γ
Zc
(7.22)
L = =γZcω−1 (7.23)
C = =
γ
Zc
ω−1 (7.24)
2. Transmission Lines on Silicon Substrate
In distributed circuits, interconnection lines become an integrated part of the circuits.
The key to successful design of distributed circuits is the modeling of transmission line
used in the circuits. One can have two ways to arrive at the desired circuit. One is
have a well modeled transmission line, then design the circuit based on that line. The
other way is to build a general macro model of transmission lines, design the circuit
using that model then implement the line to map the macro model. Both methods
require a good modeling. There are two types of transmission lines which are suitable
to be integrated on silicon, they are coplanar stripeline and micro-strip line. Among
them, coplanar stripline seems more suitable for the purpose. The following sessions
investigate these two different lines.
The structure of the silicon and coplanar stripline is demonstrated in Fig. 109 and
Fig. 110. They are the structure dimensional drawing and the rendered 3D drawing
in HFSS respectively. The substrate structure of the TSMC 0.18 µm CMOS process
is very complicated, the structure shown here is a simplified version. Some of the
layers are lumped together and their parameters are averaged over their thickness.
The spacing and width of the lines (M6) are chosen to be 5µm [64]. The total length
184
of the line is 500µm. The dielectric thickness between the bottom of metal 6 and
substrate under field oxide (FOX) is 8.15µm. Using the line width comparable to the
thickness of the dielectric, the electric-field (E-field) will only penetrate the surface
of the lossy silicon substrate and at the same time large metal surface area is used
to conducting current. So loss due to lossy silicon substrate and metal skin effect is
reduced [65]. The skin depth of a transmission line can be calculated by
δs =
√
2
ωµσ(7.25)
For metal 1 and metal 6 the skin depth is about 0.6µm at 30 GHz.
PASS1_2(4.2)
SILICON(12)
PASS3(7.9)
IMD5b(4.2)IMD5a(3.7)
IMD1_4(3.77)
FOXILD(4.0)
300
1.10
5.521.180.352.650.60
AIR(1.0)
2.34
5 5 5
M6
Silicon Resistivity 8ohm.cm
M6 Conductivity 2.40E+07
80
500
400
NOT DRAWNON SCALE
ThicknessPermitivity
Unit: µm
Fig. 109. Coplanar stripline formed by metal 6 (dimensional drawing)
There exist two modes of operation for the coplanar stripline, even-mode and
odd-mode. Fig. 111 depicts the field distribution of these two operation modes. The
desired propagation mode is the odd-mode. It has better field confinement than that
of even mode, therefore less loss. Simulation shows that at 30 GHz the loss of the
line is within 0.8 dB per millimeter (dB/mm).
The micro-stripline structure is depicted in Fig. 112. The ground plane is formed
185
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Fig. 110. Coplanar stripline rendered by HFSS
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tsmc018_1
(a)
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tsmc018_1
(b)
Fig. 111. Coplanar stripline operation mode (a) Even mode (b) Odd mode
186
by metal 1. The signal line is formed by metal 6, which is the highest level and thickest
metal available in this technology. There is only one operation mode for the micro-
stripline. Fig. 113 shows the field distribution. For line width from 5µm to 25µm,
the loss is approximately 0.44 dB/mm at 30 GHz. The smaller loss is due to better
field confinement than the coplanar stripline.
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Fig. 112. Micro-stripline HFSS render
Now comes the question: Which type of transmission line is more suitable for
silicon integration? Note that the transmission line will be loaded by transistors, thus
lowering its effective characteristic impedance. If the loaded input and/or output line
is required to be 50Ω, then the line itself should be greater than 50Ω. Fig. 114 shows
the characteristic impedance of different dimensions of coplanar stripline and micro-
stripline. It shows that for reasonable line width and spacing, the impedance of a
coplanar stripline can be controlled from around 66Ω to 124Ω. On the other hand,
the line width of micro-stripline is the only changeable variable by the designer. It
is observed that the wider the line, the smaller the impedance. In order to keep the
impedance greater than 50Ω before loading, the line width should be smaller than
7µm. For a larger impedance value, the line width will be even smaller. This will
187
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mstrip
Fig. 113. Field distribution of micro-stripline
increase the line loss due to its high resistance. So the coplanar stripline is preferred
for distributed circuit design on silicon.
3. Distributed Amplifier as LNA
Distributed circuits can be realized by using either artificial transmission lines or
planar transmission lines. Artificial line uses lumped inductors and capacitors to
emulate the behavior of a real transmission lines. It generally requires high quality
inductors and capacitors which are usually not readily available in regular silicon
process, especially for inductors. Artificial line also has intrinsic cut-off characteris-
tics which will limit the operation bandwidth. Planar transmission lines discussed
in the previous section may be a better choice for large bandwidth and high opera-
tion frequency. The distributed LNA is implemented by periodically loading planar
transmission lines with active devices usually MOSFET transistors. Fig. 115 is the
schematic representation of a distributed LNA. Two transmission lines, the gate line
188
60
70
80
90
100
110
120
130
4 8 12 16 20 24 28
Line spacing (
Zo (O
hms)
8
11
14
Line width
5
µµµµm)
((((µµµµm)
(a)
20
25
30
35
40
45
50
55
60
65
4 9 14 19 24 29
Width of signal line (M1)
Zo (O
hms)
(b)
Fig. 114. Zc of (a) coplanar stripline and (b) micro-stripline at 30 GHz
189
and drain line are coupled unilaterally by MOS transistors. The portion between
the dashed lines is a unit section or cell. The amplifier shown in this figure has four
sections. Fig. 116 is the equivalent circuit for the unit section. For simplicity, the
T-lines are assumed to be lossless, the MOS transistor is modeled by its gate-source
capacitance, drain-source capacitance and a transconductance.
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Fig. 115. Schematic representation of a distributed LNA
Due to the periodic loading nature of the T-lines, Cgs and Cds can be treated
as uniformly distributed along the length (lg for gate line, ld for drain line) of the
unit cell. If the intrinsic gate line and drain have Lg, Cg and Ld, Cd as their dis-
tributed parameters, the propagation constants and characteristic impedances of the
two loaded lines can be obtained as
γg = jβg ≈ jω
√
Lg
(
Cg +Cgs
lg
)
(7.26)
Zgc ≈
√
LgCg + Cgs/lg
(7.27)
190
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for the gate line and
γd = jβd ≈ jω
√
Ld
(
Cd +Cds
ld
)
(7.28)
Zdc ≈
√
LdCd + Cds/ld
(7.29)
for the drain line.
The current generated by the transconductance is also deemed as spread over
the length of the drain line. Under matched conditions both lines are terminated by
their characteristic impedances:
Zs = Zgc = ZT
g (7.30)
ZTd = Zd
c = ZLd (7.31)
and assume the phase synchronization condition
βdld = βglg = θ (7.32)
191
The voltage gain of the amplifier [66] can be shown to be
Av = −NgmZ
dc
2e−jNθ (7.33)
where N is the number of unit sections. It is observed that within the valid frequency
range of uniform loading assumptions made in (7.26) through (7.29), the amplifier has
a gain which is increasing linearly with the total number of sections and a constant
group delay which is also a linear function of N. So increase gain by adding more
sections will increase the time delay between input and output. The power gain can
be written
G =N2g2mZ
dcZ
gc
4(7.34)
In practice, losses exist both in the transmission lines and the active loading
MOS transistors. The gate line is then loaded by Cgs and Rgs in series, and the drain
line is loaded by Cdsand Rds in parallel. In silicon implementation, losses come from
the T-lines may also need to be considered. Therefore the propagation constants of
loaded gate line and drain line will have a real part αg and αd respectively. Imaginary
components will appear in the loaded characteristic impedances but their contribution
is usually small within the useful frequency range. Under the phase synchronization
condition of (7.32), the power gain [66] of the amplifier is
G ≈ g2mZdcZ
gc
4
∣
∣
∣
∣
e−Nαglg − e−Nαdld
αglg − αdld
∣
∣
∣
∣
2
(7.35)
Thus the gain does not increase monotonically with N and at a particular fre-
quency, the optimal value of N is given by
Nopt, LNA =ln (αdld)− ln (αglg)
αdld − αglg(7.36)
In a practical amplifier, the major losses is due to the gate loading, an upper
192
bound for the total number of sections can be found as [66]
N ≤ 2
Rgsω2CgsZdc
(7.37)
A five-section distributed LNA is implemented using TSMC 0.18 µm CMOS
process. The T-lines are formed by coplanar striplines. This circuit draws 45 mA
from 1.2 V power supply. Fig. 117 is the layout view of the distributed LNA. Fig. 118
is the S-parameters plot. The flat gain bandwidth is from DC to 18 GHz with 2 dB
ripple. From DC to 14 GHz, the input and output return losses are better than 10 dB.
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Fig. 118. S-parameters of the five-section distributed LNA
Fig. 119 is the noise figure plot of this 5-section distributed LNA. From 8 GHz to
193
20 GHz, the noise figure is better than 6 dB. A detailed noise analysis will be carried
out in the following text to show the noise performance. The loss due to T-lines
loading and T-line loss itself will be ignored for simplicity. Before the noise figure
can be calculated, one must obtain the noise contribution due to MOS transistors
and termination resistors ( ZTs and ZT
d ) as well as the noise power available from the
source generator. The noise of load impedance ZLd belongs to the next stage, so it is
not included in the noise figure calculation.
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Fig. 119. Noise figure of the five-section distributed LNA
The noise contributed from the transistors in different unit sections is assumed to
be uncorrelated with each other. Thus one can first calculate the noise power delivered
into the load due to the transistor in one unit section, then sum the noise power over
the whole N sections to obtain the total noise power generated by transistors in the
distributed circuit. For this purpose, Fig. 120 shows the noise model of a unit section
of the distributed LNA.
The major noise sources are the MOS transistor’s drain noise current ind and
194
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induced gate noise current ing. Their mean-square values are
i2nd = 4kTγ
αgm∆f (7.38)
and
i2ng = 4kTδαω2C2gs5gm
∆f (7.39)
respectively. The drain noise sources will be treated as uniformly distributed over the
unit section. That is to say the drain T-line is periodically driven by noise current
indld
. The noise voltage developed across the load ZLd due to the drain noise source of
the k-th section can be found by the following integral:
vnd, k =∫ kld(k−1)ld
indld
Zdc2e−jβd(Nld−xd)dxd
= 12indZ
dcsin θ
2θ2
e−jθ(N−k+ 1
2)(7.40)
When the gate noise current is injected into the k-th section gate T-line at
position (k − 1) lg, the voltage generated across the load ZLd of the drain T-line due
195
to the forward traveling signal is
v+ng, k =1
4gmZ
gcZ
dc ing
(
N − k + 1
2
)
e−j(N−k+ 1
2)θ (7.41)
and due to the reverse propagation is
v−ng, k =1
4gmZ
gcZ
dc ing
sin(
k − 12
)
θ
θe−j(k−
1
2)θe−j(N−k+ 1
2)θ (7.42)
The noise contributed from the k-th section gate noise is the sum of the forward and
reverse voltage:
vng, k = v+ng, k + v−ng, k
= 14gmZ
gcZ
dc ing
[
(
N − k + 12
)
+sin(k− 1
2)θθ
e−j(k−1
2)θ]
e−j(N−k+ 1
2)θ(7.43)
Adding (7.40) and (7.43) together, the output noise voltage due to transistors in
the k-th section will be obtained as
vno, k =
[
sin θ2
θind +
1
4M(k)gmZ
gc ing
]
Zdc e
−jθ(N−k+ 1
2) (7.44)
where
M (k) =
(
N − k + 1
2
)
+sin(
k − 12
)
θ
θe−j(k−
1
2)θ (7.45)
It is known that ing and ind are correlated with correlation coefficient c which is
purely imaginary and equals j0.395 for long channel devices. ing can be decomposed
into a component ingc which is fully correlated with ind and another component ingu
which is uncorrelated with ind :
ing = ingc + ingu (7.46)
where
i2ngu = 4kTGu∆f (7.47)
196
ingc = Fcind (7.48)
and
Gu = δαω2C2gs5gm
(
1− |c|2)
(7.49)
Fc ≡ ingcind
=ingci∗ndindi
∗
nd
=ingi∗nd
√
i2nd
√i2ng
√i2ng
√
i2nd
= c
√i2ng
√
i2nd
= j |c|α√
δ5γ
ωCgsgm
(7.50)
Using the above notations, the noise power delivered to the load by transistors
in the distributed circuit is
Pno = 4kTgmZdcγα∆f∑N
k=1
∣
∣
∣
sin θ2
θ+ 14gmZ
gcFcM (k)
∣
∣
∣
2
+ 14kTg2mGu (Z
gc )2 Zd
c∆f∑N
k=1 |M (k)|2(7.51)
The output noise power contributed by the drain T-line termination impedance
ZTd is
PndT = kT∆f (7.52)
The gate T-line termination impedance ZTg contributes to the output noise power
in the form of
PnsT = kTG
∣
∣
∣
∣
sinNθ
Nθ
∣
∣
∣
∣
2
∆f
The noise power available from the signal source is
Pns = kT∆f (7.53)
The noise figure can then be calculated from
F = 1 +Pno + PndT + PnsT
PnsG(7.54)
197
where G is the power gain as expressed in (7.34). Written explicitly
F = 1 +∣
∣
sinNθNθ
∣
∣
2+ 4
N2g2mZdcZ
gc
+ 16N2gmZ
gc
γα
∑Nk=1
∣
∣
∣
sin θ2
θ+ 14gmZ
gcFcM (k)
∣
∣
∣
2
+ 1N2GuZ
gc
∑Nk=1 |M (k)|2
(7.55)
In order to gain insights, a simplified version of (7.55) is needed. For large number of
sections, one can assume that the first term in (7.45) dominates, so two summations
in (7.55) will be written as
N∑
k=1
∣
∣
∣
∣
∣
sin θ2
θ+
1
4gmZ
gcFcM (k)
∣
∣
∣
∣
∣
2
∼ N
(
sin θ2
θ
)2
+1
16g2m (Zg
c )2 |Fc|2
N3
3
ΣNk=1 |M (k)|2 ∼ N3
3
This essentially removes the correlation between the gate and drain noise current
sources. The second and third term in (7.55) are small quantities for a large N,
therefore are ignored. So the noise figure can be simplified as
F = 1 +1
NZgc
4γ
α
1
gm
(
sin θ2
θ2
)2
+NZgc
αδ
3
ω2C2gs5gm
(7.56)
It is observed that there is an optimal value of NZgc to minimize noise figure. It is
easy to show that at a specific frequency when
NZgc =
2
α
√
15γ
δ
(
sin θ2
θ2
)
1
ωCgs
(7.57)
the noise figure has a minimum value of
Fmin = 1 + 4
√
δγ
15
ω
ωT
(
sin θ2
θ2
)
(7.58)
where ωT = gmCgs
.
The sinc function in (7.56) dominates the low frequency portion of the noise
figure. Between DC and the first null, the sinc is a descending function of frequency.
198
Thus the noise figure decreases with frequency increasing as shown in Fig. 119. When
frequency increases the gate noise contribution denoted by the ω2 term in (7.56) be-
comes more significant and at the same time the gain drops from its ideal value,
therefore noise figure goes up again with frequency increasing. [67] gives the noise
figure analysis for distributed amplifiers using artificial transmission lines. The sim-
plified form of noise figure is almost the same as derived here except that there is no
sinc function in [67]. For the exact noise figure calculation, [67] did not consider the
fact that the forward and reverse propagated gate noise currents are actually fully
correlated.
4. Analysis of Distributed Mixer
Distributed mixers are constructed the same way as distributed amplifiers. Three
types of distributed mixers are studied in [68]. Cascoded mixer mimics the dual-gate
FET mixer. Matrix mixer utilizes three tiers of transistor to implement RF ampli-
fication, mixing and IF amplification. Balanced mixers use CG-CS FET pairs. By
injecting signals from different terminals of a FET, different mixing modes can be ob-
tained, [69] studied four different distributed mixing modes of FET. It demonstrated
that LO-Gate/RF-Drain and LO-Source/RF-Gate mixing can provide conversion gain
and good port isolation (RF/LO to IF 40 dB).
Fig. 121 is a typical distributed mixer block diagram. Ignore losses introduced by
the T-lines and resistive loading by the transistors, assume the loaded characteristic
impedances and propagation constants of the three transmission lines as followings:
ZRFc and βRF for RF line, ZLO
c and βLO for LO line, ZIFc and βIF for IF line. And
further assume all the T-lines are terminated by their characteristic impedances. The
199
RF signal traveling along the RF line can be written as
vRF (xRF ) = VRF e−jβRF xRF (7.59)
where VRF is the signal incidence into the RF port. The conversion transconductance
gmc of a unit section is uniformly spread over the unit length lIF of IF line. The LO
signal traveling along the LO T-line can be modeled by the phase-shift of conversion
transconductance. Therefore the distributed conversion transconductance gdistm (xLO)
is given by
gdistm (xLO) =gmclIF
e−jβLOxLO (7.60)
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The total voltage developed across the IF load impedance ZLIF can be calculated
by
VIF =1
2
∫ NlIF
0
gdistm (xLO) v∗RF (xRF )Z
IFc e−jβIF (NlIF−xIF )dxIF (7.61)
where down-conversion is assumed, N is the number of sections, and v∗RF (xRF ) rep-
200
resents the complex conjugate of vRF (xRF ).
It is easy to show that
xLO =lLOlIF
xIF (7.62)
and
xRF =lRFlIF
xIF (7.63)
Substitute (7.59), (7.60), (7.62) and (7.63) into (7.61), the voltage conversion
gain can be found to be
Avc =VIFVRF
=N
2gmcZ
IFc e−jNθIF
[
sin N2Θ
N2Θ
e−jN2Θ
]
(7.64)
where Θ = θLO − θRF − θIF . If (LLO, CLO), (LRF , CRF ) and (LIF , CIF ) are the
distributed parameters of the loaded LO, RF and IF T-lines respectively, then one
can write:
θLO = βLOlLO = ωLOlLO√
LLOCLO (7.65)
θRF = βRF lRF = ωRF lRF√
LRFCRF (7.66)
θIF = βIF lIF = ωIF lIF√
LIFCIF (7.67)
The phase synchronization can be established by arranging the T-line parameters
such that
lLO√
LLOCLO = lRF√
LRFCRF = lIF√
LIFCIF (7.68)
Notice that ωIF = ωLO − ωRF and combined with (7.68), then Θ = 0 and the
voltage conversion gain has constant amplitude and group delay over a valid frequency
range:
Avc =N
2gmcZ
IFc e−jNθIF (7.69)
Similar to the distributed LNA voltage gain, the conversion gain and group delay is
linearly proportional to the number of sections.
201
Consider the loss in the circuit, αRF , αLO and αIF are the attenuation constants
of loaded RF, LO and IF T-lines. Furthermore, assume that the loss in the LO signal
will introduce the corresponding reduction in the conversion transconductance gmc.
Under the phase synchronization condition of (7.68), the conversion power gain is
approximately
Gc ≈g2mcZ
IFc ZRF
c
4
∣
∣
∣
∣
e−N(αRF lRF+αLOlLO) − e−N(αIF lIF )αRF lRF + αLOlLO − αIF lIF
∣
∣
∣
∣
2
(7.70)
If the LO signal is large enough such that its attenuation along the line will
not affect the conversion transconductance, then the power conversion gain is not
dependent on αLO:
Gc ≈g2mcZ
IFc ZRF
c
4
∣
∣
∣
∣
e−NαRF lRF − e−NαIF lIF
αRF lRF − αIF lIF
∣
∣
∣
∣
2
(7.71)
This resembles the distributed LNA power gain equation (7.35), so the optimal num-
ber of sections is
Nopt,mixer =ln (αRF lRF )− ln (αIF lIF )
αRF lRF − αIF lIF(7.72)
and if the loss is dominated by the RF T-line loading due to the MOS transistor’s
gate resistance, (7.37) can also be applied to determine the upper bound of N by
changing Zdc to ZIF
c .
C. Wide-Band Impedance Match Using Lumped Components
In the wide-band LNA design, the input impedance matching is another major prob-
lem additional to bandwidth. There are several ways to provide matching. One
solution is to use common gate or common base as input stage. Another way is to
use feedback. These two methods can only work for a moderately wide bandwidth.
For a wider bandwidth new topologies must be developed. Distributed structures
202
using artificial or real transmission lines have good wide band matching property.
It provides 50 Ohm input and output intrinsically. Even for non-distributed circuit,
transmission line matching network can also achieve relatively large bandwidth for
prescribed matching requirement. For on-chip implementation, especially at lower fre-
quency range (several GHz) transmission line’s dimension will be prohibitively large.
So using lumped components will be more appropriate.
1. Impedance Matching Procedure Using Lumped Components
Fig. 122 shows the detailed procedure to match a specific input impedance (s11)
over a specific frequency band to around the center of Smith chart using lumped
components.
First, for a start point, the input impedance of a unilateral MOS transistor is
obtained. This impedance can be modeled approximately by a capacitor and resistor
in series. The capacitance comes from the gate-source capacitance
Cgs = CoxWLov +2
3CoxWLeff (7.73)
where Lov is the gate-source overlap length, Leff is the effective gate length which
equals L − 2Lov. L is the drawn length of the gate. The resistance is due to poly
resistance Rpoly and non-quasi-state (NQS) gate resistance Rnqs. The poly resistance
comes from the physical resistance of gate poly material and will contributes noise.
In order to reduce the gate poly resistance, multiple transistors usually connect in
parallel instead of using just one big transistor. Suppose a transistor comprises num-
ber of n smaller transistors with channel length L and channel width W , then the
gate poly resistance can be calculated from
Rg, poly =Rsh, poly
12n2W
L(7.74)
203
VB
RB
TLine
L1
C1
L2
CcM1
VB
RB
Cc
M1
S11
VB
RB
L2
CcM1
S11
VB
RBL1
C1
L2
CcM1
S11
S11
VB
RBL1
C1
L2
CcM1
S11
Start
Step1
Step2
Step3
Finish
Fig. 122. Wide band matching procedure using lumped components
204
where Rsh, poly is the gate poly sheet resistance. Here it is assumed the both ends of
the gate are connected together in parallel.
For operation frequency comparable to transistor’s cut-off frequency fT , quasi-
state (QS) assumption for the charge behavior under the gate dose not hold anymore.
The NQS effect can be modeled by a resistor Rnqs in series with the gate capacitor
Cgs [70]. Note that resistor Rnqsdoes not contribute to noise, because it is not a
physical resistor. The value of Rnqs is approximately 15gm
[70].
The start point impedance is plotted in the Smith chart over the desired fre-
quency range. The impedance curve is located at position Start in Fig. 122. Then
the following steps are carried out:
1. Series a proper value of inductance such that the conductance at the frequency
edges have the same real part. The impedance curve should move to the position
Step1 in Fig. 122.
2. Parallel an inductor and capacitor tank to bring the frequency edges close to
each other. The impedance contour resembles a circle and moves to the position
Step2 in Fig. 122.
3. Series an inductor again to move the center of the impedance contour to a pure
resistance point as at the position Step3 in Fig. 122. This inductor can be
implemented using bond wire and/or off-chip inductors.
Finally, a quarter-wave transmission line with a proper characteristic impedance is
used to rotate the impedance contour to the center of the Smith Chart, as shown at
the position Finish in Fig. 122. The output impedance matching can be achieved
similarly if required.
205
2. Wide-Band LNA with Lumped-Matched Network
An implementation of wide-band LNA using the impedance matching technique dis-
cussed in the previous section is shown in Fig. 123. This circuit is simulated using
TSMC 0.18µm CMOS technology. It draws 5 mA from a 1.8 V power supply.
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Fig. 124 gives the S-parameters and noise figure plots from 2.8 GHz to 5.0 GHz.
Table XXI summarizes the post-layout simulation results of this wide-band LNA. This
LNA can cover the first 3 bands (from 3.168 GHz to 4.752 GHz) of Texas Instruments
OFDM UWB proposal and can be used in its Mode 1 UWB devices [71].
206
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 51
1.1
1.2
1.3
1.4
1.5
1.6
S21
S11
S22NF
S12
S-para
meter
s (dB
)
Noise
Figu
re (dB
)
Frequency (GHz)
Fig. 124. Wide-band LNA S-parameters and noise figure
Table XXI. Simulation results of lumped-matched wide-band LNA
Parameter Value Unit
Bandwidth 2.8-5.0 GHz
S11 < -13 dB
S21 > 12 dB
Noise Figure < 1.9 dB
P1dB@ input -4.4 dBm
Power 9 mW
207
CHAPTER VIII
SUMMARY AND CONCLUSION
In the dissertation, LNA design aspects and the major design considerations were
first reviewed. In order to implement a good design, a lot of information from the
process capability to system requirements are needed to give access to RF designers.
This makes the seemingly simple circuit of a LNA actually the trickiest part in the
front end of a receiver system. Two design approaches exist. One is the microwave
approach, which first selects a specific microwave transistor according to the data
sheet obtained from manufacture. The choice of device relies on its gain, noise and
linearity capability. Then trade-offs are made for gain, impedance match and noise
match. The matching network at input and output will finally be implemented con-
sidering the above merits and stability. The way RF IC designers are adopted is more
complicated. In IC design, one has the freedom to change the geometry of the devices
as well as bias condition. The microwave design target is to find an optimal matching
network for a specific device, but the IC designers want to find an optimal structure
for all possible devices. Of course, this is not always possible, but the freedom of
varying device sizes really gives more room for IC designers. Another consideration is
that if the LNA does not require driving off-chip filters, it is not necessary to match
its output to 50 ohm or even there is no need to realize matching network between
the output of the LNA and the input of the next stage (usually mixers). Of course,
proper interface between them still needs to be implemented.
As an important frequency translation functional block, the mixer design deals
with three different frequencies. Mixer translates the amplified signal form the LNA
to a frequency band suitable for the baseband circuit to process. Conversion gain
208
shows the mixer’s frequency translation efficiency. A mixer is more noisy than a
LNA. Especially for low-IF applications, low frequency flicker noise dominates the
mixer’s noise performance. It is vital to choose a proper IF frequency such that the
MOS transistor’s flicker noise corner is lower than the IF frequency. Mixers in sili-
con implementation usually use double-balanced structure to improve port isolations
and suppress common-mode noise and interferences. A low-IF Bluetooth receiver is
designed and tested. The mixer for this receiver using the current-bleeding technique
to reduce the flicker noise effect of the current switching pairs. Measurements show
that the mixer worked properly with other blocks in the whole system.
A detailed implementation was discussed for a Blutooth/WiFi dual-mode direct
conversion receiver RF front-end. The LNA features inductive degeneration, gate-
induced noise reduction and bipolar cascoded techniques and the down-conversion
mixer has combined RF driver and bipolar current switching pairs. A PTAT biasing
circuit is also included for stable bias condition setup. The dual-mode receiver with
this front-end has sensitivity for Bluetooth mode -91 dBm and for WiFi mode (11
Mb/s) -86 dBm.
More research effort was exerted on LNA design techniques. With the devel-
opment of the IC fabrication, bipolar transistor will be readily available in CMOS
process. For the LNA design, the possibility of using both MOS transistor and bipolar
transistor was explored. This hybrid structure was inspired by the multi-gated MOS
configuration for linearization purpose. It is the first structure that MOS transistor
and BJT are working together at the signal path. A mutual inductive degenerated
LNA designed for dual-band application was studied to show the benefits of mutual
inductive coupling in the LNA design.
UWB technology can provide costumers more bandwidth, high speed and versa-
tile services. It has enormous potential applications, especially in the wireless PAN
209
standards. Distributed circuits are applicable in the RF front-end of UWB systems
due to their inherent wide-band nature. For lower frequency bands, lumped-matched
wide-band LNA occupies less silicon area and is more power efficient. A successful
design of a UWB system will require multi-disciplinary knowledge, such as channel
measurements, antenna theory, RF and high speed analog design, software devel-
opment and system simulation. For the RF front-end portion, the LNA/antenna
co-design may be needed for optimal performance.
To conclude, the contributions of the dissertation include: design RF front-end
for a low-IF Bluetooth receiver and a direct conversion Bluetooth/WiFi dual mode
receiver (Chameleon); LNA linearization technique using MOS/BJT hybrid; mutual
inductive degeneration for a dual-band cellular LNA; analysis of distributed LNA
and mixer, and the proposed procedure to achieve wide band impedance match using
lumped components.
210
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219
APPENDIX A
CONSTANT CIRCLES
Circle Equation in the Complex Plane
A circle in complex plane can be represented by
|z|2 − c ∗ z − cz∗ = b (A.1)
where z is the point on the circle, c is a complex constant number, b is a real constant
number and b+ |c|2 > 0. The proof is given as follows.
Adding |c|2 to both sides of (A.1) leads to |z|2− c∗z− cz ∗+ |c|2 = b+ |c|2. Since
|z|2 − c ∗ z − cz ∗ + |c|2 = |z − c|2, then |z − c|2 = b + |c|2 and |z − c| =√
b+ |c|2.
Because b+ |c|2 > 0, it is the equation for a circle with center located at point c and
having radius r =√
b+ |c|2.
Constant Gain Circle
Taking the input mismatch factor (??) for example. We will prove that for fixed value
of s11 and Gs, Γs resides on a circle and find its center and radius.
Let us define gs = Gs
(
1− |s11|2)
= GsGsmax
. Substituting (??) in to gs gives
gs =
(
1− |s11|2) (
1− |Γs|2)
|1− s11Γs|2
gs (1− s11Γs) (1− s∗11Γ∗s) = 1− |s11|2 − |Γs|2 + |s11|2 |Γs|2
gs(
1− s11Γs − s∗11Γ∗s + |s11|2 |Γs|2
)
= 1− |s11|2 − |Γs|2 + |s11|2 |Γs|2
220
Finally,
|Γs|2 −gss11
1− |s11|2 (1− gs)Γs −
gss∗11
1− |s11|2 (1− gs)Γ∗s =
(1− gs)− |s11|2
1− |s11|2 (1− gs)(A.2)
Notice that gs is a real number and 0 < gs < 1, according to (A.1), (A.2)
represents a circle with
c =gss
∗11
1− |s11|2 (1− gs)(A.3)
which is the center of the circle, and
b =(1− gs)− |s11|2
1− |s11|2 (1− gs)
The radius of the circle is
r =
√
b+ |c|2 =√1− gs
(
1− |s11|2)
1− |s11|2 (1− gs)
The proof for output constance circle can be carried out similarly.
Constant Noise Circle
We want to show that (2.66) is a circle equation for variable Γs. Rewriting (2.66) as
(Γs − Γopt)(
Γ∗s − Γ∗
opt
)
= N(
1− |Γs|2)
and then
(1 +N) |Γs|2 − Γ∗optΓs − ΓoptΓ
∗s = N − |Γopt|2
at last
|Γs|2 −(
Γopt1 +N
)∗Γs −
(
Γopt1 +N
)
Γ∗s =
N − |Γopt|21 +N
(A.4)
According to (A.1), (A.4) describes a circle with
c =Γopt1 +N
221
which is center location, and
b =N − |Γopt|2
1 +N
The radius of the circle is
r =
√
b+ |c|2 = N
1 +N
√
1 +1
N
(
1− |Γopt|2)
222
APPENDIX B
VOLTERRA SERIES AND EXAMPLES
Vito Volterra first studied the functional series named after him in the 1880s as a
generalization of the Taylor series expansion of a non-linear function. In 1942, N.
Wiener applied the Volterra theory to the analysis of a series RLC circuit with a non-
linear resistor to a white Gaussian excitation. The systematic study of the application
of the Volterra series to non-linear system was conducted by J. F. Barrett in 1957.
D. A. George extended Barrett’s work and developed a system algebra and used
the multidimensional Laplace transformation to study Volterra operators and their
application to non-linear system. The development of the Volterra theory has led
to an extensive study of its application to practical problems in may fields including
the calculation of small, but nevertheless troublesome, distortion terms in transistor
amplifiers and systems.
Volterra Series Representation of Non-Linear Systems
A linear, causal and time-invariant system with memory can be described by the
convolution integral
y (t) =
∫ ∞
−∞h (τ)x (t− τ) dτ (B.1)
where h (t) is the impulse response of the system. A non-linear system without
memory can be represented using a Taylor series
y (t) = K1x (t) +K2 [x (t)]2 +K3 [x (t)]
3 + · · ·+Kn [x (t)]n + · · · (B.2)
A Volterra series combines (B.1) and (B.2) to describe a non-linear system with
223
memory [72]
y (t) = H1 [x (t)] +H2 [x (t)] +H3 [x (t)] + · · ·+Hn [x (t)] + · · · (B.3)
in which
Hn [x (t)] =
∫ ∞
−∞· · ·∫ ∞
−∞hn (τ1, · · · , τn)x (t− τ1) · · · x (t− τn) dτ1 · · · dτn (B.4)
Therefore, Volterra series is an infinite sum of n-fold convolution integrals. Hn [·]
is called the n-th order Volterra operator. hn (τ1, · · · , τn)is the n-th order Volterra
kernel and for n = 1, 2, · · ·,
hn (τ1, · · · , τn) = 0 for any τj < 0, j = 1, 2, · · · , n (B.5)
In general, kernel hn (τ1, · · · , τn) is not symmetrical to its variables. However,
it can be shown that it is always possible to construct a symmetrical kernel from an
asymmetrical form of the kernel h(a)n (τ1, · · · , τn):
h(s)n (τ1, · · · , τn) =1
n!
∑
P
han (τ1, · · · , τn) (B.6)
where the summation runs through all possible permutations of the n τ ’s.
To gain more insights, one would like to study the non-linear system in fre-
quency domain. The basic integral transform, Fourier transform can be extended
to the Volterra series representation. For an n-th order kernel hn (τ1, · · · , τn), its
n-dimensional Fourier transform is
Hn (jω1, · · · , jωn) =∫ ∞
−∞· · ·∫ ∞
−∞hn (τ1, · · · , τn) ej(ω1τ1+···+ωnτn)dτ1 · · · dτn (B.7)
If the input’s Fourier transform is X (jω), then the Fourier transform of the n-th
224
order system (B.4) can be shown to be
Yn (jω) = 1(2π)n−1
∫∞−∞ · · ·
∫∞−∞Hn (jω − jν1, jν1 − jν2, jν2 − jν3, · · · , jνn−1)
× X (jω − jν1)X (jν1 − jν2)X (jν2 − jν3) · · · X (jνn−1) dν1 · · · dνn(B.8)
The Fourier transform of the whole Volterra series will be the sum of different orders.
Written the first three terms explicitly in terms of frequency f :
Y (f) = H1 (f)X (f)
+∫∞−∞H2 (f − f1, f1)X (f − f1)X (f1) df1
+∫∞−∞H3 (f − f1, f1 − f2, f2)X (f − f1)X (f1 − f2)X (f2) df1df2
+ · · ·
(B.9)
Circuit Model of a Non-linear Time-Invariant System
In a general non-linear system or circuit, the memory effect and non-linearity are not
distinctly separated, which makes the circuit representation rather complicated even
if possible. An important simplification assumes that frequency dependent signal
paths are multiplied so that the multiplication does not affect the time constant of
the following filters. For example, a lot of circuits can be approximated as a non-
linear memoryless gain stage with input and output filters, as shown in Fig. 125. The
non-linear gain stage is represented by the Taylor series as in (B.1). The first order
response of this system is simply
H1 (jω) = F (jω)K1G (jω) (B.10)
The second and third order responses are depicted in Fig. 126. For the second order
response, the input filter is evaluated at two different frequencies, then the response
are multiplied and further scaled by the second order gain and output filter response
225
( )ωjF ( )xA ( )ωjGX Y
Memorybut linear
Non-linearbut memoryless
Fig. 125. Circuit model of a non-linear time-invariant system
at the output frequency:
H2 (jω1, jω2) = F (jω1)F (jω2)K2G [j (ω1 + ω2)] (B.11)
Similarly, the third order response is
H3 (jω1, jω2, jω3) = F (jω1)F (jω2)F (jω3)K3G [j (ω1 + ω2 + ω3)] (B.12)
For sinusoidal inputs, a short-hand notation is used to represent the output
frequency components of the non-linear system. Suppose the input has m frequency
components
X = X1 cosω1t+X2 cosω2t+ · · · +Xm cosωmt (B.13)
The output of the system can be denoted as
Y = H1 (jωp1) X +H2 (jωp1, jωp2) X2 +H3 (jωp1, jωp2, jωp3) X3 + · · · (B.14)
where ωp1, ωp1, . . ., ωpn choose from all the possible n out of m permutations of ±ω1,
±ω2, . . ., ±ωm. Xn represents the corresponding amplitude Xp1Xp2 · · · Xpn. The op-
erator generates all the items cos (ωp1 + ωp2 + · · · + ωpn) and scale their magnitudes
226
( )3ωjF
( )1ωjF
( )2ωjF ( )321 ωωω jjjG ++3K
3rd order response
( )21 ωω jjG +2K
( )1ωjF
( )2ωjF
2nd order response
Fig. 126. Second and third order response block diagrams
with |Hn (jωp1, jωp2, · · · jωpn)| and modify their phases with ∠Hn (jωp1, jωp2, · · · jωpn).
The short-hand notation (B.14) is usually used for actual circuit non-linear analysis.
An Example: Volterra Series of a MOS Differential Pair
In this section, a detailed procedure for deriving a MOS differential pair’s Volterra
series is given as an example [37]. The MOS differential under study is shown in
Fig. 127. This seemingly simple circuit can not be represented using the circuit model
representation given in Fig. 125, so full Volterra expansion has to be employed. The
small signal input to the differential pair is assumed to have only differential voltage
vd. The input common-mode voltage provides DC bias. The small signal voltages
applied to the gates ofM1 andM2 arevd2and −vd
2respectively. The tail current source
is assumed to be ideal and provides DC bias current Iss. The small signal voltage at
227
Cs
M1 M2
Iss
idvd2
vd2
vs
Fig. 127. A MOS differential pair for Volterra analysis
the common-source node is vs. The only memory effect is introduced by the parasitic
capacitance Cs at node vs. All other capacitances are ignored for simplicity. The
MOS transistors are modeled as square law devices and
Iss = K (VGS − Vt)2 (B.15)
The goal is to obtain the Volterra series expansion for the small signal drain
current id of M1 (or M2) in terms of input differential voltage vd up to 3rd order. To
this end, the Volterra series of the common-source voltage vs will be determined first,
i.e. vs will be expanded into
vs = G1 vd +G2 v2d +G3 v3d + · · ·
= vs1 + vs2 + vs3 + · · ·(B.16)
where vsk = Gk vkd , is the k-th order term of the Volterra series of vs. Applying KCL
at the common-source node
CsdVsdt
+ Iss =K
2
[
(Vgs1 − Vt)2 + (Vgs2 − Vt)2]
(B.17)
228
where Vs, Vgs1 and Vgs2 can be written into DC and signal small signal terms
Vs = VS + vs (B.18)
Vgs1 = VGS + vgs1 (B.19)
Vgs2 = VGS + vgs2 (B.20)
and further express vgs1 and vgs2 in terms of differential input voltage vd and common-
source voltage vs
vgs1 =vd2− vs (B.21)
vgs2 = −vd2− vs (B.22)
Substituting from (B.18) to (B.22) into (B.17) and simplifying it,
Csdvsdt
+ 2gmvs −Kv2s =K
4v2d (B.23)
where gm = K (VGS − Vt) is the MOS transistor’s transconductance. Substituting
(B.16) into (B.23) and taking the phasor form of dvsdt
(jωCs + 2gm) (vs1 + vs2 + vs3 + · · ·)−K (vs1 + vs2 + vs3 + · · ·)2 =K
4v2d (B.24)
The Volterra kernel Gk can be obtained by equating the same order term of vd
at both sides of (B.24). Keeping only the first order terms
(jωCs + 2gm)G1 (ω) vd = 0 (B.25)
Hence
G1 (ω) = 0 (B.26)
This means vs1 = 0. Substituting it into (B.24)
(jωCs + 2gm) (vs2 + vs3 + · · ·)−K (vs2 + vs3 + · · ·)2 =K
4v2d (B.27)
229
Keeping only the second order terms
[j (ω1 + ω2)Cs + 2gm]G2 (ω1, ω2) v2d =K
4v2d (B.28)
Thus
G2 (ω1, ω2) =K4
j (ω1 + ω2)Cs + 2gm(B.29)
Cs is parasitic capacitance, so usually (ω1 + ω2)Cs¿ 2gm. (B.29) can be simplified
by taking its Taylor expansion and only retain the first two terms
G2 (ω1, ω2) ≈K
8gm
[
1− j (ω1 + ω2)Cs
2gm
]
(B.30)
Now factoring out the third order terms from (B.27)
[j (ω1 + ω2 + ω3)Cs + 2gm]G3 (ω1, ω2, ω3) v3d = 0 (B.31)
This means that
G3 (ω1, ω2, ω3) = 0 (B.32)
Higher order kernels can be calculated by repeating the above procedures.
Now, vs has been expanded into Volterra series up to the third order. Note that
G1 and G3 are all zero, so
vs = vs2 + · · · = G2 (ω1, ω2) v2d + · · · (B.33)
Because of the operator , (B.33) actually consists of four terms corresponding four
different cases: ω1, ω2 = ±ωa, ±ωb.
Remember that the final goal is to obtain the Volterra series expansion for id in
terms of vd, i.e.
id = H1 vd +H2 v2d +H3 v3d + · · ·
= id1 + id2 + id3 + · · ·(B.34)
230
Using the MOS device equation, the small-signal output current id can be related to
the input differential voltage and common-source voltage vs as
id =K
2
(vd2− vs
)2
+ gm
(vd2− vs
)
(B.35)
Substituting (B.33) and (B.34) into (B.35)
id1+ id2+ id3+ · · · =K
8v2d +
K
2(vs2 + · · ·)2−
K
2vd (vs2 + · · ·)+ gm
(
1
2vd − vs2 − · · ·
)
(B.36)
Keeping the first order terms in (B.36)
id1 =1
2gmvd (B.37)
Thus
H1 (ω) =1
2gm (B.38)
This is the transconductance of the differential pair for a single-ended output.
Isolating the second order terms in (B.36)
id2 (ω1, ω2) =K
8v2d − gmG2 (ω1, ω2) v2d (B.39)
So
H2 (ω1, ω2) =K
8
[
1− 1
1 + j (ω1 + ω2)Cs2gm
]
≈ j (ω1 + ω2)K
16
Cs
gm(B.40)
To obtain the third order kernel, separating the 3rd order terms from (B.36)
id3 (ω1, ω2, ω3) = −K2vdvs2 = −K
2G2 (ω1, ω2) v3d
= −K2
[
G2(ω1, ω2)+G2(ω1, ω3)+G2(ω2, ω3)3
]
v3d(B.41)
The summation of permutations of G2 notated by G2 is used to obtain a symmetrical
231
kernel. Substituting (B.30) into the above equation
H3 (ω1, ω2, ω3) ≈ −K2
16gm
[
1− j (ω1 + ω2 + ω3)Cs
3gm
]
(B.42)
This leads to the end of the Volterra series expansion of drain current id in terms
of differential input vs. Table XXII compares the results obtained from the above
analysis with low frequency Taylor series analysis. It is seen that Taylor series does
not reveal the high frequency second-order nonlinearity for a differential pair.
Table XXII. Volterra series versus Taylor series
Volterra Kernel Taylor Coefficient
1st order 12gm
12gm
2nd order j (ω1 + ω2)K16
Csgm
0
3rd order − K2
16gm
[
1− j (ω1 + ω2 + ω3)Cs3gm
]
− K2
16gm
Another Example: Resistive-Degenerated BJT
Here the detailed derivation of the Volterra series of a resistive-degenerated bipolar
transistor (see Fig. 75) is given. The results were used in Chapter V. We start from
the equation (5.67) in Chapter V. This equation is rewritten as following by using
Hk instead of Bk as the kernel notation:
H0 +H1 vi +H2 v2i +H3 v3i + · · · =
IQ
1 + 1It[−H0 + (ge −H1) vi −H2 v2i −H3 v3i + · · ·]
+ 12I2t
[−H0 + (ge −H1) vi −H2 v2i −H3 v3i + · · ·]2
+ 16I3t
[−H0 + (ge −H1) vi −H2 v2i −H3 v3i + · · ·]3+ · · ·
(B.43)
232
In the above expression, the frequency variables of Hk are dropped for conciseness.
Hk actually means Hk (ω1, ω2, · · · , ωk), k = 0, 1, 2, · · ·. Also the following equations
hold:
It (ω) = It0
(
1 + jω
ωπ
)
(B.44)
It0 = φtge (B.45)
ωπ =geCπ
(B.46)
Re =1
ge(B.47)
The Volterra kernels can be calculated by equating the same order terms from both
sides of (B.43). The zero-th order or DC term will be calculated first, then the first
order, second order and third order, etc.
To calculate the zero-th order, isolating H0 from both sides of (B.43)
H0IQ
= 1− H0It0
+H20
2I2t0− H3
0
6I3t0+ · · · = e
−H0Ito (B.48)
H0
It0and
IQIt0
are much less than unity values, high order terms in (B.48) can be ignored
and
H0 ≈IQ
1 +IQIto
≈ IQ (B.49)
For the 1st order kernel H1 (ω), we have
H1
IQ= 1
It1(ge −H1) + 1
I2t1[−H0 (ge −H1)] + 1
2I3t1H20 (ge −H1) + · · ·
= 1It1
(ge −H1)[
1 + −H0
It1+
H20
2I2t1+ · · ·
]
= 1It1
(ge −H1) e−H0It1
(B.50)
where It1 = It (ω) = It0
(
1 + j ωωπ
)
. Solving for H1 from (B.50)
H1 =IQgee
−H0It1
It1 + IQe−H0It1
(B.51)
233
Note that
H0It0≈ IQIt0
=IQφtge
= gmRe (B.52)
For intermediate frequency of operation ω ¿ ωπ and also notice e−H0It0 ≈ 1,
e−H0It1 = e
− H0
It0(1+j ωωπ ) ≈ e
−H0It0 · ej
H0It0
ωωπ ≈ ej
ωωπ
gmRe (B.53)
Substituting (B.52) and (B.53) into (B.51), an intermediate frequency approximation
can be obtained:
H1 ≈gm(1+j ω
ωπgmRe)
(1+gmRe)+jωωπ(1+g2mR
2e)
≈ gm1+gmRe
(
1 + j ωωπgmRe
) [
1− j ωωπ
(1− gmRe)]
≈ gm1+gmRe
[
1− j ωωπ
(1− 2gmRe)]
≈ gm1+gmRe
(
1− j ωωπ
)
(B.54)
For DC and low frequency operations ωωπ∼ 0,
H1 ≈gm
1 + gmRe
(B.55)
This is the same as using Taylor series expansion for the circuit’s transconductance.
The 2nd order kernel H2 (ω1, ω2) satisfies
H2
IQ= −H2
It2+ 12I2t2
(ge −H1)2 + 1I2t2H0H2
−H0
2I3t2(ge −H1)2 + −H2
0
2I3t2H2 + · · ·
(B.56)
where It2 = It (ω1 + ω2) = It0
(
1 + j ω1+ω2
ωπ
)
, and
(ge −H1)2 =1
2
[ge −H1 (ω1)]2 + [ge −H1 (ω2)]2
(B.57)
Rearranging the terms in (B.56) yields
(
It2IQ
+ 1− H0It2
+1
2
H20
I2t2− · · ·
)
H2 =1
2It2(ge −H1)2
(
1− H0It2
+ · · ·)
(B.58)
234
or equivalently(
It2IQ
+ e−H0It2
)
H2 =1
2It2(ge −H1)2e−
H0It2 (B.59)
and solving for H2
H2 =IQ2It2
(ge −H1)2e−H0It2
It2 + IQe−H0It2
(B.60)
An intermediate frequency approximation can be obtained easily by going through
a procedure similar to that of H1, and using the H1’s low frequency approximation.
The result is given below:
H2 ≈g2m2IQ
1
(1 + gmRe)3
[
1− j 2 (ω1 + ω2)
ωπ
]
(B.61)
The DC and low frequency approximation is
H2 ≈g2m2IQ
1
(1 + gmRe)3 (B.62)
The 3rd order kernel fulfills
H3
IQ= −H3
It3+ 1
I2t3H0H3 − 1
I2t3(ge −H1)H2
+ 16I3t3
(ge −H1)3 − 12I3t3
H20H3 + · · ·
(B.63)
where It3 = It (ω1 + ω2 + ω3) = It0
(
1 + j ω1+ω2+ω3
ωπ
)
, and
(ge −H1)H2 = 13[ge −H1 (ω1)]H2 (ω2, ω3)
+ [ge −H1 (ω2)]H2 (ω1, ω3)
+ [ge −H1 (ω3)]H2 (ω2, ω1)
(B.64)
(ge −H1)3 =1
3
[ge −H1 (ω1)]3 + [ge −H1 (ω2)]3 + [ge −H1 (ω3)]3
(B.65)
Rearranging the terms in (B.63) yields
(
It3IQ
+ 1− H0It3
+H20
2I2t3− · · ·
)
H3 ≈1
6I2t3(ge −H1)3 −
1
It3(ge −H1)H2 (B.66)
235
or equivalently
(
It3IQ
+ e−H0It3
)
H3 ≈1
6I2t3(ge −H1)3 −
1
It3(ge −H1)H2 (B.67)
Solving for H3
H3 ≈IQ6I2t3
(ge −H1)3 − 6It3(ge −H1)H2It3 + IQe
−H0It3
(B.68)
Applying for intermediate frequency approximation ω ¿ ωπ, and using low frequency
approximation for H1 and H2
H3 ≈ g3m6I2Q(1+gmRe)
5 (1− 2gmRe)[
1− j ω1+ω2+ω3
ωπ(3− gmRe)
]
≈ g3m6I2Q(1+gmRe)
5 (1− 2gmRe)[
1− j 3(ω1+ω2+ω3)ωπ
] (B.69)
A low frequency approximation is given by dropping the frequency term in (B.69)
H3 ≈g3m
6I2Q (1 + gmRe)5 (1− 2gmRe) (B.70)
Higher order kernels can be calculated by repeating the above procedures. For
quick reference, the results in this example are summarized in Table XXIII.
Table XXIII. Volterra kernels of degenerated BJT
Exact expression Intermediate frequency
H0 IQ IQ
H1IQgee
−H0It1
It1+IQe−H0It1
gm1+gmRe
(
1− j ωωπ
)
H2IQ2It2
(ge−H1)2e
−H0It2
It2+IQe−H0It2
g2m2IQ
1(1+gmRe)
3
[
1− j 2(ω1+ω2)ωπ
]
H3IQ6I2t3
(ge−H1)3−6It3(ge−H1)H2
It3+IQe−H0It3
g3m6I2Q(1+gmRe)
5 (1− 2gmRe)[
1− j 3(ω1+ω2+ω3)ωπ
]
236
VITA
Chunyu Xin was born in Tianjin, China. He received his B.S. and M.S. degrees from
Nankai University, Tianjin, China in 1997 and 1999 respectively. He is presently work-
ing toward his Ph.D. degree under the supervision of Dr. Edgar Sanchez-Sinencio in
the Analog and Mixed Signal Center, Texas A&M University. From September 2001
to August 2002 he worked for Motorola in Austin, TX for his internship. His re-
search interests are focused on integrated radio frequency circuits design for wireless
receivers. He held a Motorola fellowship in 2000. He has been an IEEE student mem-
ber since 2001. He can be reached through the Department of Electrical Engineering,
Texas A&M University, College Station, TX 77843.
The typist for this dissertation was Chunyu Xin.